Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu.v
D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.08
Part Number GW1NSR-LV4CQN48GC7/I6
Device GW1NSR-4C
Created Time Wed Oct 19 10:17:04 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.322s, Peak memory usage = 47.008MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 47.008MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 47.008MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 47.008MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 47.008MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 47.008MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 47.008MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 47.008MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 47.008MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 47.008MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 47.008MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 47.008MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.455s, Peak memory usage = 57.883MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 57.883MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 57.883MB
Total Time and Memory Usage CPU time = 0h 0m 0.808s, Elapsed time = 0h 0m 0.913s, Peak memory usage = 57.883MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 20
I/O Buf 20
    IBUF 3
    OBUF 1
    IOBUF 16
Register 127
    DFFP 1
    DFFPE 2
    DFFC 49
    DFFCE 59
    DFFNCE 16
LUT 140
    LUT2 30
    LUT3 57
    LUT4 53
INV 22
    INV 22
BSRAM 8
    SDPB 8
Black Box 1
    EMCU 1
User Flash 1
    FLASH256K 1

Resource Utilization Summary

Resource Usage Utilization
Logic 162(162 LUTs, 0 ALUs) / 4608 4%
Register 127 / 3570 4%
  --Register as Latch 0 / 3570 0%
  --Register as FF 127 / 3570 4%
BSRAM 8 / 10 80%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sys_clk Base 20.000 50.0 0.000 10.000 sys_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk 50.0(MHz) 93.8(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.672
Data Arrival Time 6.117
Data Required Time 10.789
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 143 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/CLK
1.336 0.340 tC2Q RF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/I1
2.506 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/I0
3.627 0.765 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/F
3.982 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s14/I2
4.591 0.609 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s14/F
4.947 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/I1
5.761 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/F
6.117 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL FF 1 sys_clk_ibuf/I
10.729 0.729 tINS FF 143 sys_clk_ibuf/O
11.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/CLK
10.789 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.003, 58.636%; route: 1.778, 34.731%; tC2Q: 0.340, 6.633%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 2

Path Summary:
Slack 4.721
Data Arrival Time 6.067
Data Required Time 10.789
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 143 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/CLK
1.336 0.340 tC2Q RF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_cpol_s0/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/I1
2.506 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s21/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/I0
3.627 0.765 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/F
3.982 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s14/I2
4.591 0.609 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s14/F
4.947 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/I0
5.712 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/F
6.067 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL FF 1 sys_clk_ibuf/I
10.729 0.729 tINS FF 143 sys_clk_ibuf/O
11.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/CLK
10.789 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 2.953, 58.231%; route: 1.778, 35.071%; tC2Q: 0.340, 6.698%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack 4.767
Data Arrival Time 6.022
Data Required Time 10.789
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 143 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/CLK
1.336 0.340 tC2Q RF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n416_s5/I1
2.506 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n416_s5/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n416_s4/I3
3.326 0.464 tINS FF 12 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n416_s4/F
3.681 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/I1
4.496 0.814 tINS FF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/F
4.851 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/I1
5.666 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/F
6.022 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL FF 1 sys_clk_ibuf/I
10.729 0.729 tINS FF 143 sys_clk_ibuf/O
11.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK
10.789 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 2.907, 57.850%; route: 1.778, 35.391%; tC2Q: 0.340, 6.759%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack 5.997
Data Arrival Time 4.791
Data Required Time 10.789
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 143 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n95_s1/I1
2.506 0.814 tINS FF 3 Gowin_EMPU_inst/u_flash_wrap/n95_s1/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n77_s1/I2
3.471 0.609 tINS FF 14 Gowin_EMPU_inst/u_flash_wrap/n77_s1/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n157_s0/I2
4.436 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n157_s0/F
4.791 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL FF 1 sys_clk_ibuf/I
10.729 0.729 tINS FF 143 sys_clk_ibuf/O
11.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3/CLK
10.789 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 2.033, 53.561%; route: 1.423, 37.490%; tC2Q: 0.340, 8.949%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 5

Path Summary:
Slack 5.997
Data Arrival Time 4.791
Data Required Time 10.789
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 143 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n95_s1/I1
2.506 0.814 tINS FF 3 Gowin_EMPU_inst/u_flash_wrap/n95_s1/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n77_s1/I2
3.471 0.609 tINS FF 14 Gowin_EMPU_inst/u_flash_wrap/n77_s1/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n156_s0/I2
4.436 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n156_s0/F
4.791 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL FF 1 sys_clk_ibuf/I
10.729 0.729 tINS FF 143 sys_clk_ibuf/O
11.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3/CLK
10.789 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 2.033, 53.561%; route: 1.423, 37.490%; tC2Q: 0.340, 8.949%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%