Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\ahb_def_slave.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\ahb_s_mux.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\ahb_to_sram.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\BusMatrix.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_bus_matrix.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_cdc_capt_sync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_cdc_connect.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_cdc_random.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_clk_gate.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_code_mux.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_mst.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_slv.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_sync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dap_ahb_ap_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_16bit_dec.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_32bit_dec.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu_bshift.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu_ctl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu_dp.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_alu_srtdiv.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_br_dec.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_dec.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_etmintf.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_exec.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_fetch.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_fetch_ahbintf.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_fetch_ctl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_lsu.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_lsu_ahbintf.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_lsu_ctl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_regbank.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_regfile.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_status.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dpu_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_apb_if.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_comp.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_packet_gen.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_packet_state.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_dwt_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_apb_if.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_clk_gate.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_control_reg.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_event_gen.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_fifo.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_gen.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_res_control.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_sync_count.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trace.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trace_out.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trc_en.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trig_gen.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_trigger.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_etm_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_example_pmu.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_flash_mux.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_fpb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_fpb_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_fpb_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_htm_port.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_arb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_emit.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_fifo.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_fifo_byte.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_if.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_itm_ts.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_lic_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_ahb_ctl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_align.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_comp.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_default.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_full.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_maskgen.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_ppb_intf.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_region.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_regions.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mpu_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_bit_master.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_decode_dap.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_decode_dcore.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_decode_icore.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_input_stage_dap.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_input_stage_dcore.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_input_stage_icore.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_output_stage_dcode.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_output_stage_icode.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_output_stage_ppb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_output_stage_sys.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_mtx_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_cell.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_int_state.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_main.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_ppb_intf.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_preempt.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_reg.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_tree.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_nvic_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_ppb_ahb_to_apb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_ppb_decoder.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_rom_table.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_sync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_apb_if.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_atb_fifo.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_atb_sync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_formatter.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_trace_clk.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_trace_fifo.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_trace_out.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_trace_sync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_tpiu_undefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cm3_wic.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\CM3ETM.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_miim_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_rx_to_buffer.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_rx_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_tx_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_ethmac_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_gpio.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_ahbif_ctrl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_arbiter.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_async_fifo_clr.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_config.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_const.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_ctrl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_eilmif_ctrl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_fifo.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_gck.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_pad_lib.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_reg.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_regif.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_regif_ctrl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_spiif.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_sync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_sync_l2l.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_spi_flash_sync_p2p.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_ahb_to_iop.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_spi.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_timer.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_uart.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_watchdog.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_watchdog_defs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_apb_watchdog_frc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\cmsdk_iop_gpio.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\CORTEXM3.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\CORTEXM3INTEGRATION.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpApbDefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpApbIfClamp.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpApbSync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpClamp0.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpEnSync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpIMux.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPDpSync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPJtagDpDefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPJtagDpProtocol.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwDpApbIf.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwDpDefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwDpProtocol.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwDpSync.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSWJDP.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwjDpDefs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DAPSwjWatcher.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\ddr3_1_4code.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DDR3_define.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\ddr3_name.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\ddr3_to_ahb_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\DDR3_TOP.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\dtcm.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\Gowin_EMPU_M3_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\GowinAhbExt.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\GowinCM3AhbExt.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\GowinCM3AhbExtWrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\gw_apb_i2c.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\gw_apb_int_wrapper.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\gw_apb_sd.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\gw_gpio.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\InputStage.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\itcm.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\m3_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\MatrixDecodeS0.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\MatrixDecodeS1.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\MatrixDecodeS2.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\OutputArb1.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\OutputArb2.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\OutputArb3.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\OutputStage1.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\OutputStage2.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\OutputStage3.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\p_sse050_interconnect_f0_ahb_to_apb.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\p_sse050_interconnect_f0_apb_slave_mux.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\Rtc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\RtcApbif.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\RtcControl.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\RtcCounter.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\RtcInterrupt.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\RtcParams.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\RtcRevAnd.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\RtcSynctoPCLK.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\RtcUpdate.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\sse050_int_apb_decoder.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\sse050_integration_peripherals.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\sync_p2p.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\GOWIN_EMPU_M3\data\triple_speed_mac_name.v
C:\Users\liukai\Desktop\gowin_empu_m3\src\gowin_empu_m3\temp\gw_empu_m3\cm3_option_defs.v
C:\Users\liukai\Desktop\gowin_empu_m3\src\gowin_empu_m3\temp\gw_empu_m3\ahb_option_defs.v
C:\Users\liukai\Desktop\gowin_empu_m3\src\gowin_empu_m3\temp\gw_empu_m3\triple_speed_mac_param.v
C:\Users\liukai\Desktop\gowin_empu_m3\src\gowin_empu_m3\temp\gw_empu_m3\triple_speed_mac_define.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Tue Aug 22 08:53:33 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_M3_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 15s, Elapsed time = 0h 0m 17s, Peak memory usage = 310.699MB
Running netlist conversion:
    CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.83s, Peak memory usage = 310.699MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 310.699MB
    Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 310.699MB
    Optimizing Phase 2: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 310.699MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 310.699MB
    Inferring Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.187s, Peak memory usage = 310.699MB
    Inferring Phase 2: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.257s, Peak memory usage = 310.699MB
    Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 310.699MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 310.699MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 310.699MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 310.699MB
    Tech-Mapping Phase 3: CPU time = 0h 2m 37s, Elapsed time = 0h 2m 37s, Peak memory usage = 310.699MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 310.699MB
Generate output files:
    CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 310.699MB
Total Time and Memory Usage CPU time = 0h 3m 23s, Elapsed time = 0h 3m 25s, Peak memory usage = 310.699MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 44
I/O Buf 44
    IBUF 6
    OBUF 15
    IOBUF 23
Register 5672
    DFF 83
    DFFE 74
    DFFR 18
    DFFP 34
    DFFPE 158
    DFFC 258
    DFFCE 5038
    DFFNPE 7
    DL 1
    DLN 1
LUT 25354
    LUT2 1902
    LUT3 7602
    LUT4 15850
ALU 1945
    ALU 1945
SSRAM 20
    RAM16S4 4
    RAM16SDP4 16
INV 51
    INV 51
DSP
    MULT36X36 1
BSRAM 65
    SP 32
    SDPB 32
    pROM 1

Resource Utilization Summary

Resource Usage Utilization
Logic 27470(25405 LUT, 1945 ALU, 20 RAM16) / 54720 51%
Register 5672 / 41997 14%
  --Register as Latch 2 / 41997 <1%
  --Register as FF 5670 / 41997 14%
BSRAM 65 / 140 47%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
HCLK Base 10.000 100.0 0.000 5.000 HCLK_ibuf/I
JTAG_9 Base 10.000 100.0 0.000 5.000 JTAG_9_ibuf/I
u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/TCKn_6 Base 10.000 100.0 0.000 5.000 u_M3_inst/uCORTEXM3INTEGRATION/uDAPSWJDP/uDAPJtagDpProtocol/TCKn_s2/O
u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/master_gclk_0/n4_6 Base 10.000 100.0 0.000 5.000 u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/master_gclk_0/n4_s2/O
u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_17 Base 10.000 100.0 0.000 5.000 u_GowinCM3AhbExtWrapper/u_GowinCM3AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s7/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.0(MHz) 46.3(MHz) 30 TOP
2 JTAG_9 100.0(MHz) 102.4(MHz) 14 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -11.586
Data Arrival Time 22.413
Data Required Time 10.828
From u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0
To u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_0_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 5449 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/CLK
1.095 0.232 tC2Q RF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/Q
1.332 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/I1
1.887 0.555 tINS FF 85 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/F
2.124 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/I2
2.577 0.453 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/F
2.814 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/I1
3.369 0.555 tINS FF 4 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/F
3.606 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/I3
3.977 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/F
4.214 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/I1
4.769 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/F
5.006 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/I1
5.561 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/F
5.798 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/I2
6.251 0.453 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/F
6.488 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/I0
7.005 0.517 tINS FF 8 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/F
7.242 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/I0
7.759 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/F
7.996 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/I0
8.513 0.517 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/F
8.750 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/I2
9.203 0.453 tINS FF 3 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/F
9.440 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/I1
10.010 0.570 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT
10.010 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN
10.045 0.035 tINS RF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT
10.045 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN
10.080 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT
10.080 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN
10.115 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT
10.115 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN
10.150 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT
10.150 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN
10.186 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT
10.186 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN
10.221 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT
10.221 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN
10.256 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT
10.256 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN
10.291 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT
10.291 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN
10.326 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT
10.326 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN
10.362 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT
10.362 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN
10.397 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT
10.397 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN
10.432 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT
10.432 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN
10.467 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT
10.467 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN
10.502 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT
10.502 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN
10.538 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT
10.538 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN
10.573 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT
10.573 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN
10.608 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT
10.608 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN
10.643 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT
10.643 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN
10.678 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT
10.678 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN
11.148 0.470 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/SUM
11.385 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s0/I0
11.934 0.549 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s0/COUT
11.934 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/CIN
12.404 0.470 tINS RF 9 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/SUM
12.641 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s17/I0
13.158 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s17/F
13.395 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s8/I3
13.766 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s8/F
14.003 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s5/I0
14.520 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s5/F
14.757 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s3/I0
15.274 0.517 tINS FF 14 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s3/F
15.511 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s26/I0
16.028 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s26/F
16.265 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s14/I0
16.782 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s14/F
17.019 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s5/I1
17.574 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s5/F
17.811 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s0/I1
18.366 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s0/F
18.603 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/I0
19.120 0.517 tINS FF 56 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/F
19.357 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s123/I1
19.912 0.555 tINS FF 11 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s123/F
20.149 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s113/I1
20.704 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s113/F
20.941 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s151/I1
21.496 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s151/F
21.733 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s148/I1
21.836 0.103 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s148/O
22.073 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s102/I0
22.176 0.103 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_0_s102/O
22.413 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 5449 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_0_s0/CLK
10.828 -0.035 tSu 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 30
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 14.683, 68.131%; route: 6.636, 30.792%; tC2Q: 0.232, 1.077%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack -11.586
Data Arrival Time 22.413
Data Required Time 10.828
From u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0
To u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_1_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 5449 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/CLK
1.095 0.232 tC2Q RF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/Q
1.332 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/I1
1.887 0.555 tINS FF 85 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/F
2.124 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/I2
2.577 0.453 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/F
2.814 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/I1
3.369 0.555 tINS FF 4 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/F
3.606 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/I3
3.977 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/F
4.214 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/I1
4.769 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/F
5.006 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/I1
5.561 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/F
5.798 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/I2
6.251 0.453 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/F
6.488 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/I0
7.005 0.517 tINS FF 8 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/F
7.242 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/I0
7.759 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/F
7.996 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/I0
8.513 0.517 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/F
8.750 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/I2
9.203 0.453 tINS FF 3 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/F
9.440 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/I1
10.010 0.570 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT
10.010 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN
10.045 0.035 tINS RF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT
10.045 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN
10.080 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT
10.080 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN
10.115 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT
10.115 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN
10.150 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT
10.150 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN
10.186 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT
10.186 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN
10.221 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT
10.221 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN
10.256 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT
10.256 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN
10.291 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT
10.291 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN
10.326 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT
10.326 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN
10.362 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT
10.362 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN
10.397 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT
10.397 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN
10.432 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT
10.432 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN
10.467 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT
10.467 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN
10.502 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT
10.502 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN
10.538 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT
10.538 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN
10.573 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT
10.573 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN
10.608 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT
10.608 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN
10.643 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT
10.643 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN
10.678 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT
10.678 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN
11.148 0.470 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/SUM
11.385 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s0/I0
11.934 0.549 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s0/COUT
11.934 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/CIN
12.404 0.470 tINS RF 9 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/SUM
12.641 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s17/I0
13.158 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s17/F
13.395 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s8/I3
13.766 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s8/F
14.003 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s5/I0
14.520 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s5/F
14.757 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s3/I0
15.274 0.517 tINS FF 14 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s3/F
15.511 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s26/I0
16.028 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s26/F
16.265 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s14/I0
16.782 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s14/F
17.019 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s5/I1
17.574 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s5/F
17.811 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s0/I1
18.366 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s0/F
18.603 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/I0
19.120 0.517 tINS FF 56 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/F
19.357 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s132/I1
19.912 0.555 tINS FF 7 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s132/F
20.149 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s120/I1
20.704 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s120/F
20.941 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s194/I1
21.496 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s194/F
21.733 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s192/I0
21.836 0.103 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s192/O
22.073 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s108/I0
22.176 0.103 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_1_s108/O
22.413 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 5449 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_1_s0/CLK
10.828 -0.035 tSu 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 30
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 14.683, 68.131%; route: 6.636, 30.792%; tC2Q: 0.232, 1.077%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack -11.586
Data Arrival Time 22.413
Data Required Time 10.828
From u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0
To u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_3_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 5449 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/CLK
1.095 0.232 tC2Q RF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/Q
1.332 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/I1
1.887 0.555 tINS FF 85 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/F
2.124 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/I2
2.577 0.453 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/F
2.814 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/I1
3.369 0.555 tINS FF 4 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/F
3.606 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/I3
3.977 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/F
4.214 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/I1
4.769 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/F
5.006 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/I1
5.561 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/F
5.798 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/I2
6.251 0.453 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/F
6.488 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/I0
7.005 0.517 tINS FF 8 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/F
7.242 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/I0
7.759 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/F
7.996 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/I0
8.513 0.517 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/F
8.750 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/I2
9.203 0.453 tINS FF 3 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/F
9.440 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/I1
10.010 0.570 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT
10.010 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN
10.045 0.035 tINS RF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT
10.045 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN
10.080 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT
10.080 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN
10.115 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT
10.115 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN
10.150 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT
10.150 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN
10.186 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT
10.186 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN
10.221 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT
10.221 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN
10.256 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT
10.256 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN
10.291 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT
10.291 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN
10.326 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT
10.326 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN
10.362 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT
10.362 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN
10.397 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT
10.397 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN
10.432 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT
10.432 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN
10.467 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT
10.467 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN
10.502 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT
10.502 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN
10.538 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT
10.538 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN
10.573 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT
10.573 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN
10.608 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT
10.608 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN
10.643 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT
10.643 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN
10.678 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT
10.678 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN
11.148 0.470 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/SUM
11.385 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s0/I0
11.934 0.549 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s0/COUT
11.934 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/CIN
12.404 0.470 tINS RF 9 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/SUM
12.641 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s17/I0
13.158 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s17/F
13.395 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s8/I3
13.766 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s8/F
14.003 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s5/I0
14.520 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s5/F
14.757 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s3/I0
15.274 0.517 tINS FF 14 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s3/F
15.511 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s26/I0
16.028 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s26/F
16.265 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s14/I0
16.782 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s14/F
17.019 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s5/I1
17.574 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s5/F
17.811 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s0/I1
18.366 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s0/F
18.603 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/I0
19.120 0.517 tINS FF 56 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/F
19.357 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s125/I1
19.912 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s125/F
20.149 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s113/I1
20.704 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s113/F
20.941 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s166/I1
21.496 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s166/F
21.733 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s163/I1
21.836 0.103 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s163/O
22.073 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s102/I0
22.176 0.103 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_3_s102/O
22.413 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 5449 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_3_s0/CLK
10.828 -0.035 tSu 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 30
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 14.683, 68.131%; route: 6.636, 30.792%; tC2Q: 0.232, 1.077%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack -11.578
Data Arrival Time 22.405
Data Required Time 10.828
From u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0
To u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_31_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 5449 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/CLK
1.095 0.232 tC2Q RF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/Q
1.332 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/I1
1.887 0.555 tINS FF 85 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/F
2.124 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/I2
2.577 0.453 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/F
2.814 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/I1
3.369 0.555 tINS FF 4 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/F
3.606 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/I3
3.977 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/F
4.214 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/I1
4.769 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/F
5.006 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/I1
5.561 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/F
5.798 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/I2
6.251 0.453 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/F
6.488 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/I0
7.005 0.517 tINS FF 8 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/F
7.242 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/I0
7.759 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/F
7.996 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/I0
8.513 0.517 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/F
8.750 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/I2
9.203 0.453 tINS FF 3 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/F
9.440 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/I1
10.010 0.570 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT
10.010 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN
10.045 0.035 tINS RF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT
10.045 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN
10.080 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT
10.080 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN
10.115 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT
10.115 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN
10.150 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT
10.150 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN
10.186 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT
10.186 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN
10.221 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT
10.221 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN
10.256 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT
10.256 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN
10.291 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT
10.291 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN
10.326 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT
10.326 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN
10.362 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT
10.362 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN
10.397 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT
10.397 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN
10.432 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT
10.432 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN
10.467 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT
10.467 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN
10.502 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT
10.502 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN
10.538 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT
10.538 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN
10.573 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT
10.573 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN
10.608 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT
10.608 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN
10.643 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT
10.643 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN
10.678 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT
10.678 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN
10.714 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/COUT
10.714 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/CIN
11.184 0.470 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s/SUM
11.421 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/I0
11.970 0.549 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/COUT
11.970 0.000 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_32_s0/CIN
12.440 0.470 tINS RF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_32_s0/SUM
12.677 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_cin_ex_s1/I3
13.048 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_cin_ex_s1/F
13.285 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_0_s0/I1
13.855 0.570 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_0_s0/COUT
13.855 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_1_s0/CIN
13.890 0.035 tINS RF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_1_s0/COUT
13.890 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_2_s0/CIN
13.925 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_2_s0/COUT
13.925 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_3_s0/CIN
13.960 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_3_s0/COUT
13.960 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_4_s0/CIN
13.995 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_4_s0/COUT
13.995 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_5_s0/CIN
14.031 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_5_s0/COUT
14.031 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_6_s0/CIN
14.066 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_6_s0/COUT
14.066 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_7_s0/CIN
14.101 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_7_s0/COUT
14.101 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_8_s0/CIN
14.136 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_8_s0/COUT
14.136 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_9_s0/CIN
14.171 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_9_s0/COUT
14.171 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_10_s0/CIN
14.641 0.470 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/top_adder_res_ex_10_s0/SUM
14.878 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s40/I1
15.433 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s40/F
15.670 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s37/I2
16.123 0.453 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s37/F
16.360 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s29/I3
16.731 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s29/F
16.968 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s15/I3
17.339 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s15/F
17.576 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s6/I3
17.947 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s6/F
18.184 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s2/I2
18.637 0.453 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s2/F
18.874 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s0/I2
19.327 0.453 tINS FF 3 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s0/F
19.564 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s/I2
20.017 0.453 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_exec/rf_wr_d_data_erly_ex_Z_26_s/F
20.254 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_26_s/I0
20.803 0.549 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_26_s/COUT
20.803 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_27_s/CIN
20.839 0.035 tINS RF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_27_s/COUT
20.839 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_28_s/CIN
20.874 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_28_s/COUT
20.874 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_29_s/CIN
20.909 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_29_s/COUT
20.909 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_30_s/CIN
20.944 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_30_s/COUT
20.944 0.000 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_31_s/CIN
21.414 0.470 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/br_adder_res_ex_31_s/SUM
21.651 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_31_s0/I0
22.168 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/nxt_rf_pc_fwd_ex_31_s0/F
22.405 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_31_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 5449 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_31_s0/CLK
10.828 -0.035 tSu 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_regbank/rf_pc_fwd_ex_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 33
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 15.149, 70.319%; route: 6.162, 28.604%; tC2Q: 0.232, 1.077%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack -11.548
Data Arrival Time 22.375
Data Required Time 10.828
From u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0
To u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_2_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.683 0.683 tINS RR 5449 HCLK_ibuf/O
0.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/CLK
1.095 0.232 tC2Q RF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_ctl/shift_in2_fast_ex_4_s0/Q
1.332 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/I1
1.887 0.555 tINS FF 85 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_15_s8/F
2.124 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/I2
2.577 0.453 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_17_s13/F
2.814 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/I1
3.369 0.555 tINS FF 4 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_0_s29/F
3.606 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/I3
3.977 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s18/F
4.214 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/I1
4.769 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_9_s8/F
5.006 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/I1
5.561 0.555 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s5/F
5.798 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/I2
6.251 0.453 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s3/F
6.488 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/I0
7.005 0.517 tINS FF 8 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/nxt_mcyc_temp_upp_ex_10_s1/F
7.242 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/I0
7.759 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s2/F
7.996 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/I0
8.513 0.517 tINS FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s1/F
8.750 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/I2
9.203 0.453 tINS FF 3 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_in2_ex_10_s11/F
9.440 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/I1
10.010 0.570 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_10_s/COUT
10.010 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/CIN
10.045 0.035 tINS RF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_11_s/COUT
10.045 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/CIN
10.080 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_12_s/COUT
10.080 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/CIN
10.115 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_13_s/COUT
10.115 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/CIN
10.150 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_14_s/COUT
10.150 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/CIN
10.186 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_15_s/COUT
10.186 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/CIN
10.221 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_16_s/COUT
10.221 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/CIN
10.256 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_17_s/COUT
10.256 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/CIN
10.291 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_18_s/COUT
10.291 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/CIN
10.326 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_19_s/COUT
10.326 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/CIN
10.362 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_20_s/COUT
10.362 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/CIN
10.397 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_21_s/COUT
10.397 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/CIN
10.432 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_22_s/COUT
10.432 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/CIN
10.467 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_23_s/COUT
10.467 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/CIN
10.502 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_24_s/COUT
10.502 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/CIN
10.538 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_25_s/COUT
10.538 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/CIN
10.573 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_26_s/COUT
10.573 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/CIN
10.608 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_27_s/COUT
10.608 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/CIN
10.643 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_28_s/COUT
10.643 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/CIN
10.678 0.035 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_29_s/COUT
10.678 0.000 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/CIN
11.148 0.470 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s/SUM
11.385 0.237 tNET FF 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s0/I0
11.934 0.549 tINS FR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_30_s0/COUT
11.934 0.000 tNET RR 2 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/CIN
12.404 0.470 tINS RF 9 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_alu/u_cm3_dpu_alu_dp/adder_res_ex_31_s0/SUM
12.641 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s17/I0
13.158 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s17/F
13.395 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s8/I3
13.766 0.371 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s8/F
14.003 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s5/I0
14.520 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s5/F
14.757 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s3/I0
15.274 0.517 tINS FF 14 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/n338_s3/F
15.511 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s26/I0
16.028 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s26/F
16.265 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s14/I0
16.782 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s14/F
17.019 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s5/I1
17.574 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s5/F
17.811 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s0/I1
18.366 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s0/F
18.603 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/I0
19.120 0.517 tINS FF 56 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_status/instr_ccpass_de_Z_s/F
19.357 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s124/I1
19.912 0.555 tINS FF 10 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s124/F
20.149 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s106/I0
20.666 0.517 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s106/F
20.903 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s186/I1
21.458 0.555 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s186/F
21.695 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s184/I0
21.798 0.103 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s184/O
22.035 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s98/I0
22.138 0.103 tINS FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/nxt_state_2_s98/O
22.375 0.237 tNET FF 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.682 0.683 tINS RR 5449 HCLK_ibuf/O
10.863 0.180 tNET RR 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_2_s0/CLK
10.828 -0.035 tSu 1 u_M3_inst/uCORTEXM3INTEGRATION/uCORTEXM3/u_cm3_dpu/u_cm3_dpu_lsu/u_cm3_dpu_lsu_ctl/state_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 30
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 14.645, 68.075%; route: 6.636, 30.847%; tC2Q: 0.232, 1.078%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%