Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW1NSR-LV4CQN48GC7/I6
Device GW1NSR-4C
Created Time Mon Aug 21 16:22:05 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.369s, Peak memory usage = 40.000MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 40.000MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 40.000MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 40.000MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 40.000MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 40.000MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 40.000MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 40.000MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 40.000MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 40.000MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 40.000MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 40.000MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.155s, Peak memory usage = 52.398MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 52.398MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 52.398MB
Total Time and Memory Usage CPU time = 0h 0m 0.451s, Elapsed time = 0h 0m 0.654s, Peak memory usage = 52.398MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 20
I/O Buf 20
    IBUF 3
    OBUF 1
    IOBUF 16
Register 33
    DFFPE 1
    DFFC 19
    DFFCE 13
LUT 22
    LUT2 1
    LUT3 5
    LUT4 16
INV 22
    INV 22
BSRAM 8
    SDPB 8
User Flash 1
    FLASH256K 1
EMCU 1

Resource Utilization Summary

Resource Usage Utilization
Logic 44(44 LUT, 0 ALU) / 4608 <1%
Register 33 / 3570 <1%
  --Register as Latch 0 / 3570 0%
  --Register as FF 33 / 3570 <1%
BSRAM 8 / 10 80%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sys_clk Base 20.000 50.0 0.000 10.000 sys_clk_ibuf/I
Gowin_EMPU_inst/u_flash_wrap/clk_inv_6 Base 20.000 50.0 0.000 10.000 Gowin_EMPU_inst/u_flash_wrap/clk_inv_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk 50.0(MHz) 300.1(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 16.116
Data Arrival Time 3.827
Data Required Time 19.943
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s1
Launch Clk sys_clk[R]
Latch Clk Gowin_EMPU_inst/u_flash_wrap/clk_inv_6[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 37 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n79_s2/I1
2.506 0.814 tINS FF 17 Gowin_EMPU_inst/u_flash_wrap/n79_s2/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n141_s0/I2
3.471 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n141_s0/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_EMPU_inst/u_flash_wrap/clk_inv_6
20.000 0.000 tCL RR 13 Gowin_EMPU_inst/u_flash_wrap/clk_inv_s2/O
20.269 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s1/CLK
20.239 -0.030 tUnc Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s1
19.943 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s1
Path Statistics:
Clock Skew: -0.728
Setup Relationship: 20.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 1.423, 50.297%; route: 1.067, 37.703%; tC2Q: 0.340, 12.000%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 2

Path Summary:
Slack 16.116
Data Arrival Time 3.827
Data Required Time 19.943
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s1
Launch Clk sys_clk[R]
Latch Clk Gowin_EMPU_inst/u_flash_wrap/clk_inv_6[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 37 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n79_s2/I1
2.506 0.814 tINS FF 17 Gowin_EMPU_inst/u_flash_wrap/n79_s2/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n140_s0/I2
3.471 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n140_s0/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_EMPU_inst/u_flash_wrap/clk_inv_6
20.000 0.000 tCL RR 13 Gowin_EMPU_inst/u_flash_wrap/clk_inv_s2/O
20.269 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s1/CLK
20.239 -0.030 tUnc Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s1
19.943 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s1
Path Statistics:
Clock Skew: -0.728
Setup Relationship: 20.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 1.423, 50.297%; route: 1.067, 37.703%; tC2Q: 0.340, 12.000%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack 16.116
Data Arrival Time 3.827
Data Required Time 19.943
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_2_s1
Launch Clk sys_clk[R]
Latch Clk Gowin_EMPU_inst/u_flash_wrap/clk_inv_6[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 37 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n79_s2/I1
2.506 0.814 tINS FF 17 Gowin_EMPU_inst/u_flash_wrap/n79_s2/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n139_s0/I2
3.471 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n139_s0/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_EMPU_inst/u_flash_wrap/clk_inv_6
20.000 0.000 tCL RR 13 Gowin_EMPU_inst/u_flash_wrap/clk_inv_s2/O
20.269 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_2_s1/CLK
20.239 -0.030 tUnc Gowin_EMPU_inst/u_flash_wrap/rom_addr_2_s1
19.943 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_2_s1
Path Statistics:
Clock Skew: -0.728
Setup Relationship: 20.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 1.423, 50.297%; route: 1.067, 37.703%; tC2Q: 0.340, 12.000%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack 16.116
Data Arrival Time 3.827
Data Required Time 19.943
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_3_s1
Launch Clk sys_clk[R]
Latch Clk Gowin_EMPU_inst/u_flash_wrap/clk_inv_6[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 37 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n79_s2/I1
2.506 0.814 tINS FF 17 Gowin_EMPU_inst/u_flash_wrap/n79_s2/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n138_s0/I2
3.471 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n138_s0/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_EMPU_inst/u_flash_wrap/clk_inv_6
20.000 0.000 tCL RR 13 Gowin_EMPU_inst/u_flash_wrap/clk_inv_s2/O
20.269 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_3_s1/CLK
20.239 -0.030 tUnc Gowin_EMPU_inst/u_flash_wrap/rom_addr_3_s1
19.943 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_3_s1
Path Statistics:
Clock Skew: -0.728
Setup Relationship: 20.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 1.423, 50.297%; route: 1.067, 37.703%; tC2Q: 0.340, 12.000%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 5

Path Summary:
Slack 16.116
Data Arrival Time 3.827
Data Required Time 19.943
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_4_s1
Launch Clk sys_clk[R]
Latch Clk Gowin_EMPU_inst/u_flash_wrap/clk_inv_6[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 37 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n79_s2/I1
2.506 0.814 tINS FF 17 Gowin_EMPU_inst/u_flash_wrap/n79_s2/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n137_s0/I2
3.471 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n137_s0/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_EMPU_inst/u_flash_wrap/clk_inv_6
20.000 0.000 tCL RR 13 Gowin_EMPU_inst/u_flash_wrap/clk_inv_s2/O
20.269 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_4_s1/CLK
20.239 -0.030 tUnc Gowin_EMPU_inst/u_flash_wrap/rom_addr_4_s1
19.943 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_4_s1
Path Statistics:
Clock Skew: -0.728
Setup Relationship: 20.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 1.423, 50.297%; route: 1.067, 37.703%; tC2Q: 0.340, 12.000%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%