`ifndef DEFINE_V
`define DEFINE_V

`define GW_FPGA
`define MODULE_NAME RiscV_AE250_Top
`define IP_name "AE250"
`define AE250_DMA_EXTREQ_NUM 6'd5
`define AE250_DMA_EXTREQ_SUPPORT "yes"
`define AE250_INOUT_SUPPORT 
`define AE250_PLIC_SUPPORT "no"
`define AE250_PLIC_SW_SUPPORT "no"
`define AE250_PLMT_SUPPORT "no"
`define AE250_SMU_EXT_WAKEUP_LEVEL "high"
`define AE250_SMU_MDP_PWR_OFF_LEVEL "high"
`define AE250_SMU_RESET_VECTOR_DEFAULT 32'h00000000
`define AE250_SMU_SCRATCH_BIT 32
`define AE250_SMU_SCRATCH_DEFAULT 0
`define AE250_SMU_SCRATCH_SUPPORT "yes"
`define AE250_SMU_USERDR0_BIT 32
`define AE250_SMU_USERDR0_DEFAULT 0
`define AE250_SMU_USERDR0_SUPPORT "yes"
`define AE250_SMU_USERDR1_BIT 32
`define AE250_SMU_USERDR1_DEFAULT 0
`define AE250_SMU_USERDR1_SUPPORT "yes"
`define AE250_UART1_SUPPORT 
`define AHB_LOW_LATENCY "no"
`define ASYNC_INT 1024'h0
`define ATCAPBBRG100_ADDR_DECODE_WIDTH 27
`define ATCAPBBRG100_FLOP_OUT 0
`define ATCAPBBRG100_SLV0_OFFSET 25'h0000000
`define ATCAPBBRG100_SLV0_SIZE 4'h1
`define ATCAPBBRG100_SLV10_OFFSET 27'h0f00000
`define ATCAPBBRG100_SLV10_SIZE 4'h1
`define ATCAPBBRG100_SLV11_OFFSET 27'h1a00000
`define ATCAPBBRG100_SLV11_SIZE 4'h1
`define ATCAPBBRG100_SLV12_OFFSET 27'h1b00000
`define ATCAPBBRG100_SLV12_SIZE 4'h1
`define ATCAPBBRG100_SLV13_OFFSET 27'h1100000
`define ATCAPBBRG100_SLV13_SIZE 4'h1
`define ATCAPBBRG100_SLV14_OFFSET 27'h1b00000
`define ATCAPBBRG100_SLV14_SIZE 4'h1
`define ATCAPBBRG100_SLV15_OFFSET 27'h1300000
`define ATCAPBBRG100_SLV15_SIZE 4'h1
`define ATCAPBBRG100_SLV16_OFFSET 27'h1400000
`define ATCAPBBRG100_SLV16_SIZE 4'h1
`define ATCAPBBRG100_SLV17_OFFSET 27'h1500000
`define ATCAPBBRG100_SLV17_SIZE 4'h1
`define ATCAPBBRG100_SLV18_OFFSET 27'h1600000
`define ATCAPBBRG100_SLV18_SIZE 4'h1
`define ATCAPBBRG100_SLV19_OFFSET 27'h4c00000
`define ATCAPBBRG100_SLV19_SIZE 4'h1
`define ATCAPBBRG100_SLV1_OFFSET 27'h0100000
`define ATCAPBBRG100_SLV1_SIZE 4'h3
`define ATCAPBBRG100_SLV20_OFFSET 27'h5000000
`define ATCAPBBRG100_SLV20_SIZE 4'h1
`define ATCAPBBRG100_SLV21_OFFSET 27'h5400000
`define ATCAPBBRG100_SLV21_SIZE 4'h1
`define ATCAPBBRG100_SLV22_OFFSET 27'h5800000
`define ATCAPBBRG100_SLV22_SIZE 4'h1
`define ATCAPBBRG100_SLV23_OFFSET 27'h5c00000
`define ATCAPBBRG100_SLV23_SIZE 4'h1
`define ATCAPBBRG100_SLV24_OFFSET 27'h6000000
`define ATCAPBBRG100_SLV24_SIZE 4'h1
`define ATCAPBBRG100_SLV25_OFFSET 27'h6400000
`define ATCAPBBRG100_SLV25_SIZE 4'h1
`define ATCAPBBRG100_SLV26_OFFSET 27'h6800000
`define ATCAPBBRG100_SLV26_SIZE 4'h1
`define ATCAPBBRG100_SLV27_OFFSET 27'h6c00000
`define ATCAPBBRG100_SLV27_SIZE 4'h1
`define ATCAPBBRG100_SLV28_OFFSET 27'h7000000
`define ATCAPBBRG100_SLV28_SIZE 4'h1
`define ATCAPBBRG100_SLV29_OFFSET 27'h7400000
`define ATCAPBBRG100_SLV29_SIZE 4'h1
`define ATCAPBBRG100_SLV2_OFFSET 27'h0200000
`define ATCAPBBRG100_SLV2_SIZE 4'h1
`define ATCAPBBRG100_SLV30_OFFSET 27'h7800000
`define ATCAPBBRG100_SLV30_SIZE 4'h1
`define ATCAPBBRG100_SLV31_OFFSET 27'h7c00000
`define ATCAPBBRG100_SLV31_SIZE 4'h1
`define ATCAPBBRG100_SLV3_OFFSET 27'h0300000
`define ATCAPBBRG100_SLV3_SIZE 4'h1
`define ATCAPBBRG100_SLV4_OFFSET 27'h0400000
`define ATCAPBBRG100_SLV4_SIZE 4'h1
`define ATCAPBBRG100_SLV5_OFFSET 27'h0500000
`define ATCAPBBRG100_SLV5_SIZE 4'h1
`define ATCAPBBRG100_SLV6_OFFSET 27'h0600000
`define ATCAPBBRG100_SLV6_SIZE 4'h1
`define ATCAPBBRG100_SLV7_OFFSET 27'h0700000
`define ATCAPBBRG100_SLV7_SIZE 4'h1
`define ATCAPBBRG100_SLV8_OFFSET 27'h0a00000
`define ATCAPBBRG100_SLV8_SIZE 4'h1
`define ATCAPBBRG100_SLV9_OFFSET 27'h0b00000
`define ATCAPBBRG100_SLV9_SIZE 4'h1
`define ATCBMC200_AHB_SLV0_BASE 32'he0000000
`define ATCBMC200_AHB_SLV0_SIZE 4'h1
`define ATCBMC200_AHB_SLV10_BASE 32'ha0000000
`define ATCBMC200_AHB_SLV10_SIZE 4'h1
`define ATCBMC200_AHB_SLV11_BASE 32'h00e00000
`define ATCBMC200_AHB_SLV11_SIZE 4'h1
`define ATCBMC200_AHB_SLV12_BASE 32'h00f00000
`define ATCBMC200_AHB_SLV12_SIZE 4'h1
`define ATCBMC200_AHB_SLV13_BASE 32'h01000000
`define ATCBMC200_AHB_SLV13_SIZE 4'h1
`define ATCBMC200_AHB_SLV14_BASE 32'h01100000
`define ATCBMC200_AHB_SLV14_SIZE 4'h1
`define ATCBMC200_AHB_SLV15_BASE 32'h01200000
`define ATCBMC200_AHB_SLV15_SIZE 4'h1
`define ATCBMC200_AHB_SLV1_BASE 32'hf0000000
`define ATCBMC200_AHB_SLV1_SIZE 6'h6
`define ATCBMC200_AHB_SLV2_BASE 32'he0e00000
`define ATCBMC200_AHB_SLV2_SIZE 4'h1
`define ATCBMC200_AHB_SLV3_BASE 32'h00400000
`define ATCBMC200_AHB_SLV3_SIZE 4'h1
`define ATCBMC200_AHB_SLV4_BASE 32'h00700000
`define ATCBMC200_AHB_SLV4_SIZE 4'h1
`define ATCBMC200_AHB_SLV5_BASE 32'h00800000
`define ATCBMC200_AHB_SLV5_SIZE 4'h1
`define ATCBMC200_AHB_SLV6_BASE 32'h00900000
`define ATCBMC200_AHB_SLV6_SIZE 4'h1
`define ATCBMC200_AHB_SLV7_BASE 32'h00a00000
`define ATCBMC200_AHB_SLV7_SIZE 4'h1
`define ATCBMC200_AHB_SLV8_BASE 32'h00b00000
`define ATCBMC200_AHB_SLV8_SIZE 4'h1
`define ATCBMC200_AHB_SLV9_BASE 32'h00c00000
`define ATCBMC200_AHB_SLV9_SIZE 4'h1
`define ATCDMAC100_CHAIN_TRANSFER_SUPPORT "yes"
`define ATCDMAC100_CH_NUM 8
`define ATCDMAC100_FIFO_DEPTH 6'd8
`define ATCDMAC100_REQ_SYNC_SUPPORT "yes"
`define ATCGPIO100_DEBOUNCE_SUPPORT "yes"
`define ATCGPIO100_GPIO_NUM 32
`define ATCGPIO100_INTR_SUPPORT "yes"
`define ATCGPIO100_PULL_SUPPORT "yes"
`define ATCIIC100_1_FIFO_DEPTH 4
`define ATCIIC100_2_FIFO_DEPTH 4
`define ATCIIC100_3_FIFO_DEPTH 4
`define ATCIIC100_4_FIFO_DEPTH 4
`define ATCPIT100_1_CH1_SUPPORT 
`define ATCPIT100_1_CH2_SUPPORT 
`define ATCPIT100_1_CH3_SUPPORT 
`define ATCPIT100_1_NUM_CHANNEL 3'h4
`define ATCPIT100_2_CH1_SUPPORT 
`define ATCPIT100_2_CH2_SUPPORT 
`define ATCPIT100_2_CH3_SUPPORT 
`define ATCPIT100_2_NUM_CHANNEL 3'h4
`define ATCRTC100_DAY_WIDTH 5
`define ATCRTC100_HALF_SECOND_SUPPORT "yes"
`define ATCSPI200_1_CS2CLK_DEFAULT 3'h0
`define ATCSPI200_1_CSHT_DEFAULT 3'h2
`define ATCSPI200_1_DIRECT_IO_SUPPORT "no"
`define ATCSPI200_1_DUALSPI_SUPPORT "no"
`define ATCSPI200_1_MEM_RDCMD_DEFAULT 4'd0
`define ATCSPI200_1_RXFIFO_DEPTH 4
`define ATCSPI200_1_SCLKDIV_DEFAULT 8'h1
`define ATCSPI200_1_SLAVE_SUPPORT "no"
`define ATCSPI200_1_TXFIFO_DEPTH 4
`define ATCSPI200_2_CS2CLK_DEFAULT 3'h0
`define ATCSPI200_2_CSHT_DEFAULT 3'h2
`define ATCSPI200_2_DIRECT_IO_SUPPORT "no"
`define ATCSPI200_2_DUALSPI_SUPPORT "no"
`define ATCSPI200_2_MEM_RDCMD_DEFAULT 4'd0
`define ATCSPI200_2_RXFIFO_DEPTH 4
`define ATCSPI200_2_SCLKDIV_DEFAULT 8'h1
`define ATCSPI200_2_SLAVE_SUPPORT "no"
`define ATCSPI200_2_TXFIFO_DEPTH 4
`define ATCSPI200_3_CS2CLK_DEFAULT 3'h0
`define ATCSPI200_3_CSHT_DEFAULT 3'h2
`define ATCSPI200_3_DIRECT_IO_SUPPORT "no"
`define ATCSPI200_3_DUALSPI_SUPPORT "no"
`define ATCSPI200_3_MEM_RDCMD_DEFAULT 4'd0
`define ATCSPI200_3_RXFIFO_DEPTH 4
`define ATCSPI200_3_SCLKDIV_DEFAULT 8'h1
`define ATCSPI200_3_SLAVE_SUPPORT "no"
`define ATCSPI200_3_TXFIFO_DEPTH 4
`define ATCSPI200_4_CS2CLK_DEFAULT 3'h0
`define ATCSPI200_4_CSHT_DEFAULT 3'h2
`define ATCSPI200_4_DIRECT_IO_SUPPORT "no"
`define ATCSPI200_4_DUALSPI_SUPPORT "no"
`define ATCSPI200_4_MEM_RDCMD_DEFAULT 4'd0
`define ATCSPI200_4_RXFIFO_DEPTH 4
`define ATCSPI200_4_SCLKDIV_DEFAULT 8'h1
`define ATCSPI200_4_SLAVE_SUPPORT "no"
`define ATCSPI200_4_TXFIFO_DEPTH 4
`define ATCUART100_1_FIFO_DEPTH 16
`define ATCUART100_2_FIFO_DEPTH 16
`define ATCUART100_3_FIFO_DEPTH 16
`define ATCUART100_4_FIFO_DEPTH 16
`define ATCWDT200_32BIT_TIMER 0
`define ATCWDT200_RESTART_NUM 16'hcafe
`define ATCWDT200_WP_NUM 16'h5aa5
`define Amem "E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250/Amem.dat"
`define BRANCH_PREDICTION "none"
`define Bmem "E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250/Bmem.dat"
`define CACHE_LINE_SIZE 32
`define CODENSE_SUPPORT "yes"
`define Cmem "E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250/Cmem.dat"
`define DCACHE_ECC_TYPE "none"
`define DCACHE_LRU "lru"
`define DCACHE_SIZE_KB 0
`define DCACHE_WAY 2
`define DEBUG_INTERFACE "jtag"
`define DEBUG_SUPPORT 
`define DEBUG_VEC 64'h00000000e6800000
`define DEVICE_REGION0_BASE 64'h0000000080000000
`define DEVICE_REGION0_MASK 64'hffffffff80000000
`define DEVICE_REGION1_BASE 64'hffffffffffffffff
`define DEVICE_REGION1_MASK 64'h0000000000000000
`define DEVICE_REGION2_BASE 64'hffffffffffffffff
`define DEVICE_REGION2_MASK 64'h0000000000000000
`define DEVICE_REGION3_BASE 64'hffffffffffffffff
`define DEVICE_REGION3_MASK 64'h0000000000000000
`define DEVICE_REGION4_BASE 64'hffffffffffffffff
`define DEVICE_REGION4_MASK 64'h0000000000000000
`define DEVICE_REGION5_BASE 64'hffffffffffffffff
`define DEVICE_REGION5_MASK 64'h0000000000000000
`define DEVICE_REGION6_BASE 64'hffffffffffffffff
`define DEVICE_REGION6_MASK 64'h0000000000000000
`define DEVICE_REGION7_BASE 64'hffffffffffffffff
`define DEVICE_REGION7_MASK 64'h0000000000000000
`define DLM_BASE 64'h0000000000200000
`define DLM_ECC_TYPE "none"
`define DLM_SIZE_KB 32
`define DSP_SUPPORT "no"
`define DTLB_ENTRIES 0
`define Dmem "E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250/Dmem.dat"
`define EDGE_TRIGGER 1024'h0
`define FAST_MULT_ALGO "logic"
`define FPU_TYPE "none"
`define ICACHE_ECC_TYPE "none"
`define ICACHE_LRU "lru"
`define ICACHE_SIZE_KB 0
`define ICACHE_WAY 2
`define ILM_BASE 64'h0000000000000000
`define ILM_ECC_TYPE "none"
`define ILM_SIZE_KB 32
`define INT_NUM 10'd8
`define ISA_BASE "rv32i"
`define ISA_BBZ "yes"
`define ISA_BEQC "yes"
`define ISA_BFO "yes"
`define ISA_GP "yes"
`define ISA_LEA "yes"
`define ISA_STR "yes"
`define ITLB_ENTRIES 0
`define LM_ENABLE_CTRL "no"
`define LM_INTERFACE "ram"
`define LSU_PREFETCH "no"
`define MAX_PRIORITY 8'd15
`define MMU_SCHEME "bare"
`define MULTIPLIER "radix2"
`define MULT_ACCELERATOR_TYPE "auto"
`define NON_CRITICAL_WORD_FIRST "no"
`define NUM_PRIVILEGE_LEVELS 1
`define NUM_TRIGGER 2
`define PERFORMANCE_MONITOR "no"
`define PLDM_BASE 32'he6800000
`define PLDM_MASK 32'hfff00000
`define PLIC_BASE 32'he400000
`define PLIC_MASK 32'hffc00000
`define PLIC_SW_BASE 32'he6400000
`define PLIC_SW_MASK 32'hffc00000
`define PLMT_BASE 32'he6000000
`define PLMT_MASK 32'hfffffc00
`define PMP_ENTRIES 0
`define POWERBRAKE_SUPPORT "no"
`define PROGBUF_SIZE 8
`define RVA_SUPPORT "no"
`define RVN_SUPPORT "no"
`define SLAVE_PORT_SUPPORT "no"
`define STACKSAFE_SUPPORT "no"
`define STLB_ENTRIES 0
`define STLB_SP_ENTRIES 0
`define SYSTEM_BUS_ACCESS_SUPPORT "yes"
`define TRACE_INTERFACE "none"
`define UNALIGNED_ACCESS "yes"
`define VECTOR_PLIC_SUPPORT "yes"
`define WRITETHROUGH_REGION0_BASE 64'h0000000040000000
`define WRITETHROUGH_REGION0_MASK 64'hffffffffc0000000
`define WRITETHROUGH_REGION1_BASE 64'h0fffffffffffffff
`define WRITETHROUGH_REGION1_MASK 64'h0000000000000000
`define WRITETHROUGH_REGION2_BASE 64'h0fffffffffffffff
`define WRITETHROUGH_REGION2_MASK 64'h0000000000000000
`define WRITETHROUGH_REGION3_BASE 64'h0fffffffffffffff
`define WRITETHROUGH_REGION3_MASK 64'h0000000000000000
`define WRITETHROUGH_REGION4_BASE 64'h0fffffffffffffff
`define WRITETHROUGH_REGION4_MASK 64'h0000000000000000
`define WRITETHROUGH_REGION5_BASE 64'h0fffffffffffffff
`define WRITETHROUGH_REGION5_MASK 64'h0000000000000000
`define WRITETHROUGH_REGION6_BASE 64'h0fffffffffffffff
`define WRITETHROUGH_REGION6_MASK 64'h0000000000000000
`define WRITETHROUGH_REGION7_BASE 64'h0fffffffffffffff
`define WRITETHROUGH_REGION7_MASK 64'h0000000000000000

`endif
