@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":976:19:976:23|Converting bidirection inout port X_tms to input port. Because it's a pure input port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":977:22:977:26|Converting bidirection inout port X_tdi to input port. Because it's a pure input port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":976:19:976:23|Converting bidirection inout port X_tms to input port. Because it's a pure input port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":977:22:977:26|Converting bidirection inout port X_tdi to input port. Because it's a pure input port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":978:22:978:26|Converting bidirection inout port X_tdo to output port. Because it's a pure output port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":979:22:979:27|Converting bidirection inout port X_trst to output port. Because it's a pure output port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":976:19:976:23|Converting bidirection inout port X_tms to input port. Because it's a pure input port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":977:22:977:26|Converting bidirection inout port X_tdi to input port. Because it's a pure input port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":978:22:978:26|Converting bidirection inout port X_tdo to output port. Because it's a pure output port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":979:22:979:27|Converting bidirection inout port X_trst to output port. Because it's a pure output port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":976:19:976:23|Converting bidirection inout port X_tms to input port. Because it's a pure input port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":977:22:977:26|Converting bidirection inout port X_tdi to input port. Because it's a pure input port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":978:22:978:26|Converting bidirection inout port X_tdo to output port. Because it's a pure output port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":979:22:979:27|Converting bidirection inout port X_trst to output port. Because it's a pure output port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":976:19:976:23|Converting bidirection inout port X_tms to input port. Because it's a pure input port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":977:22:977:26|Converting bidirection inout port X_tdi to input port. Because it's a pure input port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":978:22:978:26|Converting bidirection inout port X_tdo to output port. Because it's a pure output port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":979:22:979:27|Converting bidirection inout port X_trst to output port. Because it's a pure output port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":976:19:976:23|Converting bidirection inout port X_tms to input port. Because it's a pure input port
@W: BN710 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":977:22:977:26|Converting bidirection inout port X_tdi to input port. Because it's a pure input port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":978:22:978:26|Converting bidirection inout port X_tdo to output port. Because it's a pure output port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":979:22:979:27|Converting bidirection inout port X_trst to output port. Because it's a pure output port
@W: MT420 |Found inferred clock RiscV_AE250_Top|X_oschin with period 14.62ns. Please declare a user-defined clock on port X_oschin.
@W: MT420 |Found inferred clock RiscV_AE250_Top|X_tck with period 4.87ns. Please declare a user-defined clock on port X_tck.
@W: MT420 |Found inferred clock RiscV_AE250_Top|X_osclin with period 0.71ns. Please declare a user-defined clock on port X_osclin.
