<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\riscv_ae250_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>RiscV_AE250_Top|X_oschin</data>
<data>68.4 MHz</data>
<data>58.1 MHz</data>
<data>-2.580</data>
</row>
<row>
<data>RiscV_AE250_Top|X_osclin</data>
<data>1402.3 MHz</data>
<data>1191.9 MHz</data>
<data>-0.126</data>
</row>
<row>
<data>RiscV_AE250_Top|X_tck</data>
<data>205.4 MHz</data>
<data>153.1 MHz</data>
<data>-0.859</data>
</row>
<row>
<data>System</data>
<data>150.0 MHz</data>
<data>NA</data>
<data>6.890</data>
</row>
</report_table>
