#--  Synopsys, Inc.
#--  Version P-2019.09G
#--  Project file E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\run_options.txt
#--  Written on Mon Mar 30 14:07:10 2020


#project files
add_file -verilog "C:/Gowin/Gowin_V1.9.5Beta/IDE/ipcore/RiscVN25/data/AE250.v"
add_file -verilog "C:/Gowin/Gowin_V1.9.5Beta/IDE/ipcore/RiscVN25/data/ae250_chip_wrap.v"



#implementation: "rcv_1"
impl -add rcv_1 -type fpga

#
#implementation attributes

set_option -project_relative_includes 1
set_option -include_path {E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250;C:/Gowin/Gowin_V1.9.5Beta/IDE/ipcore/RiscVN25/data}

#device options
set_option -technology GOWIN-GW2A
set_option -part GW2A_18
set_option -package PBGA256
set_option -speed_grade -8
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "RiscV_AE250_Top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency auto
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# GOWIN-GW2A
set_option -maxfan 10000
set_option -rw_check_on_ram 1
set_option -disable_io_insertion 1
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fix_gated_and_generated_clocks 1
set_option -run_prop_extract 1

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rcv_1/riscv_ae250.vm"
impl -active "rcv_1"
