`

    #Build: Synplify Pro (R) P-2019.09G, Build 284R, Feb 28 2020
    #install: C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro
    #OS: Windows 8 6.2
    #Hostname: GW-SW-063

    # Mon Mar 30 14:07:10 2020

    #Implementation: rcv_1

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.09G
    Install: C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rcv_1
    Synopsys HDL Compiler, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.09G
    Install: C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rcv_1
    Synopsys Verilog Compiler, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\Gowin\Gowin_V1.9.5Beta\IDE\ipcore\RiscVN25\data\AE250.v" (library work)
    @W:CS133 : AE250.v(4537) | Ignoring property syn_keep
    @W:CS133 : AE250.v(4538) | Ignoring property syn_keep
    @W:CS133 : AE250.v(4539) | Ignoring property syn_keep
    @W:CS133 : AE250.v(6796) | Ignoring property syn_keep
    @W:CS133 : AE250.v(6797) | Ignoring property syn_keep
    @N:CG334 : AE250.v(93547) | Read directive translate_off.
    @N:CG333 : AE250.v(93549) | Read directive translate_on.
    @N:CG334 : AE250.v(93578) | Read directive translate_off.
    @N:CG333 : AE250.v(93582) | Read directive translate_on.
    @N:CG334 : AE250.v(93626) | Read directive translate_off.
    @N:CG333 : AE250.v(93637) | Read directive translate_on.
    @N:CG334 : AE250.v(93677) | Read directive translate_off.
    @N:CG333 : AE250.v(93679) | Read directive translate_on.
    @N:CG334 : AE250.v(93719) | Read directive translate_off.
    @N:CG333 : AE250.v(93721) | Read directive translate_on.
    @N:CG334 : AE250.v(93725) | Read directive translate_off.
    @N:CG333 : AE250.v(93727) | Read directive translate_on.
    @N:CG334 : AE250.v(93772) | Read directive translate_off.
    @N:CG333 : AE250.v(93784) | Read directive translate_on.
    @N:CG334 : AE250.v(93818) | Read directive translate_off.
    @N:CG333 : AE250.v(93821) | Read directive translate_on.
    @N:CG334 : AE250.v(93860) | Read directive translate_off.
    @N:CG333 : AE250.v(93862) | Read directive translate_on.
    @N:CG334 : AE250.v(93901) | Read directive translate_off.
    @N:CG333 : AE250.v(93913) | Read directive translate_on.
    @I::"C:\Gowin\Gowin_V1.9.5Beta\IDE\ipcore\RiscVN25\data\ae250_chip_wrap.v" (library work)
    @I:"C:\Gowin\Gowin_V1.9.5Beta\IDE\ipcore\RiscVN25\data\ae250_chip_wrap.v":"E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\define.v" (library work)
    @I:"C:\Gowin\Gowin_V1.9.5Beta\IDE\ipcore\RiscVN25\data\ae250_chip_wrap.v":"C:\Gowin\Gowin_V1.9.5Beta\IDE\ipcore\RiscVN25\data\static_macro_define.v" (library work)
    Verilog syntax check successful!
    Selecting top level module RiscV_AE250_Top
    Running optimization stage 1 on ae250_clkgen .......
    Running optimization stage 1 on ae250_rstgen .......
    Running optimization stage 1 on nds_sync_l2l .......
    Running optimization stage 1 on ae250_smu_apbif_Z1 .......
    Running optimization stage 1 on ae250_smu_mpd_AE250_0_0_1_3_2 .......
    Running optimization stage 1 on nds_sync_p2p_0 .......
    Running optimization stage 1 on nds_sync_p2p_data_3s_0_0 .......
    Running optimization stage 1 on ae250_smu_aopd_core_yes_32s_0s_high_high_0_1_3_2 .......
    Running optimization stage 1 on ae250_aopd_rstgen .......
    Running optimization stage 1 on ae250_smu_aopd_top_AE250_yes_32s_0s_high_high .......
    Running optimization stage 1 on ae250_smu_pd_Z2 .......
    Running optimization stage 1 on ae250_smu_Z3 .......
    Running optimization stage 1 on nds_sync_fifo_data_40s_2s_2s .......
    Running optimization stage 1 on nds_sync_fifo_data_32s_2s_2s .......
    Running optimization stage 1 on atcapbbrg100_Z4 .......
    Running optimization stage 1 on atcbmc200_mux_Z5 .......
    Running optimization stage 1 on atcbmc200_ahbslv_rf_Z6 .......
    Running optimization stage 1 on atcbmc200_addrdec_AE250_32s_31s_11s .......
    Running optimization stage 1 on atcbmc200_mst_decoder_Z8 .......
    Running optimization stage 1 on atcbmc200_mst_ctrl_Z9 .......
    Running optimization stage 1 on atcbmc200_mst_commander_Z10 .......
    Running optimization stage 1 on atcbmc200_slv_commander_AE250_32s_31s_11s_0_1_2_3_0 .......

    Only the first 100 messages of id 'CG360' are reported. To see all messages use 'report_messages -log E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\riscv_ae250_compiler.srr -id CG360' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG360} -count unlimited' in the Tcl shell.
    Running optimization stage 1 on atcbmc200_Z7 .......

    Only the first 100 messages of id 'CL318' are reported. To see all messages use 'report_messages -log E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\riscv_ae250_compiler.srr -id CL318' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL318} -count unlimited' in the Tcl shell.
    Running optimization stage 1 on atcbusdec250_Z11 .......
    Running optimization stage 1 on atcmstmux100_exec_Z12 .......
    Running optimization stage 1 on atcmstmux100_mux_Z13 .......
    Running optimization stage 1 on atcmstmux100_mst_ctrl_AE250_32s_32s_0_2_0_1_2_3 .......
    Running optimization stage 1 on atcmstmux100_Z14 .......
    Running optimization stage 1 on vc_ipipe_Z15 .......
    Running optimization stage 1 on vc_rf .......
    Running optimization stage 1 on vc_alu_Z16 .......
    Running optimization stage 1 on vc_mdu_Z17 .......
    Running optimization stage 1 on vc_csr_Z18 .......
    Running optimization stage 1 on vc_trigm_Z19 .......
    Running optimization stage 1 on vc_lsu_Z20 .......
    Running optimization stage 1 on vc_dcu_Z21 .......
    Running optimization stage 1 on vc_ifu_Z22 .......
    Running optimization stage 1 on vc_icu_Z23 .......
    Running optimization stage 1 on vc_biu_path_Z24 .......
    Running optimization stage 1 on nds_sync_fifo_afe_32s_2s_0s_0s_2s_1s .......
    Running optimization stage 1 on vc_biu_ahb_wrapper_Z25 .......
    Running optimization stage 1 on vc_biu_ahb_no_32s_32s_1s_0s_bare .......
    Running optimization stage 1 on vc_mmu_Z26 .......
    Running optimization stage 1 on vc_fastmul_recode .......
    Running optimization stage 1 on vc_fastmul_cmp112_64s .......
    Running optimization stage 1 on vc_fastmul_cmp42_64s .......
    Running optimization stage 1 on vc_fastmul_radix2_0_1_2_3_8 .......
    Running optimization stage 1 on vc_ilm_Z28 .......
    Running optimization stage 1 on vc_dlm_Z29 .......
    Running optimization stage 1 on vc_core_Z27 .......
    Opening data file E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250/Amem.dat from directory E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250
    Opening data file E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250/Bmem.dat from directory E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250
    Opening data file E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250/Cmem.dat from directory E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250
    Opening data file E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250/Dmem.dat from directory E:/W_File/RISC_V/Ref_Design/project/Ref_Design/src/riscv_ae250/temp/Riscvae250
    Running optimization stage 1 on vc_ilm_ram_Z30 .......
    Running optimization stage 1 on vc_dlm_ram_Z31 .......
    Running optimization stage 1 on nds_ram_model_1s_1s_0s_yes_1_0_2s .......
    Running optimization stage 1 on nds_ram_model_1s_1s_0s_no_1_0_2s .......
    Running optimization stage 1 on vc_icache_ram_2s_1s_1s_1s_1s .......
    Running optimization stage 1 on nds_ram_model_bwe_1s_1s_0.100000_1_yes_8s_1_0_8s_2s .......
    Running optimization stage 1 on nds_ram_model_bit_we_1s_1s_0.100000_1_yes_1_0_2s .......
    Running optimization stage 1 on nds_ram_model_bwe_1s_1s_0.100000_1_no_8s_1_0_8s_2s .......
    Running optimization stage 1 on nds_ram_model_bit_we_1s_1s_0.100000_1_no_1_0_2s .......
    Running optimization stage 1 on vc_dcache_ram_Z32 .......
    Running optimization stage 1 on nds_ram_model_38s_1s_0s_yes_1_0_2s .......

    Only the first 100 messages of id 'CL169' are reported. To see all messages use 'report_messages -log E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\riscv_ae250_compiler.srr -id CL169' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL169} -count unlimited' in the Tcl shell.
    Running optimization stage 1 on vc_btb_ram_1s_38s .......
    Running optimization stage 1 on vc_core_mem_Z33 .......
    Running optimization stage 1 on ncejdtm200_tap_Z35 .......
    Running optimization stage 1 on ncejdtm200_dmi_Z36 .......
    Running optimization stage 1 on ncejdtm200_AE250_jtag_32s_7s_2s_41s .......
    Running optimization stage 1 on ncepldm200_Z37 .......

    Only the first 100 messages of id 'CL113' are reported. To see all messages use 'report_messages -log E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\riscv_ae250_compiler.srr -id CL113' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL113} -count unlimited' in the Tcl shell.
    Running optimization stage 1 on debug_subsystem_Z38 .......

    Only the first 100 messages of id 'CG781' are reported. To see all messages use 'report_messages -log E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\riscv_ae250_compiler.srr -id CG781' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG781} -count unlimited' in the Tcl shell.
    Running optimization stage 1 on ae250_cpu_uncore_Z34 .......
    Running optimization stage 1 on nds_sync_p2p_data_4s_0_8 .......
    Running optimization stage 1 on nds_sync_p2p_data_7s_0_0 .......
    Running optimization stage 1 on atcuart100_apbif_reg_AE250_16s_33624072_4s_0 .......
    Running optimization stage 1 on nds_sync_l2l_1 .......
    Running optimization stage 1 on atcuart100_modem_AE250 .......
    Running optimization stage 1 on atcuart100_baud_AE250 .......
    Running optimization stage 1 on nds_sync_fifo_clr_8s_16s_5s .......
    Running optimization stage 1 on nds_async_buff_8s .......
    Running optimization stage 1 on atcuart100_txctrl_AE250_16s_4s .......
    Running optimization stage 1 on nds_sync_fifo_clr_11s_16s_5s .......
    Running optimization stage 1 on nds_async_buff_11s .......
    Running optimization stage 1 on atcuart100_rxctrl_AE250_16s_4s .......
    Running optimization stage 1 on atcuart100_uart_tx_Z40 .......
    Running optimization stage 1 on atcuart100_uart_rx_Z41 .......
    Running optimization stage 1 on atcuart100_AE250_16s_33624072 .......
    Running optimization stage 1 on ae250_chip_Z39 .......
    @N:CG364 : ae250_chip_wrap.v(3) | Synthesizing module RiscV_AE250_Top in library work.
    Running optimization stage 1 on RiscV_AE250_Top .......
    Running optimization stage 2 on RiscV_AE250_Top .......
    Running optimization stage 2 on atcuart100_AE250_16s_33624072 .......
    Running optimization stage 2 on atcuart100_uart_rx_Z41 .......
    Extracted state machine for register uart_rx_cs_r
    State machine has 27 reachable states with original encodings of:
       00001
       00010
       00011
       00101
       00111
       01000
       01001
       01010
       01011
       01100
       01101
       01110
       01111
       10001
       10010
       10011
       10100
       10101
       10111
       11000
       11001
       11010
       11011
       11100
       11101
       11110
       11111
    Running optimization stage 2 on atcuart100_uart_tx_Z40 .......
    Extracted state machine for register uart_tx_cs_r
    State machine has 14 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0111
       1000
       1001
       1010
       1011
       1100
       1101
       1110
       1111
    Running optimization stage 2 on atcuart100_rxctrl_AE250_16s_4s .......
    Running optimization stage 2 on nds_async_buff_11s .......
    Running optimization stage 2 on nds_sync_fifo_clr_11s_16s_5s .......
    Running optimization stage 2 on atcuart100_txctrl_AE250_16s_4s .......
    Running optimization stage 2 on nds_async_buff_8s .......
    Running optimization stage 2 on nds_sync_fifo_clr_8s_16s_5s .......
    Running optimization stage 2 on atcuart100_baud_AE250 .......
    Running optimization stage 2 on atcuart100_modem_AE250 .......
    Running optimization stage 2 on nds_sync_l2l_1 .......
    Running optimization stage 2 on atcuart100_apbif_reg_AE250_16s_33624072_4s_0 .......
    Running optimization stage 2 on nds_sync_p2p_data_7s_0_0 .......
    Running optimization stage 2 on nds_sync_p2p_data_4s_0_8 .......
    Running optimization stage 2 on ae250_chip_Z39 .......
    Running optimization stage 2 on debug_subsystem_Z38 .......
    Running optimization stage 2 on ncepldm200_Z37 .......
    Extracted state machine for register abs_cs
    State machine has 5 reachable states with original encodings of:
       000
       001
       010
       011
       110
    Extracted state machine for register abs_cmderr
    State machine has 5 reachable states with original encodings of:
       000
       001
       010
       011
       100
    Running optimization stage 2 on ncejdtm200_AE250_jtag_32s_7s_2s_41s .......
    Running optimization stage 2 on ncejdtm200_dmi_Z36 .......
    Running optimization stage 2 on ncejdtm200_tap_Z35 .......
    Extracted state machine for register tap_ctr_cs
    State machine has 16 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
       0110
       0111
       1000
       1001
       1010
       1011
       1100
       1101
       1110
       1111
    Running optimization stage 2 on ae250_cpu_uncore_Z34 .......
    Running optimization stage 2 on vc_core_mem_Z33 .......
    Running optimization stage 2 on vc_btb_ram_1s_38s .......
    Running optimization stage 2 on nds_ram_model_38s_1s_0s_yes_1_0_2s .......

    Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\riscv_ae250_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell.
    Running optimization stage 2 on vc_dcache_ram_Z32 .......
    Running optimization stage 2 on nds_ram_model_bit_we_1s_1s_0.100000_1_no_1_0_2s .......
    Running optimization stage 2 on nds_ram_model_bwe_1s_1s_0.100000_1_no_8s_1_0_8s_2s .......
    Running optimization stage 2 on nds_ram_model_bit_we_1s_1s_0.100000_1_yes_1_0_2s .......
    Running optimization stage 2 on nds_ram_model_bwe_1s_1s_0.100000_1_yes_8s_1_0_8s_2s .......
    Running optimization stage 2 on vc_icache_ram_2s_1s_1s_1s_1s .......
    Running optimization stage 2 on nds_ram_model_1s_1s_0s_no_1_0_2s .......
    Running optimization stage 2 on nds_ram_model_1s_1s_0s_yes_1_0_2s .......
    Running optimization stage 2 on vc_dlm_ram_Z31 .......
    Running optimization stage 2 on vc_ilm_ram_Z30 .......
    Running optimization stage 2 on vc_dlm_Z29 .......
    Running optimization stage 2 on vc_ilm_Z28 .......
    Running optimization stage 2 on vc_fastmul_radix2_0_1_2_3_8 .......
    Running optimization stage 2 on vc_fastmul_cmp42_64s .......
    Running optimization stage 2 on vc_fastmul_cmp112_64s .......
    Running optimization stage 2 on vc_fastmul_recode .......
    Running optimization stage 2 on vc_core_Z27 .......
    Running optimization stage 2 on vc_mmu_Z26 .......
    Running optimization stage 2 on vc_biu_ahb_wrapper_Z25 .......
    Running optimization stage 2 on nds_sync_fifo_afe_32s_2s_0s_0s_2s_1s .......
    Running optimization stage 2 on vc_biu_ahb_no_32s_32s_1s_0s_bare .......
    Running optimization stage 2 on vc_biu_path_Z24 .......
    Running optimization stage 2 on vc_icu_Z23 .......
    Running optimization stage 2 on vc_ifu_Z22 .......
    Extracted state machine for register resp_ptr
    State machine has 4 reachable states with original encodings of:
       00
       01
       10
       11
    Extracted state machine for register issue_ptr
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    Extracted state machine for register init_ctr_cs
    State machine has 4 reachable states with original encodings of:
       00
       01
       10
       11
    Running optimization stage 2 on vc_dcu_Z21 .......
    Running optimization stage 2 on vc_lsu_Z20 .......
    Running optimization stage 2 on vc_trigm_Z19 .......
    Running optimization stage 2 on vc_csr_Z18 .......
    Running optimization stage 2 on vc_mdu_Z17 .......
    Extracted state machine for register state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    Running optimization stage 2 on vc_alu_Z16 .......
    Running optimization stage 2 on vc_rf .......
    Running optimization stage 2 on vc_ipipe_Z15 .......
    Extracted state machine for register ex_src1_bypass
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       100
    Extracted state machine for register ex_src2_bypass
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       100
    Extracted state machine for register gen_una_access.ex_micro_state_reg
    State machine has 2 reachable states with original encodings of:
       00
       10
    Running optimization stage 2 on atcmstmux100_mst_ctrl_AE250_32s_32s_0_2_0_1_2_3 .......
    Extracted state machine for register mst_cs
    State machine has 4 reachable states with original encodings of:
       00
       01
       10
       11
    Running optimization stage 2 on atcmstmux100_Z14 .......
    Running optimization stage 2 on atcmstmux100_mux_Z13 .......
    Running optimization stage 2 on atcmstmux100_exec_Z12 .......
    Extracted state machine for register exec_cs
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    Running optimization stage 2 on atcbusdec250_Z11 .......
    Running optimization stage 2 on atcbmc200_slv_commander_AE250_32s_31s_11s_0_1_2_3_0 .......
    Running optimization stage 2 on atcbmc200_mst_commander_Z10 .......
    Running optimization stage 2 on atcbmc200_mst_ctrl_Z9 .......
    Extracted state machine for register ctrl_cs
    State machine has 8 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
       111
    Running optimization stage 2 on atcbmc200_addrdec_AE250_32s_31s_11s .......
    Running optimization stage 2 on atcbmc200_mst_decoder_Z8 .......
    Running optimization stage 2 on atcbmc200_Z7 .......

    Only the first 100 messages of id 'CL156' are reported. To see all messages use 'report_messages -log E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\riscv_ae250_compiler.srr -id CL156' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL156} -count unlimited' in the Tcl shell.
    Running optimization stage 2 on atcbmc200_ahbslv_rf_Z6 .......
    Running optimization stage 2 on atcbmc200_mux_Z5 .......
    Running optimization stage 2 on atcapbbrg100_Z4 .......
    Extracted state machine for register hctrl_cs
    State machine has 6 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
    Running optimization stage 2 on nds_sync_fifo_data_32s_2s_2s .......
    Running optimization stage 2 on nds_sync_fifo_data_40s_2s_2s .......
    Running optimization stage 2 on ae250_smu_Z3 .......
    Running optimization stage 2 on ae250_smu_pd_Z2 .......
    Extracted state machine for register pwr_state
    State machine has 6 reachable states with original encodings of:
       000
       010
       011
       100
       101
       110
    Running optimization stage 2 on ae250_smu_aopd_top_AE250_yes_32s_0s_high_high .......
    Running optimization stage 2 on ae250_aopd_rstgen .......
    Running optimization stage 2 on ae250_smu_aopd_core_yes_32s_0s_high_high_0_1_3_2 .......
    Extracted state machine for register mpd_pwr_cs_r
    State machine has 4 reachable states with original encodings of:
       00
       01
       10
       11
    Running optimization stage 2 on nds_sync_p2p_data_3s_0_0 .......
    Running optimization stage 2 on nds_sync_p2p_0 .......
    Running optimization stage 2 on ae250_smu_mpd_AE250_0_0_1_3_2 .......
    Extracted state machine for register standby_cs_r
    State machine has 4 reachable states with original encodings of:
       00
       01
       10
       11
    Running optimization stage 2 on ae250_smu_apbif_Z1 .......
    Running optimization stage 2 on nds_sync_l2l .......
    Running optimization stage 2 on ae250_rstgen .......
    Running optimization stage 2 on ae250_clkgen .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:42s; CPU Time elapsed 0h:00m:41s; Memory used current: 392MB peak: 469MB)

    Process took 0h:00m:42s realtime, 0h:00m:41s cputime

    Process completed successfully.
    # Mon Mar 30 14:07:55 2020

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.09G
    Install: C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rcv_1
    Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 176MB peak: 179MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime

    Process completed successfully.
    # Mon Mar 30 14:07:59 2020

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  riscv_ae250_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:47s; CPU Time elapsed 0h:00m:44s; Memory used current: 20MB peak: 20MB)

    Process took 0h:00m:47s realtime, 0h:00m:44s cputime

    Process completed successfully.
    # Mon Mar 30 14:07:59 2020

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.09G
    Install: C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rcv_1
    Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 219MB peak: 222MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime

    Process completed successfully.
    # Mon Mar 30 14:08:04 2020

    ###########################################################]

`
`

    Premap Report

`
`

    # Mon Mar 30 14:08:06 2020

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.09G
    Install: C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rcv_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1564R, Built Mar  4 2020 10:56:38

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  riscv_ae250_scck.rpt
    See clock summary report "E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\riscv_ae250_scck.rpt"
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 268MB peak: 282MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 268MB peak: 282MB)

    Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 271MB peak: 282MB)

    Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 283MB peak: 285MB)

    @W:BN709 : ae250_chip_wrap.v(978) | Converting bidirection inout port X_tdo to output port. Because it's a pure output port
    @W:BN709 : ae250_chip_wrap.v(979) | Converting bidirection inout port X_trst to output port. Because it's a pure output port
    @W:MO112 : ae250_chip_wrap.v(2128) | Deleting tristate instance un1_X_tdi (in view: work.RiscV_AE250_Top(verilog)) on net X_tdi (in view: work.RiscV_AE250_Top(verilog)) because its enable is connected to 0.
    @W:MO112 : ae250_chip_wrap.v(2132) | Deleting tristate instance un1_X_tms (in view: work.RiscV_AE250_Top(verilog)) on net X_tms (in view: work.RiscV_AE250_Top(verilog)) because its enable is connected to 0.
    Encoding state machine standby_cs_r[3:0] (in view: work.ae250_smu_mpd_AE250_0_0_1_3_2(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Encoding state machine mpd_pwr_cs_r[3:0] (in view: work.ae250_smu_aopd_core_yes_32s_0s_high_high_0_1_3_2(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Encoding state machine pwr_state[5:0] (in view: work.ae250_smu_pd_Z2(verilog))
    original code -> new code
       000 -> 000001
       010 -> 000010
       011 -> 000100
       100 -> 001000
       101 -> 010000
       110 -> 100000
    Encoding state machine uart_tx_cs_r[13:0] (in view: work.atcuart100_uart_tx_Z40(verilog))
    original code -> new code
       0000 -> 00000000000001
       0001 -> 00000000000010
       0010 -> 00000000000100
       0011 -> 00000000001000
       0100 -> 00000000010000
       0111 -> 00000000100000
       1000 -> 00000001000000
       1001 -> 00000010000000
       1010 -> 00000100000000
       1011 -> 00001000000000
       1100 -> 00010000000000
       1101 -> 00100000000000
       1110 -> 01000000000000
       1111 -> 10000000000000
    Encoding state machine uart_rx_cs_r[26:0] (in view: work.atcuart100_uart_rx_Z41(verilog))
    original code -> new code
       00001 -> 000000000000000000000000001
       00010 -> 000000000000000000000000010
       00011 -> 000000000000000000000000100
       00101 -> 000000000000000000000001000
       00111 -> 000000000000000000000010000
       01000 -> 000000000000000000000100000
       01001 -> 000000000000000000001000000
       01010 -> 000000000000000000010000000
       01011 -> 000000000000000000100000000
       01100 -> 000000000000000001000000000
       01101 -> 000000000000000010000000000
       01110 -> 000000000000000100000000000
       01111 -> 000000000000001000000000000
       10001 -> 000000000000010000000000000
       10010 -> 000000000000100000000000000
       10011 -> 000000000001000000000000000
       10100 -> 000000000010000000000000000
       10101 -> 000000000100000000000000000
       10111 -> 000000001000000000000000000
       11000 -> 000000010000000000000000000
       11001 -> 000000100000000000000000000
       11010 -> 000001000000000000000000000
       11011 -> 000010000000000000000000000
       11100 -> 000100000000000000000000000
       11101 -> 001000000000000000000000000
       11110 -> 010000000000000000000000000
       11111 -> 100000000000000000000000000
    Encoding state machine hctrl_cs[5:0] (in view: work.atcapbbrg100_Z4(verilog))
    original code -> new code
       000 -> 000001
       001 -> 000010
       010 -> 000100
       011 -> 001000
       100 -> 010000
       101 -> 100000
    Encoding state machine ctrl_cs[7:0] (in view: work.atcbmc200_mst_ctrl_Z9(verilog))
    original code -> new code
       000 -> 00000001
       001 -> 00000010
       010 -> 00000100
       011 -> 00001000
       100 -> 00010000
       101 -> 00100000
       110 -> 01000000
       111 -> 10000000
    Encoding state machine tap_ctr_cs[15:0] (in view: work.ncejdtm200_tap_Z35(verilog))
    original code -> new code
       0000 -> 0000
       0001 -> 0001
       0010 -> 0010
       0011 -> 0011
       0100 -> 0100
       0101 -> 0101
       0110 -> 0110
       0111 -> 0111
       1000 -> 1000
       1001 -> 1001
       1010 -> 1010
       1011 -> 1011
       1100 -> 1100
       1101 -> 1101
       1110 -> 1110
       1111 -> 1111
    Encoding state machine abs_cs[4:0] (in view: work.ncepldm200_Z37(verilog))
    original code -> new code
       000 -> 00001
       001 -> 00010
       010 -> 00100
       011 -> 01000
       110 -> 10000
    Encoding state machine abs_cmderr[4:0] (in view: work.ncepldm200_Z37(verilog))
    original code -> new code
       000 -> 00001
       001 -> 00010
       010 -> 00100
       011 -> 01000
       100 -> 10000
    Encoding state machine exec_cs[2:0] (in view: work.atcmstmux100_exec_Z12(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine mst_cs[3:0] (in view: work.atcmstmux100_mst_ctrl_AE250_32s_32s_0_2_0_2_3_1(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Encoding state machine mst_cs[3:0] (in view: work.atcmstmux100_mst_ctrl_AE250_32s_32s_0_2_0_2_3_0(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Encoding state machine ex_src2_bypass[3:0] (in view: work.vc_ipipe_Z15(verilog))
    original code -> new code
       000 -> 00
       001 -> 01
       010 -> 10
       100 -> 11
    Encoding state machine ex_src1_bypass[3:0] (in view: work.vc_ipipe_Z15(verilog))
    original code -> new code
       000 -> 00
       001 -> 01
       010 -> 10
       100 -> 11
    Encoding state machine gen_una_access\.ex_micro_state_reg[1:0] (in view: work.vc_ipipe_Z15(verilog))
    original code -> new code
       00 -> 0
       10 -> 1
    Encoding state machine state[6:0] (in view: work.vc_mdu_Z17(verilog))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    Encoding state machine resp_ptr[3:0] (in view: work.vc_ifu_Z22(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11
    Encoding state machine issue_ptr[2:0] (in view: work.vc_ifu_Z22(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine init_ctr_cs[3:0] (in view: work.vc_ifu_Z22(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
       11 -> 11

    Starting clock optimization phase (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 377MB peak: 377MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 379MB peak: 379MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 379MB peak: 379MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 380MB peak: 380MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 380MB peak: 380MB)

    Clock Summary
    ******************

              Start                        Requested     Requested     Clock        Clock                     Clock
    Level     Clock                        Frequency     Period        Type         Group                     Load
    ---------------------------------------------------------------------------------------------------------------
    0 -       RiscV_AE250_Top|X_oschin     51.6 MHz      19.397        inferred     Autoconstr_clkgroup_0     5217

    0 -       RiscV_AE250_Top|X_tck        192.2 MHz     5.203         inferred     Autoconstr_clkgroup_1     106

    0 -       RiscV_AE250_Top|X_osclin     691.2 MHz     1.447         inferred     Autoconstr_clkgroup_2     17
    ===============================================================================================================

    Clock Load Summary
    ***********************

                                 Clock     Source             Clock Pin                                                                        Non-clock Pin     Non-clock Pin
    Clock                        Load      Pin                Seq Example                                                                      Seq Example       Comb Example
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    RiscV_AE250_Top|X_oschin     5217      X_oschin(port)     ae250_chip.uncore.vc_core_mem.vc_dlm_ram.doA[7:0].C                              -                 ae250_chip.ae250_clkgen.core_clk.I[0](keepbuf)

    RiscV_AE250_Top|X_tck        106       X_tck(port)        ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.pwr_rst_n_sync2.C     -                 ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.un1_tck.I[0](inv)

    RiscV_AE250_Top|X_osclin     17        X_osclin(port)     ae250_chip.u_smu.ae250_smu_aopd_top.ae250_aopd_rstgen.rtc_rstn_32ksync2.C        -                 -
    ========================================================================================================================================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    7 non-gated/non-generated clock tree(s) driving 5167 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           port                   3442       ENCRYPTED
    ClockId_0_1       ENCRYPTED           port                   1181       ENCRYPTED
    ClockId_0_2       X_tck               port                   106        ENCRYPTED
    ClockId_0_3       X_oschin            port                   249        ENCRYPTED
    ClockId_0_4       ENCRYPTED           port                   26         ENCRYPTED
    ClockId_0_5       ENCRYPTED           port                   146        ENCRYPTED
    ClockId_0_6       X_osclin            port                   17         ENCRYPTED
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\riscv_ae250.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 356MB peak: 380MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 357MB peak: 380MB)

    Finished constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 362MB peak: 380MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 239MB peak: 380MB)

    Process took 0h:00m:13s realtime, 0h:00m:12s cputime
    # Mon Mar 30 14:08:20 2020

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Mon Mar 30 14:08:21 2020

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.09G
    Install: C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro
    OS: Windows 6.2

    Hostname: GW-SW-063

    Implementation : rcv_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1564R, Built Mar  4 2020 10:56:38

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB)

    Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 123MB peak: 129MB)

    Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 136MB peak: 138MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 292MB peak: 292MB)

    @W:BN710 : ae250_chip_wrap.v(976) | Converting bidirection inout port X_tms to input port. Because it's a pure input port
    @W:BN710 : ae250_chip_wrap.v(977) | Converting bidirection inout port X_tdi to input port. Because it's a pure input port
    @W:BN710 : ae250_chip_wrap.v(976) | Converting bidirection inout port X_tms to input port. Because it's a pure input port
    @W:BN710 : ae250_chip_wrap.v(977) | Converting bidirection inout port X_tdi to input port. Because it's a pure input port
    @W:BN709 : ae250_chip_wrap.v(978) | Converting bidirection inout port X_tdo to output port. Because it's a pure output port
    @W:BN709 : ae250_chip_wrap.v(979) | Converting bidirection inout port X_trst to output port. Because it's a pure output port

    Available hyper_sources - for debug and ip models
    	None Found

    @W:BN710 : ae250_chip_wrap.v(976) | Converting bidirection inout port X_tms to input port. Because it's a pure input port
    @W:BN710 : ae250_chip_wrap.v(977) | Converting bidirection inout port X_tdi to input port. Because it's a pure input port
    @W:BN709 : ae250_chip_wrap.v(978) | Converting bidirection inout port X_tdo to output port. Because it's a pure output port
    @W:BN709 : ae250_chip_wrap.v(979) | Converting bidirection inout port X_trst to output port. Because it's a pure output port
    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 304MB peak: 304MB)

    Starting factoring (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:15s; Memory used current: 387MB peak: 491MB)

    Auto Dissolve of vc_rf (inst of view:work.vc_rf(verilog))

    Finished factoring (Real Time elapsed 0h:00m:40s; CPU Time elapsed 0h:00m:36s; Memory used current: 483MB peak: 491MB)

    @W:BN710 : ae250_chip_wrap.v(976) | Converting bidirection inout port X_tms to input port. Because it's a pure input port
    @W:BN710 : ae250_chip_wrap.v(977) | Converting bidirection inout port X_tdi to input port. Because it's a pure input port
    @W:BN709 : ae250_chip_wrap.v(978) | Converting bidirection inout port X_tdo to output port. Because it's a pure output port
    @W:BN709 : ae250_chip_wrap.v(979) | Converting bidirection inout port X_trst to output port. Because it's a pure output port
    @W:BN710 : ae250_chip_wrap.v(976) | Converting bidirection inout port X_tms to input port. Because it's a pure input port
    @W:BN710 : ae250_chip_wrap.v(977) | Converting bidirection inout port X_tdi to input port. Because it's a pure input port
    @W:BN709 : ae250_chip_wrap.v(978) | Converting bidirection inout port X_tdo to output port. Because it's a pure output port
    @W:BN709 : ae250_chip_wrap.v(979) | Converting bidirection inout port X_trst to output port. Because it's a pure output port

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:52s; CPU Time elapsed 0h:00m:48s; Memory used current: 431MB peak: 512MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:57s; CPU Time elapsed 0h:00m:53s; Memory used current: 440MB peak: 512MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:01m:20s; CPU Time elapsed 0h:01m:15s; Memory used current: 458MB peak: 512MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:01m:21s; CPU Time elapsed 0h:01m:16s; Memory used current: 458MB peak: 512MB)

    Finished preparing to map (Real Time elapsed 0h:01m:26s; CPU Time elapsed 0h:01m:21s; Memory used current: 457MB peak: 512MB)

    Finished technology mapping (Real Time elapsed 0h:01m:43s; CPU Time elapsed 0h:01m:36s; Memory used current: 554MB peak: 554MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:01m:38s		    -6.56ns		13076 /      4846
       2		0h:01m:38s		    -6.43ns		12992 /      4846
       3		0h:01m:39s		    -6.18ns		12993 /      4846
       4		0h:01m:40s		    -6.18ns		12994 /      4846
       5		0h:01m:40s		    -6.18ns		12994 /      4846
       6		0h:01m:40s		    -6.18ns		12995 /      4846
       7		0h:01m:40s		    -6.18ns		12994 /      4846
    Timing driven replication report
    Added 12 Registers via timing driven replication
    Added 0 LUTs via timing driven replication

       8		0h:01m:49s		    -5.06ns		13002 /      4858
       9		0h:01m:49s		    -4.95ns		13004 /      4858
      10		0h:01m:50s		    -4.97ns		13008 /      4858
      11		0h:01m:50s		    -4.92ns		13009 /      4858
      12		0h:01m:51s		    -4.69ns		13011 /      4858
      13		0h:01m:51s		    -4.39ns		13023 /      4858
      14		0h:01m:52s		    -4.24ns		13025 /      4858
      15		0h:01m:52s		    -4.24ns		13025 /      4858
      16		0h:01m:52s		    -4.24ns		13025 /      4858
      17		0h:01m:52s		    -4.24ns		13026 /      4858
      18		0h:01m:52s		    -4.24ns		13027 /      4858
    Timing driven replication report
    Added 14 Registers via timing driven replication
    Added 12 LUTs via timing driven replication

      19		0h:01m:55s		    -3.87ns		13059 /      4872
      20		0h:01m:56s		    -3.75ns		13061 /      4872
      21		0h:01m:56s		    -3.76ns		13063 /      4872
      22		0h:01m:56s		    -3.62ns		13064 /      4872
      23		0h:01m:56s		    -3.62ns		13066 /      4872
      24		0h:01m:56s		    -3.49ns		13067 /      4872
      25		0h:01m:58s		    -3.89ns		13067 /      4872
      26		0h:01m:58s		    -4.16ns		13067 /      4872
      27		0h:01m:58s		    -4.02ns		13067 /      4872

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:02m:07s; CPU Time elapsed 0h:02m:00s; Memory used current: 504MB peak: 554MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
    @W:BN710 : ae250_chip_wrap.v(976) | Converting bidirection inout port X_tms to input port. Because it's a pure input port
    @W:BN710 : ae250_chip_wrap.v(977) | Converting bidirection inout port X_tdi to input port. Because it's a pure input port
    @W:BN709 : ae250_chip_wrap.v(978) | Converting bidirection inout port X_tdo to output port. Because it's a pure output port
    @W:BN709 : ae250_chip_wrap.v(979) | Converting bidirection inout port X_trst to output port. Because it's a pure output port

    Finished restoring hierarchy (Real Time elapsed 0h:02m:14s; CPU Time elapsed 0h:02m:06s; Memory used current: 485MB peak: 554MB)

    Start Writing Netlists (Real Time elapsed 0h:02m:16s; CPU Time elapsed 0h:02m:09s; Memory used current: 305MB peak: 554MB)

    Writing Analyst data base E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synwork\riscv_ae250_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:02m:20s; CPU Time elapsed 0h:02m:12s; Memory used current: 413MB peak: 554MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:02m:26s; CPU Time elapsed 0h:02m:17s; Memory used current: 414MB peak: 554MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:02m:26s; CPU Time elapsed 0h:02m:18s; Memory used current: 414MB peak: 554MB)

    Start final timing analysis (Real Time elapsed 0h:02m:28s; CPU Time elapsed 0h:02m:19s; Memory used current: 393MB peak: 554MB)

    @W:MT420 :  | Found inferred clock RiscV_AE250_Top|X_oschin with period 14.62ns. Please declare a user-defined clock on port X_oschin.
    @W:MT420 :  | Found inferred clock RiscV_AE250_Top|X_tck with period 4.87ns. Please declare a user-defined clock on port X_tck.
    @W:MT420 :  | Found inferred clock RiscV_AE250_Top|X_osclin with period 0.71ns. Please declare a user-defined clock on port X_osclin.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Mon Mar 30 14:10:49 2020
    #

    Top view:               RiscV_AE250_Top
    Requested Frequency:    68.4 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -2.580

                                 Requested      Estimated      Requested     Estimated                Clock        Clock
    Starting Clock               Frequency      Frequency      Period        Period        Slack      Type         Group
    ------------------------------------------------------------------------------------------------------------------------------------
    RiscV_AE250_Top|X_oschin     68.4 MHz       58.1 MHz       14.619        17.198        -2.580     inferred     Autoconstr_clkgroup_0
    RiscV_AE250_Top|X_osclin     1402.3 MHz     1191.9 MHz     0.713         0.839         -0.126     inferred     Autoconstr_clkgroup_2
    RiscV_AE250_Top|X_tck        205.4 MHz      153.1 MHz      4.869         6.530         -0.859     inferred     Autoconstr_clkgroup_1
    System                       150.0 MHz      NA             6.667         NA            6.890      system       system_clkgroup
    ====================================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise
    --------------------------------------------------------------------------------------------------------------------------------------------
    Starting                  Ending                    |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
    --------------------------------------------------------------------------------------------------------------------------------------------
    System                    RiscV_AE250_Top|X_oschin  |  14.619      6.890   |  No paths    -      |  No paths    -       |  No paths    -
    RiscV_AE250_Top|X_oschin  System                    |  14.619      -0.865  |  No paths    -      |  No paths    -       |  No paths    -
    RiscV_AE250_Top|X_oschin  RiscV_AE250_Top|X_oschin  |  14.619      -2.580  |  No paths    -      |  No paths    -       |  No paths    -
    RiscV_AE250_Top|X_oschin  RiscV_AE250_Top|X_tck     |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -
    RiscV_AE250_Top|X_tck     System                    |  4.869       4.091   |  No paths    -      |  No paths    -       |  No paths    -
    RiscV_AE250_Top|X_tck     RiscV_AE250_Top|X_oschin  |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -
    RiscV_AE250_Top|X_tck     RiscV_AE250_Top|X_tck     |  4.869       -0.859  |  No paths    -      |  2.435       -0.831  |  No paths    -
    RiscV_AE250_Top|X_osclin  RiscV_AE250_Top|X_osclin  |  0.713       -0.126  |  No paths    -      |  No paths    -       |  No paths    -
    ============================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: RiscV_AE250_Top|X_oschin
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                                                                                   Starting                                                                         Arrival
    Instance                                                                                                                       Reference                    Type      Pin     Net                               Time        Slack
                                                                                                                                   Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0]                                                                     RiscV_AE250_Top|X_oschin     DFFP      Q       retire_ptr[0]                     0.243       -2.580
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[2]                                                                     RiscV_AE250_Top|X_oschin     DFFC      Q       retire_ptr[2]                     0.243       -2.519
    ae250_chip.uncore.vc_core_mem.vc_core.vc_biu.gen_ahb_wrapper\.vc_biu_ahb_wrapper0.gen_no_burst_support\.rdata_reg_fast[33]     RiscV_AE250_Top|X_oschin     DFFCE     Q       rdata_reg_fast[33]                0.243       -2.355
    ae250_chip.uncore.vc_core_mem.vc_core.vc_biu.gen_ahb_wrapper\.vc_biu_ahb_wrapper0.gen_no_burst_support\.rdata_reg_fast[32]     RiscV_AE250_Top|X_oschin     DFFCE     Q       rdata_reg_fast[32]                0.243       -2.334
    ae250_chip.uncore.vc_core_mem.vc_core.vc_biu.gen_ahb_wrapper\.vc_biu_ahb_wrapper0.gen_no_burst_support\.rdata_valid_fast       RiscV_AE250_Top|X_oschin     DFFC      Q       rdata_valid_fast                  0.243       -2.247
    ae250_chip.uncore.vc_core_mem.vc_core.vc_trigm.gen_reg_trig0\.reg_trig0_addr[5]                                                RiscV_AE250_Top|X_oschin     DFFCE     Q       un1_compared_addr_for_trig0_5     0.243       -2.233
    ae250_chip.uncore.vc_core_mem.vc_core.vc_trigm.gen_reg_trig0\.reg_trig0_addr[4]                                                RiscV_AE250_Top|X_oschin     DFFCE     Q       un1_compared_addr_for_trig0_4     0.243       -2.212
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fq_ready[0]                                                                       RiscV_AE250_Top|X_oschin     DFFC      Q       fq_ready[0]                       0.243       -2.193
    ae250_chip.uncore.vc_core_mem.vc_core.vc_trigm.gen_reg_trig0\.reg_trig0_addr[0]                                                RiscV_AE250_Top|X_oschin     DFFCE     Q       un1_compared_addr_for_trig0_0     0.243       -2.186
    ae250_chip.uncore.vc_core_mem.vc_core.vc_trigm.gen_reg_trig0_match\.reg_trig0_match[1]                                         RiscV_AE250_Top|X_oschin     DFFCE     Q       reg_trig0_match[1]                0.243       -2.175
    ==================================================================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                                                Starting                                                              Required
    Instance                                                                                    Reference                    Type      Pin     Net                    Time         Slack
                                                                                                Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.\.reg_align_valid                            RiscV_AE250_Top|X_oschin     DFFC      D       reg_align_valid_nx     14.558       -2.580
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0]                                  RiscV_AE250_Top|X_oschin     DFFP      D       retire_ptre_0[0]       14.558       -2.540
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[1]                                  RiscV_AE250_Top|X_oschin     DFFC      D       retire_ptre_0[1]       14.558       -2.540
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[2]                                  RiscV_AE250_Top|X_oschin     DFFC      D       retire_ptre_0[2]       14.558       -2.540
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fq_full                                        RiscV_AE250_Top|X_oschin     DFFC      D       fq_full_nx             14.558       -2.514
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_valid                                 RiscV_AE250_Top|X_oschin     DFFCE     D       un1_ex_valid_nx        14.558       -2.472
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.gen_codense_enabled\.reg_resolving_ex_it     RiscV_AE250_Top|X_oschin     DFFC      D       resolving_ex_it_nx     14.558       -2.472
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.gen_reg_insert_hss\.reg_insert_hss           RiscV_AE250_Top|X_oschin     DFFC      D       N_5440_i               14.558       -2.472
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src1[0]                               RiscV_AE250_Top|X_oschin     DFFE      D       ex_reg_src1_2[0]       14.558       -2.413
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src1[1]                               RiscV_AE250_Top|X_oschin     DFFE      D       ex_reg_src1_2[1]       14.558       -2.413
    =====================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      14.619
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         14.558

        - Propagation time:                      17.137
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -2.580

        Number of logic level(s):                15
        Starting point:                          ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0] / Q
        Ending point:                            ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.\.reg_align_valid / D
        The start point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK

    Instance / Net                                                                       Pin      Pin               Arrival     No. of
    Name                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0]                  DFFP     Q        Out     0.243     0.243       -
    retire_ptr[0]                                                               Net      -        -       0.901     -           75
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     I1       In      -         1.144       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     F        Out     0.570     1.714       -
    un1_retire_fq_ready                                                         Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     I2       In      -         2.249       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     F        Out     0.462     2.711       -
    retire_N_3_mux_0                                                            Net      -        -       0.779     -           42
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[14]              LUT3     I1       In      -         3.490       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[14]              LUT3     F        Out     0.570     4.060       -
    fetch_instr_d[14]                                                           Net      -        -       0.401     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[14]                LUT4     I0       In      -         4.461       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[14]                LUT4     F        Out     0.549     5.010       -
    fetch_instr[14]                                                             Net      -        -       0.535     -           4
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[14]                 LUT4     I0       In      -         5.545       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[14]                 LUT4     F        Out     0.549     6.094       -
    ii_instr[14]                                                                Net      -        -       0.901     -           75
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     I1       In      -         6.995       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     F        Out     0.570     7.565       -
    un1_ii_instr_60                                                             Net      -        -       0.596     -           14
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     I2       In      -         8.161       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     F        Out     0.462     8.623       -
    N_5179                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     I0       In      -         9.158       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     F        Out     0.549     9.707       -
    instr_cb_type                                                               Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     I1       In      -         10.242      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     F        Out     0.570     10.812      -
    g0_4_1                                                                      Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     I0       In      -         11.347      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     F        Out     0.549     11.896      -
    rs1_ren                                                                     Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     I2       In      -         12.431      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     F        Out     0.462     12.893      -
    rs1_ex_bypass_4                                                             Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     I1       In      -         13.428      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     F        Out     0.570     13.998      -
    g0_6_1                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_x                       LUT3     I0       In      -         14.533      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_x                       LUT3     F        Out     0.549     15.082      -
    g0_6_x                                                                      Net      -        -       0.401     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_stall                     LUT3     I0       In      -         15.483      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_stall                     LUT3     F        Out     0.549     16.032      -
    ii_stall                                                                    Net      -        -       0.535     -           10
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.reg_align_valid_nx           LUT4     I1       In      -         16.567      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.reg_align_valid_nx           LUT4     F        Out     0.570     17.137      -
    reg_align_valid_nx                                                          Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.\.reg_align_valid            DFFC     D        In      -         17.137      -
    ======================================================================================================================================
    Total path delay (propagation time + setup) of 17.198 is 8.404(48.9%) logic and 8.794(51.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      14.619
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         14.558

        - Propagation time:                      17.137
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -2.580

        Number of logic level(s):                15
        Starting point:                          ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0] / Q
        Ending point:                            ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.\.reg_align_valid / D
        The start point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK

    Instance / Net                                                                       Pin      Pin               Arrival     No. of
    Name                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0]                  DFFP     Q        Out     0.243     0.243       -
    retire_ptr[0]                                                               Net      -        -       0.901     -           75
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     I1       In      -         1.144       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     F        Out     0.570     1.714       -
    un1_retire_fq_ready                                                         Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     I2       In      -         2.249       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     F        Out     0.462     2.711       -
    retire_N_3_mux_0                                                            Net      -        -       0.779     -           42
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[29]              LUT3     I1       In      -         3.490       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[29]              LUT3     F        Out     0.570     4.060       -
    fetch_instr_d[29]                                                           Net      -        -       0.401     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[29]                LUT4     I0       In      -         4.461       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[29]                LUT4     F        Out     0.549     5.010       -
    fetch_instr[29]                                                             Net      -        -       0.535     -           4
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[13]                 LUT4     I1       In      -         5.545       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[13]                 LUT4     F        Out     0.570     6.115       -
    ii_instr[13]                                                                Net      -        -       0.901     -           63
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     I0       In      -         7.016       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     F        Out     0.549     7.565       -
    un1_ii_instr_60                                                             Net      -        -       0.596     -           14
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     I2       In      -         8.161       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     F        Out     0.462     8.623       -
    N_5179                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     I0       In      -         9.158       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     F        Out     0.549     9.707       -
    instr_cb_type                                                               Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     I1       In      -         10.242      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     F        Out     0.570     10.812      -
    g0_4_1                                                                      Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     I0       In      -         11.347      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     F        Out     0.549     11.896      -
    rs1_ren                                                                     Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     I2       In      -         12.431      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     F        Out     0.462     12.893      -
    rs1_ex_bypass_4                                                             Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     I1       In      -         13.428      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     F        Out     0.570     13.998      -
    g0_6_1                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_x                       LUT3     I0       In      -         14.533      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_x                       LUT3     F        Out     0.549     15.082      -
    g0_6_x                                                                      Net      -        -       0.401     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_stall                     LUT3     I0       In      -         15.483      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_stall                     LUT3     F        Out     0.549     16.032      -
    ii_stall                                                                    Net      -        -       0.535     -           10
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.reg_align_valid_nx           LUT4     I1       In      -         16.567      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.reg_align_valid_nx           LUT4     F        Out     0.570     17.137      -
    reg_align_valid_nx                                                          Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.\.reg_align_valid            DFFC     D        In      -         17.137      -
    ======================================================================================================================================
    Total path delay (propagation time + setup) of 17.198 is 8.404(48.9%) logic and 8.794(51.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      14.619
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         14.558

        - Propagation time:                      17.116
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -2.559

        Number of logic level(s):                15
        Starting point:                          ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0] / Q
        Ending point:                            ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.\.reg_align_valid / D
        The start point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK

    Instance / Net                                                                       Pin      Pin               Arrival     No. of
    Name                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0]                  DFFP     Q        Out     0.243     0.243       -
    retire_ptr[0]                                                               Net      -        -       0.901     -           75
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     I1       In      -         1.144       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     F        Out     0.570     1.714       -
    un1_retire_fq_ready                                                         Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     I2       In      -         2.249       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     F        Out     0.462     2.711       -
    retire_N_3_mux_0                                                            Net      -        -       0.779     -           42
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[13]              LUT3     I1       In      -         3.490       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[13]              LUT3     F        Out     0.570     4.060       -
    fetch_instr_d[13]                                                           Net      -        -       0.401     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[13]                LUT4     I0       In      -         4.461       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[13]                LUT4     F        Out     0.549     5.010       -
    fetch_instr[13]                                                             Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[13]                 LUT4     I0       In      -         5.545       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[13]                 LUT4     F        Out     0.549     6.094       -
    ii_instr[13]                                                                Net      -        -       0.901     -           63
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     I0       In      -         6.995       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     F        Out     0.549     7.544       -
    un1_ii_instr_60                                                             Net      -        -       0.596     -           14
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     I2       In      -         8.140       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     F        Out     0.462     8.602       -
    N_5179                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     I0       In      -         9.137       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     F        Out     0.549     9.686       -
    instr_cb_type                                                               Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     I1       In      -         10.221      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     F        Out     0.570     10.791      -
    g0_4_1                                                                      Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     I0       In      -         11.326      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     F        Out     0.549     11.875      -
    rs1_ren                                                                     Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     I2       In      -         12.410      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     F        Out     0.462     12.872      -
    rs1_ex_bypass_4                                                             Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     I1       In      -         13.407      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     F        Out     0.570     13.977      -
    g0_6_1                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_x                       LUT3     I0       In      -         14.512      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_x                       LUT3     F        Out     0.549     15.061      -
    g0_6_x                                                                      Net      -        -       0.401     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_stall                     LUT3     I0       In      -         15.462      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_stall                     LUT3     F        Out     0.549     16.011      -
    ii_stall                                                                    Net      -        -       0.535     -           10
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.reg_align_valid_nx           LUT4     I1       In      -         16.546      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.reg_align_valid_nx           LUT4     F        Out     0.570     17.116      -
    reg_align_valid_nx                                                          Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.\.reg_align_valid            DFFC     D        In      -         17.116      -
    ======================================================================================================================================
    Total path delay (propagation time + setup) of 17.177 is 8.383(48.8%) logic and 8.794(51.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      14.619
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         14.558

        - Propagation time:                      17.097
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -2.540

        Number of logic level(s):                15
        Starting point:                          ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0] / Q
        Ending point:                            ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[2] / D
        The start point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK

    Instance / Net                                                                       Pin      Pin               Arrival     No. of
    Name                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0]                  DFFP     Q        Out     0.243     0.243       -
    retire_ptr[0]                                                               Net      -        -       0.901     -           75
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     I1       In      -         1.144       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     F        Out     0.570     1.714       -
    un1_retire_fq_ready                                                         Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     I2       In      -         2.249       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     F        Out     0.462     2.711       -
    retire_N_3_mux_0                                                            Net      -        -       0.779     -           42
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[14]              LUT3     I1       In      -         3.490       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[14]              LUT3     F        Out     0.570     4.060       -
    fetch_instr_d[14]                                                           Net      -        -       0.401     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[14]                LUT4     I0       In      -         4.461       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[14]                LUT4     F        Out     0.549     5.010       -
    fetch_instr[14]                                                             Net      -        -       0.535     -           4
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[14]                 LUT4     I0       In      -         5.545       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[14]                 LUT4     F        Out     0.549     6.094       -
    ii_instr[14]                                                                Net      -        -       0.901     -           75
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     I1       In      -         6.995       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     F        Out     0.570     7.565       -
    un1_ii_instr_60                                                             Net      -        -       0.596     -           14
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     I2       In      -         8.161       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     F        Out     0.462     8.623       -
    N_5179                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     I0       In      -         9.158       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     F        Out     0.549     9.707       -
    instr_cb_type                                                               Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     I1       In      -         10.242      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     F        Out     0.570     10.812      -
    g0_4_1                                                                      Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     I0       In      -         11.347      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     F        Out     0.549     11.896      -
    rs1_ren                                                                     Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     I2       In      -         12.431      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     F        Out     0.462     12.893      -
    rs1_ex_bypass_4                                                             Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     I1       In      -         13.428      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     F        Out     0.570     13.998      -
    g0_6_1                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6                         LUT4     I1       In      -         14.533      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6                         LUT4     F        Out     0.570     15.103      -
    ii_stall_1                                                                  Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.g0_0                           LUT4     I2       In      -         15.638      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.g0_0                           LUT4     F        Out     0.462     16.100      -
    un2_N_5_mux                                                                 Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.g0                             LUT3     I2       In      -         16.635      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.g0                             LUT3     F        Out     0.462     17.097      -
    retire_ptre_0[2]                                                            Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[2]                  DFFC     D        In      -         17.097      -
    ======================================================================================================================================
    Total path delay (propagation time + setup) of 17.158 is 8.230(48.0%) logic and 8.928(52.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      14.619
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         14.558

        - Propagation time:                      17.097
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -2.540

        Number of logic level(s):                15
        Starting point:                          ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0] / Q
        Ending point:                            ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[2] / D
        The start point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK

    Instance / Net                                                                       Pin      Pin               Arrival     No. of
    Name                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[0]                  DFFP     Q        Out     0.243     0.243       -
    retire_ptr[0]                                                               Net      -        -       0.901     -           75
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     I1       In      -         1.144       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.un1_fq_valid_clr_1_0           LUT2     F        Out     0.570     1.714       -
    un1_retire_fq_ready                                                         Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     I2       In      -         2.249       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_m1_e_0                  LUT4     F        Out     0.462     2.711       -
    retire_N_3_mux_0                                                            Net      -        -       0.779     -           42
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[29]              LUT3     I1       In      -         3.490       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr_d[29]              LUT3     F        Out     0.570     4.060       -
    fetch_instr_d[29]                                                           Net      -        -       0.401     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[29]                LUT4     I0       In      -         4.461       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.fetch_instr[29]                LUT4     F        Out     0.549     5.010       -
    fetch_instr[29]                                                             Net      -        -       0.535     -           4
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[13]                 LUT4     I1       In      -         5.545       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ii_instr[13]                 LUT4     F        Out     0.570     6.115       -
    ii_instr[13]                                                                Net      -        -       0.901     -           63
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     I0       In      -         7.016       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.un1_ii_instr_60              LUT3     F        Out     0.549     7.565       -
    un1_ii_instr_60                                                             Net      -        -       0.596     -           14
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     I2       In      -         8.161       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_reg_src2_nx_7_tz_1[3]     LUT3     F        Out     0.462     8.623       -
    N_5179                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     I0       In      -         9.158       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.instr_cb_type                LUT3     F        Out     0.549     9.707       -
    instr_cb_type                                                               Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     I1       In      -         10.242      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.rs1_ren_N_6L9                LUT4     F        Out     0.570     10.812      -
    g0_4_1                                                                      Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     I0       In      -         11.347      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_4                         LUT4     F        Out     0.549     11.896      -
    rs1_ren                                                                     Net      -        -       0.535     -           6
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     I2       In      -         12.431      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_2                         LUT4     F        Out     0.462     12.893      -
    rs1_ex_bypass_4                                                             Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     I1       In      -         13.428      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6_1                       LUT4     F        Out     0.570     13.998      -
    g0_6_1                                                                      Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6                         LUT4     I1       In      -         14.533      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.g0_6                         LUT4     F        Out     0.570     15.103      -
    ii_stall_1                                                                  Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.g0_0                           LUT4     I2       In      -         15.638      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.g0_0                           LUT4     F        Out     0.462     16.100      -
    un2_N_5_mux                                                                 Net      -        -       0.535     -           3
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.g0                             LUT3     I2       In      -         16.635      -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.g0                             LUT3     F        Out     0.462     17.097      -
    retire_ptre_0[2]                                                            Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ifu.retire_ptr[2]                  DFFC     D        In      -         17.097      -
    ======================================================================================================================================
    Total path delay (propagation time + setup) of 17.158 is 8.230(48.0%) logic and 8.928(52.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: RiscV_AE250_Top|X_osclin
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                                Starting                                                            Arrival
    Instance                                                                    Reference                    Type     Pin     Net                   Time        Slack
                                                                                Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.u_smu.ae250_smu_aopd_top.ae250_aopd_rstgen.rtc_rstn_32ksync1     RiscV_AE250_Top|X_osclin     DFFC     Q       rtc_rstn_32ksync1     0.243       -0.126
    ==================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                                Starting                                                            Required
    Instance                                                                    Reference                    Type     Pin     Net                   Time         Slack
                                                                                Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.u_smu.ae250_smu_aopd_top.ae250_aopd_rstgen.rtc_rstn_32ksync2     RiscV_AE250_Top|X_osclin     DFFC     D       rtc_rstn_32ksync1     0.652        -0.126
    ===================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      0.713
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         0.652

        - Propagation time:                      0.778
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.126

        Number of logic level(s):                0
        Starting point:                          ae250_chip.u_smu.ae250_smu_aopd_top.ae250_aopd_rstgen.rtc_rstn_32ksync1 / Q
        Ending point:                            ae250_chip.u_smu.ae250_smu_aopd_top.ae250_aopd_rstgen.rtc_rstn_32ksync2 / D
        The start point is clocked by            RiscV_AE250_Top|X_osclin [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_osclin [rising] on pin CLK

    Instance / Net                                                                       Pin      Pin               Arrival     No. of
    Name                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.u_smu.ae250_smu_aopd_top.ae250_aopd_rstgen.rtc_rstn_32ksync1     DFFC     Q        Out     0.243     0.243       -
    rtc_rstn_32ksync1                                                           Net      -        -       0.535     -           1
    ae250_chip.u_smu.ae250_smu_aopd_top.ae250_aopd_rstgen.rtc_rstn_32ksync2     DFFC     D        In      -         0.778       -
    ======================================================================================================================================
    Total path delay (propagation time + setup) of 0.839 is 0.304(36.2%) logic and 0.535(63.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: RiscV_AE250_Top|X_tck
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                                                   Starting                                                         Arrival
    Instance                                                                                       Reference                 Type      Pin     Net                  Time        Slack
                                                                                                   Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[4]            RiscV_AE250_Top|X_tck     DFFCE     Q       tap_ir[4]            0.243       -0.859
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.busy_mask            RiscV_AE250_Top|X_tck     DFFCE     Q       busy_mask            0.243       -0.840
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[3]            RiscV_AE250_Top|X_tck     DFFCE     Q       tap_ir[3]            0.243       -0.838
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[2]            RiscV_AE250_Top|X_tck     DFFCE     Q       tap_ir[2]            0.243       -0.831
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.nds_sync_dmi_tap.b_signal           RiscV_AE250_Top|X_tck     DFFC      Q       dmi_tap_tck_ack      0.243       -0.819
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[1]            RiscV_AE250_Top|X_tck     DFFCE     Q       tap_ir[1]            0.243       -0.810
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_dmi_req          RiscV_AE250_Top|X_tck     DFFCE     Q       tap_dmi_tck_req      0.243       -0.732
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.dmi[1]               RiscV_AE250_Top|X_tck     DFFCE     Q       tap_dmi_data[1]      0.243       -0.634
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.dtmcs_dmistat[0]     RiscV_AE250_Top|X_tck     DFFCE     Q       dtmcs_dmistat[0]     0.243       -0.613
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ctr_cs[1]        RiscV_AE250_Top|X_tck     DFFC      Q       tap_ctr_cs[1]        0.243       -0.578
    ==================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                                                    Starting                                                 Required
    Instance                                                                                        Reference                 Type       Pin     Net         Time         Slack
                                                                                                    Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[11]     RiscV_AE250_Top|X_tck     DFFCE      D       N_311_i     4.808        -0.859
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[0]      RiscV_AE250_Top|X_tck     DFFCE      D       N_155_i     4.808        -0.845
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[1]      RiscV_AE250_Top|X_tck     DFFCE      D       N_168_i     4.808        -0.845
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tdo                   RiscV_AE250_Top|X_tck     DFFNCE     D       N_104_i     2.373        -0.831
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[10]     RiscV_AE250_Top|X_tck     DFFCE      D       N_296_i     4.808        -0.768
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[13]     RiscV_AE250_Top|X_tck     DFFCE      D       N_341_i     4.808        -0.768
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[28]     RiscV_AE250_Top|X_tck     DFFCE      D       N_566_i     4.808        -0.768
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[5]      RiscV_AE250_Top|X_tck     DFFCE      D       N_221_i     4.808        -0.747
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[12]     RiscV_AE250_Top|X_tck     DFFCE      D       N_326_i     4.808        -0.747
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[14]     RiscV_AE250_Top|X_tck     DFFCE      D       N_356_i     4.808        -0.747
    ============================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.869
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.808

        - Propagation time:                      5.667
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.859

        Number of logic level(s):                5
        Starting point:                          ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[4] / Q
        Ending point:                            ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[11] / D
        The start point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK

    Instance / Net                                                                                            Pin      Pin               Arrival     No. of
    Name                                                                                            Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[4]             DFFCE     Q        Out     0.243     0.243       -
    tap_ir[4]                                                                                       Net       -        -       0.535     -           7
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access_1_0     LUT2      I1       In      -         0.778       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access_1_0     LUT2      F        Out     0.570     1.348       -
    is_dmi_access_1                                                                                 Net       -        -       0.535     -           3
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access         LUT4      I0       In      -         1.883       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access         LUT4      F        Out     0.549     2.432       -
    is_dmi_access                                                                                   Net       -        -       0.596     -           18
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_write          LUT2      I0       In      -         3.028       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_write          LUT2      F        Out     0.549     3.577       -
    is_dmi_write                                                                                    Net       -        -       0.657     -           25
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i_1             LUT4      I1       In      -         4.234       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i_1             LUT4      F        Out     0.570     4.804       -
    N_311_i_1                                                                                       Net       -        -       0.401     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i               LUT4      I2       In      -         5.205       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i               LUT4      F        Out     0.462     5.667       -
    N_311_i                                                                                         Net       -        -       0.000     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[11]     DFFCE     D        In      -         5.667       -
    ===========================================================================================================================================================
    Total path delay (propagation time + setup) of 5.728 is 3.004(52.4%) logic and 2.724(47.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.869
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.808

        - Propagation time:                      5.653
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.845

        Number of logic level(s):                5
        Starting point:                          ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[4] / Q
        Ending point:                            ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[0] / D
        The start point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK

    Instance / Net                                                                                                Pin      Pin               Arrival     No. of
    Name                                                                                                Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[4]                 DFFCE     Q        Out     0.243     0.243       -
    tap_ir[4]                                                                                           Net       -        -       0.535     -           7
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access_1_0         LUT2      I1       In      -         0.778       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access_1_0         LUT2      F        Out     0.570     1.348       -
    is_dmi_access_1                                                                                     Net       -        -       0.535     -           3
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access             LUT4      I0       In      -         1.883       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access             LUT4      F        Out     0.549     2.432       -
    is_dmi_access                                                                                       Net       -        -       0.596     -           18
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_busy                   LUT3      I1       In      -         3.028       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_busy                   LUT3      F        Out     0.570     3.598       -
    is_busy                                                                                             Net       -        -       0.535     -           2
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan_3_m2[0]     LUT4      I1       In      -         4.133       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan_3_m2[0]     LUT4      F        Out     0.570     4.703       -
    N_7873_mux                                                                                          Net       -        -       0.401     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_155_i_0                 LUT4      I0       In      -         5.104       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_155_i_0                 LUT4      F        Out     0.549     5.653       -
    N_155_i                                                                                             Net       -        -       0.000     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[0]          DFFCE     D        In      -         5.653       -
    ===============================================================================================================================================================
    Total path delay (propagation time + setup) of 5.714 is 3.112(54.5%) logic and 2.602(45.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.869
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.808

        - Propagation time:                      5.653
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.845

        Number of logic level(s):                5
        Starting point:                          ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[4] / Q
        Ending point:                            ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[1] / D
        The start point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK

    Instance / Net                                                                                                Pin      Pin               Arrival     No. of
    Name                                                                                                Type      Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[4]                 DFFCE     Q        Out     0.243     0.243       -
    tap_ir[4]                                                                                           Net       -        -       0.535     -           7
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access_1_0         LUT2      I1       In      -         0.778       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access_1_0         LUT2      F        Out     0.570     1.348       -
    is_dmi_access_1                                                                                     Net       -        -       0.535     -           3
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access             LUT4      I0       In      -         1.883       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access             LUT4      F        Out     0.549     2.432       -
    is_dmi_access                                                                                       Net       -        -       0.596     -           18
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_busy                   LUT3      I1       In      -         3.028       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_busy                   LUT3      F        Out     0.570     3.598       -
    is_busy                                                                                             Net       -        -       0.535     -           2
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan_3_m2[1]     LUT3      I1       In      -         4.133       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan_3_m2[1]     LUT3      F        Out     0.570     4.703       -
    N_7874_mux                                                                                          Net       -        -       0.401     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_168_i                   LUT4      I0       In      -         5.104       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_168_i                   LUT4      F        Out     0.549     5.653       -
    N_168_i                                                                                             Net       -        -       0.000     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[1]          DFFCE     D        In      -         5.653       -
    ===============================================================================================================================================================
    Total path delay (propagation time + setup) of 5.714 is 3.112(54.5%) logic and 2.602(45.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.869
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.808

        - Propagation time:                      5.648
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.840

        Number of logic level(s):                5
        Starting point:                          ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.busy_mask / Q
        Ending point:                            ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[11] / D
        The start point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK

    Instance / Net                                                                                              Pin      Pin               Arrival     No. of
    Name                                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.busy_mask               DFFCE     Q        Out     0.243     0.243       -
    busy_mask                                                                                         Net       -        -       0.535     -           2
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.un1_dmi_access_done     LUT3      I1       In      -         0.778       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.un1_dmi_access_done     LUT3      F        Out     0.570     1.348       -
    un1_dmi_access_done                                                                               Net       -        -       0.535     -           5
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_write_2          LUT4      I1       In      -         1.883       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_write_2          LUT4      F        Out     0.570     2.453       -
    is_dmi_write_2                                                                                    Net       -        -       0.535     -           9
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_write            LUT2      I1       In      -         2.988       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_write            LUT2      F        Out     0.570     3.558       -
    is_dmi_write                                                                                      Net       -        -       0.657     -           25
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i_1               LUT4      I1       In      -         4.215       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i_1               LUT4      F        Out     0.570     4.785       -
    N_311_i_1                                                                                         Net       -        -       0.401     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i                 LUT4      I2       In      -         5.186       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i                 LUT4      F        Out     0.462     5.648       -
    N_311_i                                                                                           Net       -        -       0.000     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[11]       DFFCE     D        In      -         5.648       -
    =============================================================================================================================================================
    Total path delay (propagation time + setup) of 5.709 is 3.046(53.4%) logic and 2.663(46.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.869
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.808

        - Propagation time:                      5.646
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.838

        Number of logic level(s):                5
        Starting point:                          ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[3] / Q
        Ending point:                            ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[11] / D
        The start point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK
        The end   point is clocked by            RiscV_AE250_Top|X_tck [rising] on pin CLK

    Instance / Net                                                                                            Pin      Pin               Arrival     No. of
    Name                                                                                            Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_ir[3]             DFFCE     Q        Out     0.243     0.243       -
    tap_ir[3]                                                                                       Net       -        -       0.535     -           7
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access_1_0     LUT2      I0       In      -         0.778       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access_1_0     LUT2      F        Out     0.549     1.327       -
    is_dmi_access_1                                                                                 Net       -        -       0.535     -           3
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access         LUT4      I0       In      -         1.862       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_access         LUT4      F        Out     0.549     2.411       -
    is_dmi_access                                                                                   Net       -        -       0.596     -           18
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_write          LUT2      I0       In      -         3.007       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.is_dmi_write          LUT2      F        Out     0.549     3.556       -
    is_dmi_write                                                                                    Net       -        -       0.657     -           25
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i_1             LUT4      I1       In      -         4.213       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i_1             LUT4      F        Out     0.570     4.783       -
    N_311_i_1                                                                                       Net       -        -       0.401     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i               LUT4      I2       In      -         5.184       -
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.N_311_i               LUT4      F        Out     0.462     5.646       -
    N_311_i                                                                                         Net       -        -       0.000     -           1
    ae250_chip.uncore.gen_Debug_Module\.debug_subsystem.u_jdtm.ncejdtm200_tap.tap_data_scan[11]     DFFCE     D        In      -         5.646       -
    ===========================================================================================================================================================
    Total path delay (propagation time + setup) of 5.707 is 2.983(52.3%) logic and 2.724(47.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                               Starting                                                     Arrival
    Instance                                                                   Reference     Type     Pin     Net                           Time        Slack
                                                                               Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_0_0_RNO     System        INV      O       un1_adder_op2_cry_0_0_RNO     0.000       6.890
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_1_0_RNO     System        INV      O       un1_adder_op2_cry_1_0_RNO     0.000       6.925
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_2_0_RNO     System        INV      O       un1_adder_op2_cry_2_0_RNO     0.000       6.960
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_3_0_RNO     System        INV      O       un1_adder_op2_cry_3_0_RNO     0.000       6.995
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_4_0_RNO     System        INV      O       un1_adder_op2_cry_4_0_RNO     0.000       7.030
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_5_0_RNO     System        INV      O       un1_adder_op2_cry_5_0_RNO     0.000       7.065
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_6_0_RNO     System        INV      O       un1_adder_op2_cry_6_0_RNO     0.000       7.100
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_7_0_RNO     System        INV      O       un1_adder_op2_cry_7_0_RNO     0.000       7.135
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_8_0_RNO     System        INV      O       un1_adder_op2_cry_8_0_RNO     0.000       7.170
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_9_0_RNO     System        INV      O       un1_adder_op2_cry_9_0_RNO     0.000       7.205
    =========================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                           Starting                                                Required
    Instance                                                               Reference     Type      Pin     Net                     Time         Slack
                                                                           Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_reg_mispred          System        DFFE      D       ex_mispred              14.558       6.890
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_pred_addr_op1[0]     System        DFFCE     D       ii_pred_addr_op1[0]     14.558       6.937
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_pred_addr_op1[1]     System        DFFCE     D       ii_pred_addr_op1[1]     14.558       7.084
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_taken                System        DFFE      D       ex_taken                14.558       7.460
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_wdata[0]             System        DFFE      D       alu_result[0]           14.558       8.992
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_wdata[31]            System        DFFE      D       alu_result[31]          14.558       8.995
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_wdata[30]            System        DFFE      D       alu_result[30]          14.558       9.030
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_wdata[29]            System        DFFE      D       alu_result[29]          14.558       9.065
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_wdata[28]            System        DFFE      D       alu_result[28]          14.558       9.100
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_wdata[27]            System        DFFE      D       alu_result[27]          14.558       9.135
    =================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      14.619
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         14.558

        - Propagation time:                      7.667
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 6.890

        Number of logic level(s):                37
        Starting point:                          ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_0_0_RNO / O
        Ending point:                            ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_reg_mispred / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            RiscV_AE250_Top|X_oschin [rising] on pin CLK

    Instance / Net                                                                      Pin      Pin               Arrival     No. of
    Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_0_0_RNO     INV      O        Out     0.000     0.000       -
    un1_adder_op2_cry_0_0_RNO                                                  Net      -        -       0.535     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_0_0         ALU      I3       In      -         0.535       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_0_0         ALU      COUT     Out     0.371     0.906       -
    un1_adder_op2_cry_0                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_1_0         ALU      CIN      In      -         0.906       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_1_0         ALU      COUT     Out     0.035     0.941       -
    un1_adder_op2_cry_1                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_2_0         ALU      CIN      In      -         0.941       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_2_0         ALU      COUT     Out     0.035     0.976       -
    un1_adder_op2_cry_2                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_3_0         ALU      CIN      In      -         0.976       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_3_0         ALU      COUT     Out     0.035     1.011       -
    un1_adder_op2_cry_3                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_4_0         ALU      CIN      In      -         1.011       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_4_0         ALU      COUT     Out     0.035     1.046       -
    un1_adder_op2_cry_4                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_5_0         ALU      CIN      In      -         1.046       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_5_0         ALU      COUT     Out     0.035     1.081       -
    un1_adder_op2_cry_5                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_6_0         ALU      CIN      In      -         1.081       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_6_0         ALU      COUT     Out     0.035     1.116       -
    un1_adder_op2_cry_6                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_7_0         ALU      CIN      In      -         1.116       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_7_0         ALU      COUT     Out     0.035     1.151       -
    un1_adder_op2_cry_7                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_8_0         ALU      CIN      In      -         1.151       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_8_0         ALU      COUT     Out     0.035     1.186       -
    un1_adder_op2_cry_8                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_9_0         ALU      CIN      In      -         1.186       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_9_0         ALU      COUT     Out     0.035     1.221       -
    un1_adder_op2_cry_9                                                        Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_10_0        ALU      CIN      In      -         1.221       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_10_0        ALU      COUT     Out     0.035     1.256       -
    un1_adder_op2_cry_10                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_11_0        ALU      CIN      In      -         1.256       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_11_0        ALU      COUT     Out     0.035     1.291       -
    un1_adder_op2_cry_11                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_12_0        ALU      CIN      In      -         1.291       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_12_0        ALU      COUT     Out     0.035     1.326       -
    un1_adder_op2_cry_12                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_13_0        ALU      CIN      In      -         1.326       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_13_0        ALU      COUT     Out     0.035     1.361       -
    un1_adder_op2_cry_13                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_14_0        ALU      CIN      In      -         1.361       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_14_0        ALU      COUT     Out     0.035     1.396       -
    un1_adder_op2_cry_14                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_15_0        ALU      CIN      In      -         1.396       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_15_0        ALU      COUT     Out     0.035     1.431       -
    un1_adder_op2_cry_15                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_16_0        ALU      CIN      In      -         1.431       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_16_0        ALU      COUT     Out     0.035     1.466       -
    un1_adder_op2_cry_16                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_17_0        ALU      CIN      In      -         1.466       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_17_0        ALU      COUT     Out     0.035     1.501       -
    un1_adder_op2_cry_17                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_18_0        ALU      CIN      In      -         1.501       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_18_0        ALU      COUT     Out     0.035     1.536       -
    un1_adder_op2_cry_18                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_19_0        ALU      CIN      In      -         1.536       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_19_0        ALU      COUT     Out     0.035     1.571       -
    un1_adder_op2_cry_19                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_20_0        ALU      CIN      In      -         1.571       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_20_0        ALU      COUT     Out     0.035     1.606       -
    un1_adder_op2_cry_20                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_21_0        ALU      CIN      In      -         1.606       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_21_0        ALU      COUT     Out     0.035     1.641       -
    un1_adder_op2_cry_21                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_22_0        ALU      CIN      In      -         1.641       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_22_0        ALU      COUT     Out     0.035     1.676       -
    un1_adder_op2_cry_22                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_23_0        ALU      CIN      In      -         1.676       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_23_0        ALU      COUT     Out     0.035     1.711       -
    un1_adder_op2_cry_23                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_24_0        ALU      CIN      In      -         1.711       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_24_0        ALU      COUT     Out     0.035     1.746       -
    un1_adder_op2_cry_24                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_25_0        ALU      CIN      In      -         1.746       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_25_0        ALU      COUT     Out     0.035     1.781       -
    un1_adder_op2_cry_25                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_26_0        ALU      CIN      In      -         1.781       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_26_0        ALU      COUT     Out     0.035     1.816       -
    un1_adder_op2_cry_26                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_27_0        ALU      CIN      In      -         1.816       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_27_0        ALU      COUT     Out     0.035     1.851       -
    un1_adder_op2_cry_27                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_28_0        ALU      CIN      In      -         1.851       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_28_0        ALU      COUT     Out     0.035     1.886       -
    un1_adder_op2_cry_28                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_29_0        ALU      CIN      In      -         1.886       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_29_0        ALU      COUT     Out     0.035     1.921       -
    un1_adder_op2_cry_29                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_30_0        ALU      CIN      In      -         1.921       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_30_0        ALU      COUT     Out     0.035     1.956       -
    un1_adder_op2_cry_30                                                       Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_31_0        ALU      CIN      In      -         1.956       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.un1_adder_op2_cry_31_0        ALU      SUM      Out     0.470     2.426       -
    un1_adder_op2_cry_31_0_SUM                                                 Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.cmp_lt                        LUT3     I0       In      -         2.961       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.cmp_lt                        LUT3     F        Out     0.549     3.510       -
    cmp_lt                                                                     Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.alu_br_taken_4                LUT4     I1       In      -         4.045       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.alu_br_taken_4                LUT4     F        Out     0.570     4.615       -
    N_10                                                                       Net      -        -       0.401     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.alu_br_taken_7                LUT4     I2       In      -         5.016       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_alu.alu_br_taken_7                LUT4     F        Out     0.462     5.478       -
    alu_br_taken                                                               Net      -        -       0.535     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_taken                    LUT4     I0       In      -         6.013       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_taken                    LUT4     F        Out     0.549     6.562       -
    ex_taken                                                                   Net      -        -       0.535     -           2
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_mispred                  LUT3     I1       In      -         7.097       -
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.ex_mispred                  LUT3     F        Out     0.570     7.667       -
    ex_mispred                                                                 Net      -        -       0.000     -           1
    ae250_chip.uncore.vc_core_mem.vc_core.vc_ipipe.mm_reg_mispred              DFFE     D        In      -         7.667       -
    =====================================================================================================================================
    Total path delay (propagation time + setup) of 7.728 is 4.652(60.2%) logic and 3.076(39.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:02m:28s; CPU Time elapsed 0h:02m:20s; Memory used current: 398MB peak: 554MB)

    Finished timing report (Real Time elapsed 0h:02m:28s; CPU Time elapsed 0h:02m:20s; Memory used current: 398MB peak: 554MB)

    ---------------------------------------
    Resource Usage Report for RiscV_AE250_Top

    Mapping to part: gw2a_18pbga256-8
    Cell usage:
    ALU             905 uses
    DFFC            309 uses
    DFFCE           1963 uses
    DFFE            1960 uses
    DFFNCE          1 use
    DFFP            51 uses
    DFFPE           35 uses
    DFFR            1 use
    DFFRE           491 uses
    DFFSE           1 use
    GSR             1 use
    INV             70 uses
    MUX2_LUT5       1103 uses
    MUX2_LUT6       254 uses
    MUX2_LUT7       68 uses
    MUX2_LUT8       1 use
    RAM16SDP4       20 uses
    SP              32 uses
    LUT2            1345 uses
    LUT3            4886 uses
    LUT4            6324 uses

    I/O ports: 35
    I/O primitives: 1
    TBUF           1 use

    I/O Register bits:                  0
    Register bits not including I/Os:   4812 of 15552 (30%)

    RAM/ROM usage summary
    Block Rams : 32 of 46 (69%)

    Total load per clock:
       RiscV_AE250_Top|X_oschin: 241
       RiscV_AE250_Top|X_tck: 102
       RiscV_AE250_Top|X_osclin: 3

    @S |Mapping Summary:
    Total  LUTs: 12555 (60%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:02m:29s; CPU Time elapsed 0h:02m:20s; Memory used current: 139MB peak: 554MB)

    Process took 0h:02m:29s realtime, 0h:02m:20s cputime
    # Mon Mar 30 14:10:50 2020

    ###########################################################]

`