C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\bin64\m_generic.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1   -part GW2A_18  -package PBGA256  -grade -8    -maxfan 10000 -RWCheckOnRam 1 -block -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\report\riscv_ae250_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  RiscV_AE250_Top  -implementation  rcv_1  -flow mapping  -multisrs  -ovm  E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\riscv_ae250.vm   -autoconstraint  -freq 150.000   E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synwork\riscv_ae250_prem.srd  -sap  E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\riscv_ae250.sap  -otap  E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\riscv_ae250.tap  -omap  E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\riscv_ae250.map  -devicelib  C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\lib\generic\gw2a.v  -ologparam  E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\syntmp\riscv_ae250.plg  -osyn  E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\riscv_ae250.srm  -prjdir  E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\  -prjname  Riscvae250  -log  E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\synlog\riscv_ae250_fpga_mapper.srr  -sn  2019.09  -jobname  "fpga_mapper" 
relcom:C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\rcv_1 -part GW2A_18 -package PBGA256 -grade -8 -maxfan 10000 -RWCheckOnRam 1 -block -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile ..\synlog\report\riscv_ae250_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module RiscV_AE250_Top -implementation rcv_1 -flow mapping -multisrs -ovm ..\riscv_ae250.vm -autoconstraint -freq 150.000 ..\synwork\riscv_ae250_prem.srd -sap ..\riscv_ae250.sap -otap ..\riscv_ae250.tap -omap ..\riscv_ae250.map -devicelib C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\lib\generic\gw2a.v -ologparam riscv_ae250.plg -osyn ..\riscv_ae250.srm -prjdir ..\..\ -prjname Riscvae250 -log ..\synlog\riscv_ae250_fpga_mapper.srr -sn 2019.09 -jobname "fpga_mapper"
rc:1 success:1 runtime:150
file:..\riscv_ae250.vm|io:o|time:1585548646|size:5658654|exec:0|csum:
file:..\synwork\riscv_ae250_prem.srd|io:i|time:1585548495|size:12499836|exec:0|csum:26135999F736070C8651315DD6E7C65F
file:..\riscv_ae250.sap|io:o|time:1585548500|size:311|exec:0|csum:
file:..\riscv_ae250.tap|io:o|time:0|size:-1|exec:0|csum:
file:..\riscv_ae250.map|io:o|time:1585548650|size:28|exec:0|csum:
file:C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\lib\generic\gw2a.v|io:i|time:1582921032|size:163815|exec:0|csum:9E2600B864B99F5A90D449698CC6DFCB
file:riscv_ae250.plg|io:o|time:1585548650|size:1405|exec:0|csum:
file:..\riscv_ae250.srm|io:o|time:1585548641|size:65081|exec:0|csum:
file:..\synlog\riscv_ae250_fpga_mapper.srr|io:o|time:1585548650|size:118926|exec:0|csum:
file:C:\Gowin\Gowin_V1.9.5Beta\SynplifyPro\bin64\m_generic.exe|io:i|time:1583356322|size:41925120|exec:1|csum:F16849560D7337BE2F854162B25FBD4B
