Project Settings
Project Name | Riscvae250 | Device Name | rcv_1: GOWIN-GW2A : GW2A_18
Implementation Name | rcv_1 | Top Module | RiscV_AE250_Top
Pipelining | 1 | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 1 | Disable Sequential Optimizations | 0
Clock Conversion | 1 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 26 | 5 | 0 | - | 00m:49s | - | 2020/3/30 14:07:59
(premap) | Complete | 5 | 4 | 0 | 0m:12s | 0m:13s | 380MB | 2020/3/30 14:08:20
(fpga_mapper) | Complete | 9 | 25 | 0 | 02m:20s | 02m:29s | 554MB | 2020/3/30 14:10:50
Multi-srs Generator | Complete |  |  |  | 00m:03s |  |  | 2020/3/30 14:08:04

Area Summary
I/O ports (io_port) | 35 | Non I/O Register bits (non_io_reg) | 4812 (30%)
I/O Register bits (total_io_reg) | 0 | Ultra Rams | 0
Block Rams (v_ram) | 32 (46) | Block Multipliers (dsp_used) | 0 (24)
LUTs (total_luts) | 12555 (60%) |  |

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
RiscV_AE250_Top|X_oschin | 68.4 MHz | 58.1 MHz | -2.580
RiscV_AE250_Top|X_osclin | 1402.3 MHz | 1191.9 MHz | -0.126
RiscV_AE250_Top|X_tck | 205.4 MHz | 153.1 MHz | -0.859
System | 150.0 MHz | NA | 6.890

Optimizations Summary
Combined Clock Conversion | 7 / 0 |  |