{
 "Allow_Duplicate_Modules" : false,
 "Annotated_Properties_for_Analyst" : true,
 "BACKGROUND_PROGRAMMING" : false,
 "Beta_Features_for_VHDL" : false,
 "Beta_Features_for_Verilog" : false,
 "COMPRESS" : false,
 "CRC_CHECK" : true,
 "Clock_Conversion" : true,
 "DONE" : false,
 "DOWNLOAD_SPEED" : "250/100",
 "Default_Enum_Encoding" : "default",
 "Disable_I/O_Insertion" : false,
 "Disable_Insert_Pad" : false,
 "ENCRYPTION_KEY" : false,
 "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
 "FORMAT_BINARY" : false,
 "FORMAT_TEXT" : true,
 "FSM Compiler" : true,
 "Fanout_Guide" : 10000,
 "Frequency" : "Auto",
 "Generate_Constraint_File_of_Ports" : false,
 "Generate_IBIS_File" : false,
 "Generate_Plain_Text_Timing_Report" : false,
 "Generate_Post_PNR_Simulation_Model_File" : false,
 "Generate_Post_Place_File" : false,
 "Generate_SDF_File" : false,
 "GwSyn_Loop_Limit" : 2000,
 "Implicit_Initial_Value_Support" : false,
 "IncludePath" : [

 ],
 "Initialize_Primitives" : false,
 "JTAG" : false,
 "JTAG_ENABLE" : true,
 "Loop_Limit" : 2000,
 "MODE_IO" : false,
 "MSPI" : false,
 "Multiple_File_Compilation_Unit" : true,
 "Not_place_register_to_IOB" : true,
 "Number_of_Critical_Paths" : "",
 "Number_of_Start/End_Points" : "",
 "PRINT_BSRAM_VALUE" : true,
 "Pipelining" : true,
 "Place_Option" : "1",
 "Process_Configuration_Verion" : "1.0",
 "Promote_Physical_Constraint_Warning_to_Error" : false,
 "Push_Tristates" : true,
 "READY" : false,
 "RECONFIG_N" : false,
 "Ram_RW_Check" : true,
 "Read_Write_Check_on_RAM" : true,
 "Report_Auto-Placed_Io_Information" : false,
 "Resolve_Mixed_Drivers" : false,
 "Resource_Sharing" : true,
 "Retiming" : false,
 "Route_Option" : "0",
 "Run_Timing_Driven" : true,
 "SECURE_MODE" : false,
 "SECURITY_BIT" : true,
 "SPI_FLASH_ADDR" : "00FFF000",
 "SSPI" : false,
 "Show_All_Warnings" : false,
 "Synthesis On/Off Implemented as Translate On/Off" : false,
 "Synthesize_tool" : "Synplify",
 "TopModule" : "",
 "USERCODE_CUSTOM" : false,
 "USERCODE_CUSTOM_TEXT" : "00000000",
 "USERCODE_DEFAULT" : true,
 "Update_Compile_Point_Timing_Data" : false,
 "Use_Clock_Period_for_Unconstrainted IO" : false,
 "Use_SCF" : false,
 "VHDL_2008" : false,
 "VHDL_2019" : false,
 "Verilog_Language" : "System Verilog",
 "WAKE_UP" : "0",
 "Write_Vendor_Constraint_File" : true,
 "verilogchoose" : "System Verilog 2017"
}