
module ae250_exp (CLKX, CLK, LED1, LED2, LED3, LED4, KEY1, KEY2, KEY3, KEY4, SW1, SW2, SW3, SW4, JTAG_TDI, 
        JTAG_TDO, JTAG_TMS, JTAG_TCK, SPI_CS, SPI_CLK, SPI_MISO, SPI_MOSI, J11_1, J11_2, J11_5, J11_6, J11_9, J11_10, J11_13, J11_14, 
        J11_17, J11_18, J10_1, J10_2, J10_5, J10_6, J10_9, J10_10, J10_13, J10_14, J10_17, J10_18, J4_5, J4_6, J4_7, 
        J4_8, J4_9, J4_10, J4_11, J4_12, J4_13, J4_14, J4_15, J4_16, J4_17, J4_18, J4_19, J4_20, J4_21, J4_22, 
        J4_23, J4_24, J4_25, J4_26, J4_27, J4_28, J3_3, J3_4, J3_5, J3_6, J3_7, J3_8, J3_9, J3_10, J3_11, 
        J3_12, J3_13, J3_14, J3_15, J3_16, J3_17, J3_18) ;
    input CLKX ; 
    input CLK ; 
    output LED1 ; 
    output LED2 ; 
    output LED3 ; 
    output LED4 ; 
    input KEY1 ; 
    input KEY2 ; 
    input KEY3 ; 
    input KEY4 ; 
    input SW1 ; 
    input SW2 ; 
    input SW3 ; 
    input SW4 ; 
    inout JTAG_TDI ; 
    inout JTAG_TDO ; 
    inout JTAG_TMS ; 
    inout JTAG_TCK ; 
    inout SPI_CS ; 
    inout SPI_CLK ; 
    inout SPI_MISO ; 
    inout SPI_MOSI ; 
    inout J11_1 ; 
    inout J11_2 ; 
    inout J11_5 ; 
    inout J11_6 ; 
    inout J11_9 ; 
    inout J11_10 ; 
    inout J11_13 ; 
    inout J11_14 ; 
    inout J11_17 ; 
    inout J11_18 ; 
    inout J10_1 ; 
    inout J10_2 ; 
    inout J10_5 ; 
    inout J10_6 ; 
    inout J10_9 ; 
    inout J10_10 ; 
    inout J10_13 ; 
    inout J10_14 ; 
    inout J10_17 ; 
    inout J10_18 ; 
    output J4_5 ; 
    inout J4_6 ; 
    inout J4_7 ; 
    inout J4_8 ; 
    inout J4_9 ; 
    inout J4_10 ; 
    inout J4_11 ; 
    inout J4_12 ; 
    inout J4_13 ; 
    inout J4_14 ; 
    inout J4_15 ; 
    inout J4_16 ; 
    inout J4_17 ; 
    inout J4_18 ; 
    inout J4_19 ; 
    inout J4_20 ; 
    inout J4_21 ; 
    inout J4_22 ; 
    inout J4_23 ; 
    inout J4_24 ; 
    inout J4_25 ; 
    inout J4_26 ; 
    inout J4_27 ; 
    inout J4_28 ; 
    inout J3_3 ; 
    inout J3_4 ; 
    inout J3_5 ; 
    inout J3_6 ; 
    inout J3_7 ; 
    inout J3_8 ; 
    inout J3_9 ; 
    inout J3_10 ; 
    inout J3_11 ; 
    inout J3_12 ; 
    inout J3_13 ; 
    inout J3_14 ; 
    inout J3_15 ; 
    inout J3_16 ; 
    inout J3_17 ; 
    inout J3_18 ; 
    wire hwRstn = KEY1 ; 
    wire por = KEY1 ; 
    wire sysClk ; 
    wire rtcClk ; 
    RiscV_AE250_Top iChip (.X_om(), .X_pd_pwr_off(), .X_aopd_por_b(por), .X_mpd_pwr_off(), .X_osclin(rtcClk), .X_osclio(), .X_rtc_wakeup(), .X_wakeup_in(1'b0), .X_tck(J3_9), .X_oschin(sysClk), .X_oschio(), .X_hw_rstn(hwRstn), .X_por_b(por), .X_tms(J3_7), .X_tdi(J3_5), 
                .X_tdo(J3_13), .X_trst(J3_3), .X_uart1_ctsn(), .X_uart1_rtsn(), .X_uart1_dcdn(), .X_uart1_dsrn(), .X_uart1_dtrn(), .X_uart1_out1n(), .X_uart1_out2n(), .X_uart1_rin(), .X_uart1_rxd(J4_9), .X_uart1_txd(J4_19), .ext_int_src()) ; 
    GW_PLL iPll2sysClk (.clkout(sysClk), .lock(lock), .clkoutd(rtcClk), .clkin(CLK)) ; 
    assign J3_15 = hwRstn ; 
endmodule



module GW_PLL (clkout, lock, clkoutd, clkoutd3, clkin) ;
    output clkout ; 
    output lock ; 
    output clkoutd ; 
    output clkoutd3 ; 
    input clkin ; 
    wire clkoutp_o ; 
    wire gw_gnd ; 
    assign gw_gnd = 1'b0 ; 
    PLL pll_inst (.CLKOUT(clkout), .LOCK(lock), .CLKOUTP(clkoutp_o), .CLKOUTD(clkoutd), .CLKOUTD3(clkoutd3), .RESET(gw_gnd), .RESET_P(gw_gnd), .RESET_I(gw_gnd), .RESET_S(gw_gnd), .CLKIN(clkin), .CLKFB(gw_gnd), .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), 
                .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})) ; 
    defparam pll_inst.FCLKIN = "50" ; 
    defparam pll_inst.DYN_IDIV_SEL = "false" ; 
    defparam pll_inst.IDIV_SEL = 4 ; 
    defparam pll_inst.DYN_FBDIV_SEL = "false" ; 
    defparam pll_inst.FBDIV_SEL = 0 ; 
    defparam pll_inst.DYN_ODIV_SEL = "false" ; 
    defparam pll_inst.ODIV_SEL = 128 ; 
    defparam pll_inst.PSDA_SEL = "0000" ; 
    defparam pll_inst.DYN_DA_EN = "false" ; 
    defparam pll_inst.DUTYDA_SEL = "1000" ; 
    defparam pll_inst.CLKOUT_FT_DIR = 1'b1 ; 
    defparam pll_inst.CLKOUTP_FT_DIR = 1'b1 ; 
    defparam pll_inst.CLKOUT_DLY_STEP = 0 ; 
    defparam pll_inst.CLKOUTP_DLY_STEP = 0 ; 
    defparam pll_inst.CLKFB_SEL = "internal" ; 
    defparam pll_inst.CLKOUT_BYPASS = "false" ; 
    defparam pll_inst.CLKOUTP_BYPASS = "false" ; 
    defparam pll_inst.CLKOUTD_BYPASS = "false" ; 
    defparam pll_inst.DYN_SDIV_SEL = 128 ; 
    defparam pll_inst.CLKOUTD_SRC = "CLKOUT" ; 
    defparam pll_inst.CLKOUTD3_SRC = "CLKOUT" ; 
    defparam pll_inst.DEVICE = "GW2A-18" ; 
endmodule


