@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":978:22:978:26|Converting bidirection inout port X_tdo to output port. Because it's a pure output port
@W: BN709 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":979:22:979:27|Converting bidirection inout port X_trst to output port. Because it's a pure output port
@W: MO112 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":2128:16:2128:51|Deleting tristate instance un1_X_tdi (in view: work.RiscV_AE250_Top(verilog)) on net X_tdi (in view: work.RiscV_AE250_Top(verilog)) because its enable is connected to 0.
@W: MO112 :"c:\gowin\gowin_v1.9.5beta\ide\ipcore\riscvn25\data\ae250_chip_wrap.v":2132:14:2132:49|Deleting tristate instance un1_X_tms (in view: work.RiscV_AE250_Top(verilog)) on net X_tms (in view: work.RiscV_AE250_Top(verilog)) because its enable is connected to 0.
