@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file E:\W_File\RISC_V\Ref_Design\project\Ref_Design\src\riscv_ae250\temp\Riscvae250\rcv_1\riscv_ae250.sap.
