# Written by Synplify Pro version mapgw, Build 1564R. Synopsys Run ID: sid1585548501 
# Top Level Design Parameters 

# Clocks 
create_clock -period 14.619 -waveform {0.000 7.309} -name {RiscV_AE250_Top|X_oschin} [get_ports {X_oschin}] 
create_clock -period 4.869 -waveform {0.000 2.435} -name {RiscV_AE250_Top|X_tck} [get_ports {X_tck}] 
create_clock -period 0.713 -waveform {0.000 0.357} -name {RiscV_AE250_Top|X_osclin} [get_ports {X_osclin}] 

# Virtual Clocks 

# Generated Clocks 

# Paths Between Clocks 

# Multicycle Constraints 

# Point-to-point Delay Constraints 

# False Path Constraints 

# Output Load Constraints 

# Driving Cell Constraints 

# Input Delay Constraints 

# Output Delay Constraints 

# Wire Loads 

# Other Constraints 

# syn_hier Attributes 

# set_case Attributes 

# Clock Delay Constraints 
set Autoconstr_clkgroup_0 [list RiscV_AE250_Top|X_oschin]
set Autoconstr_clkgroup_1 [list RiscV_AE250_Top|X_tck]
set Autoconstr_clkgroup_2 [list RiscV_AE250_Top|X_osclin]
set_clock_groups -asynchronous -group $Autoconstr_clkgroup_0 -group $Autoconstr_clkgroup_1 -group $Autoconstr_clkgroup_2

# syn_mode Attributes 

# Cells 

# Port DRC Rules 

# Input Transition Constraints 

# Unused constraints (intentionally commented out) 


# Non-forward-annotatable constraints (intentionally commented out) 

# Block Path constraints 

