Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW2A : GW2A_18
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:05s - 2019/11/12
10:09:40
(premap)Complete 6 0 0 0m:02s 0m:03s 227MB 2019/11/12
10:09:45
(fpga_mapper)Complete 9 2 0 0m:09s 0m:10s 258MB 2019/11/12
10:09:56
Multi-srs Generator Complete00m:01s2019/11/12
10:09:41

Area Summary
I/O ports (io_port) 160 Non I/O Register bits (non_io_reg) 699 (4%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 8 (46) Block Multipliers (dsp_used) 0 (24)
LUTs (total_luts) 569 (2%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i226.8 MHz192.8 MHz-0.778
ao_top_0|control[0]157.1 MHz133.6 MHz-1.123
System150.0 MHz227.3 MHz2.266

Optimizations Summary
Combined Clock Conversion 2 / 0