Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\src\button.v
C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\src\sdio_sdr104_slave_controller\sdio_sdr104_slave_controller.v
C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\src\top.v
C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\src\user_cpu_slave_reg_if.v
C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\src\user_sdio_cmd52_if.v
C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v
C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\src\user_tuning_pattern.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.10
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Mon Dec 05 10:29:37 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 130.625MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 130.625MB
    Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 130.625MB
    Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.164s, Peak memory usage = 130.625MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 130.625MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 130.625MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 130.625MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 130.625MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 130.625MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 130.625MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 130.625MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 135.395MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.171s, Peak memory usage = 135.395MB
Generate output files:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.271s, Peak memory usage = 135.395MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 135.395MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 127
I/O Buf 127
    IBUF 5
    OBUF 117
    IOBUF 5
Register 2001
    DFF 126
    DFFE 25
    DFFR 14
    DFFRE 4
    DFFP 70
    DFFPE 52
    DFFC 516
    DFFCE 1186
    DFFNP 2
    DFFNC 5
    DFFNCE 1
LUT 3639
    LUT2 654
    LUT3 679
    LUT4 2306
ALU 145
    ALU 145
INV 4
    INV 4
CLOCK 1
    CLKDIV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3788(3643 LUTs, 145 ALUs) / 20736 18%
Register 2001 / 16173 12%
  --Register as Latch 0 / 16173 0%
  --Register as FF 2001 / 16173 12%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sdio_clk Base 10.000 100.0 0.000 5.000 sdio_clk_ibuf/I
cpu_clk Base 10.000 100.0 0.000 5.000 cpu_clk_ibuf/I
u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 sdio_clk_ibuf/I sdio_clk u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 sdio_clk 100.0(MHz) 272.3(MHz) 5 TOP
2 cpu_clk 100.0(MHz) 236.9(MHz) 6 TOP
3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk 50.0(MHz) 179.0(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.923
Data Arrival Time 16.357
Data Required Time 20.281
From u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1
To u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1
Launch Clk cpu_clk[R]
Latch Clk u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cpu_clk
10.000 0.000 tCL RR 1 cpu_clk_ibuf/I
10.682 0.683 tINS RR 215 cpu_clk_ibuf/O
10.863 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/CLK
11.094 0.232 tC2Q RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/Q
11.332 0.237 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/I0
11.880 0.549 tINS FR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/COUT
11.880 0.000 tNET RR 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/CIN
11.916 0.035 tINS RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/COUT
11.916 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/CIN
11.951 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/COUT
11.951 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/CIN
11.986 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/COUT
11.986 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/CIN
12.021 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/COUT
12.021 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/CIN
12.057 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/COUT
12.056 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/CIN
12.092 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/COUT
12.092 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/CIN
12.127 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/COUT
12.127 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/CIN
12.162 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/COUT
12.162 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/CIN
12.197 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/COUT
12.197 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/CIN
12.233 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/COUT
12.233 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/CIN
12.268 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/COUT
12.268 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/CIN
12.303 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/COUT
12.303 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/CIN
12.338 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/COUT
12.575 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/I2
13.028 0.453 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/F
13.265 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/I1
13.820 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/F
14.057 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/I1
14.612 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/F
14.849 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/n129_s6/I0
15.366 0.517 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/n129_s6/F
15.603 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/n129_s5/I0
16.120 0.517 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/n129_s5/F
16.357 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk
20.170 0.170 tCL RR 1717 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT
20.351 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1/CLK
20.316 -0.035 tUnc u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1
20.281 -0.035 tSu 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1
Path Statistics:
Clock Skew: -0.512
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.604, 65.585%; route: 1.659, 30.193%; tC2Q: 0.232, 4.222%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 3.987
Data Arrival Time 16.293
Data Required Time 20.281
From u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1
To u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1
Launch Clk cpu_clk[R]
Latch Clk u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cpu_clk
10.000 0.000 tCL RR 1 cpu_clk_ibuf/I
10.682 0.683 tINS RR 215 cpu_clk_ibuf/O
10.863 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/CLK
11.094 0.232 tC2Q RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/Q
11.332 0.237 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/I0
11.880 0.549 tINS FR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/COUT
11.880 0.000 tNET RR 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/CIN
11.916 0.035 tINS RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/COUT
11.916 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/CIN
11.951 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/COUT
11.951 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/CIN
11.986 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/COUT
11.986 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/CIN
12.021 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/COUT
12.021 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/CIN
12.057 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/COUT
12.056 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/CIN
12.092 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/COUT
12.092 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/CIN
12.127 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/COUT
12.127 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/CIN
12.162 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/COUT
12.162 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/CIN
12.197 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/COUT
12.197 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/CIN
12.233 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/COUT
12.233 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/CIN
12.268 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/COUT
12.268 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/CIN
12.303 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/COUT
12.303 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/CIN
12.338 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/COUT
12.575 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/I2
13.028 0.453 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/F
13.265 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/I1
13.820 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/F
14.057 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/I1
14.612 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/F
14.849 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/n130_s6/I0
15.366 0.517 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/n130_s6/F
15.603 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/n130_s5/I2
16.056 0.453 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/n130_s5/F
16.293 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk
20.170 0.170 tCL RR 1717 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT
20.351 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1/CLK
20.316 -0.035 tUnc u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1
20.281 -0.035 tSu 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1
Path Statistics:
Clock Skew: -0.512
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.540, 65.179%; route: 1.659, 30.549%; tC2Q: 0.232, 4.272%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 4.035
Data Arrival Time 16.245
Data Required Time 20.281
From u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1
To u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1
Launch Clk cpu_clk[R]
Latch Clk u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cpu_clk
10.000 0.000 tCL RR 1 cpu_clk_ibuf/I
10.682 0.683 tINS RR 215 cpu_clk_ibuf/O
10.863 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/CLK
11.094 0.232 tC2Q RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/Q
11.332 0.237 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/I0
11.880 0.549 tINS FR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/COUT
11.880 0.000 tNET RR 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/CIN
11.916 0.035 tINS RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/COUT
11.916 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/CIN
11.951 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/COUT
11.951 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/CIN
11.986 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/COUT
11.986 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/CIN
12.021 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/COUT
12.021 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/CIN
12.057 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/COUT
12.056 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/CIN
12.092 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/COUT
12.092 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/CIN
12.127 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/COUT
12.127 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/CIN
12.162 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/COUT
12.162 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/CIN
12.197 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/COUT
12.197 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/CIN
12.233 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/COUT
12.233 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/CIN
12.268 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/COUT
12.268 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/CIN
12.303 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/COUT
12.303 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/CIN
12.338 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/COUT
12.575 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/I2
13.028 0.453 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/F
13.265 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/I1
13.820 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/F
14.057 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/I1
14.612 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/F
14.849 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s6/I0
15.366 0.517 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s6/F
15.603 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s3/I2
16.065 0.462 tINS FR 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s3/F
16.245 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk
20.170 0.170 tCL RR 1717 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT
20.351 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1/CLK
20.316 -0.035 tUnc u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1
20.281 -0.035 tSu 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_2_s1
Path Statistics:
Clock Skew: -0.512
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.549, 65.927%; route: 1.602, 29.763%; tC2Q: 0.232, 4.310%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 4.035
Data Arrival Time 16.245
Data Required Time 20.281
From u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1
To u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s1
Launch Clk cpu_clk[R]
Latch Clk u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cpu_clk
10.000 0.000 tCL RR 1 cpu_clk_ibuf/I
10.682 0.683 tINS RR 215 cpu_clk_ibuf/O
10.863 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/CLK
11.094 0.232 tC2Q RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/Q
11.332 0.237 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/I0
11.880 0.549 tINS FR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/COUT
11.880 0.000 tNET RR 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/CIN
11.916 0.035 tINS RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/COUT
11.916 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/CIN
11.951 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/COUT
11.951 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/CIN
11.986 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/COUT
11.986 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/CIN
12.021 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/COUT
12.021 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/CIN
12.057 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/COUT
12.056 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/CIN
12.092 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/COUT
12.092 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/CIN
12.127 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/COUT
12.127 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/CIN
12.162 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/COUT
12.162 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/CIN
12.197 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/COUT
12.197 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/CIN
12.233 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/COUT
12.233 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/CIN
12.268 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/COUT
12.268 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/CIN
12.303 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/COUT
12.303 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/CIN
12.338 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/COUT
12.575 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/I2
13.028 0.453 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/F
13.265 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/I1
13.820 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/F
14.057 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/I1
14.612 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/F
14.849 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s6/I0
15.366 0.517 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s6/F
15.603 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s3/I2
16.065 0.462 tINS FR 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s3/F
16.245 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk
20.170 0.170 tCL RR 1717 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT
20.351 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s1/CLK
20.316 -0.035 tUnc u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s1
20.281 -0.035 tSu 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s1
Path Statistics:
Clock Skew: -0.512
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.549, 65.927%; route: 1.602, 29.763%; tC2Q: 0.232, 4.310%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 4.035
Data Arrival Time 16.245
Data Required Time 20.281
From u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1
To u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1
Launch Clk cpu_clk[R]
Latch Clk u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 cpu_clk
10.000 0.000 tCL RR 1 cpu_clk_ibuf/I
10.682 0.683 tINS RR 215 cpu_clk_ibuf/O
10.863 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/CLK
11.094 0.232 tC2Q RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_slv_cpu_if/fbr1_max_blk_size_1_s1/Q
11.332 0.237 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/I0
11.880 0.549 tINS FR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s33/COUT
11.880 0.000 tNET RR 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/CIN
11.916 0.035 tINS RF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s34/COUT
11.916 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/CIN
11.951 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s35/COUT
11.951 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/CIN
11.986 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s36/COUT
11.986 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/CIN
12.021 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s37/COUT
12.021 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/CIN
12.057 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s38/COUT
12.056 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/CIN
12.092 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s39/COUT
12.092 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/CIN
12.127 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s40/COUT
12.127 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/CIN
12.162 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s41/COUT
12.162 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/CIN
12.197 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s42/COUT
12.197 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/CIN
12.233 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s43/COUT
12.233 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/CIN
12.268 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s44/COUT
12.268 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/CIN
12.303 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s45/COUT
12.303 0.000 tNET FF 2 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/CIN
12.338 0.035 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_cmd_dec/n1005_s46/COUT
12.575 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/I2
13.028 0.453 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s11/F
13.265 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/I1
13.820 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_card_fixed_regs/card_st_out_of_range_s6/F
14.057 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/I1
14.612 0.555 tINS FF 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s10/F
14.849 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s6/I0
15.366 0.517 tINS FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s6/F
15.603 0.237 tNET FF 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s3/I2
16.065 0.462 tINS FR 3 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_0_s3/F
16.245 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT.default_gen_clk
20.170 0.170 tCL RR 1717 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_if/clkdiv_inst/CLKOUT
20.351 0.180 tNET RR 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1/CLK
20.316 -0.035 tUnc u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1
20.281 -0.035 tSu 1 u_sdio_slave_ctrl/u_sdio_slave_ctrl/u_sdio_biu/io_current_state_1_s1
Path Statistics:
Clock Skew: -0.512
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.549, 65.927%; route: 1.602, 29.763%; tC2Q: 0.232, 4.310%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%