#Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019 #install: D:\Gowin\sdio_sweg\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-050 # Tue Nov 12 10:07:45 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\sdio_slave_controller\sdio_slave_controller.v" (library work) @I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\button.v" (library work) @I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\top.v" (library work) @I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_cpu_slave_reg_if.v" (library work) @I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd52_if.v" (library work) @I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v" (library work) @I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_tuning_pattern.v" (library work) Verilog syntax check successful! Selecting top level module top @N:CG364 : gw2a.v(1908) | Synthesizing module GSR in library work. Running optimization stage 1 on GSR ....... Running optimization stage 1 on LUT3 ....... Running optimization stage 1 on LUT4 ....... Running optimization stage 1 on LUT2 ....... Running optimization stage 1 on DFFNP ....... Running optimization stage 1 on DFFNC ....... Running optimization stage 1 on GND ....... Running optimization stage 1 on VCC ....... Running optimization stage 1 on \~sdio_if.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on MUX2_LUT5 ....... Running optimization stage 1 on INV ....... Running optimization stage 1 on DFFC ....... Running optimization stage 1 on DFFCE ....... Running optimization stage 1 on DFFP ....... Running optimization stage 1 on DFFPE ....... Running optimization stage 1 on ALU ....... Running optimization stage 1 on \~cmd_dec.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on MUX2_LUT6 ....... Running optimization stage 1 on \~sdio_biu.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on \~card_fixed_regs.SDIO_Slave_Controller_Top__16744448_0_1_2_3_4_5 ....... Running optimization stage 1 on \~crc7_chk.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on \~resp_gen.SDIO_Slave_Controller_Top__Z1 ....... Running optimization stage 1 on \~resp_conv.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on MUX2_LUT7 ....... Running optimization stage 1 on DFFNCE ....... Running optimization stage 1 on \~fn0_reg.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on \~slv_cpu_if.SDIO_Slave_Controller_Top__3_5_4 ....... Running optimization stage 1 on \~cmd53_ctrl.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on \~crc16_gen.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on \~crc16_gen.SDIO_Slave_Controller_Top__3 ....... Running optimization stage 1 on \~crc16_gen.SDIO_Slave_Controller_Top__4 ....... Running optimization stage 1 on \~crc16_gen.SDIO_Slave_Controller_Top__5 ....... Running optimization stage 1 on \~cmd53_tx_rx.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on \~cis_fnx_if.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on \~irq_gen.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on \~cmd19_tx.SDIO_Slave_Controller_Top_ ....... Running optimization stage 1 on \~sdio_slave_ctrl.SDIO_Slave_Controller_Top_ ....... @N:CG364 : sdio_slave_controller.v(51061) | Synthesizing module SDIO_Slave_Controller_Top in library work. Running optimization stage 1 on SDIO_Slave_Controller_Top ....... @N:CG364 : user_sdio_cmd53_if.v(1) | Synthesizing module user_sdio_cmd53_if in library work. @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_Z1 Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_Z1 ....... @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000001100 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100100101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_Z2 Running optimization stage 1 on syn_hyper_source_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_Z2 ....... Running optimization stage 1 on user_sdio_cmd53_if_xmr0 ....... @W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_wr_en_d1. Make sure that there are no unused intermediate registers. @W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_rd_en_d1. Make sure that there are no unused intermediate registers. @W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_fn_num_d1. Make sure that there are no unused intermediate registers. @W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_addr_d1[16:0]. Make sure that there are no unused intermediate registers. @W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_op_code_d1. Make sure that there are no unused intermediate registers. @W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_wr_end_d1. Make sure that there are no unused intermediate registers. @W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_wr_ok_d1. Make sure that there are no unused intermediate registers. @W:CL190 : user_sdio_cmd53_if.v(209) | Optimizing register bit user_cmd53_rd_data_reg[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_sdio_cmd53_if.v(209) | Optimizing register bit user_cmd53_rd_data_reg[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_sdio_cmd53_if.v(209) | Optimizing register bit user_cmd53_rd_data_reg[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 7 of user_cmd53_rd_data_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 4 of user_cmd53_rd_data_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 1 of user_cmd53_rd_data_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : user_sdio_cmd52_if.v(1) | Synthesizing module user_sdio_cmd52_if in library work. @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100110101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_Z3 Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_Z3 ....... @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101000101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_Z4 Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_Z4 ....... @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_Z5 Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_Z5 ....... @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101100101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_Z6 Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_Z6 ....... @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000010001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101110101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_Z7 Running optimization stage 1 on syn_hyper_source_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_Z7 ....... @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000001000 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001110000101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_Z8 Running optimization stage 1 on syn_hyper_source_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_Z8 ....... @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000001000 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001110010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_Z9 Running optimization stage 1 on syn_hyper_source_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_Z9 ....... @N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111011000010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 Generated name = syn_hyper_source_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_Z10 Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_Z10 ....... Running optimization stage 1 on user_sdio_cmd52_if_xmr1 ....... @W:CL190 : user_sdio_cmd52_if.v(86) | Optimizing register bit user_cmd52_read_reg[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_sdio_cmd52_if.v(86) | Optimizing register bit user_cmd52_read_reg[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_sdio_cmd52_if.v(86) | Optimizing register bit user_cmd52_read_reg[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_sdio_cmd52_if.v(86) | Optimizing register bit user_cmd52_read_reg[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_sdio_cmd52_if.v(99) | Optimizing register bit user_cmd52_write_return_reg[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_sdio_cmd52_if.v(99) | Optimizing register bit user_cmd52_write_return_reg[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_sdio_cmd52_if.v(99) | Optimizing register bit user_cmd52_write_return_reg[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : user_sdio_cmd52_if.v(86) | Pruning register bit 7 of user_cmd52_read_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : user_sdio_cmd52_if.v(86) | Pruning register bit 5 of user_cmd52_read_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : user_sdio_cmd52_if.v(86) | Pruning register bits 1 to 0 of user_cmd52_read_reg[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : user_sdio_cmd52_if.v(99) | Pruning register bits 6 to 5 of user_cmd52_write_return_reg[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : user_sdio_cmd52_if.v(99) | Pruning register bit 2 of user_cmd52_write_return_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : user_tuning_pattern.v(1) | Synthesizing module user_tuning_pattern in library work. Running optimization stage 1 on user_tuning_pattern ....... @N:CG364 : button.v(1) | Synthesizing module deUstb in library work. Running optimization stage 1 on deUstb ....... @N:CG364 : user_cpu_slave_reg_if.v(1) | Synthesizing module user_cpu_slave_reg_if in library work. @N:CG179 : user_cpu_slave_reg_if.v(89) | Removing redundant assignment. Running optimization stage 1 on user_cpu_slave_reg_if ....... @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_addr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_addr[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_addr[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_addr[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 31 to 28 of slv_cpu_wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 26 to 25 of slv_cpu_wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 23 to 15 of slv_cpu_wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 10 to 1 of slv_cpu_wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 7 to 6 of slv_cpu_addr[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 1 to 0 of slv_cpu_addr[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : top.v(2) | Synthesizing module top in library work. @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100110101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_5s_1_Z11 Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_5s_1_Z11 ....... @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101000101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_5s_1_Z12 Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_5s_1_Z12 ....... @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_5s_1_Z13 Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_5s_1_Z13 ....... @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101100101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_5s_1_Z14 Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_5s_1_Z14 ....... @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000010001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101110101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_5s_1_Z15 Running optimization stage 1 on syn_hyper_connect_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_5s_1_Z15 ....... @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000001000 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001110000101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_5s_1_Z16 Running optimization stage 1 on syn_hyper_connect_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_5s_1_Z16 ....... @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000001000 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001110010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_5s_1_Z17 Running optimization stage 1 on syn_hyper_connect_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_5s_1_Z17 ....... @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111011000010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_5s_1_Z18 Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_5s_1_Z18 ....... @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000000001 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_5s_1_Z19 Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_5s_1_Z19 ....... @N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__. w=32'b00000000000000000000000000001100 tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100100101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001 dflt=32'b00000000000000000000000000000101 mustconnect=1'b1 Generated name = syn_hyper_connect_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_5s_1_Z20 Running optimization stage 1 on syn_hyper_connect_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_5s_1_Z20 ....... Running optimization stage 1 on top ....... Running optimization stage 2 on syn_hyper_connect_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_5s_1_Z20 ....... Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_5s_1_Z19 ....... Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_5s_1_Z18 ....... Running optimization stage 2 on syn_hyper_connect_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_5s_1_Z17 ....... Running optimization stage 2 on syn_hyper_connect_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_5s_1_Z16 ....... Running optimization stage 2 on syn_hyper_connect_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_5s_1_Z15 ....... Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_5s_1_Z14 ....... Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_5s_1_Z13 ....... Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_5s_1_Z12 ....... Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_5s_1_Z11 ....... Running optimization stage 2 on top ....... Running optimization stage 2 on user_cpu_slave_reg_if ....... @N:CL159 : user_cpu_slave_reg_if.v(3) | Input cpu_rst is unused. @N:CL159 : user_cpu_slave_reg_if.v(10) | Input slv_cpu_rd_data is unused. @N:CL159 : user_cpu_slave_reg_if.v(12) | Input slv_cpu_err is unused. Running optimization stage 2 on deUstb ....... Running optimization stage 2 on user_tuning_pattern ....... Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_Z10 ....... Running optimization stage 2 on syn_hyper_source_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_Z9 ....... Running optimization stage 2 on syn_hyper_source_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_Z8 ....... Running optimization stage 2 on syn_hyper_source_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_Z7 ....... Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_Z6 ....... Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_Z5 ....... Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_Z4 ....... Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_Z3 ....... Running optimization stage 2 on user_sdio_cmd52_if_xmr1 ....... @W:CL279 : user_sdio_cmd52_if.v(86) | Pruning register bits 4 to 3 of user_cmd52_read_reg[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : user_sdio_cmd52_if.v(99) | Pruning register bit 1 of user_cmd52_write_return_reg[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : user_sdio_cmd52_if.v(99) | Pruning register bit 4 of user_cmd52_write_return_reg[4:3]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Running optimization stage 2 on syn_hyper_source_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_Z2 ....... Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_Z1 ....... Running optimization stage 2 on user_sdio_cmd53_if_xmr0 ....... @N:CL201 : user_sdio_cmd53_if.v(102) | Trying to extract state machine for register c_state. Extracted state machine for register c_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 3 of user_cmd53_rd_data_reg[3:2]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 6 of user_cmd53_rd_data_reg[6:5]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL159 : user_sdio_cmd53_if.v(9) | Input sdio_cmd53_fn_num is unused. @N:CL159 : user_sdio_cmd53_if.v(10) | Input sdio_cmd53_addr is unused. @N:CL159 : user_sdio_cmd53_if.v(12) | Input sdio_cmd53_op_code is unused. @N:CL159 : user_sdio_cmd53_if.v(15) | Input sdio_cmd53_wr_data is unused. @N:CL159 : user_sdio_cmd53_if.v(17) | Input sdio_cmd53_wr_ok is unused. @N:CL159 : user_sdio_cmd53_if.v(23) | Input sdio_cmd53_rd_end is unused. Running optimization stage 2 on SDIO_Slave_Controller_Top ....... @W:CL246 : sdio_slave_controller.v(51150) | Input port bits 1 to 0 of slv_cpu_addr[7:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on \~sdio_slave_ctrl.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on \~cmd19_tx.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on \~irq_gen.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on \~cis_fnx_if.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on \~cmd53_tx_rx.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on \~crc16_gen.SDIO_Slave_Controller_Top__5 ....... Running optimization stage 2 on \~crc16_gen.SDIO_Slave_Controller_Top__4 ....... Running optimization stage 2 on \~crc16_gen.SDIO_Slave_Controller_Top__3 ....... Running optimization stage 2 on \~crc16_gen.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on \~cmd53_ctrl.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on \~slv_cpu_if.SDIO_Slave_Controller_Top__3_5_4 ....... Running optimization stage 2 on \~fn0_reg.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on DFFNCE ....... Running optimization stage 2 on MUX2_LUT7 ....... Running optimization stage 2 on \~resp_conv.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on \~resp_gen.SDIO_Slave_Controller_Top__Z1 ....... Running optimization stage 2 on \~crc7_chk.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on \~card_fixed_regs.SDIO_Slave_Controller_Top__16744448_0_1_2_3_4_5 ....... Running optimization stage 2 on \~sdio_biu.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on MUX2_LUT6 ....... Running optimization stage 2 on \~cmd_dec.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on ALU ....... Running optimization stage 2 on DFFPE ....... Running optimization stage 2 on DFFP ....... Running optimization stage 2 on DFFCE ....... Running optimization stage 2 on DFFC ....... Running optimization stage 2 on INV ....... Running optimization stage 2 on MUX2_LUT5 ....... Running optimization stage 2 on \~sdio_if.SDIO_Slave_Controller_Top_ ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on DFFNC ....... Running optimization stage 2 on DFFNP ....... Running optimization stage 2 on LUT2 ....... Running optimization stage 2 on LUT4 ....... Running optimization stage 2 on LUT3 ....... Running optimization stage 2 on GSR ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 129MB peak: 130MB) Process took 0h:00m:05s realtime, 0h:00m:05s cputime Process completed successfully. # Tue Nov 12 10:07:50 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode @N:NF107 : top.v(2) | Selected library: work cell: top view verilog as top level @N:NF107 : top.v(2) | Selected library: work cell: top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Nov 12 10:07:51 2019 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: sdio_test_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 18MB peak: 19MB) Process took 0h:00m:05s realtime, 0h:00m:05s cputime Process completed successfully. # Tue Nov 12 10:07:51 2019 ###########################################################]