#Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019
#install: D:\Gowin\sdio_sweg\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-050

# Tue Nov 12 10:09:35 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_0\gw_ao_parameter.v" (library work)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_0\gw_ao_top_define.v" (library work)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_0\gw_ao_expression.v" (library work)
@I::"D:\Gowin\sdio_sweg\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
@I::"D:\Gowin\sdio_sweg\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
@I::"D:\Gowin\sdio_sweg\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
@W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
@I::"D:\Gowin\sdio_sweg\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
@W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
@I::"D:\Gowin\sdio_sweg\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
@W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
@W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
@W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
@W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
@W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
@W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
@W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
@W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
@W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
@W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
@W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
@W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
@W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
@W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
@W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
@W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
@W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
@W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
@W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
@W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
Verilog syntax check successful!
@N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
Selecting top level module ao_top_0
Running optimization stage 1 on ao_mem_ctrl_0_1024s_140s_10s .......
Running optimization stage 1 on ao_crc32_0 .......
Running optimization stage 1 on ao_match_0_0s_10s_140s_1_1_0_1_2_3_4 .......
Running optimization stage 1 on ao_top_0 .......
Running optimization stage 2 on ao_match_0_0s_10s_140s_1_1_0_1_2_3_4 .......
Running optimization stage 2 on ao_top_0 .......
Extracted state machine for register module_state
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1001
   1010
   1011
Running optimization stage 2 on ao_crc32_0 .......
Running optimization stage 2 on ao_mem_ctrl_0_1024s_140s_10s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 113MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 12 10:09:38 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 12 10:09:40 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  ao_0_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:01s; Memory used current: 19MB peak: 19MB)

Process took 0h:00m:03s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 12 10:09:40 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 90MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 12 10:09:41 2019

###########################################################]


Premap Report



# Tue Nov 12 10:09:42 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A:MF827 :  | No constraint file specified. 
Linked File:  ao_0_scck.rpt
Printing clock  summary report in "C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)

@N:BN133 :  | Ignoring syn_hier=hard property on top-level design. 

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1001 -> 00100000000
   1010 -> 01000000000
   1011 -> 10000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)



Clock Summary
******************

          Start                   Requested     Requested     Clock        Clock                     Clock
Level     Clock                   Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------------------
0 -       ao_top_0|control[0]     186.5 MHz     5.362         inferred     Autoconstr_clkgroup_1     652  
                                                                                                          
0 -       ao_top_0|clk_i          198.1 MHz     5.048         inferred     Autoconstr_clkgroup_0     331  
==========================================================================================================



Clock Load Summary
***********************

                        Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin       
Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example        
--------------------------------------------------------------------------------------------------------------------------------------
ao_top_0|control[0]     652       control[0](port)     data_register[160:0].C                   -                 -                   
                                                                                                                                      
ao_top_0|clk_i          331       clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
======================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 844 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       ENCRYPTED           port                   192        ENCRYPTED      
ClockId_0_1       ENCRYPTED           IO_port                652        ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_0\rev_1\ao_0.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 225MB peak: 225MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 225MB peak: 226MB)


Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 227MB)

Process took 0h:00m:03s realtime, 0h:00m:02s cputime
# Tue Nov 12 10:09:46 2019

###########################################################]


Map & Optimize Report



# Tue Nov 12 10:09:46 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 218MB peak: 218MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)


Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 232MB peak: 232MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)


Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 233MB peak: 233MB)


Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 255MB peak: 255MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:04s		    -2.87ns		 631 /       697
   2		0h:00m:04s		    -2.87ns		 612 /       697
   3		0h:00m:04s		    -2.73ns		 612 /       697
Timing driven replication report
Added 2 Registers via timing driven replication
Added 2 LUTs via timing driven replication

   4		0h:00m:05s		    -2.75ns		 618 /       699
   5		0h:00m:05s		    -2.87ns		 620 /       699
   6		0h:00m:05s		    -2.32ns		 620 /       699
   7		0h:00m:05s		    -2.59ns		 620 /       699
   8		0h:00m:05s		    -2.32ns		 622 /       699
   9		0h:00m:05s		    -2.42ns		 622 /       699


  10		0h:00m:05s		    -2.29ns		 623 /       699

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 256MB peak: 256MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 256MB peak: 256MB)


Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 183MB peak: 258MB)

Writing Analyst data base C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 257MB peak: 258MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 258MB peak: 258MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 258MB peak: 258MB)


Start final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 254MB peak: 258MB)

@W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 4.41ns. Please declare a user-defined clock on port clk_i. 
@W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 6.36ns. Please declare a user-defined clock on port control[0]. 


##### START OF TIMING REPORT #####[
# Timing report written on Tue Nov 12 10:09:56 2019
#


Top view:               ao_top_0
Requested Frequency:    157.1 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.123

                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------
ao_top_0|clk_i          226.8 MHz     192.8 MHz     4.408         5.186         -0.778     inferred     Autoconstr_clkgroup_0
ao_top_0|control[0]     157.1 MHz     133.6 MHz     6.364         7.488         -1.123     inferred     Autoconstr_clkgroup_1
System                  150.0 MHz     227.3 MHz     6.667         4.400         2.266      system       system_clkgroup      
=============================================================================================================================





Clock Relationships
*******************

Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------
Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------
System               ao_top_0|clk_i       |  4.408       2.266   |  No paths    -      |  No paths    -      |  No paths    -    
System               ao_top_0|control[0]  |  6.364       4.448   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       System               |  4.408       3.569   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       ao_top_0|clk_i       |  4.408       -0.778  |  4.408       3.569  |  No paths    -      |  2.204       1.365
ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  System               |  6.364       5.586   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|control[0]  |  6.364       -1.123  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ao_top_0|clk_i
====================================



Starting Points with Worst Slack
********************************

                                      Starting                                                                 Arrival           
Instance                              Reference          Type     Pin     Net                                  Time        Slack 
                                      Clock                                                                                      
---------------------------------------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]      ao_top_0|clk_i     DFFC     Q       internal_reg_force_triger_syn[1]     0.243       -0.778
genblk1\.u_ao_match_0.match_sep       ao_top_0|clk_i     DFFC     Q       match                                0.243       -0.757
capture_window_sel[1]                 ao_top_0|clk_i     DFFC     Q       capture_window_sel[1]                0.243       -0.738
capture_window_sel[0]                 ao_top_0|clk_i     DFFC     Q       capture_window_sel[0]                0.243       -0.717
triger_level_cnt[2]                   ao_top_0|clk_i     DFFC     Q       triger_level_cnt[2]                  0.243       -0.670
genblk1\.u_ao_match_0.trig_dly[5]     ao_top_0|clk_i     DFFC     Q       trig_dly[5]                          0.243       -0.604
genblk1\.u_ao_match_0.trig_dly[9]     ao_top_0|clk_i     DFFC     Q       trig_dly[9]                          0.243       -0.604
triger_level_cnt[3]                   ao_top_0|clk_i     DFFC     Q       triger_level_cnt[3]                  0.243       -0.579
genblk1\.u_ao_match_0.trig_dly[0]     ao_top_0|clk_i     DFFC     Q       trig_dly[0]                          0.243       -0.492
genblk1\.u_ao_match_0.trig_dly[4]     ao_top_0|clk_i     DFFC     Q       trig_dly[4]                          0.243       -0.422
=================================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                         Required           
Instance                              Reference          Type      Pin     Net                         Time         Slack 
                                      Clock                                                                               
--------------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      un1_start_reg               4.347        -0.778
u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      un1_capture_length_zero     4.347        -0.774
genblk1\.u_ao_match_0.match_sep       ao_top_0|clk_i     DFFC      D       match_sep_10                4.347        -0.604
u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     D       mem_addr_inc_en7            4.347        -0.023
triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]       4.347        0.038 
triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]       4.347        0.038 
u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6        4.347        0.057 
u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]      4.347        0.057 
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]      4.347        0.057 
u_ao_mem_ctrl.capture_mem_addr[2]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[2]      4.347        0.057 
==========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.408
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.347

    - Propagation time:                      5.125
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.778

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                 Type      Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]     DFFC      Q        Out     0.243     0.243       -         
internal_reg_force_triger_syn[1]     Net       -        -       0.535     -           1         
un1_match_final_3                    LUT4      I1       In      -         0.778       -         
un1_match_final_3                    LUT4      F        Out     0.570     1.348       -         
un1_match_final_3                    Net       -        -       0.401     -           1         
match_final                          LUT4      I3       In      -         1.749       -         
match_final                          LUT4      F        Out     0.371     2.120       -         
match_final                          Net       -        -       0.535     -           6         
triger_level_cnt_0_sqmuxa            LUT4      I0       In      -         2.655       -         
triger_level_cnt_0_sqmuxa            LUT4      F        Out     0.549     3.204       -         
triger_level_cnt_0_sqmuxa            Net       -        -       0.596     -           15        
u_ao_mem_ctrl.un1_start_reg_1        LUT4      I2       In      -         3.800       -         
u_ao_mem_ctrl.un1_start_reg_1        LUT4      F        Out     0.462     4.262       -         
un1_start_reg_1                      Net       -        -       0.401     -           1         
u_ao_mem_ctrl.un1_start_reg          LUT4      I2       In      -         4.663       -         
u_ao_mem_ctrl.un1_start_reg          LUT4      F        Out     0.462     5.125       -         
un1_start_reg                        Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr         DFFCE     CE       In      -         5.125       -         
================================================================================================
Total path delay (propagation time + setup) of 5.186 is 2.718(52.4%) logic and 2.468(47.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.408
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.347

    - Propagation time:                      5.121
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.774

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                      Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]          DFFC      Q        Out     0.243     0.243       -         
internal_reg_force_triger_syn[1]          Net       -        -       0.535     -           1         
un1_match_final_3                         LUT4      I1       In      -         0.778       -         
un1_match_final_3                         LUT4      F        Out     0.570     1.348       -         
un1_match_final_3                         Net       -        -       0.401     -           1         
match_final                               LUT4      I3       In      -         1.749       -         
match_final                               LUT4      F        Out     0.371     2.120       -         
match_final                               Net       -        -       0.535     -           6         
triger_level_cnt_0_sqmuxa                 LUT4      I0       In      -         2.655       -         
triger_level_cnt_0_sqmuxa                 LUT4      F        Out     0.549     3.204       -         
triger_level_cnt_0_sqmuxa                 Net       -        -       0.596     -           15        
u_ao_mem_ctrl.un1_triger_2                LUT2      I0       In      -         3.800       -         
u_ao_mem_ctrl.un1_triger_2                LUT2      F        Out     0.549     4.349       -         
un1_triger_2                              Net       -        -       0.401     -           1         
u_ao_mem_ctrl.un1_capture_length_zero     LUT4      I3       In      -         4.750       -         
u_ao_mem_ctrl.un1_capture_length_zero     LUT4      F        Out     0.371     5.121       -         
un1_capture_length_zero                   Net       -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en             DFFCE     CE       In      -         5.121       -         
=====================================================================================================
Total path delay (propagation time + setup) of 5.182 is 2.714(52.4%) logic and 2.468(47.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.408
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.347

    - Propagation time:                      5.104
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.757

    Number of logic level(s):                5
    Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
genblk1\.u_ao_match_0.match_sep     DFFC      Q        Out     0.243     0.243       -         
match                               Net       -        -       0.535     -           1         
un1_match_final_3                   LUT4      I0       In      -         0.778       -         
un1_match_final_3                   LUT4      F        Out     0.549     1.327       -         
un1_match_final_3                   Net       -        -       0.401     -           1         
match_final                         LUT4      I3       In      -         1.728       -         
match_final                         LUT4      F        Out     0.371     2.099       -         
match_final                         Net       -        -       0.535     -           6         
triger_level_cnt_0_sqmuxa           LUT4      I0       In      -         2.634       -         
triger_level_cnt_0_sqmuxa           LUT4      F        Out     0.549     3.183       -         
triger_level_cnt_0_sqmuxa           Net       -        -       0.596     -           15        
u_ao_mem_ctrl.un1_start_reg_1       LUT4      I2       In      -         3.779       -         
u_ao_mem_ctrl.un1_start_reg_1       LUT4      F        Out     0.462     4.241       -         
un1_start_reg_1                     Net       -        -       0.401     -           1         
u_ao_mem_ctrl.un1_start_reg         LUT4      I2       In      -         4.642       -         
u_ao_mem_ctrl.un1_start_reg         LUT4      F        Out     0.462     5.104       -         
un1_start_reg                       Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr        DFFCE     CE       In      -         5.104       -         
===============================================================================================
Total path delay (propagation time + setup) of 5.165 is 2.697(52.2%) logic and 2.468(47.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.408
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.347

    - Propagation time:                      5.100
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.753

    Number of logic level(s):                5
    Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                      Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
genblk1\.u_ao_match_0.match_sep           DFFC      Q        Out     0.243     0.243       -         
match                                     Net       -        -       0.535     -           1         
un1_match_final_3                         LUT4      I0       In      -         0.778       -         
un1_match_final_3                         LUT4      F        Out     0.549     1.327       -         
un1_match_final_3                         Net       -        -       0.401     -           1         
match_final                               LUT4      I3       In      -         1.728       -         
match_final                               LUT4      F        Out     0.371     2.099       -         
match_final                               Net       -        -       0.535     -           6         
triger_level_cnt_0_sqmuxa                 LUT4      I0       In      -         2.634       -         
triger_level_cnt_0_sqmuxa                 LUT4      F        Out     0.549     3.183       -         
triger_level_cnt_0_sqmuxa                 Net       -        -       0.596     -           15        
u_ao_mem_ctrl.un1_triger_2                LUT2      I0       In      -         3.779       -         
u_ao_mem_ctrl.un1_triger_2                LUT2      F        Out     0.549     4.328       -         
un1_triger_2                              Net       -        -       0.401     -           1         
u_ao_mem_ctrl.un1_capture_length_zero     LUT4      I3       In      -         4.729       -         
u_ao_mem_ctrl.un1_capture_length_zero     LUT4      F        Out     0.371     5.100       -         
un1_capture_length_zero                   Net       -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en             DFFCE     CE       In      -         5.100       -         
=====================================================================================================
Total path delay (propagation time + setup) of 5.161 is 2.693(52.2%) logic and 2.468(47.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.408
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.347

    - Propagation time:                      5.085
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.738

    Number of logic level(s):                5
    Starting point:                          capture_window_sel[1] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                              Pin      Pin               Arrival     No. of    
Name                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------
capture_window_sel[1]             DFFC      Q        Out     0.243     0.243       -         
capture_window_sel[1]             Net       -        -       0.535     -           5         
un6_start_reg_c2                  LUT4      I1       In      -         0.778       -         
un6_start_reg_c2                  LUT4      F        Out     0.570     1.348       -         
un6_start_reg_c2                  Net       -        -       0.401     -           1         
un6_start_reg_ac0_5_0             LUT4      I3       In      -         1.749       -         
un6_start_reg_ac0_5_0             LUT4      F        Out     0.371     2.120       -         
un6_start_reg_ac0_5_0             Net       -        -       0.535     -           3         
start_reg                         LUT3      I2       In      -         2.655       -         
start_reg                         LUT3      F        Out     0.462     3.117       -         
start_reg                         Net       -        -       0.535     -           3         
u_ao_mem_ctrl.un1_start_reg_1     LUT4      I1       In      -         3.652       -         
u_ao_mem_ctrl.un1_start_reg_1     LUT4      F        Out     0.570     4.222       -         
un1_start_reg_1                   Net       -        -       0.401     -           1         
u_ao_mem_ctrl.un1_start_reg       LUT4      I2       In      -         4.623       -         
u_ao_mem_ctrl.un1_start_reg       LUT4      F        Out     0.462     5.085       -         
un1_start_reg                     Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr      DFFCE     CE       In      -         5.085       -         
=============================================================================================
Total path delay (propagation time + setup) of 5.146 is 2.739(53.2%) logic and 2.407(46.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: ao_top_0|control[0]
====================================



Starting Points with Worst Slack
********************************

                                Starting                                                                  Arrival           
Instance                        Reference               Type      Pin     Net                             Time        Slack 
                                Clock                                                                                       
----------------------------------------------------------------------------------------------------------------------------
internal_register_select[3]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[3]     0.243       -1.123
internal_register_select[2]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[2]     0.243       -1.102
internal_register_select[1]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[1]     0.243       -1.029
internal_register_select[8]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[8]     0.243       -1.015
internal_register_select[0]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[0]     0.243       -1.008
internal_register_select[4]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[4]     0.243       -0.994
internal_register_select[6]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[6]     0.243       -0.924
internal_register_select[9]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]     0.243       -0.904
internal_register_select[5]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[5]     0.243       -0.903
internal_register_select[7]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]     0.243       -0.883
============================================================================================================================


Ending Points with Worst Slack
******************************

                          Starting                                                              Required           
Instance                  Reference               Type      Pin     Net                         Time         Slack 
                          Clock                                                                                    
-------------------------------------------------------------------------------------------------------------------
data_out_shift_reg[2]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[2]     6.303        -1.123
bit_count[0]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.303        -0.690
bit_count[1]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.303        -0.690
bit_count[2]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.303        -0.690
bit_count[3]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.303        -0.690
bit_count[4]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.303        -0.690
bit_count[5]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.303        -0.690
bit_count[6]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.303        -0.690
bit_count[7]              ao_top_0|control[0]     DFFCE     CE      bit_counte                  6.303        -0.690
data_out_shift_reg[0]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[0]     6.303        -0.658
===================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.364
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.303

    - Propagation time:                      7.427
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.123

    Number of logic level(s):                7
    Starting point:                          internal_register_select[3] / Q
    Ending point:                            data_out_shift_reg[2] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                            Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
internal_register_select[3]     DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[3]     Net       -        -       0.535     -           7         
data_from_internal_reg79_2      LUT2      I1       In      -         0.778       -         
data_from_internal_reg79_2      LUT2      F        Out     0.570     1.348       -         
internal_reg_start_m_2          Net       -        -       0.535     -           2         
data_from_internal_reg80_1      LUT4      I1       In      -         1.883       -         
data_from_internal_reg80_1      LUT4      F        Out     0.570     2.453       -         
data_from_internal_reg80_1      Net       -        -       0.535     -           7         
data_from_internal_reg80        LUT2      I0       In      -         2.988       -         
data_from_internal_reg80        LUT2      F        Out     0.549     3.537       -         
data_from_internal_reg80        Net       -        -       0.535     -           10        
data_from_ao_reg_0[2]           LUT4      I1       In      -         4.072       -         
data_from_ao_reg_0[2]           LUT4      F        Out     0.570     4.642       -         
data_from_ao_reg_0[2]           Net       -        -       0.401     -           1         
data_from_ao_reg_4[2]           LUT4      I0       In      -         5.043       -         
data_from_ao_reg_4[2]           LUT4      F        Out     0.549     5.592       -         
data_from_ao_reg_4[2]           Net       -        -       0.401     -           1         
data_from_ao_reg_5[2]           LUT4      I2       In      -         5.993       -         
data_from_ao_reg_5[2]           LUT4      F        Out     0.462     6.455       -         
data_from_ao_reg_5[2]           Net       -        -       0.401     -           1         
data_out_shift_reg_4[2]         LUT4      I1       In      -         6.857       -         
data_out_shift_reg_4[2]         LUT4      F        Out     0.570     7.427       -         
data_out_shift_reg_4[2]         Net       -        -       0.000     -           1         
data_out_shift_reg[2]           DFFCE     D        In      -         7.427       -         
===========================================================================================
Total path delay (propagation time + setup) of 7.488 is 4.144(55.3%) logic and 3.344(44.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.364
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.303

    - Propagation time:                      7.406
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.102

    Number of logic level(s):                7
    Starting point:                          internal_register_select[2] / Q
    Ending point:                            data_out_shift_reg[2] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                            Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
internal_register_select[2]     DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[2]     Net       -        -       0.535     -           9         
data_from_internal_reg79_2      LUT2      I0       In      -         0.778       -         
data_from_internal_reg79_2      LUT2      F        Out     0.549     1.327       -         
internal_reg_start_m_2          Net       -        -       0.535     -           2         
data_from_internal_reg80_1      LUT4      I1       In      -         1.862       -         
data_from_internal_reg80_1      LUT4      F        Out     0.570     2.432       -         
data_from_internal_reg80_1      Net       -        -       0.535     -           7         
data_from_internal_reg80        LUT2      I0       In      -         2.967       -         
data_from_internal_reg80        LUT2      F        Out     0.549     3.516       -         
data_from_internal_reg80        Net       -        -       0.535     -           10        
data_from_ao_reg_0[2]           LUT4      I1       In      -         4.051       -         
data_from_ao_reg_0[2]           LUT4      F        Out     0.570     4.621       -         
data_from_ao_reg_0[2]           Net       -        -       0.401     -           1         
data_from_ao_reg_4[2]           LUT4      I0       In      -         5.022       -         
data_from_ao_reg_4[2]           LUT4      F        Out     0.549     5.571       -         
data_from_ao_reg_4[2]           Net       -        -       0.401     -           1         
data_from_ao_reg_5[2]           LUT4      I2       In      -         5.972       -         
data_from_ao_reg_5[2]           LUT4      F        Out     0.462     6.434       -         
data_from_ao_reg_5[2]           Net       -        -       0.401     -           1         
data_out_shift_reg_4[2]         LUT4      I1       In      -         6.836       -         
data_out_shift_reg_4[2]         LUT4      F        Out     0.570     7.406       -         
data_out_shift_reg_4[2]         Net       -        -       0.000     -           1         
data_out_shift_reg[2]           DFFCE     D        In      -         7.406       -         
===========================================================================================
Total path delay (propagation time + setup) of 7.467 is 4.123(55.2%) logic and 3.344(44.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.364
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.303

    - Propagation time:                      7.333
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.029

    Number of logic level(s):                7
    Starting point:                          internal_register_select[1] / Q
    Ending point:                            data_out_shift_reg[2] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                            Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
internal_register_select[1]     DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[1]     Net       -        -       0.596     -           19        
data_from_internal_reg80_0      LUT2      I1       In      -         0.839       -         
data_from_internal_reg80_0      LUT2      F        Out     0.570     1.409       -         
data_from_internal_reg80_0      Net       -        -       0.401     -           1         
data_from_internal_reg80_1      LUT4      I0       In      -         1.810       -         
data_from_internal_reg80_1      LUT4      F        Out     0.549     2.359       -         
data_from_internal_reg80_1      Net       -        -       0.535     -           7         
data_from_internal_reg80        LUT2      I0       In      -         2.894       -         
data_from_internal_reg80        LUT2      F        Out     0.549     3.443       -         
data_from_internal_reg80        Net       -        -       0.535     -           10        
data_from_ao_reg_0[2]           LUT4      I1       In      -         3.978       -         
data_from_ao_reg_0[2]           LUT4      F        Out     0.570     4.548       -         
data_from_ao_reg_0[2]           Net       -        -       0.401     -           1         
data_from_ao_reg_4[2]           LUT4      I0       In      -         4.949       -         
data_from_ao_reg_4[2]           LUT4      F        Out     0.549     5.498       -         
data_from_ao_reg_4[2]           Net       -        -       0.401     -           1         
data_from_ao_reg_5[2]           LUT4      I2       In      -         5.900       -         
data_from_ao_reg_5[2]           LUT4      F        Out     0.462     6.362       -         
data_from_ao_reg_5[2]           Net       -        -       0.401     -           1         
data_out_shift_reg_4[2]         LUT4      I1       In      -         6.763       -         
data_out_shift_reg_4[2]         LUT4      F        Out     0.570     7.333       -         
data_out_shift_reg_4[2]         Net       -        -       0.000     -           1         
data_out_shift_reg[2]           DFFCE     D        In      -         7.333       -         
===========================================================================================
Total path delay (propagation time + setup) of 7.394 is 4.123(55.8%) logic and 3.271(44.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.364
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.303

    - Propagation time:                      7.319
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.015

    Number of logic level(s):                7
    Starting point:                          internal_register_select[8] / Q
    Ending point:                            data_out_shift_reg[2] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                    Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
internal_register_select[8]             DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[8]             Net       -        -       0.535     -           4         
internal_register_select_RNISOS5[4]     LUT2      I1       In      -         0.778       -         
internal_register_select_RNISOS5[4]     LUT2      F        Out     0.570     1.348       -         
internal_reg_start_m_10_0               Net       -        -       0.535     -           3         
data_from_internal_reg80_1              LUT4      I2       In      -         1.883       -         
data_from_internal_reg80_1              LUT4      F        Out     0.462     2.345       -         
data_from_internal_reg80_1              Net       -        -       0.535     -           7         
data_from_internal_reg80                LUT2      I0       In      -         2.880       -         
data_from_internal_reg80                LUT2      F        Out     0.549     3.429       -         
data_from_internal_reg80                Net       -        -       0.535     -           10        
data_from_ao_reg_0[2]                   LUT4      I1       In      -         3.964       -         
data_from_ao_reg_0[2]                   LUT4      F        Out     0.570     4.534       -         
data_from_ao_reg_0[2]                   Net       -        -       0.401     -           1         
data_from_ao_reg_4[2]                   LUT4      I0       In      -         4.935       -         
data_from_ao_reg_4[2]                   LUT4      F        Out     0.549     5.484       -         
data_from_ao_reg_4[2]                   Net       -        -       0.401     -           1         
data_from_ao_reg_5[2]                   LUT4      I2       In      -         5.885       -         
data_from_ao_reg_5[2]                   LUT4      F        Out     0.462     6.347       -         
data_from_ao_reg_5[2]                   Net       -        -       0.401     -           1         
data_out_shift_reg_4[2]                 LUT4      I1       In      -         6.749       -         
data_out_shift_reg_4[2]                 LUT4      F        Out     0.570     7.319       -         
data_out_shift_reg_4[2]                 Net       -        -       0.000     -           1         
data_out_shift_reg[2]                   DFFCE     D        In      -         7.319       -         
===================================================================================================
Total path delay (propagation time + setup) of 7.380 is 4.036(54.7%) logic and 3.344(45.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.364
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.303

    - Propagation time:                      7.312
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.008

    Number of logic level(s):                7
    Starting point:                          internal_register_select[0] / Q
    Ending point:                            data_out_shift_reg[2] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                            Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
internal_register_select[0]     DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[0]     Net       -        -       0.596     -           20        
data_from_internal_reg80_0      LUT2      I0       In      -         0.839       -         
data_from_internal_reg80_0      LUT2      F        Out     0.549     1.388       -         
data_from_internal_reg80_0      Net       -        -       0.401     -           1         
data_from_internal_reg80_1      LUT4      I0       In      -         1.789       -         
data_from_internal_reg80_1      LUT4      F        Out     0.549     2.338       -         
data_from_internal_reg80_1      Net       -        -       0.535     -           7         
data_from_internal_reg80        LUT2      I0       In      -         2.873       -         
data_from_internal_reg80        LUT2      F        Out     0.549     3.422       -         
data_from_internal_reg80        Net       -        -       0.535     -           10        
data_from_ao_reg_0[2]           LUT4      I1       In      -         3.957       -         
data_from_ao_reg_0[2]           LUT4      F        Out     0.570     4.527       -         
data_from_ao_reg_0[2]           Net       -        -       0.401     -           1         
data_from_ao_reg_4[2]           LUT4      I0       In      -         4.928       -         
data_from_ao_reg_4[2]           LUT4      F        Out     0.549     5.477       -         
data_from_ao_reg_4[2]           Net       -        -       0.401     -           1         
data_from_ao_reg_5[2]           LUT4      I2       In      -         5.879       -         
data_from_ao_reg_5[2]           LUT4      F        Out     0.462     6.341       -         
data_from_ao_reg_5[2]           Net       -        -       0.401     -           1         
data_out_shift_reg_4[2]         LUT4      I1       In      -         6.742       -         
data_out_shift_reg_4[2]         LUT4      F        Out     0.570     7.312       -         
data_out_shift_reg_4[2]         Net       -        -       0.000     -           1         
data_out_shift_reg[2]           DFFCE     D        In      -         7.312       -         
===========================================================================================
Total path delay (propagation time + setup) of 7.373 is 4.102(55.6%) logic and 3.271(44.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                           Arrival          
Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                         Clock                                                               
-------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       2.266
address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       4.448
=============================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                                        Required          
Instance                      Reference     Type      Pin     Net                             Time         Slack
                              Clock                                                                             
----------------------------------------------------------------------------------------------------------------
capture_window_sel[2]         System        DFFC      D       capture_window_sel_3[2]         4.347        2.266
capture_window_sel[3]         System        DFFC      D       capture_window_sel_3[3]         4.347        2.266
capture_window_sel[1]         System        DFFC      D       capture_window_sel_3[1]         4.347        2.313
capture_window_sel[0]         System        DFFC      D       capture_window_sel_3[0]         4.347        3.263
internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]     4.347        3.263
capture_end_dly               System        DFFP      D       capture_end                     4.347        3.812
address_counter[9]            System        DFFCE     D       address_counter_s[9]            6.303        4.448
address_counter[8]            System        DFFCE     D       address_counter_s[8]            6.303        4.483
address_counter[7]            System        DFFCE     D       address_counter_s[7]            6.303        4.518
address_counter[6]            System        DFFCE     D       address_counter_s[6]            6.303        4.553
================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.408
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.347

    - Propagation time:                      2.081
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 2.266

    Number of logic level(s):                2
    Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
    Ending point:                            capture_window_sel[2] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     INV      O        Out     0.000     0.000       -         
capture_end                              Net      -        -       0.535     -           6         
un1_capture_window_sel_ac0_1             LUT4     I0       In      -         0.535       -         
un1_capture_window_sel_ac0_1             LUT4     F        Out     0.549     1.084       -         
un1_capture_window_sel_c2                Net      -        -       0.535     -           2         
capture_window_sel_3[2]                  LUT3     I2       In      -         1.619       -         
capture_window_sel_3[2]                  LUT3     F        Out     0.462     2.081       -         
capture_window_sel_3[2]                  Net      -        -       0.000     -           1         
capture_window_sel[2]                    DFFC     D        In      -         2.081       -         
===================================================================================================
Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 255MB peak: 258MB)


Finished timing report (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 255MB peak: 258MB)

---------------------------------------
Resource Usage Report for ao_top_0 

Mapping to part: gw2a_18pbga256-8
Cell usage:
ALU             72 uses
DFF             139 uses
DFFC            47 uses
DFFCE           474 uses
DFFNP           2 uses
DFFP            5 uses
DFFPE           32 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       3 uses
SDPX9           8 uses
LUT2            67 uses
LUT3            115 uses
LUT4            387 uses

I/O ports: 160
I/O primitives: 160
IBUF           158 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   699 of 15552 (4%)

RAM/ROM usage summary
Block Rams : 8 of 46 (17%)

Total load per clock:
   ao_top_0|clk_i: 1
   ao_top_0|control[0]: 516

@S |Mapping Summary:
Total  LUTs: 569 (2%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 79MB peak: 258MB)

Process took 0h:00m:10s realtime, 0h:00m:09s cputime
# Tue Nov 12 10:09:56 2019

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