#Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019
#install: D:\Gowin\sdio_sweg\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-050

# Tue Nov 12 10:07:45 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\sdio_slave_controller\sdio_slave_controller.v" (library work)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\button.v" (library work)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\top.v" (library work)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_cpu_slave_reg_if.v" (library work)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd52_if.v" (library work)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v" (library work)
@I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_tuning_pattern.v" (library work)
Verilog syntax check successful!
Selecting top level module top
@N:CG364 : gw2a.v(1908) | Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on DFFNP .......
Running optimization stage 1 on DFFNC .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on \~sdio_if.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on DFFC .......
Running optimization stage 1 on DFFCE .......
Running optimization stage 1 on DFFP .......
Running optimization stage 1 on DFFPE .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on \~cmd_dec.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on MUX2_LUT6 .......
Running optimization stage 1 on \~sdio_biu.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on \~card_fixed_regs.SDIO_Slave_Controller_Top__16744448_0_1_2_3_4_5  .......
Running optimization stage 1 on \~crc7_chk.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on \~resp_gen.SDIO_Slave_Controller_Top__Z1  .......
Running optimization stage 1 on \~resp_conv.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on MUX2_LUT7 .......
Running optimization stage 1 on DFFNCE .......
Running optimization stage 1 on \~fn0_reg.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on \~slv_cpu_if.SDIO_Slave_Controller_Top__3_5_4  .......
Running optimization stage 1 on \~cmd53_ctrl.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on \~crc16_gen.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on \~crc16_gen.SDIO_Slave_Controller_Top__3  .......
Running optimization stage 1 on \~crc16_gen.SDIO_Slave_Controller_Top__4  .......
Running optimization stage 1 on \~crc16_gen.SDIO_Slave_Controller_Top__5  .......
Running optimization stage 1 on \~cmd53_tx_rx.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on \~cis_fnx_if.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on \~irq_gen.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on \~cmd19_tx.SDIO_Slave_Controller_Top_  .......
Running optimization stage 1 on \~sdio_slave_ctrl.SDIO_Slave_Controller_Top_  .......
@N:CG364 : sdio_slave_controller.v(51061) | Synthesizing module SDIO_Slave_Controller_Top in library work.
Running optimization stage 1 on SDIO_Slave_Controller_Top .......
@N:CG364 : user_sdio_cmd53_if.v(1) | Synthesizing module user_sdio_cmd53_if in library work.
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_Z1
Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_Z1 .......
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000001100
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100100101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_Z2
Running optimization stage 1 on syn_hyper_source_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_Z2 .......
Running optimization stage 1 on user_sdio_cmd53_if_xmr0 .......
@W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_wr_en_d1. Make sure that there are no unused intermediate registers.
@W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_rd_en_d1. Make sure that there are no unused intermediate registers.
@W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_fn_num_d1. Make sure that there are no unused intermediate registers.
@W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_addr_d1[16:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_op_code_d1. Make sure that there are no unused intermediate registers.
@W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_wr_end_d1. Make sure that there are no unused intermediate registers.
@W:CL169 : user_sdio_cmd53_if.v(175) | Pruning unused register sdio_cmd53_wr_ok_d1. Make sure that there are no unused intermediate registers.
@W:CL190 : user_sdio_cmd53_if.v(209) | Optimizing register bit user_cmd53_rd_data_reg[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_sdio_cmd53_if.v(209) | Optimizing register bit user_cmd53_rd_data_reg[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_sdio_cmd53_if.v(209) | Optimizing register bit user_cmd53_rd_data_reg[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 7 of user_cmd53_rd_data_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 4 of user_cmd53_rd_data_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 1 of user_cmd53_rd_data_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : user_sdio_cmd52_if.v(1) | Synthesizing module user_sdio_cmd52_if in library work.
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100110101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_Z3
Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_Z3 .......
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101000101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_Z4
Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_Z4 .......
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_Z5
Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_Z5 .......
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101100101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_Z6
Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_Z6 .......
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000010001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101110101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_Z7
Running optimization stage 1 on syn_hyper_source_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_Z7 .......
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000001000
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001110000101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_Z8
Running optimization stage 1 on syn_hyper_source_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_Z8 .......
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000001000
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001110010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_Z9
Running optimization stage 1 on syn_hyper_source_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_Z9 .......
@N:CG364 : hypermods.v(9) | Synthesizing module syn_hyper_source in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111011000010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
   Generated name = syn_hyper_source_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_Z10
Running optimization stage 1 on syn_hyper_source_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_Z10 .......
Running optimization stage 1 on user_sdio_cmd52_if_xmr1 .......
@W:CL190 : user_sdio_cmd52_if.v(86) | Optimizing register bit user_cmd52_read_reg[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_sdio_cmd52_if.v(86) | Optimizing register bit user_cmd52_read_reg[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_sdio_cmd52_if.v(86) | Optimizing register bit user_cmd52_read_reg[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_sdio_cmd52_if.v(86) | Optimizing register bit user_cmd52_read_reg[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_sdio_cmd52_if.v(99) | Optimizing register bit user_cmd52_write_return_reg[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_sdio_cmd52_if.v(99) | Optimizing register bit user_cmd52_write_return_reg[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_sdio_cmd52_if.v(99) | Optimizing register bit user_cmd52_write_return_reg[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : user_sdio_cmd52_if.v(86) | Pruning register bit 7 of user_cmd52_read_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : user_sdio_cmd52_if.v(86) | Pruning register bit 5 of user_cmd52_read_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : user_sdio_cmd52_if.v(86) | Pruning register bits 1 to 0 of user_cmd52_read_reg[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : user_sdio_cmd52_if.v(99) | Pruning register bits 6 to 5 of user_cmd52_write_return_reg[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : user_sdio_cmd52_if.v(99) | Pruning register bit 2 of user_cmd52_write_return_reg[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : user_tuning_pattern.v(1) | Synthesizing module user_tuning_pattern in library work.
Running optimization stage 1 on user_tuning_pattern .......
@N:CG364 : button.v(1) | Synthesizing module deUstb in library work.
Running optimization stage 1 on deUstb .......
@N:CG364 : user_cpu_slave_reg_if.v(1) | Synthesizing module user_cpu_slave_reg_if in library work.
@N:CG179 : user_cpu_slave_reg_if.v(89) | Removing redundant assignment.
Running optimization stage 1 on user_cpu_slave_reg_if .......
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_addr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_addr[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_addr[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_addr[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : user_cpu_slave_reg_if.v(104) | Optimizing register bit slv_cpu_wr_data[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 31 to 28 of slv_cpu_wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 26 to 25 of slv_cpu_wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 23 to 15 of slv_cpu_wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 10 to 1 of slv_cpu_wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 7 to 6 of slv_cpu_addr[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : user_cpu_slave_reg_if.v(104) | Pruning register bits 1 to 0 of slv_cpu_addr[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : top.v(2) | Synthesizing module top in library work.
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100110101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_5s_1_Z11
Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_5s_1_Z11 .......
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101000101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_5s_1_Z12
Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_5s_1_Z12 .......
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_5s_1_Z13
Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_5s_1_Z13 .......
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101100101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_5s_1_Z14
Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_5s_1_Z14 .......
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000010001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001101110101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_5s_1_Z15
Running optimization stage 1 on syn_hyper_connect_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_5s_1_Z15 .......
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000001000
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001110000101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_5s_1_Z16
Running optimization stage 1 on syn_hyper_connect_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_5s_1_Z16 .......
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000001000
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001110010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_5s_1_Z17
Running optimization stage 1 on syn_hyper_connect_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_5s_1_Z17 .......
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111011000010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_5s_1_Z18
Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_5s_1_Z18 .......
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000000001
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100010101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_5s_1_Z19
Running optimization stage 1 on syn_hyper_connect_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_5s_1_Z19 .......
@N:CG364 : hypermods.v(16) | Synthesizing module syn_hyper_connect in library __hyper__lib__.

	w=32'b00000000000000000000000000001100
	tag=376'b0101111101011111011110000110110101110010010111110111010001100001011001110101111101011111001100100101111100110000010111110110000100110011011000110011011101100011011000010110001000110011001101110011010000110101001101000011000100110010011000100011010000111001001110010011010000111000001110010011001101100101011001010011000100110010001101110011100100111001001101010011000100110001
	dflt=32'b00000000000000000000000000000101
	mustconnect=1'b1
   Generated name = syn_hyper_connect_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_5s_1_Z20
Running optimization stage 1 on syn_hyper_connect_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_5s_1_Z20 .......
Running optimization stage 1 on top .......
Running optimization stage 2 on syn_hyper_connect_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_5s_1_Z20 .......
Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_5s_1_Z19 .......
Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_5s_1_Z18 .......
Running optimization stage 2 on syn_hyper_connect_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_5s_1_Z17 .......
Running optimization stage 2 on syn_hyper_connect_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_5s_1_Z16 .......
Running optimization stage 2 on syn_hyper_connect_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_5s_1_Z15 .......
Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_5s_1_Z14 .......
Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_5s_1_Z13 .......
Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_5s_1_Z12 .......
Running optimization stage 2 on syn_hyper_connect_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_5s_1_Z11 .......
Running optimization stage 2 on top .......
Running optimization stage 2 on user_cpu_slave_reg_if .......
@N:CL159 : user_cpu_slave_reg_if.v(3) | Input cpu_rst is unused.
@N:CL159 : user_cpu_slave_reg_if.v(10) | Input slv_cpu_rd_data is unused.
@N:CL159 : user_cpu_slave_reg_if.v(12) | Input slv_cpu_err is unused.
Running optimization stage 2 on deUstb .......
Running optimization stage 2 on user_tuning_pattern .......
Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__a_0_a3c7cab3745412b4994893ee12799511_Z10 .......
Running optimization stage 2 on syn_hyper_source_8s___xmr_tag__9_0_a3c7cab3745412b4994893ee12799511_Z9 .......
Running optimization stage 2 on syn_hyper_source_8s___xmr_tag__8_0_a3c7cab3745412b4994893ee12799511_Z8 .......
Running optimization stage 2 on syn_hyper_source_17s___xmr_tag__7_0_a3c7cab3745412b4994893ee12799511_Z7 .......
Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__6_0_a3c7cab3745412b4994893ee12799511_Z6 .......
Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__5_0_a3c7cab3745412b4994893ee12799511_Z5 .......
Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__4_0_a3c7cab3745412b4994893ee12799511_Z4 .......
Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__3_0_a3c7cab3745412b4994893ee12799511_Z3 .......
Running optimization stage 2 on user_sdio_cmd52_if_xmr1 .......
@W:CL279 : user_sdio_cmd52_if.v(86) | Pruning register bits 4 to 3 of user_cmd52_read_reg[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : user_sdio_cmd52_if.v(99) | Pruning register bit 1 of user_cmd52_write_return_reg[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : user_sdio_cmd52_if.v(99) | Pruning register bit 4 of user_cmd52_write_return_reg[4:3]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Running optimization stage 2 on syn_hyper_source_12s___xmr_tag__2_0_a3c7cab3745412b4994893ee12799511_Z2 .......
Running optimization stage 2 on syn_hyper_source_1s___xmr_tag__1_0_a3c7cab3745412b4994893ee12799511_Z1 .......
Running optimization stage 2 on user_sdio_cmd53_if_xmr0 .......
@N:CL201 : user_sdio_cmd53_if.v(102) | Trying to extract state machine for register c_state.
Extracted state machine for register c_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 3 of user_cmd53_rd_data_reg[3:2]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : user_sdio_cmd53_if.v(209) | Pruning register bit 6 of user_cmd53_rd_data_reg[6:5]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CL159 : user_sdio_cmd53_if.v(9) | Input sdio_cmd53_fn_num is unused.
@N:CL159 : user_sdio_cmd53_if.v(10) | Input sdio_cmd53_addr is unused.
@N:CL159 : user_sdio_cmd53_if.v(12) | Input sdio_cmd53_op_code is unused.
@N:CL159 : user_sdio_cmd53_if.v(15) | Input sdio_cmd53_wr_data is unused.
@N:CL159 : user_sdio_cmd53_if.v(17) | Input sdio_cmd53_wr_ok is unused.
@N:CL159 : user_sdio_cmd53_if.v(23) | Input sdio_cmd53_rd_end is unused.
Running optimization stage 2 on SDIO_Slave_Controller_Top .......
@W:CL246 : sdio_slave_controller.v(51150) | Input port bits 1 to 0 of slv_cpu_addr[7:0] are unused. Assign logic for all port bits or change the input port size.
Running optimization stage 2 on \~sdio_slave_ctrl.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on \~cmd19_tx.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on \~irq_gen.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on \~cis_fnx_if.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on \~cmd53_tx_rx.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on \~crc16_gen.SDIO_Slave_Controller_Top__5  .......
Running optimization stage 2 on \~crc16_gen.SDIO_Slave_Controller_Top__4  .......
Running optimization stage 2 on \~crc16_gen.SDIO_Slave_Controller_Top__3  .......
Running optimization stage 2 on \~crc16_gen.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on \~cmd53_ctrl.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on \~slv_cpu_if.SDIO_Slave_Controller_Top__3_5_4  .......
Running optimization stage 2 on \~fn0_reg.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on DFFNCE .......
Running optimization stage 2 on MUX2_LUT7 .......
Running optimization stage 2 on \~resp_conv.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on \~resp_gen.SDIO_Slave_Controller_Top__Z1  .......
Running optimization stage 2 on \~crc7_chk.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on \~card_fixed_regs.SDIO_Slave_Controller_Top__16744448_0_1_2_3_4_5  .......
Running optimization stage 2 on \~sdio_biu.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on MUX2_LUT6 .......
Running optimization stage 2 on \~cmd_dec.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on DFFPE .......
Running optimization stage 2 on DFFP .......
Running optimization stage 2 on DFFCE .......
Running optimization stage 2 on DFFC .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on \~sdio_if.SDIO_Slave_Controller_Top_  .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on DFFNC .......
Running optimization stage 2 on DFFNP .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 129MB peak: 130MB)

Process took 0h:00m:05s realtime, 0h:00m:05s cputime

Process completed successfully.
# Tue Nov 12 10:07:50 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
@N:NF107 : top.v(2) | Selected library: work cell: top view verilog as top level
@N:NF107 : top.v(2) | Selected library: work cell: top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 12 10:07:51 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  sdio_test_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 18MB peak: 19MB)

Process took 0h:00m:05s realtime, 0h:00m:05s cputime

Process completed successfully.
# Tue Nov 12 10:07:51 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N: :  | Running in 64-bit mode 
@N:NF107 : top.v(2) | Selected library: work cell: top view verilog as top level
@N:NF107 : top.v(2) | Selected library: work cell: top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 12 10:07:53 2019

###########################################################]


Premap Report



# Tue Nov 12 10:07:53 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A:MF827 :  | No constraint file specified. 
Linked File:  sdio_test_scck.rpt
Printing clock  summary report in "C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\impl\synthesize\rev_1\sdio_test_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)


Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)


Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)

@W:BN132 : user_sdio_cmd53_if.v(209) | Removing sequential instance u_user_sdio_cmd53_if.user_cmd53_rd_data_reg[5] because it is equivalent to instance u_user_sdio_cmd53_if.user_cmd53_rd_data_reg[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : user_sdio_cmd53_if.v(209) | Removing sequential instance u_user_sdio_cmd53_if.user_cmd53_rd_data_reg[2] because it is equivalent to instance u_user_sdio_cmd53_if.user_cmd53_rd_data_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : user_sdio_cmd52_if.v(99) | Removing sequential instance u_user_sdio_cmd52_if.user_cmd52_write_return_reg[7] because it is equivalent to instance u_user_sdio_cmd52_if.user_cmd52_write_return_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : user_sdio_cmd52_if.v(99) | Removing sequential instance u_user_sdio_cmd52_if.user_cmd52_write_return_reg[3] because it is equivalent to instance u_user_sdio_cmd52_if.user_cmd52_write_return_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : user_sdio_cmd52_if.v(86) | Removing sequential instance u_user_sdio_cmd52_if.user_cmd52_read_reg[6] because it is equivalent to instance u_user_sdio_cmd52_if.user_cmd52_read_reg[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Making connections to hyper_source modules
@N:BN397 : top.v(375) | Connected syn_hyper_connect __xmr_use__1_, tag __xmr_tag__2_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd53_if.__xmr_decl__0_
@N:BN397 : top.v(352) | Connected syn_hyper_connect __xmr_use__3_, tag __xmr_tag__1_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd53_if.__xmr_decl__2_
@N:BN397 : top.v(348) | Connected syn_hyper_connect __xmr_use__5_, tag __xmr_tag__a_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd52_if.__xmr_decl__4_
@N:BN397 : top.v(347) | Connected syn_hyper_connect __xmr_use__7_, tag __xmr_tag__9_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd52_if.__xmr_decl__6_
@N:BN397 : top.v(346) | Connected syn_hyper_connect __xmr_use__9_, tag __xmr_tag__8_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd52_if.__xmr_decl__8_
@N:BN397 : top.v(345) | Connected syn_hyper_connect __xmr_use__11_, tag __xmr_tag__7_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd52_if.__xmr_decl__10_
@N:BN397 : top.v(344) | Connected syn_hyper_connect __xmr_use__13_, tag __xmr_tag__6_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd52_if.__xmr_decl__12_
@N:BN397 : top.v(343) | Connected syn_hyper_connect __xmr_use__15_, tag __xmr_tag__5_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd52_if.__xmr_decl__14_
@N:BN397 : top.v(342) | Connected syn_hyper_connect __xmr_use__17_, tag __xmr_tag__4_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd52_if.__xmr_decl__16_
@N:BN397 : top.v(341) | Connected syn_hyper_connect __xmr_use__19_, tag __xmr_tag__3_0_a3c7cab3745412b4994893ee12799511 to syn_hyper_source u_user_sdio_cmd52_if.__xmr_decl__18_
Encoding state machine c_state[3:0] (in view: work.user_sdio_cmd53_if_xmr0(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
   011 -> 11
@N:MO225 : user_sdio_cmd53_if.v(102) | There are no possible illegal states for state machine c_state[3:0] (in view: work.user_sdio_cmd53_if_xmr0(verilog)); safe FSM implementation is not required.

Starting clock optimization phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 234MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 235MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 235MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 235MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 235MB peak: 236MB)



Clock Summary
******************

          Start           Requested     Requested     Clock        Clock                     Clock
Level     Clock           Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------
0 -       System          150.0 MHz     6.667         system       system_clkgroup           0    
                                                                                                  
0 -       top|clk         150.0 MHz     6.667         inferred     Autoconstr_clkgroup_0     1605 
                                                                                                  
0 -       top|cpu_clk     157.1 MHz     6.367         inferred     Autoconstr_clkgroup_1     250  
==================================================================================================



Clock Load Summary
***********************

                Clock     Source            Clock Pin                                    Non-clock Pin     Non-clock Pin
Clock           Load      Pin               Seq Example                                  Seq Example       Comb Example 
------------------------------------------------------------------------------------------------------------------------
System          0         -                 -                                            -                 -            
                                                                                                                        
top|clk         1605      clk(port)         user_sdio_cmd52_if_user_sdio_cmd52_ack.C     -                 -            
                                                                                                                        
top|cpu_clk     250       cpu_clk(port)     led\[0\].C                                   -                 -            
========================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 1855 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       clk                 port                   1605       capture_o      
ClockId_0_1       cpu_clk             port                   250        led_reg[24:0]  
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\impl\synthesize\rev_1\sdio_test.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 236MB peak: 238MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 236MB peak: 238MB)


Finished constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 236MB peak: 238MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 156MB peak: 238MB)

Process took 0h:00m:04s realtime, 0h:00m:03s cputime
# Tue Nov 12 10:07:57 2019

###########################################################]


Map & Optimize Report



# Tue Nov 12 10:07:58 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\sdio_sweg\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-050

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@W:BN132 : user_tuning_pattern.v(17) | Removing sequential instance u_user_tuning_pattern.tuning_flag_rep because it is equivalent to instance u_user_tuning_pattern.tuning_flag. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : button.v(12) | Removing sequential instance u_deUstb.in_reg1_rep because it is equivalent to instance u_deUstb.in_reg1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : button.v(12) | Removing sequential instance u_deUstb1.in_reg1_rep because it is equivalent to instance u_deUstb1.in_reg1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(331) | Removing user instance led[0]_2 because it is equivalent to instance led[1]_2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(330) | Removing user instance led[1]_2 because it is equivalent to instance led[3]_2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(325) | Removing sequential instance led[3] because it is equivalent to instance led[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(325) | Removing sequential instance led[1] because it is equivalent to instance led[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@A:BN291 : top.v(325) | Boundary register led\[1\] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : top.v(325) | Boundary register led\[3\] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@W:BN132 : top.v(325) | Removing sequential instance led[2] because it is equivalent to instance led[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@A:BN291 : top.v(325) | Boundary register led\[2\] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 240MB peak: 240MB)

@N:MO231 : top.v(325) | Found counter in view:work.top(verilog) instance led_reg[24:0] 
@N:MO231 : user_sdio_cmd53_if.v(160) | Found counter in view:work.user_sdio_cmd53_if_xmr0(verilog) instance cnt[11:0] 
@N:MO231 : user_sdio_cmd53_if.v(145) | Found counter in view:work.user_sdio_cmd53_if_xmr0(verilog) instance buf_full_cnt[7:0] 
@N:MF179 :  | Found 13 by 13 bit equality operator ('==') un1_cnt_2 (in view: work.user_sdio_cmd53_if_xmr0(verilog)) 
@N:MO231 : user_tuning_pattern.v(32) | Found counter in view:work.user_tuning_pattern(verilog) instance cnt[7:0] 
@N:MO231 : button.v(24) | Found counter in view:work.deUstb_1(verilog) instance cnt[19:0] 
@N:MO231 : button.v(24) | Found counter in view:work.deUstb_0(verilog) instance cnt[19:0] 
@N:MO231 : user_cpu_slave_reg_if.v(85) | Found counter in view:work.user_cpu_slave_reg_if(verilog) instance cnt[9:0] 

Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 243MB)

@W:BN132 : top.v(340) | Removing instance user_sdio_cmd52_if_user_sdio_cmd52_rd_data[7] because it is equivalent to instance user_sdio_cmd52_if_user_sdio_cmd52_rd_data[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(340) | Removing instance user_sdio_cmd52_if_user_sdio_cmd52_rd_data[1] because it is equivalent to instance user_sdio_cmd52_if_user_sdio_cmd52_rd_data[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(340) | Removing instance user_sdio_cmd52_if_user_sdio_cmd52_rd_data[6] because it is equivalent to instance user_sdio_cmd52_if_user_sdio_cmd52_rd_data[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(340) | Removing instance user_sdio_cmd52_if_user_sdio_cmd52_rd_data[4] because it is equivalent to instance user_sdio_cmd52_if_user_sdio_cmd52_rd_data[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(355) | Removing instance user_sdio_cmd53_rd_data[6] because it is equivalent to instance user_sdio_cmd53_rd_data[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(355) | Removing instance user_sdio_cmd53_rd_data[5] because it is equivalent to instance user_sdio_cmd53_rd_data[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(355) | Removing instance user_sdio_cmd53_rd_data[3] because it is equivalent to instance user_sdio_cmd53_rd_data[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : top.v(355) | Removing instance user_sdio_cmd53_rd_data[2] because it is equivalent to instance user_sdio_cmd53_rd_data[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 243MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 242MB peak: 243MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 242MB peak: 243MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 242MB peak: 243MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 242MB peak: 243MB)

@N:MO106 : user_tuning_pattern.v(48) | Found ROM u_user_tuning_pattern.un11_sdio_tuning_data[3:0] (in view: work.top(verilog)) with 144 words by 4 bits.

Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 242MB peak: 243MB)


Finished technology mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 245MB peak: 245MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:06s		    -7.30ns		3366 /       268
   2		0h:00m:06s		    -7.30ns		3362 /       268

   3		0h:00m:07s		    -7.30ns		3362 /       268

   4		0h:00m:07s		    -7.30ns		3362 /       268

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 245MB peak: 245MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to inpure port. Because it's a pure input port 
@W: :  | Converting bidirection inout port to output port. Because it's a pure output port 

Finished restoring hierarchy (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 246MB peak: 246MB)


Start Writing Netlists (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 165MB peak: 248MB)

Writing Analyst data base C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\impl\synthesize\rev_1\synwork\sdio_test_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 251MB peak: 255MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 251MB peak: 255MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 251MB peak: 255MB)


Start final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 243MB peak: 255MB)

@W:MT420 :  | Found inferred clock top|clk with period 5.76ns. Please declare a user-defined clock on port clk. 
@W:MT420 :  | Found inferred clock top|cpu_clk with period 5.73ns. Please declare a user-defined clock on port cpu_clk. 


##### START OF TIMING REPORT #####[
# Timing report written on Tue Nov 12 10:08:13 2019
#


Top view:               top
Requested Frequency:    173.5 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.017

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
top|clk            173.5 MHz     147.5 MHz     5.763         6.779         -1.017     inferred     Autoconstr_clkgroup_0
top|cpu_clk        174.6 MHz     148.4 MHz     5.727         6.737         -1.011     inferred     Autoconstr_clkgroup_1
System             150.0 MHz     330.0 MHz     6.667         3.030         3.636      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------
Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
------------------------------------------------------------------------------------------------------------------
System       top|clk      |  5.763       3.637   |  No paths    -      |  No paths    -       |  No paths    -    
System       top|cpu_clk  |  5.727       5.009   |  No paths    -      |  No paths    -       |  No paths    -    
top|clk      System       |  5.763       3.534   |  No paths    -      |  No paths    -       |  No paths    -    
top|clk      top|clk      |  5.763       -1.017  |  5.763       2.648  |  2.881       -0.051  |  No paths    -    
top|clk      top|cpu_clk  |  Diff grp    -       |  No paths    -      |  No paths    -       |  No paths    -    
top|cpu_clk  System       |  5.727       3.783   |  No paths    -      |  No paths    -       |  No paths    -    
top|cpu_clk  top|clk      |  Diff grp    -       |  No paths    -      |  Diff grp    -       |  No paths    -    
top|cpu_clk  top|cpu_clk  |  5.727       -1.011  |  No paths    -      |  No paths    -       |  No paths    -    
==================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: top|clk
====================================



Starting Points with Worst Slack
********************************

                                                                                  Starting                                                      Arrival           
Instance                                                                          Reference     Type      Pin     Net                           Time        Slack 
                                                                                  Clock                                                                           
------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_user_sdio_cmd53_if.cnt[0]                                                       top|clk       DFFCE     Q       cnt0                          0.243       -1.017
u_user_sdio_cmd53_if.cnt[1]                                                       top|clk       DFFCE     Q       cnt1                          0.243       -0.982
u_user_sdio_cmd53_if.cnt[2]                                                       top|clk       DFFCE     Q       cnt2                          0.243       -0.947
u_user_sdio_cmd53_if.cnt[3]                                                       top|clk       DFFCE     Q       cnt3                          0.243       -0.912
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_cmd_dec.fn0_abort_latch                     top|clk       DFFC      Q       fn0_abort_latch               0.243       -0.909
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_cmd_dec.cmd_crc_ok_fast                     top|clk       DFFC      Q       cmd_crc_ok_fast               0.243       -0.888
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_cmd_dec.fn1_abort_latch                     top|clk       DFFC      Q       fn1_abort_latch               0.243       -0.888
u_user_tuning_pattern.cnt[1]                                                      top|clk       DFFC      Q       cnt[1]                        0.243       -0.883
u_user_sdio_cmd53_if.cnt[4]                                                       top|clk       DFFCE     Q       cnt4                          0.243       -0.877
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_fn0_reg.\\cmd53_ctrl_fn0_addr_d1_Z\[0\]     top|clk       DFFCE     Q       cmd53_ctrl_fn0_addr_d1[0]     0.243       -0.871
==================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                Starting                                                       Required           
Instance                                                                        Reference     Type      Pin     Net                            Time         Slack 
                                                                                Clock                                                                             
------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_user_sdio_cmd53_if.c_state[0]                                                 top|clk       DFFC      D       m35_0                          5.702        -1.017
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_sdio_biu.\\io_current_state_1_Z\[3\]      top|clk       DFFC      D       N_81_i                         5.702        -0.909
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_cmd19_tx.cmd19_o_dat1                     top|clk       DFFPE     D       cmd19_o_dat1_5_iv_i            5.702        -0.883
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_fn0_reg.\\cmd53_fn0_reg_rddata_Z\[0\]     top|clk       DFFCE     D       cmd53_fn0_reg_rddata_52[0]     5.702        -0.871
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_sdio_biu.\\io_current_state_1_Z\[4\]      top|clk       DFFC      D       N_83_i                         5.702        -0.693
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_cmd53_ctrl.cmd53_ctrl_fn0_reg_rd_en       top|clk       DFFC      D       cmd53_ctrl_fn0_reg_rd_en_3     5.702        -0.646
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_fn0_reg.\\cmd53_fn0_reg_rddata_Z\[5\]     top|clk       DFFCE     D       cmd53_fn0_reg_rddata_52[5]     5.702        -0.638
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_fn0_reg.\\cmd53_fn0_reg_rddata_Z\[6\]     top|clk       DFFCE     D       cmd53_fn0_reg_rddata_52[6]     5.702        -0.638
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_fn0_reg.\\cmd53_fn0_reg_rddata_Z\[7\]     top|clk       DFFCE     D       cmd53_fn0_reg_rddata_52[7]     5.702        -0.618
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_cmd53_ctrl.cmd53_ctrl_cis_fnx_rd_en       top|clk       DFFC      D       cmd53_ctrl_cis_fnx_rd_en_3     5.702        -0.576
==================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.763
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.702

    - Propagation time:                      6.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.017

    Number of logic level(s):                17
    Starting point:                          u_user_sdio_cmd53_if.cnt[0] / Q
    Ending point:                            u_user_sdio_cmd53_if.c_state[0] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u_user_sdio_cmd53_if.cnt[0]                    DFFCE     Q        Out     0.243     0.243       -         
cnt0                                           Net       -        -       0.535     -           3         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       I0       In      -         0.778       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       COUT     Out     0.549     1.327       -         
un1_cnt_2_a_4_cry_0                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       CIN      In      -         1.327       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       SUM      Out     0.470     1.797       -         
un1_cnt_2_a_4[1]                               Net       -        -       0.535     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_1_0         ALU       I0       In      -         2.332       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_1_0         ALU       COUT     Out     0.549     2.881       -         
un1_cnt_2_0_data_tmp[0]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_1        ALU       CIN      In      -         2.881       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_1        ALU       COUT     Out     0.035     2.916       -         
un1_cnt_2_0_I_27_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_0        ALU       CIN      In      -         2.916       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_0        ALU       COUT     Out     0.035     2.951       -         
un1_cnt_2_0_data_tmp[1]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_1        ALU       CIN      In      -         2.951       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_1        ALU       COUT     Out     0.035     2.986       -         
un1_cnt_2_0_I_15_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       CIN      In      -         2.986       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       COUT     Out     0.035     3.021       -         
un1_cnt_2_0_data_tmp[2]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       CIN      In      -         3.021       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       COUT     Out     0.035     3.056       -         
un1_cnt_2_0_I_21_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       CIN      In      -         3.056       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       COUT     Out     0.035     3.091       -         
un1_cnt_2_0_data_tmp[3]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       CIN      In      -         3.091       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       COUT     Out     0.035     3.126       -         
un1_cnt_2_0_I_33_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       CIN      In      -         3.126       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       COUT     Out     0.035     3.161       -         
un1_cnt_2_0_data_tmp[4]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       CIN      In      -         3.161       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       COUT     Out     0.035     3.196       -         
un1_cnt_2_0_I_9_carry                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       CIN      In      -         3.196       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       COUT     Out     0.035     3.231       -         
un1_cnt_2_0_data_tmp[5]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       CIN      In      -         3.231       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       COUT     Out     0.035     3.266       -         
un1_cnt_2_0_I_39_0_COUT                        Net       -        -       0.961     -           5         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      I1       In      -         4.227       -         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      F        Out     0.570     4.797       -         
N_26                                           Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m34_d                     LUT4      I0       In      -         5.198       -         
u_user_sdio_cmd53_if.m34_d                     LUT4      F        Out     0.549     5.747       -         
m34_d                                          Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m35                       LUT4      I1       In      -         6.148       -         
u_user_sdio_cmd53_if.m35                       LUT4      F        Out     0.570     6.718       -         
m35_0                                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.c_state[0]                DFFC      D        In      -         6.718       -         
==========================================================================================================
Total path delay (propagation time + setup) of 6.779 is 3.946(58.2%) logic and 2.833(41.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.763
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.702

    - Propagation time:                      6.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.017

    Number of logic level(s):                17
    Starting point:                          u_user_sdio_cmd53_if.cnt[0] / Q
    Ending point:                            u_user_sdio_cmd53_if.c_state[0] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u_user_sdio_cmd53_if.cnt[0]                    DFFCE     Q        Out     0.243     0.243       -         
cnt0                                           Net       -        -       0.535     -           3         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       I0       In      -         0.778       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       COUT     Out     0.549     1.327       -         
un1_cnt_2_a_4_cry_0                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       CIN      In      -         1.327       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       COUT     Out     0.035     1.362       -         
un1_cnt_2_a_4_cry_1                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_2_0     ALU       CIN      In      -         1.362       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_2_0     ALU       SUM      Out     0.470     1.832       -         
un1_cnt_2_a_4[2]                               Net       -        -       0.535     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_1        ALU       I0       In      -         2.367       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_1        ALU       COUT     Out     0.549     2.916       -         
un1_cnt_2_0_I_27_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_0        ALU       CIN      In      -         2.916       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_0        ALU       COUT     Out     0.035     2.951       -         
un1_cnt_2_0_data_tmp[1]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_1        ALU       CIN      In      -         2.951       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_1        ALU       COUT     Out     0.035     2.986       -         
un1_cnt_2_0_I_15_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       CIN      In      -         2.986       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       COUT     Out     0.035     3.021       -         
un1_cnt_2_0_data_tmp[2]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       CIN      In      -         3.021       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       COUT     Out     0.035     3.056       -         
un1_cnt_2_0_I_21_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       CIN      In      -         3.056       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       COUT     Out     0.035     3.091       -         
un1_cnt_2_0_data_tmp[3]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       CIN      In      -         3.091       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       COUT     Out     0.035     3.126       -         
un1_cnt_2_0_I_33_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       CIN      In      -         3.126       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       COUT     Out     0.035     3.161       -         
un1_cnt_2_0_data_tmp[4]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       CIN      In      -         3.161       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       COUT     Out     0.035     3.196       -         
un1_cnt_2_0_I_9_carry                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       CIN      In      -         3.196       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       COUT     Out     0.035     3.231       -         
un1_cnt_2_0_data_tmp[5]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       CIN      In      -         3.231       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       COUT     Out     0.035     3.266       -         
un1_cnt_2_0_I_39_0_COUT                        Net       -        -       0.961     -           5         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      I1       In      -         4.227       -         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      F        Out     0.570     4.797       -         
N_26                                           Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m34_d                     LUT4      I0       In      -         5.198       -         
u_user_sdio_cmd53_if.m34_d                     LUT4      F        Out     0.549     5.747       -         
m34_d                                          Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m35                       LUT4      I1       In      -         6.148       -         
u_user_sdio_cmd53_if.m35                       LUT4      F        Out     0.570     6.718       -         
m35_0                                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.c_state[0]                DFFC      D        In      -         6.718       -         
==========================================================================================================
Total path delay (propagation time + setup) of 6.779 is 3.946(58.2%) logic and 2.833(41.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.763
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.702

    - Propagation time:                      6.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.017

    Number of logic level(s):                17
    Starting point:                          u_user_sdio_cmd53_if.cnt[0] / Q
    Ending point:                            u_user_sdio_cmd53_if.c_state[0] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u_user_sdio_cmd53_if.cnt[0]                    DFFCE     Q        Out     0.243     0.243       -         
cnt0                                           Net       -        -       0.535     -           3         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       I0       In      -         0.778       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       COUT     Out     0.549     1.327       -         
un1_cnt_2_a_4_cry_0                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       CIN      In      -         1.327       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       COUT     Out     0.035     1.362       -         
un1_cnt_2_a_4_cry_1                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_2_0     ALU       CIN      In      -         1.362       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_2_0     ALU       COUT     Out     0.035     1.397       -         
un1_cnt_2_a_4_cry_2                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_3_0     ALU       CIN      In      -         1.397       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_3_0     ALU       SUM      Out     0.470     1.867       -         
un1_cnt_2_a_4[3]                               Net       -        -       0.535     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_0        ALU       I0       In      -         2.402       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_27_0        ALU       COUT     Out     0.549     2.951       -         
un1_cnt_2_0_data_tmp[1]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_1        ALU       CIN      In      -         2.951       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_1        ALU       COUT     Out     0.035     2.986       -         
un1_cnt_2_0_I_15_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       CIN      In      -         2.986       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       COUT     Out     0.035     3.021       -         
un1_cnt_2_0_data_tmp[2]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       CIN      In      -         3.021       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       COUT     Out     0.035     3.056       -         
un1_cnt_2_0_I_21_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       CIN      In      -         3.056       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       COUT     Out     0.035     3.091       -         
un1_cnt_2_0_data_tmp[3]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       CIN      In      -         3.091       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       COUT     Out     0.035     3.126       -         
un1_cnt_2_0_I_33_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       CIN      In      -         3.126       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       COUT     Out     0.035     3.161       -         
un1_cnt_2_0_data_tmp[4]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       CIN      In      -         3.161       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       COUT     Out     0.035     3.196       -         
un1_cnt_2_0_I_9_carry                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       CIN      In      -         3.196       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       COUT     Out     0.035     3.231       -         
un1_cnt_2_0_data_tmp[5]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       CIN      In      -         3.231       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       COUT     Out     0.035     3.266       -         
un1_cnt_2_0_I_39_0_COUT                        Net       -        -       0.961     -           5         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      I1       In      -         4.227       -         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      F        Out     0.570     4.797       -         
N_26                                           Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m34_d                     LUT4      I0       In      -         5.198       -         
u_user_sdio_cmd53_if.m34_d                     LUT4      F        Out     0.549     5.747       -         
m34_d                                          Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m35                       LUT4      I1       In      -         6.148       -         
u_user_sdio_cmd53_if.m35                       LUT4      F        Out     0.570     6.718       -         
m35_0                                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.c_state[0]                DFFC      D        In      -         6.718       -         
==========================================================================================================
Total path delay (propagation time + setup) of 6.779 is 3.946(58.2%) logic and 2.833(41.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.763
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.702

    - Propagation time:                      6.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.017

    Number of logic level(s):                17
    Starting point:                          u_user_sdio_cmd53_if.cnt[0] / Q
    Ending point:                            u_user_sdio_cmd53_if.c_state[0] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u_user_sdio_cmd53_if.cnt[0]                    DFFCE     Q        Out     0.243     0.243       -         
cnt0                                           Net       -        -       0.535     -           3         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       I0       In      -         0.778       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       COUT     Out     0.549     1.327       -         
un1_cnt_2_a_4_cry_0                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       CIN      In      -         1.327       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       COUT     Out     0.035     1.362       -         
un1_cnt_2_a_4_cry_1                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_2_0     ALU       CIN      In      -         1.362       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_2_0     ALU       COUT     Out     0.035     1.397       -         
un1_cnt_2_a_4_cry_2                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_3_0     ALU       CIN      In      -         1.397       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_3_0     ALU       COUT     Out     0.035     1.432       -         
un1_cnt_2_a_4_cry_3                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_4_0     ALU       CIN      In      -         1.432       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_4_0     ALU       SUM      Out     0.470     1.902       -         
un1_cnt_2_a_4[4]                               Net       -        -       0.535     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_1        ALU       I0       In      -         2.437       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_1        ALU       COUT     Out     0.549     2.986       -         
un1_cnt_2_0_I_15_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       CIN      In      -         2.986       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       COUT     Out     0.035     3.021       -         
un1_cnt_2_0_data_tmp[2]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       CIN      In      -         3.021       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       COUT     Out     0.035     3.056       -         
un1_cnt_2_0_I_21_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       CIN      In      -         3.056       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       COUT     Out     0.035     3.091       -         
un1_cnt_2_0_data_tmp[3]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       CIN      In      -         3.091       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       COUT     Out     0.035     3.126       -         
un1_cnt_2_0_I_33_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       CIN      In      -         3.126       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       COUT     Out     0.035     3.161       -         
un1_cnt_2_0_data_tmp[4]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       CIN      In      -         3.161       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       COUT     Out     0.035     3.196       -         
un1_cnt_2_0_I_9_carry                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       CIN      In      -         3.196       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       COUT     Out     0.035     3.231       -         
un1_cnt_2_0_data_tmp[5]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       CIN      In      -         3.231       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       COUT     Out     0.035     3.266       -         
un1_cnt_2_0_I_39_0_COUT                        Net       -        -       0.961     -           5         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      I1       In      -         4.227       -         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      F        Out     0.570     4.797       -         
N_26                                           Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m34_d                     LUT4      I0       In      -         5.198       -         
u_user_sdio_cmd53_if.m34_d                     LUT4      F        Out     0.549     5.747       -         
m34_d                                          Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m35                       LUT4      I1       In      -         6.148       -         
u_user_sdio_cmd53_if.m35                       LUT4      F        Out     0.570     6.718       -         
m35_0                                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.c_state[0]                DFFC      D        In      -         6.718       -         
==========================================================================================================
Total path delay (propagation time + setup) of 6.779 is 3.946(58.2%) logic and 2.833(41.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.763
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.702

    - Propagation time:                      6.718
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.017

    Number of logic level(s):                17
    Starting point:                          u_user_sdio_cmd53_if.cnt[0] / Q
    Ending point:                            u_user_sdio_cmd53_if.c_state[0] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                           Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u_user_sdio_cmd53_if.cnt[0]                    DFFCE     Q        Out     0.243     0.243       -         
cnt0                                           Net       -        -       0.535     -           3         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       I0       In      -         0.778       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_0_0     ALU       COUT     Out     0.549     1.327       -         
un1_cnt_2_a_4_cry_0                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       CIN      In      -         1.327       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_1_0     ALU       COUT     Out     0.035     1.362       -         
un1_cnt_2_a_4_cry_1                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_2_0     ALU       CIN      In      -         1.362       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_2_0     ALU       COUT     Out     0.035     1.397       -         
un1_cnt_2_a_4_cry_2                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_3_0     ALU       CIN      In      -         1.397       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_3_0     ALU       COUT     Out     0.035     1.432       -         
un1_cnt_2_a_4_cry_3                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_4_0     ALU       CIN      In      -         1.432       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_4_0     ALU       COUT     Out     0.035     1.467       -         
un1_cnt_2_a_4_cry_4                            Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_5_0     ALU       CIN      In      -         1.467       -         
u_user_sdio_cmd53_if.un1_cnt_2_a_4_cry_5_0     ALU       SUM      Out     0.470     1.937       -         
un1_cnt_2_a_4[5]                               Net       -        -       0.535     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       I0       In      -         2.472       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_15_0        ALU       COUT     Out     0.549     3.021       -         
un1_cnt_2_0_data_tmp[2]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       CIN      In      -         3.021       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_1        ALU       COUT     Out     0.035     3.056       -         
un1_cnt_2_0_I_21_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       CIN      In      -         3.056       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_21_0        ALU       COUT     Out     0.035     3.091       -         
un1_cnt_2_0_data_tmp[3]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       CIN      In      -         3.091       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_1        ALU       COUT     Out     0.035     3.126       -         
un1_cnt_2_0_I_33_carry                         Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       CIN      In      -         3.126       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_33_0        ALU       COUT     Out     0.035     3.161       -         
un1_cnt_2_0_data_tmp[4]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       CIN      In      -         3.161       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_1         ALU       COUT     Out     0.035     3.196       -         
un1_cnt_2_0_I_9_carry                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       CIN      In      -         3.196       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_9_0         ALU       COUT     Out     0.035     3.231       -         
un1_cnt_2_0_data_tmp[5]                        Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       CIN      In      -         3.231       -         
u_user_sdio_cmd53_if.un1_cnt_2_0_I_39_0        ALU       COUT     Out     0.035     3.266       -         
un1_cnt_2_0_I_39_0_COUT                        Net       -        -       0.961     -           5         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      I1       In      -         4.227       -         
u_user_sdio_cmd53_if.m34_d_RNO                 LUT2      F        Out     0.570     4.797       -         
N_26                                           Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m34_d                     LUT4      I0       In      -         5.198       -         
u_user_sdio_cmd53_if.m34_d                     LUT4      F        Out     0.549     5.747       -         
m34_d                                          Net       -        -       0.401     -           1         
u_user_sdio_cmd53_if.m35                       LUT4      I1       In      -         6.148       -         
u_user_sdio_cmd53_if.m35                       LUT4      F        Out     0.570     6.718       -         
m35_0                                          Net       -        -       0.000     -           1         
u_user_sdio_cmd53_if.c_state[0]                DFFC      D        In      -         6.718       -         
==========================================================================================================
Total path delay (propagation time + setup) of 6.779 is 3.946(58.2%) logic and 2.833(41.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: top|cpu_clk
====================================



Starting Points with Worst Slack
********************************

                                                                 Starting                                                 Arrival           
Instance                                                         Reference       Type      Pin     Net                    Time        Slack 
                                                                 Clock                                                                      
--------------------------------------------------------------------------------------------------------------------------------------------
u_user_cpu_slave_reg_if.slv_cpu_addr_1[5]                        top|cpu_clk     DFFCE     Q       slv_cpu_addr[5]        0.243       -1.011
u_user_cpu_slave_reg_if.slv_cpu_addr_1[4]                        top|cpu_clk     DFFCE     Q       slv_cpu_addr[4]        0.243       -0.990
u_user_cpu_slave_reg_if.slv_cpu_addr_1[3]                        top|cpu_clk     DFFCE     Q       slv_cpu_addr[3]        0.243       -0.060
u_user_cpu_slave_reg_if.slv_cpu_byte_en[2]                       top|cpu_clk     DFFCE     Q       slv_cpu_byte_en[2]     0.243       0.974 
u_user_cpu_slave_reg_if.slv_cpu_cs                               top|cpu_clk     DFFCE     Q       slv_cpu_cs             0.243       1.024 
u_user_cpu_slave_reg_if.slv_cpu_addr_1[2]                        top|cpu_clk     DFFCE     Q       slv_cpu_addr[2]        0.243       1.117 
u_user_cpu_slave_reg_if.slv_cpu_op                               top|cpu_clk     DFFCE     Q       slv_cpu_op             0.243       1.132 
u_user_cpu_slave_reg_if.cnt[0]                                   top|cpu_clk     DFFCE     Q       cnt[0]                 0.243       2.089 
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.slv_cpu_ack     top|cpu_clk     DFFC      Q       slv_cpu_ack            0.243       2.110 
led_reg[1]                                                       top|cpu_clk     DFF       Q       led_reg[1]             0.243       2.396 
============================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                  Starting                                                        Required           
Instance                                                                          Reference       Type      Pin     Net                           Time         Slack 
                                                                                  Clock                                                                              
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[0\]     top|cpu_clk     DFFP      D       fbr1_std_fn_if_codee_0[0]     5.666        -1.011
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[1\]     top|cpu_clk     DFFP      D       fbr1_std_fn_if_codee_0[1]     5.666        -1.011
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[2\]     top|cpu_clk     DFFP      D       fbr1_std_fn_if_codee_0[2]     5.666        -1.011
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[3\]     top|cpu_clk     DFFP      D       fbr1_std_fn_if_codee_0[3]     5.666        -1.011
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_isdio_type_Z\[0\]         top|cpu_clk     DFFCE     CE      m15_0                         5.666        -0.462
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_isdio_type_Z\[1\]         top|cpu_clk     DFFCE     CE      m15_0                         5.666        -0.462
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_isdio_type_Z\[2\]         top|cpu_clk     DFFCE     CE      m15_0                         5.666        -0.462
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_isdio_type_Z\[3\]         top|cpu_clk     DFFCE     CE      m15_0                         5.666        -0.462
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_isdio_type_Z\[4\]         top|cpu_clk     DFFCE     CE      m15_0                         5.666        -0.462
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_isdio_type_Z\[5\]         top|cpu_clk     DFFCE     CE      m15_0                         5.666        -0.462
=====================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.727
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.666

    - Propagation time:                      6.676
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.011

    Number of logic level(s):                6
    Starting point:                          u_user_cpu_slave_reg_if.slv_cpu_addr_1[5] / Q
    Ending point:                            u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[0\] / D
    The start point is clocked by            top|cpu_clk [rising] on pin CLK
    The end   point is clocked by            top|cpu_clk [rising] on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
u_user_cpu_slave_reg_if.slv_cpu_addr_1[5]                                         DFFCE     Q        Out     0.243     0.243       -         
slv_cpu_addr[5]                                                                   Net       -        -       0.535     -           7         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      I1       In      -         0.778       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      F        Out     0.570     1.348       -         
N_2                                                                               Net       -        -       0.401     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      I0       In      -         1.749       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      F        Out     0.549     2.298       -         
N_19_mux                                                                          Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      I0       In      -         2.833       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      F        Out     0.549     3.382       -         
m11_N_7_mux                                                                       Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      I1       In      -         3.917       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      F        Out     0.570     4.487       -         
m15_m2_e_0                                                                        Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      I1       In      -         5.022       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      F        Out     0.570     5.592       -         
N_17                                                                              Net       -        -       0.535     -           4         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[0\]      LUT3      I0       In      -         6.127       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[0\]      LUT3      F        Out     0.549     6.676       -         
fbr1_std_fn_if_codee_0[0]                                                         Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[0\]     DFFP      D        In      -         6.676       -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 6.737 is 3.661(54.3%) logic and 3.076(45.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.727
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.666

    - Propagation time:                      6.676
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.011

    Number of logic level(s):                6
    Starting point:                          u_user_cpu_slave_reg_if.slv_cpu_addr_1[5] / Q
    Ending point:                            u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[3\] / D
    The start point is clocked by            top|cpu_clk [rising] on pin CLK
    The end   point is clocked by            top|cpu_clk [rising] on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
u_user_cpu_slave_reg_if.slv_cpu_addr_1[5]                                         DFFCE     Q        Out     0.243     0.243       -         
slv_cpu_addr[5]                                                                   Net       -        -       0.535     -           7         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      I1       In      -         0.778       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      F        Out     0.570     1.348       -         
N_2                                                                               Net       -        -       0.401     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      I0       In      -         1.749       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      F        Out     0.549     2.298       -         
N_19_mux                                                                          Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      I0       In      -         2.833       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      F        Out     0.549     3.382       -         
m11_N_7_mux                                                                       Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      I1       In      -         3.917       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      F        Out     0.570     4.487       -         
m15_m2_e_0                                                                        Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      I1       In      -         5.022       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      F        Out     0.570     5.592       -         
N_17                                                                              Net       -        -       0.535     -           4         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[3\]      LUT2      I0       In      -         6.127       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[3\]      LUT2      F        Out     0.549     6.676       -         
fbr1_std_fn_if_codee_0[3]                                                         Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[3\]     DFFP      D        In      -         6.676       -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 6.737 is 3.661(54.3%) logic and 3.076(45.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.727
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.666

    - Propagation time:                      6.676
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.011

    Number of logic level(s):                6
    Starting point:                          u_user_cpu_slave_reg_if.slv_cpu_addr_1[5] / Q
    Ending point:                            u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[2\] / D
    The start point is clocked by            top|cpu_clk [rising] on pin CLK
    The end   point is clocked by            top|cpu_clk [rising] on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
u_user_cpu_slave_reg_if.slv_cpu_addr_1[5]                                         DFFCE     Q        Out     0.243     0.243       -         
slv_cpu_addr[5]                                                                   Net       -        -       0.535     -           7         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      I1       In      -         0.778       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      F        Out     0.570     1.348       -         
N_2                                                                               Net       -        -       0.401     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      I0       In      -         1.749       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      F        Out     0.549     2.298       -         
N_19_mux                                                                          Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      I0       In      -         2.833       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      F        Out     0.549     3.382       -         
m11_N_7_mux                                                                       Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      I1       In      -         3.917       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      F        Out     0.570     4.487       -         
m15_m2_e_0                                                                        Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      I1       In      -         5.022       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      F        Out     0.570     5.592       -         
N_17                                                                              Net       -        -       0.535     -           4         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[2\]      LUT2      I0       In      -         6.127       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[2\]      LUT2      F        Out     0.549     6.676       -         
fbr1_std_fn_if_codee_0[2]                                                         Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[2\]     DFFP      D        In      -         6.676       -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 6.737 is 3.661(54.3%) logic and 3.076(45.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.727
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.666

    - Propagation time:                      6.676
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.011

    Number of logic level(s):                6
    Starting point:                          u_user_cpu_slave_reg_if.slv_cpu_addr_1[5] / Q
    Ending point:                            u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[1\] / D
    The start point is clocked by            top|cpu_clk [rising] on pin CLK
    The end   point is clocked by            top|cpu_clk [rising] on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
u_user_cpu_slave_reg_if.slv_cpu_addr_1[5]                                         DFFCE     Q        Out     0.243     0.243       -         
slv_cpu_addr[5]                                                                   Net       -        -       0.535     -           7         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      I1       In      -         0.778       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      F        Out     0.570     1.348       -         
N_2                                                                               Net       -        -       0.401     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      I0       In      -         1.749       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      F        Out     0.549     2.298       -         
N_19_mux                                                                          Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      I0       In      -         2.833       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      F        Out     0.549     3.382       -         
m11_N_7_mux                                                                       Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      I1       In      -         3.917       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      F        Out     0.570     4.487       -         
m15_m2_e_0                                                                        Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      I1       In      -         5.022       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      F        Out     0.570     5.592       -         
N_17                                                                              Net       -        -       0.535     -           4         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[1\]      LUT2      I0       In      -         6.127       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[1\]      LUT2      F        Out     0.549     6.676       -         
fbr1_std_fn_if_codee_0[1]                                                         Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[1\]     DFFP      D        In      -         6.676       -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 6.737 is 3.661(54.3%) logic and 3.076(45.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.727
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.666

    - Propagation time:                      6.655
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.990

    Number of logic level(s):                6
    Starting point:                          u_user_cpu_slave_reg_if.slv_cpu_addr_1[4] / Q
    Ending point:                            u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[0\] / D
    The start point is clocked by            top|cpu_clk [rising] on pin CLK
    The end   point is clocked by            top|cpu_clk [rising] on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
u_user_cpu_slave_reg_if.slv_cpu_addr_1[4]                                         DFFCE     Q        Out     0.243     0.243       -         
slv_cpu_addr[4]                                                                   Net       -        -       0.535     -           7         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      I0       In      -         0.778       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m1                               LUT2      F        Out     0.549     1.327       -         
N_2                                                                               Net       -        -       0.401     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      I0       In      -         1.728       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m3                               LUT2      F        Out     0.549     2.277       -         
N_19_mux                                                                          Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      I0       In      -         2.812       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e                         LUT3      F        Out     0.549     3.361       -         
m11_N_7_mux                                                                       Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      I1       In      -         3.896       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m11_m3_e_RNIUJ55                 LUT2      F        Out     0.570     4.466       -         
m15_m2_e_0                                                                        Net       -        -       0.535     -           2         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      I1       In      -         5.001       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.m16_m3_i_m2                      LUT3      F        Out     0.570     5.571       -         
N_17                                                                              Net       -        -       0.535     -           4         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[0\]      LUT3      I0       In      -         6.106       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_codee\[0\]      LUT3      F        Out     0.549     6.655       -         
fbr1_std_fn_if_codee_0[0]                                                         Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_slv_cpu_if.\\fbr1_std_fn_if_code_Z\[0\]     DFFP      D        In      -         6.655       -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 6.716 is 3.640(54.2%) logic and 3.076(45.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                                                  Starting                                         Arrival          
Instance                                                                          Reference     Type     Pin     Net               Time        Slack
                                                                                  Clock                                                             
----------------------------------------------------------------------------------------------------------------------------------------------------
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_fn0_reg.cmd52_rst_gen_fast_fast_RNI9R86     System        INV      O       cmd52_rst_i       0.000       3.636
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.rstn_i                      System        INV      O       rstn_i            0.000       5.009
led\[0\]_RNO                                                                      System        INV      O       led_c_i[0]        0.000       5.131
u_user_cpu_slave_reg_if.slv_cpu_op_RNO                                            System        INV      O       N_324_i           0.000       5.131
u_sdio_slave_ctrl.u_sdio_slave_ctrl_slv_cpu_ack_RNIP1N9                           System        INV      O       slv_cpu_ack_i     0.000       5.131
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_cmd_dec.any_cmd_RNO                         System        INV      O       N_1220_i          0.000       5.167
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_cmd53_tx_rx.o_dat1_9_m1_xx_RNIEER4          System        INV      O       N_1175_i          0.000       5.167
rstn_ibuf_RNIC1J4                                                                 System        INV      O       rstn_c_i          0.000       5.167
====================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                        Starting                                      Required          
Instance                                                                Reference     Type      Pin     Net           Time         Slack
                                                                        Clock                                                           
----------------------------------------------------------------------------------------------------------------------------------------
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[15\]     System        DFFCE     D       rca_s[15]     5.702        3.636
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[14\]     System        DFFCE     D       rca_s[14]     5.702        3.671
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[13\]     System        DFFCE     D       rca_s[13]     5.702        3.707
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[12\]     System        DFFCE     D       rca_s[12]     5.702        3.741
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[11\]     System        DFFCE     D       rca_s[11]     5.702        3.776
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[10\]     System        DFFCE     D       rca_s[10]     5.702        3.812
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[9\]      System        DFFCE     D       rca_s[9]      5.702        3.846
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[8\]      System        DFFCE     D       rca_s[8]      5.702        3.881
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[7\]      System        DFFCE     D       rca_s[7]      5.702        3.917
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[6\]      System        DFFCE     D       rca_s[6]      5.702        3.951
========================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.763
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.702

    - Propagation time:                      2.065
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.637

    Number of logic level(s):                16
    Starting point:                          u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_fn0_reg.cmd52_rst_gen_fast_fast_RNI9R86 / O
    Ending point:                            u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[15\] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                              Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_fn0_reg.cmd52_rst_gen_fast_fast_RNI9R86     INV       O        Out     0.000     0.000       -         
cmd52_rst_i                                                                       Net       -        -       0.535     -           4         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[0\]            ALU       CIN      In      -         0.535       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[0\]            ALU       COUT     Out     0.035     0.570       -         
rca_cry[0]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[1\]            ALU       CIN      In      -         0.570       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[1\]            ALU       COUT     Out     0.035     0.605       -         
rca_cry[1]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[2\]            ALU       CIN      In      -         0.605       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[2\]            ALU       COUT     Out     0.035     0.640       -         
rca_cry[2]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[3\]            ALU       CIN      In      -         0.640       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[3\]            ALU       COUT     Out     0.035     0.675       -         
rca_cry[3]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[4\]            ALU       CIN      In      -         0.675       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[4\]            ALU       COUT     Out     0.035     0.710       -         
rca_cry[4]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[5\]            ALU       CIN      In      -         0.710       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[5\]            ALU       COUT     Out     0.035     0.745       -         
rca_cry[5]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[6\]            ALU       CIN      In      -         0.745       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[6\]            ALU       COUT     Out     0.035     0.780       -         
rca_cry[6]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[7\]            ALU       CIN      In      -         0.780       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[7\]            ALU       COUT     Out     0.035     0.815       -         
rca_cry[7]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[8\]            ALU       CIN      In      -         0.815       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[8\]            ALU       COUT     Out     0.035     0.850       -         
rca_cry[8]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[9\]            ALU       CIN      In      -         0.850       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[9\]            ALU       COUT     Out     0.035     0.885       -         
rca_cry[9]                                                                        Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[10\]           ALU       CIN      In      -         0.885       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[10\]           ALU       COUT     Out     0.035     0.920       -         
rca_cry[10]                                                                       Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[11\]           ALU       CIN      In      -         0.920       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[11\]           ALU       COUT     Out     0.035     0.955       -         
rca_cry[11]                                                                       Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[12\]           ALU       CIN      In      -         0.955       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[12\]           ALU       COUT     Out     0.035     0.990       -         
rca_cry[12]                                                                       Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[13\]           ALU       CIN      In      -         0.990       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[13\]           ALU       COUT     Out     0.035     1.025       -         
rca_cry[13]                                                                       Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[14\]           ALU       CIN      In      -         1.025       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_cry_0\[14\]           ALU       COUT     Out     0.035     1.060       -         
rca_cry[14]                                                                       Net       -        -       0.000     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_s_0\[15\]             ALU       CIN      In      -         1.060       -         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_s_0\[15\]             ALU       SUM      Out     0.470     1.530       -         
rca_s[15]                                                                         Net       -        -       0.535     -           1         
u_sdio_slave_ctrl.u_sdio_slave_ctrl.u_card_fixed_regs.\\rca_Z\[15\]               DFFCE     D        In      -         2.065       -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 2.126 is 1.056(49.7%) logic and 1.070(50.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 245MB peak: 255MB)


Finished timing report (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 245MB peak: 255MB)

---------------------------------------
Resource Usage Report for top 

Mapping to part: gw2a_18pbga256-8
Cell usage:
ALU             403 uses
DFF             118 uses
DFFC            419 uses
DFFCE           1189 uses
DFFE            1 use
DFFNC           15 uses
DFFNCE          1 use
DFFNP           7 uses
DFFP            26 uses
DFFPE           45 uses
DFFR            4 uses
GSR             1 use
INV             8 uses
MUX2_LUT5       163 uses
MUX2_LUT6       53 uses
MUX2_LUT7       16 uses
LUT1            7 uses
LUT2            779 uses
LUT3            1003 uses
LUT4            1520 uses

I/O ports: 127
I/O primitives: 127
IBUF           5 uses
IOBUF          5 uses
OBUF           117 uses

I/O Register bits:                  0
Register bits not including I/Os:   1825 of 15552 (11%)
Total load per clock:
   top|clk: 1594
   top|cpu_clk: 213

@S |Mapping Summary:
Total  LUTs: 3309 (15%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 81MB peak: 255MB)

Process took 0h:00m:15s realtime, 0h:00m:14s cputime
# Tue Nov 12 10:08:13 2019

###########################################################]