#Build: Synplify Pro (R) P-2019.03G, Build 307R, Sep 25 2019 #install: D:\Gowin\sdio_sweg\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-050 # Tue Nov 12 10:08:49 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_control\gw_con_parameter.v" (library work) @I::"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_control\gw_con_top_define.v" (library work) @I::"D:\Gowin\sdio_sweg\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v" (library work) @W:CG1337 : gw_con_top.v(194) | Net capture_dr is not declared. @W:CG1337 : gw_con_top.v(208) | Net enable_i_delay is not declared. Verilog syntax check successful! @N:CG364 : gw_con_parameter.v(1) | Synthesizing module work_C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\temp\gao\ao_control\gw_con_parameter.v_unit in library work. Selecting top level module gw_con_top Running optimization stage 1 on MUX16 ....... Running optimization stage 1 on gw_con_top ....... Running optimization stage 2 on gw_con_top ....... Running optimization stage 2 on MUX16 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 88MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Nov 12 10:08:50 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.03G Install: D:\Gowin\sdio_sweg\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-050 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Nov 12 10:08:51 2019 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: ao_control_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 19MB peak: 19MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Nov 12 10:08:51 2019 ###########################################################]