Timing Messages
Report Title | Timing Analysis Report |
Design File | C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\impl\gwsynthesis\sdio_test.vg |
Physical Constraints File | C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\src\sdio_test.cst |
Timing Constraint File | C:\Users\liangui\Desktop\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\src\sdio_test.sdc |
Version | V1.9.8.10 |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Created Time | Mon Dec 05 10:30:12 2022 |
Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 5372 |
Numbers of Endpoints Analyzed | 5238 |
Numbers of Falling Endpoints | 9 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
sdio_clkin | Base | 10.000 | 100.000 | 0.000 | 5.000 | sdio_clk | ||
sym_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | sym_clk | ||
cpu_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | cpu_clk_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | sdio_clkin | 100.000(MHz) | 315.474(MHz) | 5 | TOP |
2 | sym_clk | 100.000(MHz) | 112.023(MHz) | 7 | TOP |
3 | cpu_clk | 100.000(MHz) | 219.747(MHz) | 5 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
sdio_clkin | Setup | 0.000 | 0 |
sdio_clkin | Hold | 0.000 | 0 |
sym_clk | Setup | 0.000 | 0 |
sym_clk | Hold | 0.000 | 0 |
cpu_clk | Setup | 0.000 | 0 |
cpu_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.717 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_sync_irq_s1/D | sym_clk:[R] | sym_clk:[F] | 5.000 | -0.018 | 4.266 |
2 | 0.717 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_irq_sel_s1/D | sym_clk:[R] | sym_clk:[F] | 5.000 | -0.018 | 4.266 |
3 | 1.073 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_4_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_5_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.892 |
4 | 1.073 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/fn0_addr_d1_1_s3/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_fn0_reg_rd_data_2_s0/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.892 |
5 | 1.290 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_resp_conv/resp_bit_oen_s0/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/pos_edge_clk_send_en_s3/D | sym_clk:[R] | sym_clk:[F] | 5.000 | -0.018 | 3.693 |
6 | 1.378 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_7_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.587 |
7 | 1.389 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_3_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.576 |
8 | 1.428 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_0_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.537 |
9 | 1.463 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_5_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.502 |
10 | 1.505 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_4_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.460 |
11 | 1.571 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_12_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.394 |
12 | 1.626 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_9_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.339 |
13 | 1.626 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_11_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.339 |
14 | 1.668 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_4_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.297 |
15 | 1.668 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_6_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.297 |
16 | 1.668 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_8_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.297 |
17 | 1.668 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_10_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.297 |
18 | 1.668 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_12_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.297 |
19 | 1.668 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_14_s1/D | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.297 |
20 | 1.703 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_1_s1/CE | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.262 |
21 | 1.703 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_2_s1/CE | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.262 |
22 | 1.703 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_3_s1/CE | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.262 |
23 | 1.703 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_5_s1/CE | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.262 |
24 | 1.703 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_7_s1/CE | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.262 |
25 | 1.703 | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_8_s1/CE | sym_clk:[R] | sym_clk:[R] | 10.000 | 0.000 | 8.262 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.322 | u_user_sdio_cmd52_if/sdio_cmd52_cs_d1_s0/Q | u_user_sdio_cmd52_if/sdio_cmd52_rd_data_2_s0/CE | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.333 |
2 | 0.359 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_resp_gen/cmd52_fn0_reg_addr_15_s0/Q | u_user_cpu_slave_reg_if/int_clr_flag_d1_s0/D | sym_clk:[R] | cpu_clk:[R] | 0.000 | -0.675 | 1.081 |
3 | 0.425 | u_deUstb1/cnt_5_s0/Q | u_deUstb1/cnt_5_s0/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
4 | 0.425 | u_deUstb1/cnt_11_s0/Q | u_deUstb1/cnt_11_s0/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
5 | 0.425 | u_deUstb1/cnt_12_s0/Q | u_deUstb1/cnt_12_s0/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
6 | 0.425 | u_deUstb1/cnt_19_s0/Q | u_deUstb1/cnt_19_s0/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
7 | 0.425 | u_deUstb/cnt_1_s0/Q | u_deUstb/cnt_1_s0/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
8 | 0.425 | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_0_s3/Q | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_0_s3/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
9 | 0.425 | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_1_s3/Q | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_1_s3/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
10 | 0.425 | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_8_s3/Q | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_8_s3/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
11 | 0.425 | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_9_s3/Q | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_9_s3/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
12 | 0.425 | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_10_s3/Q | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_10_s3/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
13 | 0.425 | u_user_sdio_cmd53_if/idle_to_rd_delay_3_s1/Q | u_user_sdio_cmd53_if/idle_to_rd_delay_3_s1/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
14 | 0.425 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/data_cmd_error_cnt_6_s0/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/data_cmd_error_cnt_6_s0/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
15 | 0.425 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_2_s3/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_2_s3/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
16 | 0.425 | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_6_s3/Q | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_6_s3/D | sym_clk:[R] | sym_clk:[R] | 0.000 | 0.000 | 0.436 |
17 | 0.425 | u_user_cpu_slave_reg_if/cnt_7_s3/Q | u_user_cpu_slave_reg_if/cnt_7_s3/D | cpu_clk:[R] | cpu_clk:[R] | 0.000 | 0.000 | 0.436 |
18 | 0.425 | u_user_cpu_slave_reg_if/cnt_3_s1/Q | u_user_cpu_slave_reg_if/cnt_3_s1/D | cpu_clk:[R] | cpu_clk:[R] | 0.000 | 0.000 | 0.436 |
19 | 0.425 | led_reg_3_s0/Q | led_reg_3_s0/D | cpu_clk:[R] | cpu_clk:[R] | 0.000 | 0.000 | 0.436 |
20 | 0.425 | led_reg_7_s0/Q | led_reg_7_s0/D | cpu_clk:[R] | cpu_clk:[R] | 0.000 | 0.000 | 0.436 |
21 | 0.425 | led_reg_9_s0/Q | led_reg_9_s0/D | cpu_clk:[R] | cpu_clk:[R] | 0.000 | 0.000 | 0.436 |
22 | 0.425 | led_reg_13_s0/Q | led_reg_13_s0/D | cpu_clk:[R] | cpu_clk:[R] | 0.000 | 0.000 | 0.436 |
23 | 0.425 | led_reg_15_s0/Q | led_reg_15_s0/D | cpu_clk:[R] | cpu_clk:[R] | 0.000 | 0.000 | 0.436 |
24 | 0.425 | led_reg_19_s0/Q | led_reg_19_s0/D | cpu_clk:[R] | cpu_clk:[R] | 0.000 | 0.000 | 0.436 |
25 | 0.425 | led_reg_21_s0/Q | led_reg_21_s0/D | cpu_clk:[R] | cpu_clk:[R] | 0.000 | 0.000 | 0.436 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.911 | 4.911 | 1.000 | Low Pulse Width | sdio_clkin | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_cmd_oen_temp_1d_s0 |
2 | 3.911 | 4.911 | 1.000 | Low Pulse Width | sdio_clkin | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat1_out_temp_1d_s0 |
3 | 3.911 | 4.911 | 1.000 | Low Pulse Width | sdio_clkin | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat1_oen_temp_1d_s0 |
4 | 3.911 | 4.911 | 1.000 | Low Pulse Width | sdio_clkin | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat0_oen_s0 |
5 | 3.911 | 4.911 | 1.000 | Low Pulse Width | sdio_clkin | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/reg_pos_o_cmd_di_en_s0 |
6 | 3.911 | 4.911 | 1.000 | Low Pulse Width | sdio_clkin | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/neg_cmd19_o_dat3_s0 |
7 | 3.911 | 4.911 | 1.000 | Low Pulse Width | cpu_clk | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_slv_cpu_if/fbr1_std_fn_if_code_3_s1 |
8 | 3.911 | 4.911 | 1.000 | Low Pulse Width | cpu_clk | u_user_cpu_slave_reg_if/slv_cpu_wr_data_13_s0 |
9 | 3.911 | 4.911 | 1.000 | Low Pulse Width | cpu_clk | u_user_cpu_slave_reg_if/slv_cpu_wr_data_14_s0 |
10 | 3.911 | 4.911 | 1.000 | Low Pulse Width | cpu_clk | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_slv_cpu_if/cccr_sdta_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.717 |
Data Arrival Time | 4.509 |
Data Required Time | 5.226 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_sync_irq_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R22C28[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 998 | R22C28[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/Q |
3.939 | 3.464 | tNET | FF | 1 | R31C44[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/n183_s1/I0 |
4.509 | 0.570 | tINS | FR | 1 | R31C44[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/n183_s1/F |
4.509 | 0.000 | tNET | RR | 1 | R31C44[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_sync_irq_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | sym_clk | ||||
5.000 | 0.000 | tCL | FF | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | 1 | R31C44[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_sync_irq_s1/CLK |
5.226 | -0.035 | tSu | 1 | R31C44[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_sync_irq_s1 |
Path Statistics:
Clock Skew | 0.018 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.570, 13.362%; route: 3.464, 81.200%; tC2Q: 0.232, 5.438% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
Path2
Path Summary:
Slack | 0.717 |
Data Arrival Time | 4.509 |
Data Required Time | 5.226 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_irq_sel_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R22C28[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 998 | R22C28[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/Q |
3.939 | 3.464 | tNET | FF | 1 | R31C44[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/n182_s1/I0 |
4.509 | 0.570 | tINS | FR | 1 | R31C44[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/n182_s1/F |
4.509 | 0.000 | tNET | RR | 1 | R31C44[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_irq_sel_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | sym_clk | ||||
5.000 | 0.000 | tCL | FF | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | 1 | R31C44[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_irq_sel_s1/CLK |
5.226 | -0.035 | tSu | 1 | R31C44[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/negedge_sdio_irq_sel_s1 |
Path Statistics:
Clock Skew | 0.018 |
Setup Relationship | 5.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.570, 13.362%; route: 3.464, 81.200%; tC2Q: 0.232, 5.438% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
Path3
Path Summary:
Slack | 1.073 |
Data Arrival Time | 9.135 |
Data Required Time | 10.208 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_4_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_5_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R41C26[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_4_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 44 | R41C26[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_4_s1/Q |
2.148 | 1.673 | tNET | FF | 1 | R32C16[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/regf4_d1_8_s6/I2 |
2.703 | 0.555 | tINS | FF | 5 | R32C16[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/regf4_d1_8_s6/F |
3.643 | 0.940 | tNET | FF | 1 | R24C21[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/regf5_d1_8_s7/I2 |
4.198 | 0.555 | tINS | FF | 18 | R24C21[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/regf5_d1_8_s7/F |
5.254 | 1.056 | tNET | FF | 1 | R36C21[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n728_s26/I2 |
5.809 | 0.555 | tINS | FF | 2 | R36C21[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n728_s26/F |
6.304 | 0.494 | tNET | FF | 1 | R34C23[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n725_s9/I3 |
6.821 | 0.517 | tINS | FF | 1 | R34C23[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n725_s9/F |
7.719 | 0.899 | tNET | FF | 1 | R31C26[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n725_s3/I1 |
8.274 | 0.555 | tINS | FF | 1 | R31C26[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n725_s3/F |
8.764 | 0.490 | tNET | FF | 1 | R35C26[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n725_s1/I1 |
9.135 | 0.371 | tINS | FF | 1 | R35C26[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n725_s1/F |
9.135 | 0.000 | tNET | FF | 1 | R35C26[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R35C26[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_5_s1/CLK |
10.208 | -0.035 | tSu | 1 | R35C26[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.108, 34.954%; route: 5.552, 62.437%; tC2Q: 0.232, 2.609% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
Slack | 1.073 |
Data Arrival Time | 9.135 |
Data Required Time | 10.208 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/fn0_addr_d1_1_s3 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_fn0_reg_rd_data_2_s0 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R25C14[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/fn0_addr_d1_1_s3/CLK |
0.475 | 0.232 | tC2Q | RF | 50 | R25C14[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/fn0_addr_d1_1_s3/Q |
2.633 | 2.157 | tNET | FF | 1 | R22C16[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1051_s20/I1 |
3.188 | 0.555 | tINS | FF | 12 | R22C16[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1051_s20/F |
3.699 | 0.512 | tNET | FF | 1 | R25C16[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1049_s22/I0 |
4.216 | 0.517 | tINS | FF | 5 | R25C16[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1049_s22/F |
5.481 | 1.264 | tNET | FF | 1 | R26C19[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1050_s21/I3 |
6.036 | 0.555 | tINS | FF | 1 | R26C19[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1050_s21/F |
6.692 | 0.656 | tNET | FF | 1 | R22C19[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1050_s7/I2 |
7.209 | 0.517 | tINS | FF | 1 | R22C19[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1050_s7/F |
7.864 | 0.656 | tNET | FF | 1 | R22C23[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1050_s2/I2 |
8.413 | 0.549 | tINS | FR | 1 | R22C23[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1050_s2/F |
8.586 | 0.172 | tNET | RR | 1 | R23C23[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1050_s1/I0 |
9.135 | 0.549 | tINS | RR | 1 | R23C23[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n1050_s1/F |
9.135 | 0.000 | tNET | RR | 1 | R23C23[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_fn0_reg_rd_data_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R23C23[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_fn0_reg_rd_data_2_s0/CLK |
10.208 | -0.035 | tSu | 1 | R23C23[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_fn0_reg_rd_data_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.242, 36.461%; route: 5.418, 60.929%; tC2Q: 0.232, 2.609% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
Slack | 1.290 |
Data Arrival Time | 3.936 |
Data Required Time | 5.226 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_resp_conv/resp_bit_oen_s0 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/pos_edge_clk_send_en_s3 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R30C35[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_resp_conv/resp_bit_oen_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 14 | R30C35[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_resp_conv/resp_bit_oen_s0/Q |
1.303 | 0.828 | tNET | FF | 1 | R21C31[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/pos_edge_clk_send_en_s7/I0 |
1.820 | 0.517 | tINS | FF | 2 | R21C31[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/pos_edge_clk_send_en_s7/F |
2.585 | 0.765 | tNET | FF | 1 | R25C27[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n4075_s3/I3 |
3.140 | 0.555 | tINS | FF | 1 | R25C27[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n4075_s3/F |
3.387 | 0.247 | tNET | FF | 1 | R25C28[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n4075_s2/I1 |
3.936 | 0.549 | tINS | FR | 1 | R25C28[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n4075_s2/F |
3.936 | 0.000 | tNET | RR | 1 | R25C28[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/pos_edge_clk_send_en_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | sym_clk | ||||
5.000 | 0.000 | tCL | FF | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | 1 | R25C28[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/pos_edge_clk_send_en_s3/CLK |
5.226 | -0.035 | tSu | 1 | R25C28[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/pos_edge_clk_send_en_s3 |
Path Statistics:
Clock Skew | 0.018 |
Setup Relationship | 5.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 1.621, 43.894%; route: 1.840, 49.824%; tC2Q: 0.232, 6.282% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
Path6
Path Summary:
Slack | 1.378 |
Data Arrival Time | 8.830 |
Data Required Time | 10.208 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_7_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R41C27[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 63 | R41C27[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1/Q |
2.242 | 1.767 | tNET | FF | 1 | R26C16[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/regf2_d1_8_s4/I1 |
2.759 | 0.517 | tINS | FF | 31 | R26C16[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/regf2_d1_8_s4/F |
4.926 | 2.167 | tNET | FF | 1 | R31C25[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s25/I3 |
5.443 | 0.517 | tINS | FF | 1 | R31C25[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s25/F |
6.006 | 0.563 | tNET | FF | 1 | R33C25[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s13/I3 |
6.377 | 0.371 | tINS | FF | 1 | R33C25[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s13/F |
6.547 | 0.170 | tNET | FF | 1 | R33C26[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s5/I0 |
7.117 | 0.570 | tINS | FR | 1 | R33C26[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s5/F |
7.119 | 0.001 | tNET | RR | 1 | R33C26[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s2/I2 |
7.636 | 0.517 | tINS | RF | 1 | R33C26[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s2/F |
8.368 | 0.733 | tNET | FF | 1 | R36C25[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s1/I0 |
8.830 | 0.462 | tINS | FR | 1 | R36C25[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n723_s1/F |
8.830 | 0.000 | tNET | RR | 1 | R36C25[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R36C25[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_7_s1/CLK |
10.208 | -0.035 | tSu | 1 | R36C25[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.954, 34.401%; route: 5.401, 62.897%; tC2Q: 0.232, 2.702% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
Slack | 1.389 |
Data Arrival Time | 8.820 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_3_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.439 | 0.555 | tINS | FF | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.870 | 0.431 | tNET | FF | 1 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/I1 |
6.323 | 0.453 | tINS | FF | 56 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/F |
8.271 | 1.948 | tNET | FF | 1 | R42C37[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/n149_s3/I3 |
8.820 | 0.549 | tINS | FR | 1 | R42C37[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/n149_s3/F |
8.820 | 0.000 | tNET | RR | 1 | R42C37[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R42C37[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_3_s1/CLK |
10.208 | -0.035 | tSu | 1 | R42C37[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.994, 34.910%; route: 5.350, 62.385%; tC2Q: 0.232, 2.705% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
Slack | 1.428 |
Data Arrival Time | 8.780 |
Data Required Time | 10.208 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_0_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R41C27[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 63 | R41C27[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1/Q |
2.613 | 2.137 | tNET | FF | 1 | R26C25[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/regfb_d1_8_s4/I0 |
2.984 | 0.371 | tINS | FF | 13 | R26C25[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/regfb_d1_8_s4/F |
3.969 | 0.986 | tNET | FF | 1 | R24C18[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s32/I3 |
4.524 | 0.555 | tINS | FF | 1 | R24C18[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s32/F |
5.375 | 0.850 | tNET | FF | 1 | R35C19[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s19/I0 |
5.746 | 0.371 | tINS | FF | 1 | R35C19[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s19/F |
5.916 | 0.170 | tNET | FF | 1 | R36C19[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s9/I2 |
6.433 | 0.517 | tINS | FF | 1 | R36C19[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s9/F |
7.194 | 0.761 | tNET | FF | 1 | R26C21[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s4/I0 |
7.711 | 0.517 | tINS | FF | 1 | R26C21[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s4/F |
8.318 | 0.607 | tNET | FF | 1 | R35C21[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s1/I2 |
8.780 | 0.462 | tINS | FR | 1 | R35C21[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n730_s1/F |
8.780 | 0.000 | tNET | RR | 1 | R35C21[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R35C21[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_0_s1/CLK |
10.208 | -0.035 | tSu | 1 | R35C21[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.793, 32.718%; route: 5.512, 64.565%; tC2Q: 0.232, 2.718% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
Slack | 1.463 |
Data Arrival Time | 8.746 |
Data Required Time | 10.208 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_5_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R22C28[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 998 | R22C28[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/Q |
3.569 | 3.093 | tNET | FF | 1 | R41C34[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/o_dat1_en_s5/I3 |
4.086 | 0.517 | tINS | FF | 67 | R41C34[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/o_dat1_en_s5/F |
5.049 | 0.964 | tNET | FF | 1 | R35C37[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/crc_cnt_5_s5/I1 |
5.566 | 0.517 | tINS | FF | 67 | R35C37[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/crc_cnt_5_s5/F |
6.299 | 0.733 | tNET | FF | 1 | R39C36[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n61_s11/I3 |
6.816 | 0.517 | tINS | FF | 3 | R39C36[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n61_s11/F |
7.218 | 0.401 | tNET | FF | 1 | R39C38[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n56_s2/I2 |
7.773 | 0.555 | tINS | FF | 2 | R39C38[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n56_s2/F |
8.176 | 0.403 | tNET | FF | 1 | R40C38[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n56_s1/I0 |
8.746 | 0.570 | tINS | FR | 1 | R40C38[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n56_s1/F |
8.746 | 0.000 | tNET | RR | 1 | R40C38[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R40C38[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_5_s1/CLK |
10.208 | -0.035 | tSu | 1 | R40C38[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.676, 31.474%; route: 5.594, 65.797%; tC2Q: 0.232, 2.729% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
Slack | 1.505 |
Data Arrival Time | 8.703 |
Data Required Time | 10.208 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_4_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R41C27[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 63 | R41C27[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_ctrl_fn0_addr_d1_2_s1/Q |
2.773 | 2.298 | tNET | FF | 1 | R24C22[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n729_s29/I2 |
3.290 | 0.517 | tINS | FF | 6 | R24C22[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n729_s29/F |
4.001 | 0.711 | tNET | FF | 1 | R30C21[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s34/I3 |
4.454 | 0.453 | tINS | FF | 1 | R30C21[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s34/F |
5.502 | 1.048 | tNET | FF | 1 | R30C19[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s23/I2 |
5.873 | 0.371 | tINS | FF | 1 | R30C19[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s23/F |
5.878 | 0.004 | tNET | FF | 1 | R30C19[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s13/I0 |
6.249 | 0.371 | tINS | FF | 1 | R30C19[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s13/F |
7.519 | 1.271 | tNET | FF | 1 | R35C24[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s4/I2 |
7.981 | 0.462 | tINS | FR | 1 | R35C24[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s4/F |
8.154 | 0.172 | tNET | RR | 1 | R35C23[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s1/I2 |
8.703 | 0.549 | tINS | RR | 1 | R35C23[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n726_s1/F |
8.703 | 0.000 | tNET | RR | 1 | R35C23[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R35C23[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_4_s1/CLK |
10.208 | -0.035 | tSu | 1 | R35C23[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd53_fn0_reg_rddata_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.723, 32.188%; route: 5.505, 65.069%; tC2Q: 0.232, 2.742% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
Slack | 1.571 |
Data Arrival Time | 8.638 |
Data Required Time | 10.208 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_12_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R22C28[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 998 | R22C28[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/cmd52_rst_gen_s0/Q |
3.569 | 3.093 | tNET | FF | 1 | R41C34[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/o_dat1_en_s5/I3 |
4.086 | 0.517 | tINS | FF | 67 | R41C34[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/o_dat1_en_s5/F |
5.049 | 0.964 | tNET | FF | 1 | R35C37[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/crc_cnt_5_s5/I1 |
5.566 | 0.517 | tINS | FF | 67 | R35C37[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/crc_cnt_5_s5/F |
6.299 | 0.733 | tNET | FF | 1 | R39C36[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n61_s11/I3 |
6.816 | 0.517 | tINS | FF | 3 | R39C36[3][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n61_s11/F |
7.218 | 0.401 | tNET | FF | 1 | R39C38[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n56_s2/I2 |
7.773 | 0.555 | tINS | FF | 2 | R39C38[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n56_s2/F |
8.176 | 0.403 | tNET | FF | 1 | R40C38[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n49_s1/I0 |
8.638 | 0.462 | tINS | FR | 1 | R40C38[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n49_s1/F |
8.638 | 0.000 | tNET | RR | 1 | R40C38[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R40C38[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_12_s1/CLK |
10.208 | -0.035 | tSu | 1 | R40C38[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_reg0_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.568, 30.593%; route: 5.594, 66.644%; tC2Q: 0.232, 2.764% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
Slack | 1.626 |
Data Arrival Time | 8.583 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_9_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.439 | 0.555 | tINS | FF | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.870 | 0.431 | tNET | FF | 1 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/I1 |
6.323 | 0.453 | tINS | FF | 56 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/F |
8.121 | 1.798 | tNET | FF | 1 | R43C36[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/n143_s2/I2 |
8.583 | 0.462 | tINS | FR | 1 | R43C36[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/n143_s2/F |
8.583 | 0.000 | tNET | RR | 1 | R43C36[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R43C36[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_9_s1/CLK |
10.208 | -0.035 | tSu | 1 | R43C36[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.907, 34.858%; route: 5.200, 62.360%; tC2Q: 0.232, 2.782% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
Slack | 1.626 |
Data Arrival Time | 8.583 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_11_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.439 | 0.555 | tINS | FF | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.870 | 0.431 | tNET | FF | 1 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/I1 |
6.323 | 0.453 | tINS | FF | 56 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/F |
8.121 | 1.798 | tNET | FF | 1 | R43C36[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/n141_s2/I2 |
8.583 | 0.462 | tINS | FR | 1 | R43C36[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/n141_s2/F |
8.583 | 0.000 | tNET | RR | 1 | R43C36[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R43C36[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_11_s1/CLK |
10.208 | -0.035 | tSu | 1 | R43C36[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u1_crc16_gen/crc_data_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.907, 34.858%; route: 5.200, 62.360%; tC2Q: 0.232, 2.782% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
Slack | 1.668 |
Data Arrival Time | 8.541 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_4_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.439 | 0.555 | tINS | FF | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.870 | 0.431 | tNET | FF | 1 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/I1 |
6.323 | 0.453 | tINS | FF | 56 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/F |
7.971 | 1.648 | tNET | FF | 1 | R40C40[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n148_s2/I2 |
8.541 | 0.570 | tINS | FR | 1 | R40C40[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n148_s2/F |
8.541 | 0.000 | tNET | RR | 1 | R40C40[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R40C40[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_4_s1/CLK |
10.208 | -0.035 | tSu | 1 | R40C40[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.015, 36.337%; route: 5.050, 60.867%; tC2Q: 0.232, 2.796% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
Slack | 1.668 |
Data Arrival Time | 8.541 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_6_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.439 | 0.555 | tINS | FF | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.870 | 0.431 | tNET | FF | 1 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/I1 |
6.323 | 0.453 | tINS | FF | 56 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/F |
7.971 | 1.648 | tNET | FF | 1 | R40C40[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n146_s2/I2 |
8.541 | 0.570 | tINS | FR | 1 | R40C40[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n146_s2/F |
8.541 | 0.000 | tNET | RR | 1 | R40C40[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R40C40[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_6_s1/CLK |
10.208 | -0.035 | tSu | 1 | R40C40[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.015, 36.337%; route: 5.050, 60.867%; tC2Q: 0.232, 2.796% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
Slack | 1.668 |
Data Arrival Time | 8.541 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_8_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.439 | 0.555 | tINS | FF | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.870 | 0.431 | tNET | FF | 1 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/I1 |
6.323 | 0.453 | tINS | FF | 56 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/F |
7.971 | 1.648 | tNET | FF | 1 | R40C40[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n144_s2/I2 |
8.541 | 0.570 | tINS | FR | 1 | R40C40[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n144_s2/F |
8.541 | 0.000 | tNET | RR | 1 | R40C40[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R40C40[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_8_s1/CLK |
10.208 | -0.035 | tSu | 1 | R40C40[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.015, 36.337%; route: 5.050, 60.867%; tC2Q: 0.232, 2.796% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
Slack | 1.668 |
Data Arrival Time | 8.541 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_10_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.439 | 0.555 | tINS | FF | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.870 | 0.431 | tNET | FF | 1 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/I1 |
6.323 | 0.453 | tINS | FF | 56 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/F |
7.971 | 1.648 | tNET | FF | 1 | R40C40[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n142_s2/I2 |
8.541 | 0.570 | tINS | FR | 1 | R40C40[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n142_s2/F |
8.541 | 0.000 | tNET | RR | 1 | R40C40[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R40C40[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_10_s1/CLK |
10.208 | -0.035 | tSu | 1 | R40C40[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.015, 36.337%; route: 5.050, 60.867%; tC2Q: 0.232, 2.796% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
Slack | 1.668 |
Data Arrival Time | 8.541 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_12_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.439 | 0.555 | tINS | FF | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.870 | 0.431 | tNET | FF | 1 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/I1 |
6.323 | 0.453 | tINS | FF | 56 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/F |
7.971 | 1.648 | tNET | FF | 1 | R40C40[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n140_s2/I2 |
8.541 | 0.570 | tINS | FR | 1 | R40C40[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n140_s2/F |
8.541 | 0.000 | tNET | RR | 1 | R40C40[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R40C40[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_12_s1/CLK |
10.208 | -0.035 | tSu | 1 | R40C40[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.015, 36.337%; route: 5.050, 60.867%; tC2Q: 0.232, 2.796% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
Slack | 1.668 |
Data Arrival Time | 8.541 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_14_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.439 | 0.555 | tINS | FF | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.870 | 0.431 | tNET | FF | 1 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/I1 |
6.323 | 0.453 | tINS | FF | 56 | R40C35[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n150_s3/F |
7.971 | 1.648 | tNET | FF | 1 | R40C40[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n138_s2/I2 |
8.541 | 0.570 | tINS | FR | 1 | R40C40[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/n138_s2/F |
8.541 | 0.000 | tNET | RR | 1 | R40C40[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_14_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R40C40[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_14_s1/CLK |
10.208 | -0.035 | tSu | 1 | R40C40[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u3_crc16_gen/crc_data_14_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.015, 36.337%; route: 5.050, 60.867%; tC2Q: 0.232, 2.796% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
Slack | 1.703 |
Data Arrival Time | 8.505 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_1_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.454 | 0.570 | tINS | FR | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.632 | 0.179 | tNET | RR | 1 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/I0 |
6.003 | 0.371 | tINS | RF | 4 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/F |
6.673 | 0.669 | tNET | FF | 1 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/I1 |
7.135 | 0.462 | tINS | FR | 64 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/F |
8.505 | 1.370 | tNET | RR | 1 | R34C39[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R34C39[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_1_s1/CLK |
10.208 | -0.035 | tSu | 1 | R34C39[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.840, 34.376%; route: 5.190, 62.816%; tC2Q: 0.232, 2.808% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
Slack | 1.703 |
Data Arrival Time | 8.505 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_2_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.454 | 0.570 | tINS | FR | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.632 | 0.179 | tNET | RR | 1 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/I0 |
6.003 | 0.371 | tINS | RF | 4 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/F |
6.673 | 0.669 | tNET | FF | 1 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/I1 |
7.135 | 0.462 | tINS | FR | 64 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/F |
8.505 | 1.370 | tNET | RR | 1 | R34C39[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_2_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R34C39[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_2_s1/CLK |
10.208 | -0.035 | tSu | 1 | R34C39[0][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.840, 34.376%; route: 5.190, 62.816%; tC2Q: 0.232, 2.808% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
Slack | 1.703 |
Data Arrival Time | 8.505 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_3_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.454 | 0.570 | tINS | FR | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.632 | 0.179 | tNET | RR | 1 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/I0 |
6.003 | 0.371 | tINS | RF | 4 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/F |
6.673 | 0.669 | tNET | FF | 1 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/I1 |
7.135 | 0.462 | tINS | FR | 64 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/F |
8.505 | 1.370 | tNET | RR | 1 | R34C39[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_3_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R34C39[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_3_s1/CLK |
10.208 | -0.035 | tSu | 1 | R34C39[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.840, 34.376%; route: 5.190, 62.816%; tC2Q: 0.232, 2.808% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
Slack | 1.703 |
Data Arrival Time | 8.505 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_5_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.454 | 0.570 | tINS | FR | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.632 | 0.179 | tNET | RR | 1 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/I0 |
6.003 | 0.371 | tINS | RF | 4 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/F |
6.673 | 0.669 | tNET | FF | 1 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/I1 |
7.135 | 0.462 | tINS | FR | 64 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/F |
8.505 | 1.370 | tNET | RR | 1 | R34C39[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_5_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R34C39[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_5_s1/CLK |
10.208 | -0.035 | tSu | 1 | R34C39[1][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.840, 34.376%; route: 5.190, 62.816%; tC2Q: 0.232, 2.808% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
Slack | 1.703 |
Data Arrival Time | 8.505 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_7_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.454 | 0.570 | tINS | FR | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.632 | 0.179 | tNET | RR | 1 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/I0 |
6.003 | 0.371 | tINS | RF | 4 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/F |
6.673 | 0.669 | tNET | FF | 1 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/I1 |
7.135 | 0.462 | tINS | FR | 64 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/F |
8.505 | 1.370 | tNET | RR | 1 | R34C39[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_7_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R34C39[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_7_s1/CLK |
10.208 | -0.035 | tSu | 1 | R34C39[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.840, 34.376%; route: 5.190, 62.816%; tC2Q: 0.232, 2.808% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
Slack | 1.703 |
Data Arrival Time | 8.505 |
Data Required Time | 10.208 |
From | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_8_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/CLK |
0.475 | 0.232 | tC2Q | RF | 5 | R17C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_rd_valid_s1/Q |
1.977 | 1.502 | tNET | FF | 1 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/I1 |
2.348 | 0.371 | tINS | FF | 2 | R40C33[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s6/F |
3.252 | 0.903 | tNET | FF | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/I1 |
3.801 | 0.549 | tINS | FR | 1 | R39C33[2][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s5/F |
3.945 | 0.144 | tNET | RR | 1 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/I2 |
4.462 | 0.517 | tINS | RF | 4 | R39C33[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/n160_s2/F |
4.884 | 0.422 | tNET | FF | 1 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/I1 |
5.454 | 0.570 | tINS | FR | 3 | R39C34[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s5/F |
5.632 | 0.179 | tNET | RR | 1 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/I0 |
6.003 | 0.371 | tINS | RF | 4 | R40C34[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s4/F |
6.673 | 0.669 | tNET | FF | 1 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/I1 |
7.135 | 0.462 | tINS | FR | 64 | R36C35[3][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u0_crc16_gen/crc_reg0_15_s6/F |
8.505 | 1.370 | tNET | RR | 1 | R34C39[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_8_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | sym_clk | ||||
10.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R34C39[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_8_s1/CLK |
10.208 | -0.035 | tSu | 1 | R34C39[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cmd53_tx_rx/u2_crc16_gen/crc_reg0_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.840, 34.376%; route: 5.190, 62.816%; tC2Q: 0.232, 2.808% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.322 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | u_user_sdio_cmd52_if/sdio_cmd52_cs_d1_s0 |
To | u_user_sdio_cmd52_if/sdio_cmd52_rd_data_2_s0 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C39[0][B] | u_user_sdio_cmd52_if/sdio_cmd52_cs_d1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 13 | R25C39[0][B] | u_user_sdio_cmd52_if/sdio_cmd52_cs_d1_s0/Q |
0.517 | 0.131 | tNET | RR | 1 | R25C40[0][A] | u_user_sdio_cmd52_if/sdio_cmd52_rd_data_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R25C40[0][A] | u_user_sdio_cmd52_if/sdio_cmd52_rd_data_2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R25C40[0][A] | u_user_sdio_cmd52_if/sdio_cmd52_rd_data_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.131, 39.360%; tC2Q: 0.202, 60.640% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
Slack | 0.359 |
Data Arrival Time | 1.265 |
Data Required Time | 0.906 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_resp_gen/cmd52_fn0_reg_addr_15_s0 |
To | u_user_cpu_slave_reg_if/int_clr_flag_d1_s0 |
Launch Clk | sym_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C28[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_resp_gen/cmd52_fn0_reg_addr_15_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R21C28[2][B] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_resp_gen/cmd52_fn0_reg_addr_15_s0/Q |
0.663 | 0.277 | tNET | RR | 1 | R25C28[1][B] | u_user_cpu_slave_reg_if/int_clr_flag_s1/I2 |
0.898 | 0.235 | tINS | RR | 3 | R25C28[1][B] | u_user_cpu_slave_reg_if/int_clr_flag_s1/F |
0.901 | 0.003 | tNET | RR | 1 | R25C28[0][A] | u_user_cpu_slave_reg_if/int_clr_flag_s0/I1 |
1.265 | 0.364 | tINS | RF | 1 | R25C28[0][A] | u_user_cpu_slave_reg_if/int_clr_flag_s0/F |
1.265 | 0.000 | tNET | FF | 1 | R25C28[0][A] | u_user_cpu_slave_reg_if/int_clr_flag_d1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R25C28[0][A] | u_user_cpu_slave_reg_if/int_clr_flag_d1_s0/CLK |
0.895 | 0.035 | tUnc | u_user_cpu_slave_reg_if/int_clr_flag_d1_s0 | |||
0.906 | 0.011 | tHld | 1 | R25C28[0][A] | u_user_cpu_slave_reg_if/int_clr_flag_d1_s0 |
Path Statistics:
Clock Skew | 0.675 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.599, 55.426%; route: 0.280, 25.882%; tC2Q: 0.202, 18.691% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path3
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_deUstb1/cnt_5_s0 |
To | u_deUstb1/cnt_5_s0 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R43C42[0][A] | u_deUstb1/cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 4 | R43C42[0][A] | u_deUstb1/cnt_5_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R43C42[0][A] | u_deUstb1/n47_s1/I2 |
0.621 | 0.232 | tINS | RF | 1 | R43C42[0][A] | u_deUstb1/n47_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R43C42[0][A] | u_deUstb1/cnt_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R43C42[0][A] | u_deUstb1/cnt_5_s0/CLK |
0.195 | 0.011 | tHld | 1 | R43C42[0][A] | u_deUstb1/cnt_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_deUstb1/cnt_11_s0 |
To | u_deUstb1/cnt_11_s0 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R43C44[0][A] | u_deUstb1/cnt_11_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 4 | R43C44[0][A] | u_deUstb1/cnt_11_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R43C44[0][A] | u_deUstb1/n41_s1/I2 |
0.621 | 0.232 | tINS | RF | 1 | R43C44[0][A] | u_deUstb1/n41_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R43C44[0][A] | u_deUstb1/cnt_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R43C44[0][A] | u_deUstb1/cnt_11_s0/CLK |
0.195 | 0.011 | tHld | 1 | R43C44[0][A] | u_deUstb1/cnt_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_deUstb1/cnt_12_s0 |
To | u_deUstb1/cnt_12_s0 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R43C44[1][A] | u_deUstb1/cnt_12_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R43C44[1][A] | u_deUstb1/cnt_12_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R43C44[1][A] | u_deUstb1/n40_s1/I2 |
0.621 | 0.232 | tINS | RF | 1 | R43C44[1][A] | u_deUstb1/n40_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R43C44[1][A] | u_deUstb1/cnt_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R43C44[1][A] | u_deUstb1/cnt_12_s0/CLK |
0.195 | 0.011 | tHld | 1 | R43C44[1][A] | u_deUstb1/cnt_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_deUstb1/cnt_19_s0 |
To | u_deUstb1/cnt_19_s0 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R43C43[0][A] | u_deUstb1/cnt_19_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R43C43[0][A] | u_deUstb1/cnt_19_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R43C43[0][A] | u_deUstb1/n33_s1/I2 |
0.621 | 0.232 | tINS | RF | 1 | R43C43[0][A] | u_deUstb1/n33_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R43C43[0][A] | u_deUstb1/cnt_19_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R43C43[0][A] | u_deUstb1/cnt_19_s0/CLK |
0.195 | 0.011 | tHld | 1 | R43C43[0][A] | u_deUstb1/cnt_19_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_deUstb/cnt_1_s0 |
To | u_deUstb/cnt_1_s0 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R35C44[0][A] | u_deUstb/cnt_1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R35C44[0][A] | u_deUstb/cnt_1_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R35C44[0][A] | u_deUstb/n51_s1/I1 |
0.621 | 0.232 | tINS | RF | 1 | R35C44[0][A] | u_deUstb/n51_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R35C44[0][A] | u_deUstb/cnt_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R35C44[0][A] | u_deUstb/cnt_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R35C44[0][A] | u_deUstb/cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_0_s3 |
To | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_0_s3 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C41[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_0_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R13C41[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_0_s3/Q |
0.389 | 0.002 | tNET | RR | 1 | R13C41[0][A] | u_user_sdio_cmd53_if/n360_s3/I2 |
0.621 | 0.232 | tINS | RF | 1 | R13C41[0][A] | u_user_sdio_cmd53_if/n360_s3/F |
0.621 | 0.000 | tNET | FF | 1 | R13C41[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C41[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_0_s3/CLK |
0.195 | 0.011 | tHld | 1 | R13C41[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_1_s3 |
To | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_1_s3 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C41[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_1_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R13C41[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_1_s3/Q |
0.389 | 0.002 | tNET | RR | 1 | R13C41[1][A] | u_user_sdio_cmd53_if/n359_s3/I2 |
0.621 | 0.232 | tINS | RF | 1 | R13C41[1][A] | u_user_sdio_cmd53_if/n359_s3/F |
0.621 | 0.000 | tNET | FF | 1 | R13C41[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_1_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C41[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_1_s3/CLK |
0.195 | 0.011 | tHld | 1 | R13C41[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_1_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_8_s3 |
To | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_8_s3 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C44[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_8_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R13C44[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_8_s3/Q |
0.389 | 0.002 | tNET | RR | 1 | R13C44[0][A] | u_user_sdio_cmd53_if/n352_s3/I2 |
0.621 | 0.232 | tINS | RF | 1 | R13C44[0][A] | u_user_sdio_cmd53_if/n352_s3/F |
0.621 | 0.000 | tNET | FF | 1 | R13C44[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_8_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C44[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_8_s3/CLK |
0.195 | 0.011 | tHld | 1 | R13C44[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_8_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_9_s3 |
To | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_9_s3 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C44[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_9_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R13C44[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_9_s3/Q |
0.389 | 0.002 | tNET | RR | 1 | R13C44[1][A] | u_user_sdio_cmd53_if/n351_s3/I2 |
0.621 | 0.232 | tINS | RF | 1 | R13C44[1][A] | u_user_sdio_cmd53_if/n351_s3/F |
0.621 | 0.000 | tNET | FF | 1 | R13C44[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_9_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C44[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_9_s3/CLK |
0.195 | 0.011 | tHld | 1 | R13C44[1][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_9_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_10_s3 |
To | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_10_s3 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_10_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R13C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_10_s3/Q |
0.389 | 0.002 | tNET | RR | 1 | R13C43[0][A] | u_user_sdio_cmd53_if/n350_s3/I2 |
0.621 | 0.232 | tINS | RF | 1 | R13C43[0][A] | u_user_sdio_cmd53_if/n350_s3/F |
0.621 | 0.000 | tNET | FF | 1 | R13C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_10_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_10_s3/CLK |
0.195 | 0.011 | tHld | 1 | R13C43[0][A] | u_user_sdio_cmd53_if/sdio_cmd53_len_d1_10_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_user_sdio_cmd53_if/idle_to_rd_delay_3_s1 |
To | u_user_sdio_cmd53_if/idle_to_rd_delay_3_s1 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R16C43[1][A] | u_user_sdio_cmd53_if/idle_to_rd_delay_3_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R16C43[1][A] | u_user_sdio_cmd53_if/idle_to_rd_delay_3_s1/Q |
0.389 | 0.002 | tNET | RR | 1 | R16C43[1][A] | u_user_sdio_cmd53_if/n17_s1/I2 |
0.621 | 0.232 | tINS | RF | 1 | R16C43[1][A] | u_user_sdio_cmd53_if/n17_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R16C43[1][A] | u_user_sdio_cmd53_if/idle_to_rd_delay_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R16C43[1][A] | u_user_sdio_cmd53_if/idle_to_rd_delay_3_s1/CLK |
0.195 | 0.011 | tHld | 1 | R16C43[1][A] | u_user_sdio_cmd53_if/idle_to_rd_delay_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/data_cmd_error_cnt_6_s0 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/data_cmd_error_cnt_6_s0 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R31C42[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/data_cmd_error_cnt_6_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R31C42[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/data_cmd_error_cnt_6_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R31C42[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/n70_s1/I2 |
0.621 | 0.232 | tINS | RF | 1 | R31C42[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/n70_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R31C42[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/data_cmd_error_cnt_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R31C42[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/data_cmd_error_cnt_6_s0/CLK |
0.195 | 0.011 | tHld | 1 | R31C42[1][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_irq_gen/data_cmd_error_cnt_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_2_s3 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_2_s3 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C24[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_2_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R22C24[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_2_s3/Q |
0.389 | 0.002 | tNET | RR | 1 | R22C24[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n239_s6/I3 |
0.621 | 0.232 | tINS | RF | 1 | R22C24[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n239_s6/F |
0.621 | 0.000 | tNET | FF | 1 | R22C24[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_2_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C24[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_2_s3/CLK |
0.195 | 0.011 | tHld | 1 | R22C24[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_2_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_6_s3 |
To | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_6_s3 |
Launch Clk | sym_clk:[R] |
Latch Clk | sym_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C21[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_6_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 4 | R22C21[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_6_s3/Q |
0.389 | 0.002 | tNET | RR | 1 | R22C21[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n235_s6/I3 |
0.621 | 0.232 | tINS | RF | 1 | R22C21[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_fn0_reg/n235_s6/F |
0.621 | 0.000 | tNET | FF | 1 | R22C21[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_6_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | sym_clk | ||||
0.000 | 0.000 | tCL | RR | 1717 | RIGHTSIDE[0] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/clkdiv_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C21[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_6_s3/CLK |
0.195 | 0.011 | tHld | 1 | R22C21[0][A] | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_cis_fnx_if/rd_len_6_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | u_user_cpu_slave_reg_if/cnt_7_s3 |
To | u_user_cpu_slave_reg_if/cnt_7_s3 |
Launch Clk | cpu_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C27[1][A] | u_user_cpu_slave_reg_if/cnt_7_s3/CLK |
1.062 | 0.202 | tC2Q | RR | 5 | R20C27[1][A] | u_user_cpu_slave_reg_if/cnt_7_s3/Q |
1.064 | 0.002 | tNET | RR | 1 | R20C27[1][A] | u_user_cpu_slave_reg_if/n106_s4/I0 |
1.296 | 0.232 | tINS | RF | 1 | R20C27[1][A] | u_user_cpu_slave_reg_if/n106_s4/F |
1.296 | 0.000 | tNET | FF | 1 | R20C27[1][A] | u_user_cpu_slave_reg_if/cnt_7_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C27[1][A] | u_user_cpu_slave_reg_if/cnt_7_s3/CLK |
0.871 | 0.011 | tHld | 1 | R20C27[1][A] | u_user_cpu_slave_reg_if/cnt_7_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path18
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | u_user_cpu_slave_reg_if/cnt_3_s1 |
To | u_user_cpu_slave_reg_if/cnt_3_s1 |
Launch Clk | cpu_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C28[1][A] | u_user_cpu_slave_reg_if/cnt_3_s1/CLK |
1.062 | 0.202 | tC2Q | RR | 8 | R20C28[1][A] | u_user_cpu_slave_reg_if/cnt_3_s1/Q |
1.064 | 0.002 | tNET | RR | 1 | R20C28[1][A] | u_user_cpu_slave_reg_if/n110_s1/I3 |
1.296 | 0.232 | tINS | RF | 1 | R20C28[1][A] | u_user_cpu_slave_reg_if/n110_s1/F |
1.296 | 0.000 | tNET | FF | 1 | R20C28[1][A] | u_user_cpu_slave_reg_if/cnt_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C28[1][A] | u_user_cpu_slave_reg_if/cnt_3_s1/CLK |
0.871 | 0.011 | tHld | 1 | R20C28[1][A] | u_user_cpu_slave_reg_if/cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path19
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | led_reg_3_s0 |
To | led_reg_3_s0 |
Launch Clk | cpu_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C41[1][A] | led_reg_3_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 2 | R20C41[1][A] | led_reg_3_s0/Q |
1.064 | 0.002 | tNET | RR | 2 | R20C41[1][A] | n259_s/I1 |
1.296 | 0.232 | tINS | RF | 1 | R20C41[1][A] | n259_s/SUM |
1.296 | 0.000 | tNET | FF | 1 | R20C41[1][A] | led_reg_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C41[1][A] | led_reg_3_s0/CLK |
0.871 | 0.011 | tHld | 1 | R20C41[1][A] | led_reg_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path20
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | led_reg_7_s0 |
To | led_reg_7_s0 |
Launch Clk | cpu_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C42[0][A] | led_reg_7_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 2 | R20C42[0][A] | led_reg_7_s0/Q |
1.064 | 0.002 | tNET | RR | 2 | R20C42[0][A] | n255_s/I1 |
1.296 | 0.232 | tINS | RF | 1 | R20C42[0][A] | n255_s/SUM |
1.296 | 0.000 | tNET | FF | 1 | R20C42[0][A] | led_reg_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C42[0][A] | led_reg_7_s0/CLK |
0.871 | 0.011 | tHld | 1 | R20C42[0][A] | led_reg_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path21
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | led_reg_9_s0 |
To | led_reg_9_s0 |
Launch Clk | cpu_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C42[1][A] | led_reg_9_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 2 | R20C42[1][A] | led_reg_9_s0/Q |
1.064 | 0.002 | tNET | RR | 2 | R20C42[1][A] | n253_s/I1 |
1.296 | 0.232 | tINS | RF | 1 | R20C42[1][A] | n253_s/SUM |
1.296 | 0.000 | tNET | FF | 1 | R20C42[1][A] | led_reg_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C42[1][A] | led_reg_9_s0/CLK |
0.871 | 0.011 | tHld | 1 | R20C42[1][A] | led_reg_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path22
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | led_reg_13_s0 |
To | led_reg_13_s0 |
Launch Clk | cpu_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C43[0][A] | led_reg_13_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 2 | R20C43[0][A] | led_reg_13_s0/Q |
1.064 | 0.002 | tNET | RR | 2 | R20C43[0][A] | n249_s/I1 |
1.296 | 0.232 | tINS | RF | 1 | R20C43[0][A] | n249_s/SUM |
1.296 | 0.000 | tNET | FF | 1 | R20C43[0][A] | led_reg_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C43[0][A] | led_reg_13_s0/CLK |
0.871 | 0.011 | tHld | 1 | R20C43[0][A] | led_reg_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path23
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | led_reg_15_s0 |
To | led_reg_15_s0 |
Launch Clk | cpu_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C43[1][A] | led_reg_15_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 2 | R20C43[1][A] | led_reg_15_s0/Q |
1.064 | 0.002 | tNET | RR | 2 | R20C43[1][A] | n247_s/I1 |
1.296 | 0.232 | tINS | RF | 1 | R20C43[1][A] | n247_s/SUM |
1.296 | 0.000 | tNET | FF | 1 | R20C43[1][A] | led_reg_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C43[1][A] | led_reg_15_s0/CLK |
0.871 | 0.011 | tHld | 1 | R20C43[1][A] | led_reg_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path24
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | led_reg_19_s0 |
To | led_reg_19_s0 |
Launch Clk | cpu_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C44[0][A] | led_reg_19_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 2 | R20C44[0][A] | led_reg_19_s0/Q |
1.064 | 0.002 | tNET | RR | 2 | R20C44[0][A] | n243_s/I1 |
1.296 | 0.232 | tINS | RF | 1 | R20C44[0][A] | n243_s/SUM |
1.296 | 0.000 | tNET | FF | 1 | R20C44[0][A] | led_reg_19_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C44[0][A] | led_reg_19_s0/CLK |
0.871 | 0.011 | tHld | 1 | R20C44[0][A] | led_reg_19_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Path25
Path Summary:
Slack | 0.425 |
Data Arrival Time | 1.296 |
Data Required Time | 0.871 |
From | led_reg_21_s0 |
To | led_reg_21_s0 |
Launch Clk | cpu_clk:[R] |
Latch Clk | cpu_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C44[1][A] | led_reg_21_s0/CLK |
1.062 | 0.202 | tC2Q | RR | 2 | R20C44[1][A] | led_reg_21_s0/Q |
1.064 | 0.002 | tNET | RR | 2 | R20C44[1][A] | n241_s/I1 |
1.296 | 0.232 | tINS | RF | 1 | R20C44[1][A] | n241_s/SUM |
1.296 | 0.000 | tNET | FF | 1 | R20C44[1][A] | led_reg_21_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | cpu_clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | cpu_clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 215 | IOT27[A] | cpu_clk_ibuf/O |
0.860 | 0.184 | tNET | RR | 1 | R20C44[1][A] | led_reg_21_s0/CLK |
0.871 | 0.011 | tHld | 1 | R20C44[1][A] | led_reg_21_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.675, 78.568%; route: 0.184, 21.432% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | sdio_clkin |
Objects: | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_cmd_oen_temp_1d_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | sdio_clkin | ||
5.000 | 0.000 | tCL | FF | sdio_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | sdio_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_cmd_oen_temp_1d_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | sdio_clkin | ||
10.000 | 0.000 | tCL | RR | sdio_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | sdio_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_cmd_oen_temp_1d_s0/CLK |
MPW2
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | sdio_clkin |
Objects: | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat1_out_temp_1d_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | sdio_clkin | ||
5.000 | 0.000 | tCL | FF | sdio_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | sdio_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat1_out_temp_1d_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | sdio_clkin | ||
10.000 | 0.000 | tCL | RR | sdio_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | sdio_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat1_out_temp_1d_s0/CLK |
MPW3
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | sdio_clkin |
Objects: | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat1_oen_temp_1d_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | sdio_clkin | ||
5.000 | 0.000 | tCL | FF | sdio_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | sdio_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat1_oen_temp_1d_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | sdio_clkin | ||
10.000 | 0.000 | tCL | RR | sdio_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | sdio_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat1_oen_temp_1d_s0/CLK |
MPW4
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | sdio_clkin |
Objects: | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat0_oen_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | sdio_clkin | ||
5.000 | 0.000 | tCL | FF | sdio_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | sdio_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat0_oen_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | sdio_clkin | ||
10.000 | 0.000 | tCL | RR | sdio_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | sdio_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/sdio_dat0_oen_s0/CLK |
MPW5
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | sdio_clkin |
Objects: | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/reg_pos_o_cmd_di_en_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | sdio_clkin | ||
5.000 | 0.000 | tCL | FF | sdio_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | sdio_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/reg_pos_o_cmd_di_en_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | sdio_clkin | ||
10.000 | 0.000 | tCL | RR | sdio_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | sdio_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/reg_pos_o_cmd_di_en_s0/CLK |
MPW6
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | sdio_clkin |
Objects: | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/neg_cmd19_o_dat3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | sdio_clkin | ||
5.000 | 0.000 | tCL | FF | sdio_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | sdio_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/neg_cmd19_o_dat3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | sdio_clkin | ||
10.000 | 0.000 | tCL | RR | sdio_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | sdio_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_sdio_if/neg_cmd19_o_dat3_s0/CLK |
MPW7
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cpu_clk |
Objects: | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_slv_cpu_if/fbr1_std_fn_if_code_3_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cpu_clk | ||
5.000 | 0.000 | tCL | FF | cpu_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | cpu_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_slv_cpu_if/fbr1_std_fn_if_code_3_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cpu_clk | ||
10.000 | 0.000 | tCL | RR | cpu_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | cpu_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_slv_cpu_if/fbr1_std_fn_if_code_3_s1/CLK |
MPW8
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cpu_clk |
Objects: | u_user_cpu_slave_reg_if/slv_cpu_wr_data_13_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cpu_clk | ||
5.000 | 0.000 | tCL | FF | cpu_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | cpu_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_user_cpu_slave_reg_if/slv_cpu_wr_data_13_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cpu_clk | ||
10.000 | 0.000 | tCL | RR | cpu_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | cpu_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_user_cpu_slave_reg_if/slv_cpu_wr_data_13_s0/CLK |
MPW9
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cpu_clk |
Objects: | u_user_cpu_slave_reg_if/slv_cpu_wr_data_14_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cpu_clk | ||
5.000 | 0.000 | tCL | FF | cpu_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | cpu_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_user_cpu_slave_reg_if/slv_cpu_wr_data_14_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cpu_clk | ||
10.000 | 0.000 | tCL | RR | cpu_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | cpu_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_user_cpu_slave_reg_if/slv_cpu_wr_data_14_s0/CLK |
MPW10
MPW Summary:
Slack: | 3.911 |
Actual Width: | 4.911 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cpu_clk |
Objects: | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_slv_cpu_if/cccr_sdta_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cpu_clk | ||
5.000 | 0.000 | tCL | FF | cpu_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | cpu_clk_ibuf/O |
5.949 | 0.261 | tNET | FF | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_slv_cpu_if/cccr_sdta_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cpu_clk | ||
10.000 | 0.000 | tCL | RR | cpu_clk_ibuf/I |
10.675 | 0.675 | tINS | RR | cpu_clk_ibuf/O |
10.860 | 0.184 | tNET | RR | u_sdio_slave_ctrl/u_sdio_slave_ctrl_0/u_slv_cpu_if/cccr_sdta_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1717 | sym_clk | 0.717 | 1.041 |
998 | cmd52_rst | 0.717 | 3.464 |
215 | cpu_clk_d | 1.585 | 0.261 |
122 | n3912_9 | 4.905 | 1.533 |
69 | cmd53_ctrl_fn0_addr_d1[0] | 1.621 | 2.336 |
67 | o_dat1_en_8 | 1.463 | 2.002 |
67 | crc_cnt_5_10 | 1.463 | 0.940 |
66 | cmd53_ctrl_fn0_addr_d1[1] | 1.749 | 2.189 |
65 | cmd53_ctrl_fn0_addr_d1[3] | 1.619 | 2.003 |
65 | sdio_clk_d | 6.830 | 0.631 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R18C31 | 91.67% |
R34C21 | 91.67% |
R31C25 | 90.28% |
R30C22 | 88.89% |
R40C37 | 88.89% |
R13C31 | 87.50% |
R20C18 | 87.50% |
R21C18 | 87.50% |
R20C35 | 87.50% |
R18C33 | 87.50% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name sdio_clkin -period 10 -waveform {0 5} [get_ports {sdio_clk}] |
TC_CLOCK | Actived | create_clock -name sym_clk -period 10 -waveform {0 5} [get_nets {sym_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {sym_clk}] -group [get_clocks {sdio_clkin}] |