Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.7.03Beta\IDE\data\ipcores\gw_jtag.v
C:\Users\Noa\Desktop\TMP\sdio_sdr104\Gowin_SDIO_SDR104_Slave_Controller_RefDesign\project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.03Beta
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Fri Apr 16 16:36:02 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 36.328MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 36.328MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 36.328MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 36.328MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 36.328MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 36.328MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 36.328MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 36.328MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 36.328MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 36.328MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 36.328MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 36.328MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 50.168MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 50.168MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 50.168MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 50.168MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 102
I/O Buf 102
    IBUF 101
    OBUF 1
Register 748
    DFF 194
    DFFP 1
    DFFPE 33
    DFFC 53
    DFFCE 461
    DFFNP 2
    DFFNC 4
LUT 541
    LUT2 56
    LUT3 101
    LUT4 384
MUX 1
    MUX16 1
ALU 9
    ALU 9
INV 2
    INV 2
BSRAM 8
    SDPX9B 8

Resource Utilization Summary

Resource Usage Utilization
Logic 560(551 LUTs, 9 ALUs) / 20736 3%
Register 748 / 16173 5%
  --Register as Latch 0 / 16173 0%
  --Register as FF 748 / 16173 5%
BSRAM 8 / 46 17%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sdio_clk_d Base 10.000 100.0 0.000 5.000 sdio_clk_d_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 sdio_clk_d 100.0(MHz) 280.0(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.429
Data Arrival Time 4.398
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk sdio_clk_d[R]
Latch Clk sdio_clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sdio_clk_d
0.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
0.683 0.683 tINS RR 279 sdio_clk_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.095 0.232 tC2Q RF 12 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/I1
2.641 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/F
2.878 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s4/I1
3.433 0.555 tINS FF 11 u_la0_top/u_ao_mem_ctrl/n839_s4/F
3.670 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
4.219 0.549 tINS FR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
4.398 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sdio_clk_d
10.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
10.682 0.683 tINS RR 279 sdio_clk_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.176, 61.539%; route: 1.128, 31.900%; tC2Q: 0.232, 6.561%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 6.468
Data Arrival Time 4.359
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3
Launch Clk sdio_clk_d[R]
Latch Clk sdio_clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sdio_clk_d
0.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
0.683 0.683 tINS RR 279 sdio_clk_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.095 0.232 tC2Q RF 12 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/I1
2.641 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/F
2.878 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s4/I1
3.433 0.555 tINS FF 11 u_la0_top/u_ao_mem_ctrl/n839_s4/F
3.670 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n848_s3/I2
4.122 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n848_s3/F
4.359 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sdio_clk_d
10.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
10.682 0.683 tINS RR 279 sdio_clk_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.080, 59.480%; route: 1.185, 33.886%; tC2Q: 0.232, 6.634%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 6.468
Data Arrival Time 4.359
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk sdio_clk_d[R]
Latch Clk sdio_clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sdio_clk_d
0.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
0.683 0.683 tINS RR 279 sdio_clk_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.095 0.232 tC2Q RF 12 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/I1
2.641 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/F
2.878 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s4/I1
3.433 0.555 tINS FF 11 u_la0_top/u_ao_mem_ctrl/n839_s4/F
3.670 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n847_s1/I2
4.122 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n847_s1/F
4.359 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sdio_clk_d
10.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
10.682 0.683 tINS RR 279 sdio_clk_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.080, 59.480%; route: 1.185, 33.886%; tC2Q: 0.232, 6.634%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 6.468
Data Arrival Time 4.359
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk sdio_clk_d[R]
Latch Clk sdio_clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sdio_clk_d
0.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
0.683 0.683 tINS RR 279 sdio_clk_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.095 0.232 tC2Q RF 12 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/I1
2.641 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/F
2.878 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s4/I1
3.433 0.555 tINS FF 11 u_la0_top/u_ao_mem_ctrl/n839_s4/F
3.670 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n845_s1/I2
4.122 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n845_s1/F
4.359 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sdio_clk_d
10.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
10.682 0.683 tINS RR 279 sdio_clk_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.080, 59.480%; route: 1.185, 33.886%; tC2Q: 0.232, 6.634%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.468
Data Arrival Time 4.359
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk sdio_clk_d[R]
Latch Clk sdio_clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sdio_clk_d
0.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
0.683 0.683 tINS RR 279 sdio_clk_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.095 0.232 tC2Q RF 12 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s10/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/I1
2.641 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n839_s7/F
2.878 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n839_s4/I1
3.433 0.555 tINS FF 11 u_la0_top/u_ao_mem_ctrl/n839_s4/F
3.670 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n844_s1/I2
4.122 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n844_s1/F
4.359 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sdio_clk_d
10.000 0.000 tCL RR 1 sdio_clk_d_ibuf/I
10.682 0.683 tINS RR 279 sdio_clk_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.080, 59.480%; route: 1.185, 33.886%; tC2Q: 0.232, 6.634%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%