Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.03\IDE\ipcore\SDM\data\sdm_top.v
C:\Gowin\Gowin_V1.9.8.03\IDE\ipcore\SDM\data\sdm_top_wrap.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.03
Part Number GW1N-LV9LQ144C6/I5
Device GW1N-9
Created Time Thu Jan 20 13:50:35 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module SDM_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.257s, Peak memory usage = 45.367MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 45.367MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 45.367MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 45.367MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 45.367MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 45.367MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 45.367MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 45.367MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 45.367MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 45.367MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 45.367MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 45.367MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.348s, Peak memory usage = 56.172MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 56.172MB
Generate output files:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.127s, Peak memory usage = 56.172MB
Total Time and Memory Usage CPU time = 0h 0m 0.87s, Elapsed time = 0h 0m 0.941s, Peak memory usage = 56.172MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 61
I/O Buf 61
    IBUF 58
    OBUF 3
Register 507
    DFF 1
    DFFE 4
    DFFP 1
    DFFPE 33
    DFFC 44
    DFFCE 420
    DFFNP 4
LUT 214
    LUT2 11
    LUT3 179
    LUT4 24
ALU 184
    ALU 184
SSRAM 5
    RAM16S4 5
INV 3
    INV 3
DSP 5
    MULTALU36X18 5
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 431(217 LUTs, 184 ALUs, 5 SSRAMs) / 8640 5%
Register 507 / 6843 7%
  --Register as Latch 0 / 6843 0%
  --Register as FF 507 / 6843 7%
BSRAM 1 / 26 4%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
in_pdm_clk Base 20.000 50.0 0.000 10.000 in_pdm_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.0(MHz) 132.8(MHz) 8 TOP
2 in_pdm_clk 50.0(MHz) 137.1(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.472
Data Arrival Time 8.473
Data Required Time 20.945
From Sigma_Delta_Modulator/modulator/delay_u/dReg[0]_0_s2
To Sigma_Delta_Modulator/modulator/y_35_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 492 clk_ibuf/O
1.345 0.363 tNET RR 1 Sigma_Delta_Modulator/modulator/delay_u/dReg[0]_0_s2/CLK
1.803 0.458 tC2Q RF 12 Sigma_Delta_Modulator/modulator/delay_u/dReg[0]_0_s2/Q
2.283 0.480 tNET FF 4 Sigma_Delta_Modulator/modulator/delay_u/dReg[0]_0_s8/AD[0](chk_dup)
2.542 0.259 tINS FF 1 Sigma_Delta_Modulator/modulator/delay_u/dReg[0]_0_s8/DO[0]
3.022 0.480 tNET FF 1 Sigma_Delta_Modulator/modulator/delay_u/u_d_0_s2/I0
4.054 1.032 tINS FF 6 Sigma_Delta_Modulator/modulator/delay_u/u_d_0_s2/F
4.534 0.480 tNET FF 2 Sigma_Delta_Modulator/modulator/n287_s/I0
5.492 0.958 tINS FF 1 Sigma_Delta_Modulator/modulator/n287_s/COUT
5.492 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n286_s/CIN
5.549 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n286_s/COUT
5.549 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n285_s/CIN
5.606 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n285_s/COUT
5.606 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n284_s/CIN
5.663 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n284_s/COUT
5.663 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n283_s/CIN
5.720 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n283_s/COUT
5.720 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n282_s/CIN
5.777 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n282_s/COUT
5.777 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n281_s/CIN
5.834 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n281_s/COUT
5.834 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n280_s/CIN
5.891 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n280_s/COUT
5.891 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n279_s/CIN
5.948 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n279_s/COUT
5.948 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n278_s/CIN
6.005 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n278_s/COUT
6.005 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n277_s/CIN
6.062 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n277_s/COUT
6.062 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n276_s/CIN
6.119 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n276_s/COUT
6.119 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n275_s/CIN
6.176 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n275_s/COUT
6.176 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n274_s/CIN
6.233 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n274_s/COUT
6.233 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n273_s/CIN
6.290 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n273_s/COUT
6.290 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n272_s/CIN
6.347 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n272_s/COUT
6.347 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n271_s/CIN
6.404 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n271_s/COUT
6.404 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n270_s/CIN
6.461 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n270_s/COUT
6.461 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n269_s/CIN
6.518 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n269_s/COUT
6.518 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n268_s/CIN
6.575 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n268_s/COUT
6.575 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n267_s/CIN
6.632 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n267_s/COUT
6.632 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n266_s/CIN
6.689 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n266_s/COUT
6.689 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n265_s/CIN
6.746 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n265_s/COUT
6.746 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n264_s/CIN
6.803 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n264_s/COUT
6.803 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n263_s/CIN
6.860 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n263_s/COUT
6.860 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n262_s/CIN
6.917 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n262_s/COUT
6.917 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n261_s/CIN
6.974 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n261_s/COUT
6.974 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n260_s/CIN
7.031 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n260_s/COUT
7.031 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n259_s/CIN
7.088 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n259_s/COUT
7.088 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n258_s/CIN
7.145 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n258_s/COUT
7.145 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n257_s/CIN
7.202 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n257_s/COUT
7.202 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n256_s/CIN
7.259 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n256_s/COUT
7.259 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n255_s/CIN
7.316 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n255_s/COUT
7.316 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n254_s/CIN
7.373 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n254_s/COUT
7.373 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n253_s/CIN
7.430 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n253_s/COUT
7.430 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n252_s/CIN
7.993 0.563 tINS FF 1 Sigma_Delta_Modulator/modulator/n252_s/SUM
8.473 0.480 tNET FF 1 Sigma_Delta_Modulator/modulator/y_35_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.982 0.982 tINS RR 492 clk_ibuf/O
21.345 0.363 tNET RR 1 Sigma_Delta_Modulator/modulator/y_35_s0/CLK
20.945 -0.400 tSu 1 Sigma_Delta_Modulator/modulator/y_35_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.750, 66.636%; route: 1.920, 26.934%; tC2Q: 0.458, 6.430%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 12.707
Data Arrival Time 8.238
Data Required Time 20.945
From Sigma_Delta_Modulator/sdm_fifo/rbin_num_1_s0
To Sigma_Delta_Modulator/sdm_fifo/Empty_s0
Launch Clk in_pdm_clk[R]
Latch Clk in_pdm_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 in_pdm_clk
0.000 0.000 tCL RR 1 in_pdm_clk_ibuf/I
0.982 0.982 tINS RR 27 in_pdm_clk_ibuf/O
1.345 0.363 tNET RR 1 Sigma_Delta_Modulator/sdm_fifo/rbin_num_1_s0/CLK
1.803 0.458 tC2Q RF 4 Sigma_Delta_Modulator/sdm_fifo/rbin_num_1_s0/Q
2.283 0.480 tNET FF 1 Sigma_Delta_Modulator/sdm_fifo/Equal.rgraynext_2_s1/I1
3.382 1.099 tINS FF 6 Sigma_Delta_Modulator/sdm_fifo/Equal.rgraynext_2_s1/F
3.862 0.480 tNET FF 1 Sigma_Delta_Modulator/sdm_fifo/Equal.rgraynext_2_s0/I1
4.961 1.099 tINS FF 2 Sigma_Delta_Modulator/sdm_fifo/Equal.rgraynext_2_s0/F
5.441 0.480 tNET FF 2 Sigma_Delta_Modulator/sdm_fifo/n64_s0/I0
6.399 0.958 tINS FF 1 Sigma_Delta_Modulator/sdm_fifo/n64_s0/COUT
6.399 0.000 tNET FF 2 Sigma_Delta_Modulator/sdm_fifo/n65_s0/CIN
6.456 0.057 tINS FF 1 Sigma_Delta_Modulator/sdm_fifo/n65_s0/COUT
6.936 0.480 tNET FF 1 Sigma_Delta_Modulator/sdm_fifo/rempty_val_s1/I2
7.758 0.822 tINS FF 1 Sigma_Delta_Modulator/sdm_fifo/rempty_val_s1/F
8.238 0.480 tNET FF 1 Sigma_Delta_Modulator/sdm_fifo/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 in_pdm_clk
20.000 0.000 tCL RR 1 in_pdm_clk_ibuf/I
20.982 0.982 tINS RR 27 in_pdm_clk_ibuf/O
21.345 0.363 tNET RR 1 Sigma_Delta_Modulator/sdm_fifo/Empty_s0/CLK
20.945 -0.400 tSu 1 Sigma_Delta_Modulator/sdm_fifo/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.035, 58.535%; route: 2.400, 34.816%; tC2Q: 0.458, 6.649%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 13.057
Data Arrival Time 7.888
Data Required Time 20.945
From Sigma_Delta_Modulator/modulator/tmp_4_0_s0
To Sigma_Delta_Modulator/modulator/tmp_5_f_35_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 492 clk_ibuf/O
1.345 0.363 tNET RR 1 Sigma_Delta_Modulator/modulator/tmp_4_0_s0/CLK
1.803 0.458 tC2Q RF 2 Sigma_Delta_Modulator/modulator/tmp_4_0_s0/Q
2.283 0.480 tNET FF 2 Sigma_Delta_Modulator/modulator/n1684_s/I1
3.328 1.045 tINS FF 1 Sigma_Delta_Modulator/modulator/n1684_s/COUT
3.328 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1683_s/CIN
3.385 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1683_s/COUT
3.385 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1682_s/CIN
3.442 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1682_s/COUT
3.442 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1681_s/CIN
3.499 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1681_s/COUT
3.499 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1680_s/CIN
3.556 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1680_s/COUT
3.556 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1679_s/CIN
3.613 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1679_s/COUT
3.613 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1678_s/CIN
3.670 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1678_s/COUT
3.670 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1677_s/CIN
3.727 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1677_s/COUT
3.727 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1676_s/CIN
3.784 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1676_s/COUT
3.784 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1675_s/CIN
3.841 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1675_s/COUT
3.841 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1674_s/CIN
3.898 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1674_s/COUT
3.898 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1673_s/CIN
3.955 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1673_s/COUT
3.955 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1672_s/CIN
4.012 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1672_s/COUT
4.012 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1671_s/CIN
4.069 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1671_s/COUT
4.069 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1670_s/CIN
4.126 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1670_s/COUT
4.126 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1669_s/CIN
4.183 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1669_s/COUT
4.183 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1668_s/CIN
4.240 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1668_s/COUT
4.240 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1667_s/CIN
4.297 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1667_s/COUT
4.297 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1666_s/CIN
4.354 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1666_s/COUT
4.354 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1665_s/CIN
4.411 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1665_s/COUT
4.411 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1664_s/CIN
4.468 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1664_s/COUT
4.468 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1663_s/CIN
4.525 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1663_s/COUT
4.525 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1662_s/CIN
4.582 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1662_s/COUT
4.582 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1661_s/CIN
4.639 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1661_s/COUT
4.639 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1660_s/CIN
4.696 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1660_s/COUT
4.696 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1659_s/CIN
4.753 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1659_s/COUT
4.753 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1658_s/CIN
4.810 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1658_s/COUT
4.810 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1657_s/CIN
4.867 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1657_s/COUT
4.867 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1656_s/CIN
4.924 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1656_s/COUT
4.924 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1655_s/CIN
4.981 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1655_s/COUT
4.981 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1654_s/CIN
5.038 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1654_s/COUT
5.038 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1653_s/CIN
5.095 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1653_s/COUT
5.095 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1652_s/CIN
5.152 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1652_s/COUT
5.152 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1651_s/CIN
5.209 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1651_s/COUT
5.209 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1650_s/CIN
5.266 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1650_s/COUT
5.266 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1649_s/CIN
5.829 0.563 tINS FF 1 Sigma_Delta_Modulator/modulator/n1649_s/SUM
6.309 0.480 tNET FF 1 Sigma_Delta_Modulator/modulator/n1722_s0/I1
7.408 1.099 tINS FF 1 Sigma_Delta_Modulator/modulator/n1722_s0/F
7.888 0.480 tNET FF 1 Sigma_Delta_Modulator/modulator/tmp_5_f_35_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.982 0.982 tINS RR 492 clk_ibuf/O
21.345 0.363 tNET RR 1 Sigma_Delta_Modulator/modulator/tmp_5_f_35_s1/CLK
20.945 -0.400 tSu 1 Sigma_Delta_Modulator/modulator/tmp_5_f_35_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.645, 70.988%; route: 1.440, 22.007%; tC2Q: 0.458, 7.005%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 13.057
Data Arrival Time 7.888
Data Required Time 20.945
From Sigma_Delta_Modulator/modulator/tmp_3_0_s0
To Sigma_Delta_Modulator/modulator/tmp_4_f_35_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 492 clk_ibuf/O
1.345 0.363 tNET RR 1 Sigma_Delta_Modulator/modulator/tmp_3_0_s0/CLK
1.803 0.458 tC2Q RF 2 Sigma_Delta_Modulator/modulator/tmp_3_0_s0/Q
2.283 0.480 tNET FF 2 Sigma_Delta_Modulator/modulator/n1499_s/I1
3.328 1.045 tINS FF 1 Sigma_Delta_Modulator/modulator/n1499_s/COUT
3.328 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1498_s/CIN
3.385 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1498_s/COUT
3.385 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1497_s/CIN
3.442 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1497_s/COUT
3.442 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1496_s/CIN
3.499 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1496_s/COUT
3.499 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1495_s/CIN
3.556 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1495_s/COUT
3.556 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1494_s/CIN
3.613 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1494_s/COUT
3.613 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1493_s/CIN
3.670 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1493_s/COUT
3.670 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1492_s/CIN
3.727 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1492_s/COUT
3.727 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1491_s/CIN
3.784 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1491_s/COUT
3.784 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1490_s/CIN
3.841 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1490_s/COUT
3.841 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1489_s/CIN
3.898 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1489_s/COUT
3.898 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1488_s/CIN
3.955 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1488_s/COUT
3.955 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1487_s/CIN
4.012 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1487_s/COUT
4.012 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1486_s/CIN
4.069 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1486_s/COUT
4.069 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1485_s/CIN
4.126 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1485_s/COUT
4.126 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1484_s/CIN
4.183 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1484_s/COUT
4.183 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1483_s/CIN
4.240 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1483_s/COUT
4.240 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1482_s/CIN
4.297 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1482_s/COUT
4.297 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1481_s/CIN
4.354 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1481_s/COUT
4.354 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1480_s/CIN
4.411 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1480_s/COUT
4.411 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1479_s/CIN
4.468 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1479_s/COUT
4.468 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1478_s/CIN
4.525 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1478_s/COUT
4.525 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1477_s/CIN
4.582 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1477_s/COUT
4.582 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1476_s/CIN
4.639 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1476_s/COUT
4.639 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1475_s/CIN
4.696 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1475_s/COUT
4.696 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1474_s/CIN
4.753 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1474_s/COUT
4.753 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1473_s/CIN
4.810 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1473_s/COUT
4.810 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1472_s/CIN
4.867 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1472_s/COUT
4.867 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1471_s/CIN
4.924 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1471_s/COUT
4.924 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1470_s/CIN
4.981 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1470_s/COUT
4.981 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1469_s/CIN
5.038 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1469_s/COUT
5.038 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1468_s/CIN
5.095 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1468_s/COUT
5.095 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1467_s/CIN
5.152 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1467_s/COUT
5.152 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1466_s/CIN
5.209 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1466_s/COUT
5.209 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1465_s/CIN
5.266 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1465_s/COUT
5.266 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1464_s/CIN
5.829 0.563 tINS FF 1 Sigma_Delta_Modulator/modulator/n1464_s/SUM
6.309 0.480 tNET FF 1 Sigma_Delta_Modulator/modulator/n1537_s0/I1
7.408 1.099 tINS FF 1 Sigma_Delta_Modulator/modulator/n1537_s0/F
7.888 0.480 tNET FF 1 Sigma_Delta_Modulator/modulator/tmp_4_f_35_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.982 0.982 tINS RR 492 clk_ibuf/O
21.345 0.363 tNET RR 1 Sigma_Delta_Modulator/modulator/tmp_4_f_35_s1/CLK
20.945 -0.400 tSu 1 Sigma_Delta_Modulator/modulator/tmp_4_f_35_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.645, 70.988%; route: 1.440, 22.007%; tC2Q: 0.458, 7.005%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 13.057
Data Arrival Time 7.888
Data Required Time 20.945
From Sigma_Delta_Modulator/modulator/tmp_2_0_s0
To Sigma_Delta_Modulator/modulator/tmp_3_f_35_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 492 clk_ibuf/O
1.345 0.363 tNET RR 1 Sigma_Delta_Modulator/modulator/tmp_2_0_s0/CLK
1.803 0.458 tC2Q RF 2 Sigma_Delta_Modulator/modulator/tmp_2_0_s0/Q
2.283 0.480 tNET FF 2 Sigma_Delta_Modulator/modulator/n1314_s/I1
3.328 1.045 tINS FF 1 Sigma_Delta_Modulator/modulator/n1314_s/COUT
3.328 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1313_s/CIN
3.385 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1313_s/COUT
3.385 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1312_s/CIN
3.442 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1312_s/COUT
3.442 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1311_s/CIN
3.499 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1311_s/COUT
3.499 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1310_s/CIN
3.556 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1310_s/COUT
3.556 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1309_s/CIN
3.613 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1309_s/COUT
3.613 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1308_s/CIN
3.670 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1308_s/COUT
3.670 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1307_s/CIN
3.727 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1307_s/COUT
3.727 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1306_s/CIN
3.784 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1306_s/COUT
3.784 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1305_s/CIN
3.841 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1305_s/COUT
3.841 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1304_s/CIN
3.898 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1304_s/COUT
3.898 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1303_s/CIN
3.955 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1303_s/COUT
3.955 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1302_s/CIN
4.012 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1302_s/COUT
4.012 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1301_s/CIN
4.069 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1301_s/COUT
4.069 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1300_s/CIN
4.126 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1300_s/COUT
4.126 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1299_s/CIN
4.183 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1299_s/COUT
4.183 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1298_s/CIN
4.240 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1298_s/COUT
4.240 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1297_s/CIN
4.297 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1297_s/COUT
4.297 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1296_s/CIN
4.354 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1296_s/COUT
4.354 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1295_s/CIN
4.411 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1295_s/COUT
4.411 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1294_s/CIN
4.468 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1294_s/COUT
4.468 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1293_s/CIN
4.525 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1293_s/COUT
4.525 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1292_s/CIN
4.582 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1292_s/COUT
4.582 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1291_s/CIN
4.639 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1291_s/COUT
4.639 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1290_s/CIN
4.696 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1290_s/COUT
4.696 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1289_s/CIN
4.753 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1289_s/COUT
4.753 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1288_s/CIN
4.810 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1288_s/COUT
4.810 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1287_s/CIN
4.867 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1287_s/COUT
4.867 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1286_s/CIN
4.924 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1286_s/COUT
4.924 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1285_s/CIN
4.981 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1285_s/COUT
4.981 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1284_s/CIN
5.038 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1284_s/COUT
5.038 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1283_s/CIN
5.095 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1283_s/COUT
5.095 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1282_s/CIN
5.152 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1282_s/COUT
5.152 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1281_s/CIN
5.209 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1281_s/COUT
5.209 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1280_s/CIN
5.266 0.057 tINS FF 1 Sigma_Delta_Modulator/modulator/n1280_s/COUT
5.266 0.000 tNET FF 2 Sigma_Delta_Modulator/modulator/n1279_s/CIN
5.829 0.563 tINS FF 1 Sigma_Delta_Modulator/modulator/n1279_s/SUM
6.309 0.480 tNET FF 1 Sigma_Delta_Modulator/modulator/n1352_s0/I1
7.408 1.099 tINS FF 1 Sigma_Delta_Modulator/modulator/n1352_s0/F
7.888 0.480 tNET FF 1 Sigma_Delta_Modulator/modulator/tmp_3_f_35_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.982 0.982 tINS RR 492 clk_ibuf/O
21.345 0.363 tNET RR 1 Sigma_Delta_Modulator/modulator/tmp_3_f_35_s1/CLK
20.945 -0.400 tSu 1 Sigma_Delta_Modulator/modulator/tmp_3_f_35_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.645, 70.988%; route: 1.440, 22.007%; tC2Q: 0.458, 7.005%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%