Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPIFlashInterfaceLite\data\spi_flash_interface_lite_top.v D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPIFlashInterfaceLite\data\spiflash.v |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.8.10 |
Part Number | GW1NSR-LV4CQN48PC7/I6 |
Device | GW1NSR-4 |
Device Version | C |
Created Time | Tue Dec 13 11:09:36 2022 |
Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | SPI_Flash_Interface_Lite_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.441s, Peak memory usage = 43.047MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 43.047MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 43.047MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 43.047MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 43.047MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 43.047MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 43.047MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 43.047MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 43.047MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 43.047MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 43.047MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 43.047MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 54.270MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 54.270MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 54.270MB |
Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 54.270MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 112 |
I/O Buf | 84 |
    IBUF | 43 |
    OBUF | 39 |
    TBUF | 1 |
    IOBUF | 1 |
Register | 292 |
    DFF | 1 |
    DFFP | 4 |
    DFFPE | 2 |
    DFFC | 32 |
    DFFCE | 250 |
    DFFNC | 2 |
    DL | 1 |
LUT | 422 |
    LUT2 | 40 |
    LUT3 | 129 |
    LUT4 | 253 |
ALU | 9 |
    ALU | 9 |
INV | 2 |
    INV | 2 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 433(424 LUTs, 9 ALUs) / 4608 | 10% |
Register | 292 / 3570 | 9% |
  --Register as Latch | 1 / 3570 | <1% |
  --Register as FF | 291 / 3570 | 9% |
BSRAM | 0 / 10 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_hclk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_hclk_ibuf/I | ||
O_flash_ck_d | Base | 20.000 | 50.0 | 0.000 | 10.000 | spiflash_inst/u_spi_spiif/master_gclk_1/O_flash_ck_d_s/F |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_hclk | 50.0(MHz) | 91.3(MHz) | 11 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.672 |
Data Arrival Time | 6.117 |
Data Required Time | 10.789 |
From | spiflash_inst/u_spi_sync/arb_req_sysclk_s0 |
To | spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1 |
Launch Clk | I_hclk[F] |
Latch Clk | I_hclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_hclk | |||
0.000 | 0.000 | tCL | RR | 1 | I_hclk_ibuf/I |
0.728 | 0.728 | tINS | RR | 292 | I_hclk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_sync/arb_req_sysclk_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 6 | spiflash_inst/u_spi_sync/arb_req_sysclk_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_ns_1_s12/I1 |
2.506 | 0.814 | tINS | FF | 2 | spiflash_inst/u_spi_spiif/spi_ns_1_s12/F |
2.862 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_ns_1_s10/I0 |
3.627 | 0.765 | tINS | FF | 4 | spiflash_inst/u_spi_spiif/spi_ns_1_s10/F |
3.982 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s4/I2 |
4.591 | 0.609 | tINS | FF | 11 | spiflash_inst/u_spi_spiif/spi_txdata_rd_Z_s4/F |
4.947 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/master_clk_en_s0/I1 |
5.761 | 0.814 | tINS | FF | 1 | spiflash_inst/u_spi_spiif/master_clk_en_s0/F |
6.117 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_hclk | |||
10.000 | 0.000 | tCL | FF | 1 | I_hclk_ibuf/I |
10.729 | 0.729 | tINS | FF | 292 | I_hclk_ibuf/O |
11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1/CLK |
10.789 | -0.296 | tSu | 1 | spiflash_inst/u_spi_spiif/master_clk_d_en_r_s1 |
Clock Skew: | 0.089 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 3.003, 58.636%; route: 1.778, 34.731%; tC2Q: 0.340, 6.633% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 2
Path Summary:Slack | 6.835 |
Data Arrival Time | 13.866 |
Data Required Time | 20.700 |
From | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1 |
To | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1 |
Launch Clk | I_hclk[R] |
Latch Clk | I_hclk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_hclk | |||
10.000 | 0.000 | tCL | FF | 1 | I_hclk_ibuf/I |
10.729 | 0.729 | tINS | FF | 292 | I_hclk_ibuf/O |
11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1/CLK |
11.425 | 0.340 | tC2Q | FF | 8 | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1/Q |
11.780 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n674_s3/I0 |
12.545 | 0.765 | tINS | FF | 4 | spiflash_inst/u_spi_ctrl/n674_s3/F |
12.901 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n674_s4/I2 |
13.510 | 0.609 | tINS | FF | 1 | spiflash_inst/u_spi_ctrl/n674_s4/F |
13.866 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | I_hclk | |||
20.000 | 0.000 | tCL | RR | 1 | I_hclk_ibuf/I |
20.728 | 0.728 | tINS | RR | 292 | I_hclk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1/CLK |
20.700 | -0.296 | tSu | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1 |
Clock Skew: | -0.089 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Arrival Data Path Delay: | cell: 1.374, 49.409%; route: 1.067, 38.376%; tC2Q: 0.340, 12.215% |
Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Path 3
Path Summary:Slack | 6.835 |
Data Arrival Time | 13.866 |
Data Required Time | 20.700 |
From | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1 |
To | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1 |
Launch Clk | I_hclk[R] |
Latch Clk | I_hclk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_hclk | |||
10.000 | 0.000 | tCL | FF | 1 | I_hclk_ibuf/I |
10.729 | 0.729 | tINS | FF | 292 | I_hclk_ibuf/O |
11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1/CLK |
11.425 | 0.340 | tC2Q | FF | 8 | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1/Q |
11.780 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n673_s3/I0 |
12.545 | 0.765 | tINS | FF | 4 | spiflash_inst/u_spi_ctrl/n673_s3/F |
12.901 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n673_s4/I2 |
13.510 | 0.609 | tINS | FF | 1 | spiflash_inst/u_spi_ctrl/n673_s4/F |
13.866 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | I_hclk | |||
20.000 | 0.000 | tCL | RR | 1 | I_hclk_ibuf/I |
20.728 | 0.728 | tINS | RR | 292 | I_hclk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1/CLK |
20.700 | -0.296 | tSu | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1 |
Clock Skew: | -0.089 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Arrival Data Path Delay: | cell: 1.374, 49.409%; route: 1.067, 38.376%; tC2Q: 0.340, 12.215% |
Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Path 4
Path Summary:Slack | 6.835 |
Data Arrival Time | 13.866 |
Data Required Time | 20.700 |
From | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1 |
To | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1 |
Launch Clk | I_hclk[R] |
Latch Clk | I_hclk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_hclk | |||
10.000 | 0.000 | tCL | FF | 1 | I_hclk_ibuf/I |
10.729 | 0.729 | tINS | FF | 292 | I_hclk_ibuf/O |
11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1/CLK |
11.425 | 0.340 | tC2Q | FF | 8 | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1/Q |
11.780 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n672_s3/I0 |
12.545 | 0.765 | tINS | FF | 4 | spiflash_inst/u_spi_ctrl/n672_s3/F |
12.901 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n672_s4/I2 |
13.510 | 0.609 | tINS | FF | 1 | spiflash_inst/u_spi_ctrl/n672_s4/F |
13.866 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | I_hclk | |||
20.000 | 0.000 | tCL | RR | 1 | I_hclk_ibuf/I |
20.728 | 0.728 | tINS | RR | 292 | I_hclk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1/CLK |
20.700 | -0.296 | tSu | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_2_s1 |
Clock Skew: | -0.089 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Arrival Data Path Delay: | cell: 1.374, 49.409%; route: 1.067, 38.376%; tC2Q: 0.340, 12.215% |
Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Path 5
Path Summary:Slack | 6.835 |
Data Arrival Time | 13.866 |
Data Required Time | 20.700 |
From | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1 |
To | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1 |
Launch Clk | I_hclk[R] |
Latch Clk | I_hclk[F] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_hclk | |||
10.000 | 0.000 | tCL | FF | 1 | I_hclk_ibuf/I |
10.729 | 0.729 | tINS | FF | 292 | I_hclk_ibuf/O |
11.085 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1/CLK |
11.425 | 0.340 | tC2Q | FF | 8 | spiflash_inst/u_spi_spiif/spi_in_d1_r_s1/Q |
11.780 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n671_s3/I0 |
12.545 | 0.765 | tINS | FF | 4 | spiflash_inst/u_spi_ctrl/n671_s3/F |
12.901 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/n671_s4/I2 |
13.510 | 0.609 | tINS | FF | 1 | spiflash_inst/u_spi_ctrl/n671_s4/F |
13.866 | 0.356 | tNET | FF | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | I_hclk | |||
20.000 | 0.000 | tCL | RR | 1 | I_hclk_ibuf/I |
20.728 | 0.728 | tINS | RR | 292 | I_hclk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1/CLK |
20.700 | -0.296 | tSu | 1 | spiflash_inst/u_spi_ctrl/rx_shift_reg_r_3_s1 |
Clock Skew: | -0.089 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Arrival Data Path Delay: | cell: 1.374, 49.409%; route: 1.067, 38.376%; tC2Q: 0.340, 12.215% |
Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |