Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPINorFlash\data\spi_nor_flash_interface_top.v
D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPINorFlash\data\spinorflash.vp
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.10
Part Number GW2AN-UV18XUG400C7/I6
Device GW2AN-18
Device Version X
Created Time Fri Jan 13 17:46:20 2023
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module SPI_Nor_Flash_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.405s, Peak memory usage = 44.660MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 44.660MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 44.660MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 44.660MB
    Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 44.660MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 44.660MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 44.660MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 44.660MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 44.660MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 44.660MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 44.660MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 44.660MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 57.676MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.16s, Peak memory usage = 57.676MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 57.676MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 57.676MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 108
Embedded Port 4
I/O Buf 84
    IBUF 45
    OBUF 38
    IOBUF 1
Register 371
    DFF 1
    DFFP 8
    DFFPE 16
    DFFC 96
    DFFCE 246
    DFFNC 1
    DFFNCE 1
    DL 1
    DLN 1
LUT 761
    LUT2 66
    LUT3 182
    LUT4 513
ALU 70
    ALU 70
INV 6
    INV 6
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 837(767 LUTs, 70 ALUs) / 20736 5%
Register 371 / 16557 3%
  --Register as Latch 2 / 16557 <1%
  --Register as FF 369 / 16557 3%
BSRAM 2 / 30 7%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_hclk Base 10.000 100.0 0.000 5.000 I_hclk_ibuf/I
I_spi_clock Base 10.000 100.0 0.000 5.000 I_spi_clock_ibuf/I
O_flash_ck_d Base 10.000 100.0 0.000 5.000 spinorflash_inst/u_spi_spiif/O_flash_ck_d_s/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_hclk 100.0(MHz) 126.5(MHz) 10 TOP
2 I_spi_clock 100.0(MHz) 61.2(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -3.280
Data Arrival Time 9.357
Data Required Time 6.077
From spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1
Launch Clk I_hclk[F]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_hclk
0.000 0.000 tCL RR 1 I_hclk_ibuf/I
0.853 0.853 tINS RR 217 I_hclk_ibuf/O
1.078 0.225 tNET RR 1 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.368 0.290 tC2Q RF 3 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.664 0.296 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s16/I1
2.377 0.712 tINS FR 1 spinorflash_inst/u_spi_spiif/n147_s16/COUT
2.377 0.000 tNET RR 2 spinorflash_inst/u_spi_spiif/n147_s17/CIN
2.421 0.044 tINS RF 1 spinorflash_inst/u_spi_spiif/n147_s17/COUT
2.421 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s18/CIN
2.465 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s18/COUT
2.465 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s19/CIN
2.509 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s19/COUT
2.509 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s20/CIN
2.553 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s20/COUT
2.553 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s21/CIN
2.597 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s21/COUT
2.597 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s22/CIN
2.641 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s22/COUT
2.937 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.631 0.694 tINS FF 6 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
3.927 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s4/I2
4.493 0.566 tINS FF 3 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s4/F
4.790 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s12/I2
5.356 0.566 tINS FF 2 spinorflash_inst/u_spi_spiif/spi_ns_1_s12/F
5.652 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s10/I1
6.346 0.694 tINS FF 2 spinorflash_inst/u_spi_spiif/spi_ns_1_s10/F
6.642 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s9/I2
7.208 0.566 tINS FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s9/F
7.505 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s8/I1
8.198 0.694 tINS FF 5 spinorflash_inst/u_spi_spiif/spi_ns_1_s8/F
8.495 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/master_clk_en_s0/I2
9.061 0.566 tINS FF 2 spinorflash_inst/u_spi_spiif/master_clk_en_s0/F
9.357 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 I_spi_clock
5.000 0.000 tCL FF 1 I_spi_clock_ibuf/I
5.859 0.859 tINS FF 158 I_spi_clock_ibuf/O
6.156 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1/CLK
6.121 -0.035 tUnc spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1
6.077 -0.044 tSu 1 spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1
Path Statistics:
Clock Skew: 0.077
Setup Relationship: 5.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 5.323, 64.292%; route: 2.666, 32.205%; tC2Q: 0.290, 3.503%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 2

Path Summary:
Slack -2.398
Data Arrival Time 13.398
Data Required Time 10.999
From spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1
Launch Clk I_hclk[R]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_hclk
0.000 0.000 tCL RR 1 I_hclk_ibuf/I
0.853 0.853 tINS RR 217 I_hclk_ibuf/O
1.078 0.225 tNET RR 1 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.368 0.290 tC2Q RF 3 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.664 0.296 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s16/I1
2.377 0.712 tINS FR 1 spinorflash_inst/u_spi_spiif/n147_s16/COUT
2.377 0.000 tNET RR 2 spinorflash_inst/u_spi_spiif/n147_s17/CIN
2.421 0.044 tINS RF 1 spinorflash_inst/u_spi_spiif/n147_s17/COUT
2.421 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s18/CIN
2.465 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s18/COUT
2.465 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s19/CIN
2.509 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s19/COUT
2.509 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s20/CIN
2.553 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s20/COUT
2.553 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s21/CIN
2.597 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s21/COUT
2.597 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s22/CIN
2.641 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s22/COUT
2.937 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.631 0.694 tINS FF 6 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
3.927 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s18/I2
4.493 0.566 tINS FF 4 spinorflash_inst/u_spi_spiif/spi_ns_2_s18/F
4.790 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s12/I1
5.483 0.694 tINS FF 3 spinorflash_inst/u_spi_spiif/spi_ns_2_s12/F
5.780 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0/I1
6.473 0.694 tINS FF 4 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0/F
6.770 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s/I0
7.416 0.646 tINS FF 9 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s/F
7.712 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n245_s17/I1
8.406 0.694 tINS FF 1 spinorflash_inst/u_spi_ctrl/n245_s17/F
8.702 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n245_s16/I0
9.348 0.646 tINS FF 31 spinorflash_inst/u_spi_ctrl/n245_s16/F
9.645 0.296 tNET FF 2 spinorflash_inst/u_spi_ctrl/n14_s0/I1
10.357 0.712 tINS FR 1 spinorflash_inst/u_spi_ctrl/n14_s0/COUT
10.357 0.000 tNET RR 2 spinorflash_inst/u_spi_ctrl/n15_s0/CIN
10.401 0.044 tINS RF 1 spinorflash_inst/u_spi_ctrl/n15_s0/COUT
10.401 0.000 tNET FF 2 spinorflash_inst/u_spi_ctrl/n16_s0/CIN
10.445 0.044 tINS FF 1 spinorflash_inst/u_spi_ctrl/n16_s0/COUT
10.445 0.000 tNET FF 2 spinorflash_inst/u_spi_ctrl/n17_s0/CIN
10.489 0.044 tINS FF 11 spinorflash_inst/u_spi_ctrl/n17_s0/COUT
10.785 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n522_s7/I1
11.479 0.694 tINS FF 1 spinorflash_inst/u_spi_ctrl/n522_s7/F
11.775 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n522_s5/I3
12.239 0.464 tINS FF 1 spinorflash_inst/u_spi_ctrl/n522_s5/F
12.535 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n522_s2/I2
13.102 0.566 tINS FF 1 spinorflash_inst/u_spi_ctrl/n522_s2/F
13.398 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
10.853 0.853 tINS RR 158 I_spi_clock_ibuf/O
11.078 0.225 tNET RR 1 spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1/CLK
11.043 -0.035 tUnc spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1
10.999 -0.044 tSu 1 spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 8.179, 66.385%; route: 3.851, 31.261%; tC2Q: 0.290, 2.354%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 3

Path Summary:
Slack -2.387
Data Arrival Time 13.386
Data Required Time 10.999
From spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0
Launch Clk I_hclk[R]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_hclk
0.000 0.000 tCL RR 1 I_hclk_ibuf/I
0.853 0.853 tINS RR 217 I_hclk_ibuf/O
1.078 0.225 tNET RR 1 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.368 0.290 tC2Q RF 3 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.664 0.296 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s16/I1
2.377 0.712 tINS FR 1 spinorflash_inst/u_spi_spiif/n147_s16/COUT
2.377 0.000 tNET RR 2 spinorflash_inst/u_spi_spiif/n147_s17/CIN
2.421 0.044 tINS RF 1 spinorflash_inst/u_spi_spiif/n147_s17/COUT
2.421 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s18/CIN
2.465 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s18/COUT
2.465 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s19/CIN
2.509 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s19/COUT
2.509 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s20/CIN
2.553 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s20/COUT
2.553 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s21/CIN
2.597 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s21/COUT
2.597 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s22/CIN
2.641 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s22/COUT
2.937 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.631 0.694 tINS FF 6 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
3.927 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s16/I2
4.493 0.566 tINS FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s16/F
4.790 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s11/I1
5.483 0.694 tINS FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s11/F
5.780 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s8/I2
6.346 0.566 tINS FF 7 spinorflash_inst/u_spi_spiif/spi_ns_2_s8/F
6.642 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n243_s21/I1
7.336 0.694 tINS FF 1 spinorflash_inst/u_spi_ctrl/n243_s21/F
7.632 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n243_s17/I0
8.278 0.646 tINS FF 2 spinorflash_inst/u_spi_ctrl/n243_s17/F
8.575 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n244_s18/I1
9.268 0.694 tINS FF 23 spinorflash_inst/u_spi_ctrl/n244_s18/F
9.565 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/txf_rd_Z_s/I0
10.211 0.646 tINS FF 44 spinorflash_inst/u_spi_ctrl/txf_rd_Z_s/F
10.507 0.296 tNET FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_0_s0/I1
11.201 0.694 tINS FF 2 spinorflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_0_s0/F
11.497 0.296 tNET FF 2 spinorflash_inst/u_spi_fifo/u_spi_txfifo/n163_s0/I0
12.183 0.686 tINS FR 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/n163_s0/COUT
12.183 0.000 tNET RR 2 spinorflash_inst/u_spi_fifo/u_spi_txfifo/n164_s0/CIN
12.227 0.044 tINS RF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/n164_s0/COUT
12.524 0.296 tNET FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val_s1/I2
13.090 0.566 tINS FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val_s1/F
13.386 0.296 tNET FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
10.853 0.853 tINS RR 158 I_spi_clock_ibuf/O
11.078 0.225 tNET RR 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0/CLK
11.043 -0.035 tUnc spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0
10.999 -0.044 tSu 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 8.167, 66.353%; route: 3.851, 31.291%; tC2Q: 0.290, 2.356%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 4

Path Summary:
Slack -1.638
Data Arrival Time 12.638
Data Required Time 10.999
From spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s1
Launch Clk I_hclk[R]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_hclk
0.000 0.000 tCL RR 1 I_hclk_ibuf/I
0.853 0.853 tINS RR 217 I_hclk_ibuf/O
1.078 0.225 tNET RR 1 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.368 0.290 tC2Q RF 3 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.664 0.296 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s16/I1
2.377 0.712 tINS FR 1 spinorflash_inst/u_spi_spiif/n147_s16/COUT
2.377 0.000 tNET RR 2 spinorflash_inst/u_spi_spiif/n147_s17/CIN
2.421 0.044 tINS RF 1 spinorflash_inst/u_spi_spiif/n147_s17/COUT
2.421 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s18/CIN
2.465 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s18/COUT
2.465 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s19/CIN
2.509 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s19/COUT
2.509 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s20/CIN
2.553 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s20/COUT
2.553 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s21/CIN
2.597 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s21/COUT
2.597 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s22/CIN
2.641 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s22/COUT
2.937 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.631 0.694 tINS FF 6 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
3.927 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s18/I2
4.493 0.566 tINS FF 4 spinorflash_inst/u_spi_spiif/spi_ns_2_s18/F
4.790 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s12/I1
5.483 0.694 tINS FF 3 spinorflash_inst/u_spi_spiif/spi_ns_2_s12/F
5.780 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0/I1
6.473 0.694 tINS FF 4 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0/F
6.770 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s/I0
7.416 0.646 tINS FF 9 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s/F
7.712 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n245_s17/I1
8.406 0.694 tINS FF 1 spinorflash_inst/u_spi_ctrl/n245_s17/F
8.702 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n245_s16/I0
9.348 0.646 tINS FF 31 spinorflash_inst/u_spi_ctrl/n245_s16/F
9.645 0.296 tNET FF 2 spinorflash_inst/u_spi_ctrl/n14_s0/I1
10.357 0.712 tINS FR 1 spinorflash_inst/u_spi_ctrl/n14_s0/COUT
10.357 0.000 tNET RR 2 spinorflash_inst/u_spi_ctrl/n15_s0/CIN
10.401 0.044 tINS RF 1 spinorflash_inst/u_spi_ctrl/n15_s0/COUT
10.401 0.000 tNET FF 2 spinorflash_inst/u_spi_ctrl/n16_s0/CIN
10.445 0.044 tINS FF 1 spinorflash_inst/u_spi_ctrl/n16_s0/COUT
10.445 0.000 tNET FF 2 spinorflash_inst/u_spi_ctrl/n17_s0/CIN
10.489 0.044 tINS FF 11 spinorflash_inst/u_spi_ctrl/n17_s0/COUT
10.785 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n521_s3/I1
11.479 0.694 tINS FF 1 spinorflash_inst/u_spi_ctrl/n521_s3/F
11.775 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n521_s2/I2
12.342 0.566 tINS FF 1 spinorflash_inst/u_spi_ctrl/n521_s2/F
12.638 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
10.853 0.853 tINS RR 158 I_spi_clock_ibuf/O
11.078 0.225 tNET RR 1 spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s1/CLK
11.043 -0.035 tUnc spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s1
10.999 -0.044 tSu 1 spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 15
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 7.715, 66.738%; route: 3.555, 30.753%; tC2Q: 0.290, 2.509%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 5

Path Summary:
Slack -1.638
Data Arrival Time 12.638
Data Required Time 10.999
From spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spinorflash_inst/u_spi_ctrl/tx_bit_cnt_r_1_s1
Launch Clk I_hclk[R]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_hclk
0.000 0.000 tCL RR 1 I_hclk_ibuf/I
0.853 0.853 tINS RR 217 I_hclk_ibuf/O
1.078 0.225 tNET RR 1 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.368 0.290 tC2Q RF 3 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.664 0.296 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s16/I1
2.377 0.712 tINS FR 1 spinorflash_inst/u_spi_spiif/n147_s16/COUT
2.377 0.000 tNET RR 2 spinorflash_inst/u_spi_spiif/n147_s17/CIN
2.421 0.044 tINS RF 1 spinorflash_inst/u_spi_spiif/n147_s17/COUT
2.421 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s18/CIN
2.465 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s18/COUT
2.465 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s19/CIN
2.509 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s19/COUT
2.509 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s20/CIN
2.553 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s20/COUT
2.553 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s21/CIN
2.597 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s21/COUT
2.597 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s22/CIN
2.641 0.044 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s22/COUT
2.937 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.631 0.694 tINS FF 6 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
3.927 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s18/I2
4.493 0.566 tINS FF 4 spinorflash_inst/u_spi_spiif/spi_ns_2_s18/F
4.790 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s12/I1
5.483 0.694 tINS FF 3 spinorflash_inst/u_spi_spiif/spi_ns_2_s12/F
5.780 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0/I1
6.473 0.694 tINS FF 4 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0/F
6.770 0.296 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s/I0
7.416 0.646 tINS FF 9 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s/F
7.712 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n245_s17/I1
8.406 0.694 tINS FF 1 spinorflash_inst/u_spi_ctrl/n245_s17/F
8.702 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n245_s16/I0
9.348 0.646 tINS FF 31 spinorflash_inst/u_spi_ctrl/n245_s16/F
9.645 0.296 tNET FF 2 spinorflash_inst/u_spi_ctrl/n14_s0/I1
10.357 0.712 tINS FR 1 spinorflash_inst/u_spi_ctrl/n14_s0/COUT
10.357 0.000 tNET RR 2 spinorflash_inst/u_spi_ctrl/n15_s0/CIN
10.401 0.044 tINS RF 1 spinorflash_inst/u_spi_ctrl/n15_s0/COUT
10.401 0.000 tNET FF 2 spinorflash_inst/u_spi_ctrl/n16_s0/CIN
10.445 0.044 tINS FF 1 spinorflash_inst/u_spi_ctrl/n16_s0/COUT
10.445 0.000 tNET FF 2 spinorflash_inst/u_spi_ctrl/n17_s0/CIN
10.489 0.044 tINS FF 11 spinorflash_inst/u_spi_ctrl/n17_s0/COUT
10.785 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n455_s2/I1
11.479 0.694 tINS FF 4 spinorflash_inst/u_spi_ctrl/n455_s2/F
11.775 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/n454_s1/I2
12.342 0.566 tINS FF 1 spinorflash_inst/u_spi_ctrl/n454_s1/F
12.638 0.296 tNET FF 1 spinorflash_inst/u_spi_ctrl/tx_bit_cnt_r_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
10.853 0.853 tINS RR 158 I_spi_clock_ibuf/O
11.078 0.225 tNET RR 1 spinorflash_inst/u_spi_ctrl/tx_bit_cnt_r_1_s1/CLK
11.043 -0.035 tUnc spinorflash_inst/u_spi_ctrl/tx_bit_cnt_r_1_s1
10.999 -0.044 tSu 1 spinorflash_inst/u_spi_ctrl/tx_bit_cnt_r_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 15
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 7.715, 66.738%; route: 3.555, 30.753%; tC2Q: 0.290, 2.509%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%