Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPINorFlash\data\spi_nor_flash_interface_top.v
D:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\SPINorFlash\data\spinorflash.vp
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.10
Part Number GW1NSR-LV4CQN48GC7/I6
Device GW1NSR-4C
Created Time Fri Jan 13 14:29:51 2023
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module SPI_Nor_Flash_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.52s, Peak memory usage = 44.527MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 44.527MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 44.527MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 44.527MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 44.527MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 44.527MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 44.527MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 44.527MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 44.527MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 44.527MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 44.527MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 44.527MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 57.277MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 57.277MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 57.277MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 7s, Peak memory usage = 57.277MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 108
Embedded Port 4
I/O Buf 84
    IBUF 45
    OBUF 38
    IOBUF 1
Register 371
    DFF 1
    DFFP 8
    DFFPE 16
    DFFC 96
    DFFCE 246
    DFFNC 1
    DFFNCE 1
    DL 1
    DLN 1
LUT 761
    LUT2 66
    LUT3 182
    LUT4 513
ALU 70
    ALU 70
INV 6
    INV 6
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 837(767 LUTs, 70 ALUs) / 4608 19%
Register 371 / 3582 11%
  --Register as Latch 2 / 3582 <1%
  --Register as FF 369 / 3582 11%
BSRAM 2 / 10 20%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_hclk Base 20.000 50.0 0.000 10.000 I_hclk_ibuf/I
I_spi_clock Base 20.000 50.0 0.000 10.000 I_spi_clock_ibuf/I
O_flash_ck_d Base 20.000 50.0 0.000 10.000 spinorflash_inst/u_spi_spiif/O_flash_ck_d_s/F

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_hclk 50.0(MHz) 107.7(MHz) 10 TOP
2 I_spi_clock 50.0(MHz) 52.4(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.314
Data Arrival Time 10.445
Data Required Time 10.759
From spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1
Launch Clk I_hclk[F]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_hclk
0.000 0.000 tCL RR 1 I_hclk_ibuf/I
0.728 0.728 tINS RR 217 I_hclk_ibuf/O
0.997 0.269 tNET RR 1 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.336 0.340 tC2Q RF 3 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.692 0.356 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s16/I1
2.466 0.774 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s16/COUT
2.466 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s17/CIN
2.508 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s17/COUT
2.508 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s18/CIN
2.551 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s18/COUT
2.551 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s19/CIN
2.593 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s19/COUT
2.593 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s20/CIN
2.635 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s20/COUT
2.635 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s21/CIN
2.677 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s21/COUT
2.677 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s22/CIN
2.720 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s22/COUT
3.075 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.890 0.814 tINS FF 6 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
4.245 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s4/I2
4.854 0.609 tINS FF 3 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s4/F
5.210 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s12/I2
5.819 0.609 tINS FF 2 spinorflash_inst/u_spi_spiif/spi_ns_1_s12/F
6.175 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s10/I1
6.989 0.814 tINS FF 2 spinorflash_inst/u_spi_spiif/spi_ns_1_s10/F
7.345 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s9/I2
7.954 0.609 tINS FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s9/F
8.310 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_1_s8/I1
9.124 0.814 tINS FF 5 spinorflash_inst/u_spi_spiif/spi_ns_1_s8/F
9.480 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/master_clk_en_s0/I2
10.089 0.609 tINS FF 2 spinorflash_inst/u_spi_spiif/master_clk_en_s0/F
10.445 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL FF 1 I_spi_clock_ibuf/I
10.729 0.729 tINS FF 158 I_spi_clock_ibuf/O
11.085 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1/CLK
11.055 -0.030 tUnc spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1
10.759 -0.296 tSu 1 spinorflash_inst/u_spi_spiif/master_clk_d_en_r_s1
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 5.907, 62.524%; route: 3.201, 33.881%; tC2Q: 0.340, 3.595%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 2

Path Summary:
Slack 5.498
Data Arrival Time 15.172
Data Required Time 20.670
From spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1
Launch Clk I_hclk[R]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_hclk
0.000 0.000 tCL RR 1 I_hclk_ibuf/I
0.728 0.728 tINS RR 217 I_hclk_ibuf/O
0.997 0.269 tNET RR 1 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.336 0.340 tC2Q RF 3 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.692 0.356 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s16/I1
2.466 0.774 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s16/COUT
2.466 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s17/CIN
2.508 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s17/COUT
2.508 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s18/CIN
2.551 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s18/COUT
2.551 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s19/CIN
2.593 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s19/COUT
2.593 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s20/CIN
2.635 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s20/COUT
2.635 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s21/CIN
2.677 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s21/COUT
2.677 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s22/CIN
2.720 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s22/COUT
3.075 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.890 0.814 tINS FF 6 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
4.245 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s18/I2
4.854 0.609 tINS FF 4 spinorflash_inst/u_spi_spiif/spi_ns_2_s18/F
5.210 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s12/I1
6.024 0.814 tINS FF 3 spinorflash_inst/u_spi_spiif/spi_ns_2_s12/F
6.380 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0/I1
7.195 0.814 tINS FF 4 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s0/F
7.550 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s/I0
8.315 0.765 tINS FF 9 spinorflash_inst/u_spi_spiif/spi_txdata_rd_Z_s/F
8.671 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n245_s17/I1
9.485 0.814 tINS FF 1 spinorflash_inst/u_spi_ctrl/n245_s17/F
9.841 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n245_s16/I0
10.605 0.765 tINS FF 31 spinorflash_inst/u_spi_ctrl/n245_s16/F
10.961 0.356 tNET FF 2 spinorflash_inst/u_spi_ctrl/n14_s0/I1
11.735 0.774 tINS FF 1 spinorflash_inst/u_spi_ctrl/n14_s0/COUT
11.735 0.000 tNET FF 2 spinorflash_inst/u_spi_ctrl/n15_s0/CIN
11.778 0.042 tINS FF 1 spinorflash_inst/u_spi_ctrl/n15_s0/COUT
11.778 0.000 tNET FF 2 spinorflash_inst/u_spi_ctrl/n16_s0/CIN
11.820 0.042 tINS FF 1 spinorflash_inst/u_spi_ctrl/n16_s0/COUT
11.820 0.000 tNET FF 2 spinorflash_inst/u_spi_ctrl/n17_s0/CIN
11.862 0.042 tINS FF 11 spinorflash_inst/u_spi_ctrl/n17_s0/COUT
12.218 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n522_s7/I1
13.032 0.814 tINS FF 1 spinorflash_inst/u_spi_ctrl/n522_s7/F
13.388 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n522_s5/I3
13.852 0.464 tINS FF 1 spinorflash_inst/u_spi_ctrl/n522_s5/F
14.207 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n522_s2/I2
14.816 0.609 tINS FF 1 spinorflash_inst/u_spi_ctrl/n522_s2/F
15.172 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_spi_clock
20.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
20.728 0.728 tINS RR 158 I_spi_clock_ibuf/O
20.997 0.269 tNET RR 1 spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1/CLK
20.967 -0.030 tUnc spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1
20.670 -0.296 tSu 1 spinorflash_inst/u_spi_ctrl/rx_mask_cnt_r_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 9.212, 64.986%; route: 4.624, 32.618%; tC2Q: 0.340, 2.396%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack 5.502
Data Arrival Time 15.168
Data Required Time 20.670
From spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0
Launch Clk I_hclk[R]
Latch Clk I_spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_hclk
0.000 0.000 tCL RR 1 I_hclk_ibuf/I
0.728 0.728 tINS RR 217 I_hclk_ibuf/O
0.997 0.269 tNET RR 1 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
1.336 0.340 tC2Q RF 3 spinorflash_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.692 0.356 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s16/I1
2.466 0.774 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s16/COUT
2.466 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s17/CIN
2.508 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s17/COUT
2.508 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s18/CIN
2.551 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s18/COUT
2.551 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s19/CIN
2.593 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s19/COUT
2.593 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s20/CIN
2.635 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s20/COUT
2.635 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s21/CIN
2.677 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s21/COUT
2.677 0.000 tNET FF 2 spinorflash_inst/u_spi_spiif/n147_s22/CIN
2.720 0.042 tINS FF 1 spinorflash_inst/u_spi_spiif/n147_s22/COUT
3.075 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/I1
3.890 0.814 tINS FF 6 spinorflash_inst/u_spi_spiif/period_cnt_r_7_s5/F
4.245 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s16/I2
4.854 0.609 tINS FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s16/F
5.210 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s11/I1
6.024 0.814 tINS FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s11/F
6.380 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_ns_2_s8/I2
6.989 0.609 tINS FF 7 spinorflash_inst/u_spi_spiif/spi_ns_2_s8/F
7.345 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n243_s21/I1
8.159 0.814 tINS FF 1 spinorflash_inst/u_spi_ctrl/n243_s21/F
8.515 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n243_s17/I0
9.280 0.765 tINS FF 2 spinorflash_inst/u_spi_ctrl/n243_s17/F
9.635 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n243_s16/I0
10.400 0.765 tINS FF 24 spinorflash_inst/u_spi_ctrl/n243_s16/F
10.756 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/txf_rd_Z_s/I1
11.570 0.814 tINS FF 44 spinorflash_inst/u_spi_ctrl/txf_rd_Z_s/F
11.926 0.356 tNET FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_0_s0/I1
12.740 0.814 tINS FF 2 spinorflash_inst/u_spi_fifo/u_spi_txfifo/rgraynext_0_s0/F
13.096 0.356 tNET FF 2 spinorflash_inst/u_spi_fifo/u_spi_txfifo/n163_s0/I0
13.806 0.710 tINS FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/n163_s0/COUT
13.806 0.000 tNET FF 2 spinorflash_inst/u_spi_fifo/u_spi_txfifo/n164_s0/CIN
13.848 0.042 tINS FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/n164_s0/COUT
14.204 0.356 tNET FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val_s1/I2
14.813 0.609 tINS FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/rempty_val_s1/F
15.168 0.356 tNET FF 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_spi_clock
20.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
20.728 0.728 tINS RR 158 I_spi_clock_ibuf/O
20.997 0.269 tNET RR 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0/CLK
20.967 -0.030 tUnc spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0
20.670 -0.296 tSu 1 spinorflash_inst/u_spi_fifo/u_spi_txfifo/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 9.208, 64.977%; route: 4.624, 32.627%; tC2Q: 0.340, 2.396%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack 5.859
Data Arrival Time 14.841
Data Required Time 20.700
From spinorflash_inst/u_spi_spiif/spi_in_d1_r_1_s1
To spinorflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1
Launch Clk I_spi_clock[R]
Latch Clk I_spi_clock[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL FF 1 I_spi_clock_ibuf/I
10.729 0.729 tINS FF 158 I_spi_clock_ibuf/O
11.085 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_in_d1_r_1_s1/CLK
11.425 0.340 tC2Q FF 1 spinorflash_inst/u_spi_spiif/spi_in_d1_r_1_s1/Q
11.780 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n1079_s6/I0
12.545 0.765 tINS FF 4 spinorflash_inst/u_spi_ctrl/n1079_s6/F
12.901 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n1079_s2/I0
13.666 0.765 tINS FF 8 spinorflash_inst/u_spi_ctrl/n1079_s2/F
14.021 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n1079_s7/I3
14.485 0.464 tINS FF 1 spinorflash_inst/u_spi_ctrl/n1079_s7/F
14.841 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_spi_clock
20.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
20.728 0.728 tINS RR 158 I_spi_clock_ibuf/O
20.997 0.269 tNET RR 1 spinorflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1/CLK
20.700 -0.296 tSu 1 spinorflash_inst/u_spi_ctrl/rx_shift_reg_r_0_s1
Path Statistics:
Clock Skew: -0.089
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%
Arrival Data Path Delay: cell: 1.993, 53.075%; route: 1.423, 37.882%; tC2Q: 0.340, 9.043%
Required Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%

Path 5

Path Summary:
Slack 5.859
Data Arrival Time 14.841
Data Required Time 20.700
From spinorflash_inst/u_spi_spiif/spi_in_d1_r_1_s1
To spinorflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1
Launch Clk I_spi_clock[R]
Latch Clk I_spi_clock[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_spi_clock
10.000 0.000 tCL FF 1 I_spi_clock_ibuf/I
10.729 0.729 tINS FF 158 I_spi_clock_ibuf/O
11.085 0.356 tNET FF 1 spinorflash_inst/u_spi_spiif/spi_in_d1_r_1_s1/CLK
11.425 0.340 tC2Q FF 1 spinorflash_inst/u_spi_spiif/spi_in_d1_r_1_s1/Q
11.780 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n1079_s6/I0
12.545 0.765 tINS FF 4 spinorflash_inst/u_spi_ctrl/n1079_s6/F
12.901 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n1078_s2/I0
13.666 0.765 tINS FF 8 spinorflash_inst/u_spi_ctrl/n1078_s2/F
14.021 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/n1078_s3/I3
14.485 0.464 tINS FF 1 spinorflash_inst/u_spi_ctrl/n1078_s3/F
14.841 0.356 tNET FF 1 spinorflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_spi_clock
20.000 0.000 tCL RR 1 I_spi_clock_ibuf/I
20.728 0.728 tINS RR 158 I_spi_clock_ibuf/O
20.997 0.269 tNET RR 1 spinorflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1/CLK
20.700 -0.296 tSu 1 spinorflash_inst/u_spi_ctrl/rx_shift_reg_r_1_s1
Path Statistics:
Clock Skew: -0.089
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%
Arrival Data Path Delay: cell: 1.993, 53.075%; route: 1.423, 37.882%; tC2Q: 0.340, 9.043%
Required Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%