Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\SCALER_LITE_up\data\scaler_lite_up_top.v
D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\SCALER_LITE_up\data\scaler_core_up.vp
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18C
Created Time Fri Mar 05 17:41:53 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Scaler_Lite_Up_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 28.242MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 28.242MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 28.242MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 28.242MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 28.242MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 28.242MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 28.242MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 28.242MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 28.242MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 28.242MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 28.242MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 28.242MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 45.363MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.125s, Peak memory usage = 45.363MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 45.363MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 45.363MB

Resource

Resource Usage Summary

I/O Port 73
I/O Buf 73
    IBUF 37
    OBUF 36
Register 459
    DFFP 2
    DFFPE 5
    DFFC 335
    DFFCE 117
LUT 595
    LUT2 76
    LUT3 290
    LUT4 229
ALU 805
    ALU 805
BSRAM 4
    SDPB 4

Resource Utilization Summary

Logic 1400(595 LUTs, 805 ALUs) / 20736 7%
Register 459 / 15750 3%
  --Register as Latch 0 / 15750 0%
  --Register as FF 459 / 15750 3%
BSRAM 4 / 46 9%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_sysclk Base 10.000 100.0 0.000 5.000 I_sysclk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_sysclk 100.0(MHz) 151.0(MHz) 11 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.377
Data Arrival Time 7.450
Data Required Time 10.828
From scaler_core_up_inst/ver_calcdata_gen_inst/vval_data1_2_s1
To scaler_core_up_inst/hor_calcdata_gen_inst/mult8_data2_15_s0
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 467 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_up_inst/ver_calcdata_gen_inst/vval_data1_2_s1/CLK
1.095 0.232 tC2Q RF 5 scaler_core_up_inst/ver_calcdata_gen_inst/vval_data1_2_s1/Q
1.332 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data2_3_s2/I1
1.887 0.555 tINS FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data2_3_s2/F
2.124 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data2_3_s1/I2
2.577 0.453 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data2_3_s1/F
2.814 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data2_4_s/CIN
3.284 0.470 tINS FF 4 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data2_4_s/SUM
3.521 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1724_s/I1
4.091 0.570 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1724_s/COUT
4.091 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1723_s/CIN
4.126 0.035 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1723_s/COUT
4.126 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1722_s/CIN
4.161 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1722_s/COUT
4.161 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1721_s/CIN
4.196 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1721_s/COUT
4.196 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1720_s/CIN
4.231 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1720_s/COUT
4.231 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1719_s/CIN
4.701 0.470 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1719_s/SUM
4.938 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1730_s/I0
5.487 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1730_s/COUT
5.487 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1729_s/CIN
5.957 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1729_s/SUM
6.194 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1742_s/I0
6.743 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1742_s/COUT
6.743 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1741_s/CIN
7.213 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1741_s/SUM
7.450 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult8_data2_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 467 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult8_data2_15_s0/CLK
10.828 -0.035 tSu 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult8_data2_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.697, 71.295%; route: 1.659, 25.183%; tC2Q: 0.232, 3.522%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 3.377
Data Arrival Time 7.450
Data Required Time 10.828
From scaler_core_up_inst/ver_calcdata_gen_inst/vval_data0_2_s1
To scaler_core_up_inst/hor_calcdata_gen_inst/mult8_data1_15_s0
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 467 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_up_inst/ver_calcdata_gen_inst/vval_data0_2_s1/CLK
1.095 0.232 tC2Q RF 9 scaler_core_up_inst/ver_calcdata_gen_inst/vval_data0_2_s1/Q
1.332 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data1_3_s2/I1
1.887 0.555 tINS FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data1_3_s2/F
2.124 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data1_3_s1/I2
2.577 0.453 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data1_3_s1/F
2.814 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data1_4_s/CIN
3.284 0.470 tINS FF 4 scaler_core_up_inst/hor_calcdata_gen_inst/sum8_data1_4_s/SUM
3.521 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1685_s/I1
4.091 0.570 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1685_s/COUT
4.091 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1684_s/CIN
4.126 0.035 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1684_s/COUT
4.126 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1683_s/CIN
4.161 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1683_s/COUT
4.161 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1682_s/CIN
4.196 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1682_s/COUT
4.196 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1681_s/CIN
4.231 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1681_s/COUT
4.231 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1680_s/CIN
4.701 0.470 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1680_s/SUM
4.938 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1691_s/I0
5.487 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1691_s/COUT
5.487 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1690_s/CIN
5.957 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1690_s/SUM
6.194 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1703_s/I0
6.743 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1703_s/COUT
6.743 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1702_s/CIN
7.213 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1702_s/SUM
7.450 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult8_data1_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 467 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult8_data1_15_s0/CLK
10.828 -0.035 tSu 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult8_data1_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.697, 71.295%; route: 1.659, 25.183%; tC2Q: 0.232, 3.522%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 3.377
Data Arrival Time 7.450
Data Required Time 10.828
From scaler_core_up_inst/hor_calcdata_gen_inst/vval_data3_d1_2_s0
To scaler_core_up_inst/hor_calcdata_gen_inst/mult6_data1_15_s0
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 467 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_up_inst/hor_calcdata_gen_inst/vval_data3_d1_2_s0/CLK
1.095 0.232 tC2Q RF 5 scaler_core_up_inst/hor_calcdata_gen_inst/vval_data3_d1_2_s0/Q
1.332 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data1_3_s2/I1
1.887 0.555 tINS FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data1_3_s2/F
2.124 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data1_3_s1/I2
2.577 0.453 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data1_3_s1/F
2.814 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data1_4_s/CIN
3.284 0.470 tINS FF 4 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data1_4_s/SUM
3.521 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1490_s/I1
4.091 0.570 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1490_s/COUT
4.091 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1489_s/CIN
4.126 0.035 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1489_s/COUT
4.126 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1488_s/CIN
4.161 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1488_s/COUT
4.161 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1487_s/CIN
4.196 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1487_s/COUT
4.196 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1486_s/CIN
4.231 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1486_s/COUT
4.231 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1485_s/CIN
4.701 0.470 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1485_s/SUM
4.938 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1496_s/I0
5.487 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1496_s/COUT
5.487 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1495_s/CIN
5.957 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1495_s/SUM
6.194 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1508_s/I0
6.743 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1508_s/COUT
6.743 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1507_s/CIN
7.213 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1507_s/SUM
7.450 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult6_data1_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 467 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult6_data1_15_s0/CLK
10.828 -0.035 tSu 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult6_data1_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.697, 71.295%; route: 1.659, 25.183%; tC2Q: 0.232, 3.522%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 3.377
Data Arrival Time 7.450
Data Required Time 10.828
From scaler_core_up_inst/hor_calcdata_gen_inst/vval_data2_d1_2_s0
To scaler_core_up_inst/hor_calcdata_gen_inst/mult6_data0_15_s0
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 467 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_up_inst/hor_calcdata_gen_inst/vval_data2_d1_2_s0/CLK
1.095 0.232 tC2Q RF 7 scaler_core_up_inst/hor_calcdata_gen_inst/vval_data2_d1_2_s0/Q
1.332 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data0_3_s2/I1
1.887 0.555 tINS FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data0_3_s2/F
2.124 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data0_3_s1/I2
2.577 0.453 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data0_3_s1/F
2.814 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data0_4_s/CIN
3.284 0.470 tINS FF 4 scaler_core_up_inst/hor_calcdata_gen_inst/sum6_data0_4_s/SUM
3.521 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1451_s/I1
4.091 0.570 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1451_s/COUT
4.091 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1450_s/CIN
4.126 0.035 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1450_s/COUT
4.126 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1449_s/CIN
4.161 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1449_s/COUT
4.161 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1448_s/CIN
4.196 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1448_s/COUT
4.196 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1447_s/CIN
4.231 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1447_s/COUT
4.231 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1446_s/CIN
4.701 0.470 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1446_s/SUM
4.938 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1457_s/I0
5.487 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1457_s/COUT
5.487 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1456_s/CIN
5.957 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1456_s/SUM
6.194 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1469_s/I0
6.743 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1469_s/COUT
6.743 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1468_s/CIN
7.213 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1468_s/SUM
7.450 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult6_data0_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 467 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult6_data0_15_s0/CLK
10.828 -0.035 tSu 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult6_data0_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.697, 71.295%; route: 1.659, 25.183%; tC2Q: 0.232, 3.522%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 3.377
Data Arrival Time 7.450
Data Required Time 10.828
From scaler_core_up_inst/hor_calcdata_gen_inst/vval_data3_d2_1_s0
To scaler_core_up_inst/hor_calcdata_gen_inst/mult5_data1_15_s0
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 467 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_up_inst/hor_calcdata_gen_inst/vval_data3_d2_1_s0/CLK
1.095 0.232 tC2Q RF 12 scaler_core_up_inst/hor_calcdata_gen_inst/vval_data3_d2_1_s0/Q
1.332 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum5_data1_3_s2/I1
1.887 0.555 tINS FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum5_data1_3_s2/F
2.124 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum5_data1_3_s1/I2
2.577 0.453 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/sum5_data1_3_s1/F
2.814 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/sum5_data1_4_s/CIN
3.284 0.470 tINS FF 4 scaler_core_up_inst/hor_calcdata_gen_inst/sum5_data1_4_s/SUM
3.521 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1334_s/I1
4.091 0.570 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1334_s/COUT
4.091 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1333_s/CIN
4.126 0.035 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1333_s/COUT
4.126 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1332_s/CIN
4.161 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1332_s/COUT
4.161 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1331_s/CIN
4.196 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1331_s/COUT
4.196 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1330_s/CIN
4.231 0.035 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1330_s/COUT
4.231 0.000 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1329_s/CIN
4.701 0.470 tINS FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1329_s/SUM
4.938 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1340_s/I0
5.487 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1340_s/COUT
5.487 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1339_s/CIN
5.957 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1339_s/SUM
6.194 0.237 tNET FF 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1352_s/I0
6.743 0.549 tINS FR 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1352_s/COUT
6.743 0.000 tNET RR 2 scaler_core_up_inst/hor_calcdata_gen_inst/n1351_s/CIN
7.213 0.470 tINS RF 1 scaler_core_up_inst/hor_calcdata_gen_inst/n1351_s/SUM
7.450 0.237 tNET FF 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult5_data1_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 467 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult5_data1_15_s0/CLK
10.828 -0.035 tSu 1 scaler_core_up_inst/hor_calcdata_gen_inst/mult5_data1_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.697, 71.295%; route: 1.659, 25.183%; tC2Q: 0.232, 3.522%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%