Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7Beta_44893_20200930\IDE\ipcore\PSRAM_HS\data\PSRAM_TOP.v
D:\Gowin\Gowin_V1.9.7Beta_44893_20200930\IDE\ipcore\PSRAM_HS\data\psram_code.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.7Beta
Created Time Fri Oct 09 14:15:35 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: PSRAM_Memory_Interface_HS_Top
Part Number: GW2AR-LV18QN88PC8/I7
Device: GW2AR-18C

Resource

Resource Usage Summary

I/O Port 166
Emedded Port 26
I/O Buf 190
    IBUF 99
    OBUF 71
    IOBUF 18
    ELVDS_OBUF 2
Register 524
    DFF 1
    DFFP 3
    DFFPE 6
    DFFC 290
    DFFCE 216
    DL 8
LUT 862
    LUT2 246
    LUT3 318
    LUT4 298
ALU 42
    ALU 42
INV 6
    INV 6
IOLOGIC 56
    IDES4 16
    OSER4 22
    IODELAY 18
BSRAM 2
    SDPX9B 2
CLOCK 2
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Logic 910(868 LUTs, 42 ALUs) / 20736 4%
Register 524 / 15828 3%
BSRAM 2 / 46 4%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I
u_psram_top/clkdiv/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 memory_clk_ibuf/I memory_clk u_psram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0 MHz 208.8 MHz 6 TOP
2 u_psram_top/clkdiv/CLKOUT.default_gen_clk 50.0 MHz 272.9 MHz 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4
Data Arrival Time 2
Data Required Time 6
From u_psram_top/u_psram_sync/dll_rst_s0
To u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[6].dq_oser4
Launch Clk clk[F]
Latch Clk memory_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 31 clk_ibuf/O
0.862 0.18 tNET RR 1 u_psram_top/u_psram_sync/dll_rst_s0/CLK
1.094 0.232 tC2Q RF 3 u_psram_top/u_psram_sync/dll_rst_s0/Q
1.331 0.237 tNET FF 1 u_psram_top/u_psram_sync/ddr_rsti_s0/I1
1.886 0.555 tINS FF 522 u_psram_top/u_psram_sync/ddr_rsti_s0/F
2.123 0.237 tNET FF 2 u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[6].dq_oser4/RESET

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 memory_clk_ibuf/I
5.687 0.687 tINS FF 1 memory_clk_ibuf/O
5.924 0.237 tNET FF 3 u_psram_top/u_dqce_clk_x2p/CLKIN
6.110 0.186 tINS FF 40 u_psram_top/u_dqce_clk_x2p/CLKOUT
6.347 0.237 tNET FF 1 u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[6].dq_oser4/FCLK

Path Statistic:
Clock Skew: 0
Hold Relationship: 5
Logic Level: 2
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398%
Required Clock Path Delay: cell: 0.873, 64.824%; route: 0.474, 35.176%

Path 2

Path Summary:
Slack 4.038
Data Arrival Time 2.123
Data Required Time 6.161
From u_psram_top/u_psram_sync/dll_rst_s0
To u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4
Launch Clk clk[F]
Latch Clk memory_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 31 clk_ibuf/O
0.862 0.18 tNET RR 1 u_psram_top/u_psram_sync/dll_rst_s0/CLK
1.094 0.232 tC2Q RF 3 u_psram_top/u_psram_sync/dll_rst_s0/Q
1.331 0.237 tNET FF 1 u_psram_top/u_psram_sync/ddr_rsti_s0/I1
1.886 0.555 tINS FF 522 u_psram_top/u_psram_sync/ddr_rsti_s0/F
2.123 0.237 tNET FF 2 u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4/RESET

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 memory_clk_ibuf/I
5.687 0.687 tINS FF 1 memory_clk_ibuf/O
5.924 0.237 tNET FF 3 u_psram_top/u_dqce_clk_x2p/CLKIN
6.110 0.186 tINS FF 40 u_psram_top/u_dqce_clk_x2p/CLKOUT
6.347 0.237 tNET FF 1 u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/oserdes_data_gen[5].dq_oser4/FCLK

Path Statistic:
Clock Skew: 0.970
Hold Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%
Arrival Data Path Delay: cell: 1.110, 48.472%; route: 0.948, 41.397%; tC2Q: 0.232, 10.131%
Required Clock Path Delay: cell: 1.747, 64.824%; route: 0.948, 35.176%

Path 3

Path Summary:
Slack 4.038
Data Arrival Time 2.123
Data Required Time 6.161
From u_psram_top/u_psram_sync/dll_rst_s0
To u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[7].dq_oser4
Launch Clk clk[F]
Latch Clk memory_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 31 clk_ibuf/O
0.862 0.18 tNET RR 1 u_psram_top/u_psram_sync/dll_rst_s0/CLK
1.094 0.232 tC2Q RF 3 u_psram_top/u_psram_sync/dll_rst_s0/Q
1.331 0.237 tNET FF 1 u_psram_top/u_psram_sync/ddr_rsti_s0/I1
1.886 0.555 tINS FF 522 u_psram_top/u_psram_sync/ddr_rsti_s0/F
2.123 0.237 tNET FF 2 u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[7].dq_oser4/RESET

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 memory_clk_ibuf/I
5.687 0.687 tINS FF 1 memory_clk_ibuf/O
5.924 0.237 tNET FF 3 u_psram_top/u_dqce_clk_x2p/CLKIN
6.110 0.186 tINS FF 40 u_psram_top/u_dqce_clk_x2p/CLKOUT
6.347 0.237 tNET FF 1 u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[7].dq_oser4/FCLK

Path Statistic:
Clock Skew: 1.455
Hold Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%
Arrival Data Path Delay: cell: 1.665, 50.166%; route: 1.422, 42.844%; tC2Q: 0.232, 6.990%
Required Clock Path Delay: cell: 2.621, 64.824%; route: 1.422, 35.176%

Path 4

Path Summary:
Slack 4.038
Data Arrival Time 2.123
Data Required Time 6.161
From u_psram_top/u_psram_sync/dll_rst_s0
To u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk[F]
Latch Clk memory_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 31 clk_ibuf/O
0.862 0.18 tNET RR 1 u_psram_top/u_psram_sync/dll_rst_s0/CLK
1.094 0.232 tC2Q RF 3 u_psram_top/u_psram_sync/dll_rst_s0/Q
1.331 0.237 tNET FF 1 u_psram_top/u_psram_sync/ddr_rsti_s0/I1
1.886 0.555 tINS FF 522 u_psram_top/u_psram_sync/ddr_rsti_s0/F
2.123 0.237 tNET FF 2 u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 memory_clk_ibuf/I
5.687 0.687 tINS FF 1 memory_clk_ibuf/O
5.924 0.237 tNET FF 3 u_psram_top/u_dqce_clk_x2p/CLKIN
6.110 0.186 tINS FF 40 u_psram_top/u_dqce_clk_x2p/CLKOUT
6.347 0.237 tNET FF 1 u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK

Path Statistic:
Clock Skew: 1.940
Hold Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%
Arrival Data Path Delay: cell: 2.220, 51.058%; route: 1.896, 43.606%; tC2Q: 0.232, 5.336%
Required Clock Path Delay: cell: 3.494, 64.824%; route: 1.896, 35.176%

Path 5

Path Summary:
Slack 4.038
Data Arrival Time 2.123
Data Required Time 6.161
From u_psram_top/u_psram_sync/dll_rst_s0
To u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[2].dq_oser4
Launch Clk clk[F]
Latch Clk memory_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 clk_ibuf/I
0.682 0.682 tINS RR 31 clk_ibuf/O
0.862 0.18 tNET RR 1 u_psram_top/u_psram_sync/dll_rst_s0/CLK
1.094 0.232 tC2Q RF 3 u_psram_top/u_psram_sync/dll_rst_s0/Q
1.331 0.237 tNET FF 1 u_psram_top/u_psram_sync/ddr_rsti_s0/I1
1.886 0.555 tINS FF 522 u_psram_top/u_psram_sync/ddr_rsti_s0/F
2.123 0.237 tNET FF 2 u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[2].dq_oser4/RESET

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 memory_clk_ibuf/I
5.687 0.687 tINS FF 1 memory_clk_ibuf/O
5.924 0.237 tNET FF 3 u_psram_top/u_dqce_clk_x2p/CLKIN
6.110 0.186 tINS FF 40 u_psram_top/u_dqce_clk_x2p/CLKOUT
6.347 0.237 tNET FF 1 u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/oserdes_data_gen[2].dq_oser4/FCLK

Path Statistic:
Clock Skew: 2.425
Hold Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%
Arrival Data Path Delay: cell: 2.775, 51.609%; route: 2.370, 44.077%; tC2Q: 0.232, 4.315%
Required Clock Path Delay: cell: 4.368, 64.824%; route: 2.370, 35.176%

Synthesis completed successfully!
Process took 0h:0m:5s realtime, 0h:0m:5s cputime
Memory peak: 48.9MB