Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\DVI_TX\data\dvi_tx_top.v
D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\DVI_TX\data\rgb2dvi.vp
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18C
Created Time Fri Mar 05 15:57:11 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DVI_TX_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 24.969MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 24.969MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 24.969MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 24.969MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 24.969MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 24.969MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 24.969MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 24.969MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 24.969MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 24.969MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 24.969MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 24.969MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 43.074MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 43.074MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 43.074MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 43.074MB

Resource

Resource Usage Summary

I/O Port 38
I/O Buf 34
    IBUF 30
    TLVDS_OBUF 4
Register 73
    DFFP 3
    DFFC 70
LUT 213
    LUT2 29
    LUT3 50
    LUT4 134
ALU 68
    ALU 68
INV 4
    INV 4
IOLOGIC 4
    OSER10 4

Resource Utilization Summary

Logic 285(217 LUTs, 68 ALUs) / 20736 1%
Register 73 / 15750 1%
  --Register as Latch 0 / 15750 0%
  --Register as FF 73 / 15750 1%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_rgb_clk Base 10.000 100.0 0.000 5.000 I_rgb_clk_ibuf/I
I_serial_clk Base 10.000 100.0 0.000 5.000 I_serial_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_rgb_clk 100.0(MHz) 120.1(MHz) 12 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.675
Data Arrival Time 9.153
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0
To rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK
1.095 0.232 tC2Q RF 5 rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1
1.887 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3
2.495 0.371 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F
2.732 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0
3.249 0.517 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F
3.486 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/I0
4.003 0.517 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/F
4.240 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/I1
4.794 0.555 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/F
5.031 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I2
5.484 0.453 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
5.721 0.237 tNET FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/I1
6.292 0.570 tINS FR 1 rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/COUT
6.292 0.000 tNET RR 2 rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/CIN
6.761 0.470 tINS RF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/SUM
6.998 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n578_s6/I3
7.369 0.371 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n578_s6/F
7.606 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n578_s3/I0
8.123 0.517 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n578_s3/F
8.361 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n578_s1/I1
8.916 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n578_s1/F
9.153 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.451, 65.754%; route: 2.607, 31.448%; tC2Q: 0.232, 2.799%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 2.730
Data Arrival Time 8.097
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0
To rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK
1.095 0.232 tC2Q RF 5 rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1
1.887 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3
2.495 0.371 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F
2.732 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0
3.249 0.517 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F
3.486 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/I0
4.003 0.517 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/F
4.240 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/I1
4.794 0.555 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/F
5.031 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I2
5.484 0.453 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
5.721 0.237 tNET FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3/I1
6.276 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3/SUM
6.513 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n579_s3/I1
7.068 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n579_s3/F
7.305 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n579_s1/I1
7.860 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n579_s1/F
8.097 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.633, 64.036%; route: 2.370, 32.757%; tC2Q: 0.232, 3.207%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 2.973
Data Arrival Time 7.854
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0
To rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK
1.095 0.232 tC2Q RF 17 rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/I1
1.887 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/I0
2.641 0.517 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/F
2.878 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I1
3.433 0.555 tINS FF 3 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.670 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/I0
4.187 0.517 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/F
4.424 0.237 tNET FF 2 rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/I1
4.994 0.570 tINS FR 1 rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/COUT
4.994 0.000 tNET RR 2 rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4/CIN
5.464 0.470 tINS RF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4/SUM
5.701 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n578_s5/I3
6.071 0.371 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n578_s5/F
6.308 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n578_s3/I0
6.826 0.517 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n578_s3/F
7.063 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n578_s1/I1
7.617 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n578_s1/F
7.854 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.627, 66.176%; route: 2.133, 30.506%; tC2Q: 0.232, 3.318%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 2.999
Data Arrival Time 7.829
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0
To rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK
1.095 0.232 tC2Q RF 7 rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n658_s3/I1
1.887 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_g/n658_s3/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s21/I1
2.679 0.555 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s21/F
2.916 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/I1
3.471 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/F
3.708 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19/I3
4.079 0.371 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19/F
4.316 0.237 tNET FF 2 rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/I1
4.886 0.570 tINS FR 1 rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/COUT
4.886 0.000 tNET RR 2 rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/CIN
5.356 0.470 tINS RF 2 rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/SUM
5.593 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n578_s5/I2
6.046 0.453 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n578_s5/F
6.283 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n578_s3/I0
6.800 0.517 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n578_s3/F
7.037 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n578_s1/I1
7.592 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n578_s1/F
7.829 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.601, 66.049%; route: 2.133, 30.620%; tC2Q: 0.232, 3.330%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 3.118
Data Arrival Time 7.710
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0
To rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK
1.095 0.232 tC2Q RF 5 rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1
1.887 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3
2.495 0.371 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F
2.732 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0
3.249 0.517 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F
3.486 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/I1
4.041 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/F
4.278 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n628_s1/I1
4.832 0.555 tINS FF 6 rgb2dvi_inst/TMDS8b10b_inst_r/n628_s1/F
5.069 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n628_s3/I0
5.587 0.517 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/n628_s3/F
5.824 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n654_s1/I1
6.378 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n654_s1/F
6.615 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n654_s0/I0
6.719 0.103 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n654_s0/O
6.956 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n664_s0/I0
7.473 0.517 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n664_s0/F
7.710 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.245, 61.998%; route: 2.370, 34.614%; tC2Q: 0.232, 3.388%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%