Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\VFB\data\vfb_top.v
D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\VFB\data\vfb_wrapper.vp
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18C
Created Time Thu Mar 04 17:23:41 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Video_Frame_Buffer_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 39.090MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 39.090MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 39.090MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 39.090MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 39.090MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 39.090MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.090MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 39.090MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.090MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 39.090MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 39.090MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 39.090MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.998s, Elapsed time = 0h 0m 0.995s, Peak memory usage = 54.457MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.122s, Peak memory usage = 54.457MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 54.457MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 54.457MB

Resource

Resource Usage Summary

I/O Port 238
I/O Buf 236
    IBUF 106
    OBUF 130
Register 310
    DFF 3
    DFFP 12
    DFFPE 2
    DFFC 213
    DFFCE 72
    DFFNP 8
LUT 470
    LUT2 149
    LUT3 181
    LUT4 140
ALU 88
    ALU 88
SSRAM 6
    RAM16S4 6
INV 4
    INV 4
BSRAM 8
    SDPB 1
    SDPX9B 7

Resource Utilization Summary

Logic 598(474 LUTs, 88 ALUs, 6 SSRAMs) / 20736 3%
Register 310 / 15750 2%
  --Register as Latch 0 / 15750 0%
  --Register as FF 310 / 15750 2%
BSRAM 8 / 46 17%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_vin0_clk Base 10.000 100.0 0.000 5.000 I_vin0_clk_ibuf/I
I_dma_clk Base 10.000 100.0 0.000 5.000 I_dma_clk_ibuf/I
I_vout0_clk Base 10.000 100.0 0.000 5.000 I_vout0_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_vin0_clk 100.0(MHz) 195.2(MHz) 8 TOP
2 I_dma_clk 100.0(MHz) 168.9(MHz) 9 TOP
3 I_vout0_clk 100.0(MHz) 192.6(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.079
Data Arrival Time 6.748
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s4
To vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 196 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s4/CLK
1.095 0.232 tC2Q RF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s4/Q
1.332 0.237 tNET FF 1 vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s2/I1
1.887 0.555 tINS FF 68 vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s2/F
2.124 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I2
2.577 0.453 tINS FF 5 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F
2.814 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_0_s/I1
3.384 0.570 tINS FR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_0_s/COUT
3.384 0.000 tNET RR 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_1_s/CIN
3.419 0.035 tINS RF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_1_s/COUT
3.419 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s/CIN
3.454 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s/COUT
3.454 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_3_s/CIN
3.489 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_3_s/COUT
3.489 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_4_s/CIN
3.524 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_4_s/COUT
3.524 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_5_s/CIN
3.560 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_5_s/COUT
3.560 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_6_s/CIN
3.595 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_6_s/COUT
3.595 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_7_s/CIN
3.630 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_7_s/COUT
3.630 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_8_s/CIN
3.665 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_8_s/COUT
3.665 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_9_s/CIN
4.135 0.470 tINS FF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_9_s/SUM
4.372 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_8_s0/I1
4.927 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_8_s0/F
5.164 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s2/I1
5.719 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s2/F
5.956 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/I1
6.511 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/F
6.748 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 196 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.995, 67.871%; route: 1.659, 28.187%; tC2Q: 0.232, 3.942%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.807
Data Arrival Time 6.021
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_en_s0
To vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Launch Clk I_vout0_clk[R]
Latch Clk I_vout0_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vout0_clk
0.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
0.683 0.683 tINS RR 50 I_vout0_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_en_s0/CLK
1.095 0.232 tC2Q RF 22 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_en_s0/Q
1.332 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n68_s0/I1
1.887 0.555 tINS FF 5 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n68_s0/F
2.124 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_0_s/I1
2.694 0.570 tINS FR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_0_s/COUT
2.694 0.000 tNET RR 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_1_s/CIN
2.729 0.035 tINS RF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_1_s/COUT
2.729 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s/CIN
2.764 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s/COUT
2.764 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s/CIN
2.799 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s/COUT
2.799 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_4_s/CIN
2.834 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_4_s/COUT
2.834 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s/CIN
2.870 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s/COUT
2.870 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_6_s/CIN
2.905 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_6_s/COUT
2.905 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_7_s/CIN
2.940 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_7_s/COUT
2.940 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_8_s/CIN
2.975 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_8_s/COUT
2.975 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_9_s/CIN
3.010 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_9_s/COUT
3.010 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_10_s/CIN
3.480 0.470 tINS FF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_10_s/SUM
3.717 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_8_s0/I1
4.272 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_8_s0/F
4.509 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n460_s0/I0
5.058 0.549 tINS FR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n460_s0/COUT
5.058 0.000 tNET RR 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n461_s0/CIN
5.094 0.035 tINS RF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n461_s0/COUT
5.331 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2
5.784 0.453 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F
6.021 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vout0_clk
10.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
10.682 0.683 tINS RR 50 I_vout0_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.504, 67.933%; route: 1.422, 27.569%; tC2Q: 0.232, 4.498%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 4.831
Data Arrival Time 5.996
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2
To vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_10_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 196 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/CLK
1.095 0.232 tC2Q RF 8 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/Q
1.332 0.237 tNET FF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s10/AD[0](chk_dup)
1.849 0.517 tINS FF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s10/DO[1]
2.086 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/I1
2.641 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/F
2.878 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/I1
3.433 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/F
3.670 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s1/I0
4.187 0.517 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s1/F
4.424 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0
4.972 0.549 tINS FR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT
4.972 0.000 tNET RR 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN
5.008 0.035 tINS RF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT
5.008 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN
5.043 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT
5.043 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN
5.078 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT
5.078 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN
5.113 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT
5.113 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN
5.149 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT
5.149 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN
5.184 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT
5.184 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN
5.219 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/COUT
5.219 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/CIN
5.254 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/COUT
5.254 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/CIN
5.289 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/COUT
5.289 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_10_s/CIN
5.759 0.470 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_10_s/SUM
5.996 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 196 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_10_s0/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.480, 67.782%; route: 1.422, 27.699%; tC2Q: 0.232, 4.519%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 4.866
Data Arrival Time 5.961
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2
To vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 196 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/CLK
1.095 0.232 tC2Q RF 8 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s2/Q
1.332 0.237 tNET FF 4 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s10/AD[0](chk_dup)
1.849 0.517 tINS FF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s10/DO[1]
2.086 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/I1
2.641 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_4_s1/F
2.878 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/I1
3.433 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_1_s0/F
3.670 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s1/I0
4.187 0.517 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wcount_r_0_s1/F
4.424 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/I0
4.972 0.549 tINS FR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_0_s/COUT
4.972 0.000 tNET RR 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/CIN
5.008 0.035 tINS RF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT
5.008 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN
5.043 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT
5.043 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN
5.078 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT
5.078 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN
5.113 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT
5.113 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN
5.149 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT
5.149 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN
5.184 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT
5.184 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN
5.219 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/COUT
5.219 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/CIN
5.254 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/COUT
5.254 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/CIN
5.724 0.470 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/SUM
5.961 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 196 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.445, 67.560%; route: 1.422, 27.890%; tC2Q: 0.232, 4.550%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 4.874
Data Arrival Time 5.953
Data Required Time 10.828
From vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1
To vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 196 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/CLK
1.095 0.232 tC2Q RF 19 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/Q
1.332 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n427_s1/I1
1.887 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n427_s1/F
2.124 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_0_s/I1
2.694 0.570 tINS FR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_0_s/COUT
2.694 0.000 tNET RR 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s/CIN
2.729 0.035 tINS RF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s/COUT
2.729 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s/CIN
2.764 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s/COUT
2.764 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s/CIN
2.799 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s/COUT
2.799 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s/CIN
2.834 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s/COUT
2.834 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s/CIN
2.870 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s/COUT
2.870 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s/CIN
2.905 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s/COUT
2.905 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s/CIN
2.940 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s/COUT
2.940 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s/CIN
2.975 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s/COUT
2.975 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_9_s/CIN
3.010 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_9_s/COUT
3.010 0.000 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_10_s/CIN
3.480 0.470 tINS FF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_10_s/SUM
3.717 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_9_s0/I1
4.272 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_9_s0/F
4.509 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n460_s0/I0
5.026 0.517 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n460_s0/COUT
5.263 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2
5.716 0.453 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F
5.953 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 196 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK
10.828 -0.035 tSu 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.437, 67.510%; route: 1.422, 27.933%; tC2Q: 0.232, 4.557%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%