Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\PSRAM_HS\data\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\PSRAM_HS\data\psram_code.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
Part Number | GW2AR-LV18QN88PC8/I7 |
Device | GW2AR-18C |
Created Time | Wed Mar 03 09:20:55 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | PSRAM_Memory_Interface_HS_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 33.211MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 33.211MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 33.211MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 33.211MB Optimizing Phase 2: CPU time = 0h 0m 0.124s, Elapsed time = 0h 0m 0.111s, Peak memory usage = 33.211MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 33.211MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 33.211MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 33.211MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 33.211MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.107s, Peak memory usage = 33.211MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 33.211MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 33.211MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 49.230MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.202s, Elapsed time = 0h 0m 0.217s, Peak memory usage = 49.230MB Generate netlist file: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 49.230MB |
Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 49.230MB |
Resource
Resource Usage Summary
I/O Port | 166 |
Emedded Port | 26 |
I/O Buf | 190 |
    IBUF | 99 |
    OBUF | 71 |
    IOBUF | 18 |
    ELVDS_OBUF | 2 |
Register | 516 |
    DFF | 1 |
    DFFP | 3 |
    DFFPE | 6 |
    DFFC | 290 |
    DFFCE | 216 |
LUT | 860 |
    LUT2 | 182 |
    LUT3 | 324 |
    LUT4 | 354 |
ALU | 42 |
    ALU | 42 |
INV | 6 |
    INV | 6 |
IOLOGIC | 56 |
    IDES4 | 16 |
    OSER4 | 22 |
    IODELAY | 18 |
BSRAM | 2 |
    SDPX9B | 2 |
CLOCK | 3 |
    DLL | 1 |
    CLKDIV | 1 |
    DHCEN | 1 |
Resource Utilization Summary
Logic | 908(866 LUTs, 42 ALUs) / 20736 | 4% |
Register | 516 / 15828 | 3% |
  --Register as Latch | 0 / 15828 | 0% |
  --Register as FF | 516 / 15828 | 3% |
BSRAM | 2 / 46 | 4% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
u_psram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_ibuf/I | memory_clk | u_psram_top/clkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 280.1(MHz) | 5 | TOP |
2 | u_psram_top/clkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 436.1(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.372 |
Data Arrival Time | 1.332 |
Data Required Time | 5.704 |
From | u_psram_top/u_psram_sync/cs_memsync_4_s0 |
To | u_psram_top/u_dqce_clk_x2p |
Launch Clk | clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_4_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | u_psram_top/u_psram_sync/cs_memsync_4_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_dqce_clk_x2p/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
5.924 | 0.237 | tNET | FF | 3 | u_psram_top/u_dqce_clk_x2p/CLKIN |
5.890 | -0.035 | tUnc | u_psram_top/u_dqce_clk_x2p | ||
5.704 | -0.186 | tSu | 1 | u_psram_top/u_dqce_clk_x2p |
Clock Skew: | 0.062 |
Setup Relationship: | 5.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
Required Clock Path Delay: | cell: 0.688, 74.365%; route: 0.237, 25.635% |
Path 2
Path Summary:Slack | 6.430 |
Data Arrival Time | 4.398 |
Data Required Time | 10.828 |
From | u_psram_top/u_psram_sync/lock_d2_s0 |
To | u_psram_top/u_psram_sync/count_1_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_d2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 3 | u_psram_top/u_psram_sync/lock_d2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n389_s3/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_psram_top/u_psram_sync/n389_s3/F |
2.124 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n389_s2/I1 |
2.679 | 0.555 | tINS | FF | 2 | u_psram_top/u_psram_sync/n389_s2/F |
2.916 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n388_s2/I1 |
3.471 | 0.555 | tINS | FF | 2 | u_psram_top/u_psram_sync/n388_s2/F |
3.708 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n388_s1/I2 |
4.161 | 0.453 | tINS | FF | 1 | u_psram_top/u_psram_sync/n388_s1/F |
4.398 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/count_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/count_1_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_psram_top/u_psram_sync/count_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.118, 59.915%; route: 1.185, 33.522%; tC2Q: 0.232, 6.563% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 6.512 |
Data Arrival Time | 4.316 |
Data Required Time | 10.828 |
From | u_psram_top/u_psram_sync/lock_d2_s0 |
To | u_psram_top/u_psram_sync/count_2_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/lock_d2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 3 | u_psram_top/u_psram_sync/lock_d2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n389_s3/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_psram_top/u_psram_sync/n389_s3/F |
2.124 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n389_s2/I1 |
2.679 | 0.555 | tINS | FF | 2 | u_psram_top/u_psram_sync/n389_s2/F |
2.916 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n388_s2/I1 |
3.471 | 0.555 | tINS | FF | 2 | u_psram_top/u_psram_sync/n388_s2/F |
3.708 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n387_s3/I3 |
4.079 | 0.371 | tINS | FF | 1 | u_psram_top/u_psram_sync/n387_s3/F |
4.316 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/count_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/count_2_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_psram_top/u_psram_sync/count_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.036, 58.963%; route: 1.185, 34.318%; tC2Q: 0.232, 6.719% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 6.532 |
Data Arrival Time | 4.296 |
Data Required Time | 10.828 |
From | u_psram_top/u_psram_sync/cs_memsync_5_s0 |
To | u_psram_top/u_psram_sync/cs_memsync_1_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_5_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 6 | u_psram_top/u_psram_sync/cs_memsync_5_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n304_s15/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_psram_top/u_psram_sync/n304_s15/F |
2.124 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n304_s13/I1 |
2.679 | 0.555 | tINS | FF | 3 | u_psram_top/u_psram_sync/n304_s13/F |
2.916 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n326_s13/I2 |
3.369 | 0.453 | tINS | FF | 1 | u_psram_top/u_psram_sync/n326_s13/F |
3.606 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n326_s12/I2 |
4.059 | 0.453 | tINS | FF | 1 | u_psram_top/u_psram_sync/n326_s12/F |
4.296 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/cs_memsync_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_1_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_psram_top/u_psram_sync/cs_memsync_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.016, 58.724%; route: 1.185, 34.518%; tC2Q: 0.232, 6.758% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 6.550 |
Data Arrival Time | 4.278 |
Data Required Time | 10.828 |
From | u_psram_top/u_psram_sync/cs_memsync_5_s0 |
To | u_psram_top/u_psram_sync/cs_memsync_2_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 31 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_5_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 6 | u_psram_top/u_psram_sync/cs_memsync_5_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n359_s8/I1 |
1.887 | 0.555 | tINS | FF | 7 | u_psram_top/u_psram_sync/n359_s8/F |
2.124 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n348_s13/I1 |
2.679 | 0.555 | tINS | FF | 2 | u_psram_top/u_psram_sync/n348_s13/F |
2.916 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n315_s14/I0 |
3.433 | 0.517 | tINS | FF | 1 | u_psram_top/u_psram_sync/n315_s14/F |
3.670 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/n315_s12/I3 |
4.041 | 0.371 | tINS | FF | 1 | u_psram_top/u_psram_sync/n315_s12/F |
4.278 | 0.237 | tNET | FF | 1 | u_psram_top/u_psram_sync/cs_memsync_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 31 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_psram_top/u_psram_sync/cs_memsync_2_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_psram_top/u_psram_sync/cs_memsync_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 1.998, 58.507%; route: 1.185, 34.700%; tC2Q: 0.232, 6.794% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |