Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\SCALER_LITE_DOWN\data\scaler_lite_down_top.v
D:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\SCALER_LITE_DOWN\data\scaler_core_down.vp
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18C
Created Time Fri Mar 05 15:40:51 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Scaler_Lite_Down_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 34.699MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 34.699MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 34.699MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 34.699MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 34.699MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 34.699MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 34.699MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 34.699MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 34.699MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 34.699MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 34.699MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 34.699MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.717s, Elapsed time = 0h 0m 0.723s, Peak memory usage = 50.824MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 50.824MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 50.824MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 50.824MB

Resource

Resource Usage Summary

I/O Port 70
I/O Buf 70
    IBUF 36
    OBUF 34
Register 170
    DFF 1
    DFFC 68
    DFFCE 101
LUT 273
    LUT2 16
    LUT3 170
    LUT4 87
ALU 88
    ALU 88
SSRAM 8
    RAM16S4 8
INV 2
    INV 2
BSRAM 4
    SDPB 4

Resource Utilization Summary

Logic 411(275 LUTs, 88 ALUs, 8 SSRAMs) / 20736 2%
Register 170 / 15750 1%
  --Register as Latch 0 / 15750 0%
  --Register as FF 170 / 15750 1%
BSRAM 4 / 46 9%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_vin_clk Base 10.000 100.0 0.000 5.000 I_vin_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_vin_clk 100.0(MHz) 214.1(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.330
Data Arrival Time 5.498
Data Required Time 10.828
From scaler_core_down_inst/ver_calcdata_gen_inst/vval_data1_0_s1
To scaler_core_down_inst/hor_calcdata_gen_inst/hval_data3_6_s1
Launch Clk I_vin_clk[R]
Latch Clk I_vin_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vin_clk
0.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
0.683 0.683 tINS RR 186 I_vin_clk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_down_inst/ver_calcdata_gen_inst/vval_data1_0_s1/CLK
1.095 0.232 tC2Q RF 3 scaler_core_down_inst/ver_calcdata_gen_inst/vval_data1_0_s1/Q
1.332 0.237 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_0_s/I1
1.901 0.570 tINS FR 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_0_s/COUT
1.901 0.000 tNET RR 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_1_s/CIN
1.937 0.035 tINS RF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_1_s/COUT
1.937 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_2_s/CIN
1.972 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_2_s/COUT
1.972 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_3_s/CIN
2.007 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_3_s/COUT
2.007 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_4_s/CIN
2.042 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_4_s/COUT
2.042 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_5_s/CIN
2.078 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_5_s/COUT
2.078 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_6_s/CIN
2.113 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_6_s/COUT
2.113 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_7_s/CIN
2.583 0.470 tINS FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_7_s/SUM
2.820 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n439_s6/I1
3.375 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n439_s6/F
3.612 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n439_s4/I0
3.715 0.103 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n439_s4/O
3.952 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n503_s2/I1
4.507 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n503_s2/F
4.744 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n503_s1/I0
5.261 0.517 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n503_s1/F
5.498 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data3_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vin_clk
10.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
10.682 0.683 tINS RR 186 I_vin_clk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data3_6_s1/CLK
10.828 -0.035 tSu 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data3_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.981, 64.317%; route: 1.422, 30.678%; tC2Q: 0.232, 5.005%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 5.330
Data Arrival Time 5.498
Data Required Time 10.828
From scaler_core_down_inst/ver_calcdata_gen_inst/vval_data0_0_s1
To scaler_core_down_inst/hor_calcdata_gen_inst/hval_data2_6_s1
Launch Clk I_vin_clk[R]
Latch Clk I_vin_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vin_clk
0.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
0.683 0.683 tINS RR 186 I_vin_clk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_down_inst/ver_calcdata_gen_inst/vval_data0_0_s1/CLK
1.095 0.232 tC2Q RF 4 scaler_core_down_inst/ver_calcdata_gen_inst/vval_data0_0_s1/Q
1.332 0.237 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_0_s/I1
1.901 0.570 tINS FR 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_0_s/COUT
1.901 0.000 tNET RR 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_1_s/CIN
1.937 0.035 tINS RF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_1_s/COUT
1.937 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_2_s/CIN
1.972 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_2_s/COUT
1.972 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_3_s/CIN
2.007 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_3_s/COUT
2.007 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_4_s/CIN
2.042 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_4_s/COUT
2.042 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_5_s/CIN
2.078 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_5_s/COUT
2.078 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_6_s/CIN
2.113 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_6_s/COUT
2.113 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_7_s/CIN
2.583 0.470 tINS FF 3 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_7_s/SUM
2.820 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n431_s6/I1
3.375 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n431_s6/F
3.612 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n431_s4/I0
3.715 0.103 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n431_s4/O
3.952 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n495_s2/I1
4.507 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n495_s2/F
4.744 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n495_s1/I0
5.261 0.517 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n495_s1/F
5.498 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data2_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vin_clk
10.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
10.682 0.683 tINS RR 186 I_vin_clk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data2_6_s1/CLK
10.828 -0.035 tSu 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data2_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.981, 64.317%; route: 1.422, 30.678%; tC2Q: 0.232, 5.005%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.330
Data Arrival Time 5.498
Data Required Time 10.828
From scaler_core_down_inst/hor_calcdata_gen_inst/vval_data3_d1_0_s0
To scaler_core_down_inst/hor_calcdata_gen_inst/hval_data1_6_s1
Launch Clk I_vin_clk[R]
Latch Clk I_vin_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vin_clk
0.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
0.683 0.683 tINS RR 186 I_vin_clk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_down_inst/hor_calcdata_gen_inst/vval_data3_d1_0_s0/CLK
1.095 0.232 tC2Q RF 4 scaler_core_down_inst/hor_calcdata_gen_inst/vval_data3_d1_0_s0/Q
1.332 0.237 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_0_s/I1
1.901 0.570 tINS FR 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_0_s/COUT
1.901 0.000 tNET RR 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_1_s/CIN
1.937 0.035 tINS RF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_1_s/COUT
1.937 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_2_s/CIN
1.972 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_2_s/COUT
1.972 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_3_s/CIN
2.007 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_3_s/COUT
2.007 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_4_s/CIN
2.042 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_4_s/COUT
2.042 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_5_s/CIN
2.078 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_5_s/COUT
2.078 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_6_s/CIN
2.113 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_6_s/COUT
2.113 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_7_s/CIN
2.583 0.470 tINS FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data0_7_s/SUM
2.820 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n423_s6/I1
3.375 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n423_s6/F
3.612 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n423_s4/I0
3.715 0.103 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n423_s4/O
3.952 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n487_s2/I1
4.507 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n487_s2/F
4.744 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n487_s1/I0
5.261 0.517 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n487_s1/F
5.498 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data1_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vin_clk
10.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
10.682 0.683 tINS RR 186 I_vin_clk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data1_6_s1/CLK
10.828 -0.035 tSu 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data1_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.981, 64.317%; route: 1.422, 30.678%; tC2Q: 0.232, 5.005%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.365
Data Arrival Time 5.463
Data Required Time 10.828
From scaler_core_down_inst/ver_calcdata_gen_inst/vval_data1_0_s1
To scaler_core_down_inst/hor_calcdata_gen_inst/hval_data3_5_s1
Launch Clk I_vin_clk[R]
Latch Clk I_vin_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vin_clk
0.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
0.683 0.683 tINS RR 186 I_vin_clk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_down_inst/ver_calcdata_gen_inst/vval_data1_0_s1/CLK
1.095 0.232 tC2Q RF 3 scaler_core_down_inst/ver_calcdata_gen_inst/vval_data1_0_s1/Q
1.332 0.237 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_0_s/I1
1.901 0.570 tINS FR 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_0_s/COUT
1.901 0.000 tNET RR 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_1_s/CIN
1.937 0.035 tINS RF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_1_s/COUT
1.937 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_2_s/CIN
1.972 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_2_s/COUT
1.972 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_3_s/CIN
2.007 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_3_s/COUT
2.007 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_4_s/CIN
2.042 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_4_s/COUT
2.042 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_5_s/CIN
2.078 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_5_s/COUT
2.078 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_6_s/CIN
2.548 0.470 tINS FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum2_data3_6_s/SUM
2.785 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n440_s6/I1
3.340 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n440_s6/F
3.577 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n440_s4/I0
3.680 0.103 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n440_s4/O
3.917 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n504_s2/I1
4.472 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n504_s2/F
4.709 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n504_s1/I0
5.226 0.517 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n504_s1/F
5.463 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data3_5_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vin_clk
10.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
10.682 0.683 tINS RR 186 I_vin_clk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data3_5_s1/CLK
10.828 -0.035 tSu 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data3_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.946, 64.043%; route: 1.422, 30.913%; tC2Q: 0.232, 5.043%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.365
Data Arrival Time 5.463
Data Required Time 10.828
From scaler_core_down_inst/ver_calcdata_gen_inst/vval_data0_0_s1
To scaler_core_down_inst/hor_calcdata_gen_inst/hval_data2_5_s1
Launch Clk I_vin_clk[R]
Latch Clk I_vin_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vin_clk
0.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
0.683 0.683 tINS RR 186 I_vin_clk_ibuf/O
0.863 0.180 tNET RR 1 scaler_core_down_inst/ver_calcdata_gen_inst/vval_data0_0_s1/CLK
1.095 0.232 tC2Q RF 4 scaler_core_down_inst/ver_calcdata_gen_inst/vval_data0_0_s1/Q
1.332 0.237 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_0_s/I1
1.901 0.570 tINS FR 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_0_s/COUT
1.901 0.000 tNET RR 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_1_s/CIN
1.937 0.035 tINS RF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_1_s/COUT
1.937 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_2_s/CIN
1.972 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_2_s/COUT
1.972 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_3_s/CIN
2.007 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_3_s/COUT
2.007 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_4_s/CIN
2.042 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_4_s/COUT
2.042 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_5_s/CIN
2.078 0.035 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_5_s/COUT
2.078 0.000 tNET FF 2 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_6_s/CIN
2.548 0.470 tINS FF 3 scaler_core_down_inst/hor_calcdata_gen_inst/sum1_data1_6_s/SUM
2.785 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n432_s6/I1
3.340 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n432_s6/F
3.577 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n432_s4/I0
3.680 0.103 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n432_s4/O
3.917 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n496_s2/I1
4.472 0.555 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n496_s2/F
4.709 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n496_s1/I0
5.226 0.517 tINS FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/n496_s1/F
5.463 0.237 tNET FF 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data2_5_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vin_clk
10.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
10.682 0.683 tINS RR 186 I_vin_clk_ibuf/O
10.863 0.180 tNET RR 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data2_5_s1/CLK
10.828 -0.035 tSu 1 scaler_core_down_inst/hor_calcdata_gen_inst/hval_data2_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.946, 64.043%; route: 1.422, 30.913%; tC2Q: 0.232, 5.043%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%