Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-5 |
Part Number | GW2A-LV18PG484C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Wed Sep 27 08:58:09 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DDR3_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 70.223MB Running netlist conversion: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.13s, Peak memory usage = 70.223MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.365s, Peak memory usage = 70.223MB Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.213s, Peak memory usage = 70.223MB Optimizing Phase 2: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.796s, Peak memory usage = 70.223MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.471s, Peak memory usage = 70.223MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 70.223MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.07s, Peak memory usage = 70.223MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 70.223MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.536s, Peak memory usage = 70.223MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 70.223MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 70.223MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 77.742MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.583s, Peak memory usage = 77.742MB Generate output files: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.388s, Peak memory usage = 77.742MB |
Total Time and Memory Usage | CPU time = 0h 0m 9s, Elapsed time = 0h 0m 10s, Peak memory usage = 77.742MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 370 |
I/O Buf | 364 |
    IBUF | 182 |
    OBUF | 161 |
    TBUF | 2 |
    IOBUF | 16 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 2 |
Register | 2825 |
    DFF | 101 |
    DFFE | 4 |
    DFFS | 1 |
    DFFR | 1 |
    DFFP | 54 |
    DFFPE | 9 |
    DFFC | 2200 |
    DFFCE | 455 |
LUT | 2047 |
    LUT2 | 469 |
    LUT3 | 738 |
    LUT4 | 840 |
ALU | 181 |
    ALU | 181 |
SSRAM | 113 |
    RAM16S4 | 44 |
    RAM16SDP4 | 69 |
INV | 28 |
    INV | 28 |
IOLOGIC | 76 |
    IDES8_MEM | 16 |
    OSER8 | 24 |
    OSER8_MEM | 20 |
    IODELAY | 16 |
BSRAM | 8 |
    SDPB | 4 |
    SDPX9B | 4 |
CLOCK | 4 |
    CLKDIV | 1 |
    DQS | 2 |
    DHCEN | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2934(2075 LUT, 181 ALU, 113 RAM16) / 20736 | 15% |
Register | 2825 / 16509 | 18% |
  --Register as Latch | 0 / 16509 | 0% |
  --Register as FF | 2825 / 16509 | 18% |
BSRAM | 8 / 46 | 18% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
gw3_top/u_ddr_phy_top/u_ddr_init/n1851_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw3_top/u_ddr_phy_top/u_ddr_init/n1851_s2/O | ||
gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | memory_clk | 100.0(MHz) | 1364.3(MHz) | 1 | TOP |
2 | clk | 100.0(MHz) | 237.9(MHz) | 6 | TOP |
3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.0(MHz) | 154.5(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.214 |
Data Arrival Time | 1.611 |
Data Required Time | 5.826 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.170 | 0.170 | tCL | RR | 2977 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.350 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/CLK |
0.582 | 0.232 | tC2Q | RF | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q |
0.819 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I1 |
1.375 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
1.612 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
5.924 | 0.237 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
6.110 | 0.186 | tINS | FF | 64 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
6.347 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
6.313 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
5.826 | -0.487 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | 0.997 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 2
Path Summary:Slack | 4.214 |
Data Arrival Time | 1.611 |
Data Required Time | 5.826 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.170 | 0.170 | tCL | RR | 2977 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.350 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/CLK |
0.582 | 0.232 | tC2Q | RF | 2 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_gen[0].hold_i_s0/Q |
0.819 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I1 |
1.375 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
1.612 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
5.924 | 0.237 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
6.110 | 0.186 | tINS | FF | 64 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT |
6.347 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
6.313 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
5.826 | -0.487 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | 0.997 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Arrival Data Path Delay: | cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 3
Path Summary:Slack | 4.372 |
Data Arrival Time | 1.332 |
Data Required Time | 5.704 |
From | gw3_top/u_ddr_phy_top/stop_reg_2_s0 |
To | gw3_top/u_ddr_phy_top/fclk_dhcen |
Launch Clk | clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 39 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 1 | gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/fclk_dhcen/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
5.924 | 0.237 | tNET | FF | 3 | gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN |
5.890 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/fclk_dhcen | ||
5.704 | -0.186 | tSu | 1 | gw3_top/u_ddr_phy_top/fclk_dhcen |
Clock Skew: | 0.062 |
Setup Relationship: | 5.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 5.448 |
Data Arrival Time | 34.832 |
Data Required Time | 40.281 |
From | gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0 |
To | gw3_top/u_gwmc_top/gw_cmd0/row_change_s0 |
Launch Clk | clk[R] |
Latch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
30.000 | 0.000 | clk | |||
30.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
30.683 | 0.683 | tINS | RR | 39 | clk_ibuf/O |
30.862 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK |
31.094 | 0.232 | tC2Q | RF | 2688 | gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q |
31.332 | 0.237 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init/I1 |
31.886 | 0.555 | tINS | FF | 2 | gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init/F |
32.124 | 0.237 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init/I2 |
32.576 | 0.453 | tINS | FF | 14 | gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_init/F |
32.813 | 0.237 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/I0 |
33.331 | 0.517 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/row_in_tmp[0]_ER_s27/F |
33.568 | 0.237 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n463_s0/I1 |
34.138 | 0.570 | tINS | FR | 1 | gw3_top/u_gwmc_top/gw_cmd0/n463_s0/COUT |
34.138 | 0.000 | tNET | RR | 1 | gw3_top/u_gwmc_top/gw_cmd0/n464_s0/CIN |
34.173 | 0.035 | tINS | RF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n464_s0/COUT |
34.173 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n465_s0/CIN |
34.208 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n465_s0/COUT |
34.208 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n466_s0/CIN |
34.243 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n466_s0/COUT |
34.243 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n467_s0/CIN |
34.278 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n467_s0/COUT |
34.278 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n468_s0/CIN |
34.313 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n468_s0/COUT |
34.313 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n469_s0/CIN |
34.349 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n469_s0/COUT |
34.349 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n470_s0/CIN |
34.384 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n470_s0/COUT |
34.384 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n471_s0/CIN |
34.419 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n471_s0/COUT |
34.419 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n472_s0/CIN |
34.454 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n472_s0/COUT |
34.454 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n473_s0/CIN |
34.490 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n473_s0/COUT |
34.490 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n474_s0/CIN |
34.525 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n474_s0/COUT |
34.525 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n475_s0/CIN |
34.560 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n475_s0/COUT |
34.560 | 0.000 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n476_s0/CIN |
34.595 | 0.035 | tINS | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/n476_s0/COUT |
34.832 | 0.237 | tNET | FF | 1 | gw3_top/u_gwmc_top/gw_cmd0/row_change_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
40.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
40.171 | 0.170 | tCL | RR | 2977 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
40.350 | 0.180 | tNET | RR | 1 | gw3_top/u_gwmc_top/gw_cmd0/row_change_s0/CLK |
40.315 | -0.035 | tUnc | gw3_top/u_gwmc_top/gw_cmd0/row_change_s0 | ||
40.280 | -0.035 | tSu | 1 | gw3_top/u_gwmc_top/gw_cmd0/row_change_s0 |
Clock Skew: | -0.512 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.553, 64.304%; route: 1.185, 29.852%; tC2Q: 0.232, 5.844% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 5.796 |
Data Arrival Time | 5.032 |
Data Required Time | 10.828 |
From | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0 |
To | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 39 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_4_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/I1 |
1.887 | 0.555 | tINS | FF | 3 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s16/F |
2.124 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s14/I3 |
2.495 | 0.371 | tINS | FF | 4 | gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s14/F |
2.732 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s17/I0 |
3.249 | 0.517 | tINS | FF | 2 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s17/F |
3.486 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s13/I1 |
4.041 | 0.555 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s13/F |
4.278 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s12/I0 |
4.795 | 0.517 | tINS | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/ns_memsync_5_s12/F |
5.032 | 0.237 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 39 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
10.828 | -0.035 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.515, 60.326%; route: 1.422, 34.109%; tC2Q: 0.232, 5.565% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |