Top Level Module |
Video_Frame_Buffer_Top |
Synthesis Process |
Running parser: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.446s, Peak memory usage = 41.238MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 41.238MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 41.238MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 41.238MB Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 41.238MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 41.238MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 41.238MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 41.238MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 41.238MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.07s, Peak memory usage = 41.238MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 41.238MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 41.238MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 55.855MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.178s, Peak memory usage = 55.855MB Generate output files: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.138s, Peak memory usage = 55.855MB
|
Total Time and Memory Usage |
CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 55.855MB |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_dma_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_dma_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
237 |
I_dma_clk_ibuf/O |
0.863 |
0.180 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
1.095 |
0.232 |
tC2Q |
RF |
15 |
vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
1.332 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/I1 |
1.887 |
0.555 |
tINS |
FF |
24 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/F |
2.124 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_0_s3/I1 |
2.679 |
0.555 |
tINS |
FF |
8 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_0_s3/F |
2.916 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s4/I0 |
3.433 |
0.517 |
tINS |
FF |
6 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_3_s4/F |
3.670 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s3/I1 |
4.225 |
0.555 |
tINS |
FF |
4 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s3/F |
4.462 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_3_s1/I0 |
4.979 |
0.517 |
tINS |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_3_s1/F |
5.216 |
0.237 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n703_s0/I0 |
5.765 |
0.549 |
tINS |
FR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n703_s0/COUT |
5.765 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n704_s0/CIN |
5.800 |
0.035 |
tINS |
RF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n704_s0/COUT |
5.800 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n705_s0/CIN |
5.835 |
0.035 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n705_s0/COUT |
5.835 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n706_s0/CIN |
5.870 |
0.035 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n706_s0/COUT |
5.870 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n707_s0/CIN |
5.905 |
0.035 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n707_s0/COUT |
5.905 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n708_s0/CIN |
5.941 |
0.035 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n708_s0/COUT |
6.178 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2 |
6.631 |
0.453 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F |
6.868 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_vout0_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_vout0_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
119 |
I_vout0_clk_ibuf/O |
0.863 |
0.180 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/CLK |
1.095 |
0.232 |
tC2Q |
RF |
66 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/Q |
1.332 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s5/I1 |
1.887 |
0.555 |
tINS |
FF |
8 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s5/F |
2.124 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s4/I1 |
2.679 |
0.555 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s4/F |
2.916 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s3/I2 |
3.369 |
0.453 |
tINS |
FF |
3 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s3/F |
3.606 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s0/I1 |
4.161 |
0.555 |
tINS |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_2_s0/F |
4.398 |
0.237 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n648_s0/I0 |
4.946 |
0.549 |
tINS |
FR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n648_s0/COUT |
4.946 |
0.000 |
tNET |
RR |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n649_s0/CIN |
4.982 |
0.035 |
tINS |
RF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n649_s0/COUT |
4.982 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n650_s0/CIN |
5.017 |
0.035 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n650_s0/COUT |
5.017 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n651_s0/CIN |
5.052 |
0.035 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n651_s0/COUT |
5.052 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n652_s0/CIN |
5.087 |
0.035 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n652_s0/COUT |
5.087 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n653_s0/CIN |
5.123 |
0.035 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n653_s0/COUT |
5.123 |
0.000 |
tNET |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n654_s0/CIN |
5.158 |
0.035 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n654_s0/COUT |
5.395 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2 |
5.848 |
0.453 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F |
6.085 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_dma_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_dma_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
237 |
I_dma_clk_ibuf/O |
0.863 |
0.180 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLK |
1.095 |
0.232 |
tC2Q |
RF |
3 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/Q |
1.332 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I1 |
1.887 |
0.555 |
tINS |
FF |
138 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F |
2.124 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s1/I1 |
2.679 |
0.555 |
tINS |
FF |
7 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s1/F |
2.916 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s6/I1 |
3.471 |
0.555 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s6/F |
3.708 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s2/I1 |
4.263 |
0.555 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s2/F |
4.500 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/I1 |
5.055 |
0.555 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/F |
5.292 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_dma_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_dma_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
237 |
I_dma_clk_ibuf/O |
0.863 |
0.180 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1/CLK |
1.095 |
0.232 |
tC2Q |
RF |
4 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1/Q |
1.332 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n220_s3/I1 |
1.887 |
0.555 |
tINS |
FF |
7 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n220_s3/F |
2.124 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n211_s3/I1 |
2.679 |
0.555 |
tINS |
FF |
4 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n211_s3/F |
2.916 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n206_s3/I1 |
3.471 |
0.555 |
tINS |
FF |
5 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n206_s3/F |
3.708 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n203_s4/I0 |
4.225 |
0.517 |
tINS |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n203_s4/F |
4.462 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n202_s2/I1 |
5.016 |
0.555 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/n202_s2/F |
5.253 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_25_s1/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
I_dma_clk |
0.000 |
0.000 |
tCL |
RR |
1 |
I_dma_clk_ibuf/I |
0.683 |
0.683 |
tINS |
RR |
237 |
I_dma_clk_ibuf/O |
0.863 |
0.180 |
tNET |
RR |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_5_s1/CLK |
1.095 |
0.232 |
tC2Q |
RF |
4 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_5_s1/Q |
1.332 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n341_s3/I1 |
1.887 |
0.555 |
tINS |
FF |
7 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n341_s3/F |
2.124 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n332_s3/I1 |
2.679 |
0.555 |
tINS |
FF |
4 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n332_s3/F |
2.916 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n327_s3/I1 |
3.471 |
0.555 |
tINS |
FF |
5 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n327_s3/F |
3.708 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n324_s4/I0 |
4.225 |
0.517 |
tINS |
FF |
2 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n324_s4/F |
4.462 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n323_s2/I1 |
5.016 |
0.555 |
tINS |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n323_s2/F |
5.253 |
0.237 |
tNET |
FF |
1 |
vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_25_s1/D |