Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\impl\gwsynthesis\scaler_ref_design_live.vg
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\scaler_test_top.cst
Timing Constraint File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\scaler_ref_design_live.sdc
Version V1.9.9 Beta-6
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Mon Oct 30 16:12:50 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C C8/I7
Hold Delay Model Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed 14787
Numbers of Endpoints Analyzed 15149
Numbers of Falling Endpoints 14
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
dma_clk Base 13.333 75.002 0.000 6.667 dma_clk
I_clk Base 20.000 50.000 0.000 10.000 I_clk
memory_clk Base 3.333 300.030 0.000 1.667 memory_clk
O_adv7513_clk Base 9.259 108.003 0.000 4.630 O_adv7513_clk O_adv7513_clk_d
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 9.286 107.692 0.000 4.643 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTP
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 18.571 53.846 0.000 9.286 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTD
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 27.857 35.897 0.000 13.929 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTD3
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 3.333 300.000 0.000 1.667 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTP
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 6.667 150.000 0.000 3.333 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTD
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 10.000 100.000 0.000 5.000 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 dma_clk 75.002(MHz) 114.418(MHz) 9 TOP
2 I_clk 50.000(MHz) 151.912(MHz) 4 TOP
3 memory_clk 300.030(MHz) 2016.129(MHz) 1 TOP
4 O_adv7513_clk 108.003(MHz) 152.790(MHz) 5 TOP

No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
dma_clk Setup 0.000 0
dma_clk Hold 0.000 0
I_clk Setup 0.000 0
I_clk Hold 0.000 0
memory_clk Setup 0.000 0
memory_clk Hold 0.000 0
O_adv7513_clk Setup 0.000 0
O_adv7513_clk Hold 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.714 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[0] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_16_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 9.259 0.000 6.510
2 2.724 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[3] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_19_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 9.259 0.000 6.500
3 2.747 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_de_32b_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 9.259 0.000 6.477
4 2.783 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[0] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_0_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 9.259 0.000 6.441
5 2.800 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[1] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_17_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 9.259 0.000 6.424
6 2.810 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[15] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_23_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 9.259 0.000 6.414
7 2.835 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[6] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_6_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 9.259 0.000 6.389
8 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
9 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
10 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
11 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
12 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
13 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
14 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
15 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
16 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
17 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
18 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
19 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
20 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
21 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
22 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
23 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
24 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
25 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.074 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.323
2 0.074 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_21_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[21] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.323
3 0.074 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.323
4 0.074 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_7_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[7] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.323
5 0.074 vlb_top_inst/fifo_wr_data_23_s0/Q vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[5] I_clk:[R] I_clk:[R] 0.000 0.000 0.323
6 0.074 vlb_top_inst/fifo_wr_data_11_s0/Q vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/DI[2] I_clk:[R] I_clk:[R] 0.000 0.000 0.323
7 0.076 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.325
8 0.076 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[0] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.325
9 0.076 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_6_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[6] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.325
10 0.079 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_4_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[4] I_clk:[R] I_clk:[R] 0.000 0.000 0.328
11 0.080 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_0_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[0] I_clk:[R] I_clk:[R] 0.000 0.000 0.329
12 0.080 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_7_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[7] I_clk:[R] I_clk:[R] 0.000 0.000 0.329
13 0.083 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_1_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[1] I_clk:[R] I_clk:[R] 0.000 0.000 0.332
14 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[22] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
15 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[17] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
16 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[31] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
17 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_60_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[28] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
18 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[24] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
19 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
20 0.201 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata0_4_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_0/DI[4] I_clk:[R] I_clk:[R] 0.000 0.000 0.450
21 0.202 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[2] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.451
22 0.202 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[16] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.451
23 0.202 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[4] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.451
24 0.202 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[0] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.451
25 0.213 vlb_top_inst/fifo_wr_data_22_s0/Q vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[4] I_clk:[R] I_clk:[R] 0.000 0.000 0.462

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.817 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.356
2 1.817 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.356
3 1.817 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.356
4 1.817 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.356
5 2.204 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_2_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.372
6 2.204 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.372
7 2.204 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_5_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.372
8 2.204 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_8_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.372
9 2.204 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_3_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.372
10 2.204 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_5_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.372
11 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
12 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/PRESET O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
13 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
14 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_6_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
15 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
16 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
17 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
18 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
19 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_7_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
20 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_8_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
21 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_9_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
22 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_9_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
23 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_0_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
24 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364
25 2.212 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 4.629 0.018 2.364

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
2 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_5_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
3 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
4 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
5 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
6 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
7 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
8 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_5_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
9 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
10 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
11 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
12 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
13 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_4_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
14 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
15 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
16 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
17 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
18 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
19 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
20 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
21 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
22 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
23 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
24 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_4_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368
25 1.357 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_5_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.368

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk Pout_hs_dn_4_s0
2 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk Pout_hs_dn_3_s0
3 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk Pout_vs_dn_3_s0
4 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk syn_gen_inst/H_cnt_9_s0
5 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk syn_gen_inst/H_cnt_8_s0
6 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk syn_gen_inst/H_cnt_7_s0
7 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk syn_gen_inst/V_cnt_9_s1
8 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk syn_gen_inst/V_cnt_1_s1
9 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_0_s0
10 3.552 4.552 1.000 Low Pulse Width O_adv7513_clk Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.714
Data Arrival Time 6.753
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_16_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 32 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
2.503 2.260 tC2Q RF 1 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[0]
3.673 1.170 tNET FF 1 R14C32[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n114_s7/I0
4.044 0.371 tINS FF 1 R14C32[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n114_s7/F
4.607 0.563 tNET FF 1 R14C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n114_s5/I3
5.060 0.453 tINS FF 2 R14C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n114_s5/F
5.479 0.419 tNET FF 1 R15C36[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n106_s5/I0
5.932 0.453 tINS FF 2 R15C36[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n106_s5/F
6.183 0.252 tNET FF 1 R15C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n106_s3/I1
6.753 0.570 tINS FR 1 R15C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n106_s3/F
6.753 0.000 tNET RR 1 R15C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R15C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_16_s0/CLK
9.467 -0.035 tSu 1 R15C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9.259
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.847, 28.372%; route: 2.403, 36.912%; tC2Q: 2.260, 34.716%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack 2.724
Data Arrival Time 6.744
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_19_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 32 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
2.503 2.260 tC2Q RF 1 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[3]
3.458 0.955 tNET FF 1 R14C32[3][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n111_s7/I1
3.829 0.371 tINS FF 1 R14C32[3][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n111_s7/F
4.728 0.899 tNET FF 1 R14C35[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n111_s5/I3
5.277 0.549 tINS FR 2 R14C35[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n111_s5/F
5.451 0.174 tNET RR 1 R14C36[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n103_s5/I0
6.021 0.570 tINS RR 2 R14C36[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n103_s5/F
6.195 0.174 tNET RR 1 R14C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n103_s3/I1
6.744 0.549 tINS RR 1 R14C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n103_s3/F
6.744 0.000 tNET RR 1 R14C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R14C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_19_s0/CLK
9.467 -0.035 tSu 1 R14C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9.259
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 2.039, 31.368%; route: 2.201, 33.864%; tC2Q: 2.260, 34.768%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack 2.747
Data Arrival Time 6.721
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_de_32b_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_de_32b_s0/CLK
0.475 0.232 tC2Q RF 22 R14C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_de_32b_s0/Q
1.392 0.916 tNET FF 1 R17C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s5/I3
1.763 0.371 tINS FF 8 R17C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s5/F
2.196 0.433 tNET FF 1 R17C38[3][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s4/I1
2.766 0.570 tINS FR 1 R17C38[3][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_3_s4/F
2.767 0.001 tNET RR 1 R17C38[3][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s3/I2
3.316 0.549 tINS RR 3 R17C38[3][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s3/F
3.493 0.177 tNET RR 1 R18C38[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_3_s0/I0
4.048 0.555 tINS RF 2 R18C38[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_3_s0/F
4.709 0.660 tNET FF 2 R20C35[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n649_s0/I0
5.258 0.549 tINS FR 1 R20C35[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n649_s0/COUT
5.258 0.000 tNET RR 2 R20C35[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n650_s0/CIN
5.293 0.035 tINS RF 1 R20C35[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n650_s0/COUT
5.293 0.000 tNET FF 2 R20C35[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n651_s0/CIN
5.328 0.035 tINS FF 1 R20C35[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n651_s0/COUT
5.328 0.000 tNET FF 2 R20C36[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n652_s0/CIN
5.363 0.035 tINS FF 1 R20C36[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n652_s0/COUT
5.363 0.000 tNET FF 2 R20C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n653_s0/CIN
5.398 0.035 tINS FF 1 R20C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n653_s0/COUT
5.398 0.000 tNET FF 2 R20C36[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n654_s0/CIN
5.434 0.035 tINS FF 1 R20C36[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n654_s0/COUT
6.151 0.717 tNET FF 1 R18C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2
6.721 0.570 tINS FR 1 R18C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F
6.721 0.000 tNET RR 1 R18C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R18C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK
9.467 -0.035 tSu 1 R18C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9.259
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.340, 51.563%; route: 2.905, 44.855%; tC2Q: 0.232, 3.582%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack 2.783
Data Arrival Time 6.685
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_0_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 32 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
2.503 2.260 tC2Q RF 1 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[0]
3.673 1.170 tNET FF 1 R14C32[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n114_s7/I0
4.044 0.371 tINS FF 1 R14C32[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n114_s7/F
4.607 0.563 tNET FF 1 R14C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n114_s5/I3
5.060 0.453 tINS FF 2 R14C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n114_s5/F
5.479 0.419 tNET FF 1 R15C36[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n106_s5/I0
5.941 0.462 tINS FR 2 R15C36[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n106_s5/F
6.115 0.174 tNET RR 1 R15C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n122_s4/I0
6.685 0.570 tINS RR 1 R15C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n122_s4/F
6.685 0.000 tNET RR 1 R15C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R15C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_0_s0/CLK
9.467 -0.035 tSu 1 R15C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9.259
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.856, 28.814%; route: 2.325, 36.099%; tC2Q: 2.260, 35.086%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack 2.800
Data Arrival Time 6.667
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_17_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 32 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
2.503 2.260 tC2Q RF 1 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[1]
3.382 0.878 tNET FF 1 R14C32[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n113_s7/I1
3.899 0.517 tINS FF 1 R14C32[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n113_s7/F
4.312 0.413 tNET FF 1 R14C35[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n113_s5/I3
4.829 0.517 tINS FF 2 R14C35[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n113_s5/F
5.248 0.419 tNET FF 1 R15C37[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n105_s5/I0
5.701 0.453 tINS FF 2 R15C37[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n105_s5/F
6.118 0.418 tNET FF 1 R14C39[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n105_s3/I1
6.667 0.549 tINS FR 1 R14C39[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n105_s3/F
6.667 0.000 tNET RR 1 R14C39[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R14C39[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_17_s0/CLK
9.467 -0.035 tSu 1 R14C39[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9.259
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 2.036, 31.694%; route: 2.128, 33.124%; tC2Q: 2.260, 35.181%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack 2.810
Data Arrival Time 6.657
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_23_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 32 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
2.503 2.260 tC2Q RF 1 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[15]
3.442 0.939 tNET FF 1 R16C32[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/fifo_rd_data_b_15_s0/I0
3.997 0.555 tINS FF 1 R16C32[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/fifo_rd_data_b_15_s0/F
4.410 0.413 tNET FF 1 R15C34[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/fifo_rd_data_b_15_s/I3
4.927 0.517 tINS FF 3 R15C34[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/fifo_rd_data_b_15_s/F
5.345 0.418 tNET FF 1 R16C36[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n99_s4/I1
5.915 0.570 tINS FR 1 R16C36[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n99_s4/F
6.087 0.172 tNET RR 1 R16C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n99_s3/I0
6.657 0.570 tINS RR 1 R16C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n99_s3/F
6.657 0.000 tNET RR 1 R16C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R16C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_23_s0/CLK
9.467 -0.035 tSu 1 R16C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_23_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9.259
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 2.212, 34.487%; route: 1.942, 30.277%; tC2Q: 2.260, 35.236%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack 2.835
Data Arrival Time 6.632
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_6_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 32 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
2.503 2.260 tC2Q RF 1 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/DO[6]
3.458 0.955 tNET FF 1 R14C32[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n108_s7/I0
3.911 0.453 tINS FF 1 R14C32[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n108_s7/F
4.308 0.397 tNET FF 1 R14C34[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n108_s5/I3
4.857 0.549 tINS FR 2 R14C34[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n108_s5/F
5.031 0.174 tNET RR 1 R15C34[3][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n100_s5/I0
5.402 0.371 tINS RF 2 R15C34[3][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n100_s5/F
6.062 0.660 tNET FF 1 R15C39[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n116_s4/I0
6.632 0.570 tINS FR 1 R15C39[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/n116_s4/F
6.632 0.000 tNET RR 1 R15C39[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R15C39[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_6_s0/CLK
9.467 -0.035 tSu 1 R15C39[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_d_24b_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9.259
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.943, 30.412%; route: 2.186, 34.215%; tC2Q: 2.260, 35.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path9

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path10

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path11

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path12

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path13

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path14

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path15

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path16

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path17

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path18

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path19

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path20

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path21

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path22

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path23

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path24

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path25

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 63 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.074
Data Arrival Time 0.507
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R27C8[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/CLK
0.385 0.201 tC2Q RF 1 R27C8[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q
0.507 0.122 tNET FF 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack 0.074
Data Arrival Time 0.507
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_21_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C3[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_21_s0/CLK
0.385 0.201 tC2Q RF 1 R29C3[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_21_s0/Q
0.507 0.122 tNET FF 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[21]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack 0.074
Data Arrival Time 0.507
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C3[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/CLK
0.385 0.201 tC2Q RF 1 R29C3[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q
0.507 0.122 tNET FF 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack 0.074
Data Arrival Time 0.507
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_7_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C2[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_7_s0/CLK
0.385 0.201 tC2Q RF 1 R29C2[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_7_s0/Q
0.507 0.122 tNET FF 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack 0.074
Data Arrival Time 1.183
Data Required Time 1.109
From vlb_top_inst/fifo_wr_data_23_s0
To vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R11C50[2][B] vlb_top_inst/fifo_wr_data_23_s0/CLK
1.061 0.201 tC2Q RF 1 R11C50[2][B] vlb_top_inst/fifo_wr_data_23_s0/Q
1.183 0.122 tNET FF 1 BSRAM_R10[15] vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[15] vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA
1.109 0.249 tHld 1 BSRAM_R10[15] vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack 0.074
Data Arrival Time 1.183
Data Required Time 1.109
From vlb_top_inst/fifo_wr_data_11_s0
To vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R11C47[1][B] vlb_top_inst/fifo_wr_data_11_s0/CLK
1.061 0.201 tC2Q RF 1 R11C47[1][B] vlb_top_inst/fifo_wr_data_11_s0/Q
1.183 0.122 tNET FF 1 BSRAM_R10[14] vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[14] vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKA
1.109 0.249 tHld 1 BSRAM_R10[14] vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack 0.076
Data Arrival Time 0.509
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R27C8[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/CLK
0.386 0.202 tC2Q RR 1 R27C8[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q
0.509 0.123 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack 0.076
Data Arrival Time 0.509
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R27C8[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/CLK
0.386 0.202 tC2Q RR 1 R27C8[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/Q
0.509 0.123 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack 0.076
Data Arrival Time 0.509
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_6_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C2[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_6_s0/CLK
0.386 0.202 tC2Q RR 1 R30C2[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_6_s0/Q
0.509 0.123 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack 0.079
Data Arrival Time 1.187
Data Required Time 1.109
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_4_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R47C35[2][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_4_s0/CLK
1.062 0.202 tC2Q RR 4 R47C35[2][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_4_s0/Q
1.187 0.126 tNET RR 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/CLKA
1.109 0.249 tHld 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 38.352%; tC2Q: 0.202, 61.648%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack 0.080
Data Arrival Time 1.189
Data Required Time 1.109
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_0_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R45C35[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_0_s0/CLK
1.062 0.202 tC2Q RR 4 R45C35[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_0_s0/Q
1.189 0.127 tNET RR 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/CLKA
1.109 0.249 tHld 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.127, 38.581%; tC2Q: 0.202, 61.419%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack 0.080
Data Arrival Time 1.189
Data Required Time 1.109
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_7_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R47C35[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_7_s0/CLK
1.061 0.201 tC2Q RF 4 R47C35[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_7_s0/Q
1.189 0.128 tNET FF 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/CLKA
1.109 0.249 tHld 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.990%; tC2Q: 0.201, 61.010%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack 0.083
Data Arrival Time 1.192
Data Required Time 1.109
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_1_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R45C35[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_1_s0/CLK
1.061 0.201 tC2Q RF 4 R45C35[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_1_s0/Q
1.192 0.131 tNET FF 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/CLKA
1.109 0.249 tHld 1 BSRAM_R46[10] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.131, 39.420%; tC2Q: 0.201, 60.580%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C7[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/CLK
0.386 0.202 tC2Q RR 1 R26C7[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[22]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C8[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/CLK
0.386 0.202 tC2Q RR 1 R26C8[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[17]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C5[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0/CLK
0.386 0.202 tC2Q RR 1 R30C5[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_63_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[31]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_60_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C5[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_60_s0/CLK
0.386 0.202 tC2Q RR 1 R30C5[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_60_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[28]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C5[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0/CLK
0.386 0.202 tC2Q RR 1 R30C5[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_56_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[24]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R31C2[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/CLK
0.386 0.202 tC2Q RR 1 R31C2[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack 0.201
Data Arrival Time 1.309
Data Required Time 1.109
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata0_4_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R48C34[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata0_4_s0/CLK
1.062 0.202 tC2Q RR 4 R48C34[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata0_4_s0/Q
1.309 0.248 tNET RR 1 BSRAM_R46[9] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_0/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R46[9] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_0/CLKA
1.109 0.249 tHld 1 BSRAM_R46[9] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.248, 55.078%; tC2Q: 0.202, 44.922%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack 0.202
Data Arrival Time 0.635
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R27C8[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0/CLK
0.386 0.202 tC2Q RR 1 R27C8[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_2_s0/Q
0.635 0.249 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path22

Path Summary:

Slack 0.202
Data Arrival Time 0.635
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C3[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/CLK
0.386 0.202 tC2Q RR 1 R29C3[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q
0.635 0.249 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[16]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack 0.202
Data Arrival Time 0.635
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C2[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/CLK
0.386 0.202 tC2Q RR 1 R30C2[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_4_s0/Q
0.635 0.249 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack 0.202
Data Arrival Time 0.635
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C2[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/CLK
0.386 0.202 tC2Q RR 1 R30C2[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/Q
0.635 0.249 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path25

Path Summary:

Slack 0.213
Data Arrival Time 1.322
Data Required Time 1.109
From vlb_top_inst/fifo_wr_data_22_s0
To vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R11C51[2][B] vlb_top_inst/fifo_wr_data_22_s0/CLK
1.062 0.202 tC2Q RR 1 R11C51[2][B] vlb_top_inst/fifo_wr_data_22_s0/Q
1.322 0.260 tNET RR 1 BSRAM_R10[15] vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 1797 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R10[15] vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA
1.109 0.249 tHld 1 BSRAM_R10[15] vlb_top_inst/fifo_read_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.817
Data Arrival Time 7.247
Data Required Time 9.064
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.247 2.124 tNET FF 32 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
9.064 -0.438 tSu 1 BSRAM_R28[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.124, 90.152%; tC2Q: 0.232, 9.848%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack 1.817
Data Arrival Time 7.247
Data Required Time 9.064
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.247 2.124 tNET FF 32 BSRAM_R10[10] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 BSRAM_R10[10] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/CLKB
9.064 -0.438 tSu 1 BSRAM_R10[10] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.124, 90.152%; tC2Q: 0.232, 9.848%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack 1.817
Data Arrival Time 7.247
Data Required Time 9.064
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.247 2.124 tNET FF 32 BSRAM_R10[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 BSRAM_R10[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/CLKB
9.064 -0.438 tSu 1 BSRAM_R10[8] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.124, 90.152%; tC2Q: 0.232, 9.848%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack 1.817
Data Arrival Time 7.247
Data Required Time 9.064
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.247 2.124 tNET FF 32 BSRAM_R10[9] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 BSRAM_R10[9] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB
9.064 -0.438 tSu 1 BSRAM_R10[9] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.124, 90.152%; tC2Q: 0.232, 9.848%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack 2.204
Data Arrival Time 7.263
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_2_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.263 2.140 tNET FF 1 R17C37[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R17C37[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_2_s0/CLK
9.467 -0.035 tSu 1 R17C37[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_2_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.140, 90.218%; tC2Q: 0.232, 9.782%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack 2.204
Data Arrival Time 7.263
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.263 2.140 tNET FF 1 R17C38[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R17C38[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0/CLK
9.467 -0.035 tSu 1 R17C38[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.140, 90.218%; tC2Q: 0.232, 9.782%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack 2.204
Data Arrival Time 7.263
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_5_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.263 2.140 tNET FF 1 R17C38[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R17C38[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_5_s0/CLK
9.467 -0.035 tSu 1 R17C38[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_5_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.140, 90.218%; tC2Q: 0.232, 9.782%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack 2.204
Data Arrival Time 7.263
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_8_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.263 2.140 tNET FF 1 R17C37[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R17C37[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_8_s0/CLK
9.467 -0.035 tSu 1 R17C37[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_8_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.140, 90.218%; tC2Q: 0.232, 9.782%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack 2.204
Data Arrival Time 7.263
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_3_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.263 2.140 tNET FF 1 R17C37[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R17C37[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_3_s0/CLK
9.467 -0.035 tSu 1 R17C37[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_3_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.140, 90.218%; tC2Q: 0.232, 9.782%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack 2.204
Data Arrival Time 7.263
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_5_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.263 2.140 tNET FF 1 R17C38[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R17C38[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_5_s0/CLK
9.467 -0.035 tSu 1 R17C38[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_5_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.140, 90.218%; tC2Q: 0.232, 9.782%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R18C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R18C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0/CLK
9.467 -0.035 tSu 1 R18C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R18C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R18C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK
9.467 -0.035 tSu 1 R18C36[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R20C33[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R20C33[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1/CLK
9.467 -0.035 tSu 1 R20C33[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_6_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R17C36[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R17C36[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_6_s1/CLK
9.467 -0.035 tSu 1 R17C36[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_6_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R20C33[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R20C33[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1/CLK
9.467 -0.035 tSu 1 R20C33[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R20C33[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R20C33[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1/CLK
9.467 -0.035 tSu 1 R20C33[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R21C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R21C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1/CLK
9.467 -0.035 tSu 1 R21C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R21C35[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R21C35[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1/CLK
9.467 -0.035 tSu 1 R21C35[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_7_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R20C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R20C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_7_s1/CLK
9.467 -0.035 tSu 1 R20C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_7_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_8_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R20C38[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R20C38[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_8_s1/CLK
9.467 -0.035 tSu 1 R20C38[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_8_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_9_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R18C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R18C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_9_s1/CLK
9.467 -0.035 tSu 1 R18C35[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_9_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_9_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R18C35[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R18C35[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_9_s1/CLK
9.467 -0.035 tSu 1 R18C35[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_9_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_0_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R16C35[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R16C35[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_0_s0/CLK
9.467 -0.035 tSu 1 R16C35[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_0_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R16C35[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R16C35[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/CLK
9.467 -0.035 tSu 1 R16C35[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack 2.212
Data Arrival Time 7.255
Data Required Time 9.467
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
4.630 4.630 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF 1 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
5.123 0.232 tC2Q FF 55 R16C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
7.255 2.132 tNET FF 1 R18C38[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9.259 9.259 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR 165 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
9.502 0.243 tNET RR 1 R18C38[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0/CLK
9.467 -0.035 tSu 1 R18C38[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 4.629
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.132, 90.185%; tC2Q: 0.232, 9.815%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R31C15[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R31C15[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0/CLK
0.195 0.011 tHld 1 R31C15[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_Empty_reg_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_5_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R33C14[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C14[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_5_s0/CLK
0.195 0.011 tHld 1 R33C14[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq1_wptr_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R31C13[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R31C13[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0/CLK
0.195 0.011 tHld 1 R31C13[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R30C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0/CLK
0.195 0.011 tHld 1 R30C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R32C13[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C13[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0/CLK
0.195 0.011 tHld 1 R32C13[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path6

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R33C13[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C13[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0/CLK
0.195 0.011 tHld 1 R33C13[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path7

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R32C13[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C13[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0/CLK
0.195 0.011 tHld 1 R32C13[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_5_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R33C13[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C13[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_5_s0/CLK
0.195 0.011 tHld 1 R33C13[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wbin_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R30C13[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C13[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0/CLK
0.195 0.011 tHld 1 R30C13[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R32C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0/CLK
0.195 0.011 tHld 1 R32C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R33C13[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C13[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0/CLK
0.195 0.011 tHld 1 R33C13[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R32C13[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C13[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0/CLK
0.195 0.011 tHld 1 R32C13[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_4_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R33C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_4_s0/CLK
0.195 0.011 tHld 1 R33C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_wptr_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R30C14[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C14[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0/CLK
0.195 0.011 tHld 1 R30C14[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R30C14[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C14[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0/CLK
0.195 0.011 tHld 1 R30C14[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R30C14[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C14[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0/CLK
0.195 0.011 tHld 1 R30C14[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R31C15[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R31C15[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0/CLK
0.195 0.011 tHld 1 R31C15[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R30C15[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C15[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0/CLK
0.195 0.011 tHld 1 R30C15[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R31C15[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R31C15[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0/CLK
0.195 0.011 tHld 1 R31C15[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rbin_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R31C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R31C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0/CLK
0.195 0.011 tHld 1 R31C13[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path21

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R32C14[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C14[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0/CLK
0.195 0.011 tHld 1 R32C14[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path22

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R31C13[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R31C13[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0/CLK
0.195 0.011 tHld 1 R31C13[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R32C14[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C14[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0/CLK
0.195 0.011 tHld 1 R32C14[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_4_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R33C14[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C14[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_4_s0/CLK
0.195 0.011 tHld 1 R33C14[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path25

Path Summary:

Slack 1.357
Data Arrival Time 1.552
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_5_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C26[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.058 0.235 tINS RR 60 R36C19[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.552 0.494 tNET RR 1 R32C14[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C14[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_5_s0/CLK
0.195 0.011 tHld 1 R32C14[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[0].fifo_ctrl/if_rq2_wptr_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.235, 17.184%; route: 0.931, 68.046%; tC2Q: 0.202, 14.771%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Pout_hs_dn_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF Pout_hs_dn_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR Pout_hs_dn_4_s0/CLK

MPW2

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Pout_hs_dn_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF Pout_hs_dn_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR Pout_hs_dn_3_s0/CLK

MPW3

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Pout_vs_dn_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF Pout_vs_dn_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR Pout_vs_dn_3_s0/CLK

MPW4

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: syn_gen_inst/H_cnt_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF syn_gen_inst/H_cnt_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR syn_gen_inst/H_cnt_9_s0/CLK

MPW5

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: syn_gen_inst/H_cnt_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF syn_gen_inst/H_cnt_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR syn_gen_inst/H_cnt_8_s0/CLK

MPW6

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: syn_gen_inst/H_cnt_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF syn_gen_inst/H_cnt_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR syn_gen_inst/H_cnt_7_s0/CLK

MPW7

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: syn_gen_inst/V_cnt_9_s1

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF syn_gen_inst/V_cnt_9_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR syn_gen_inst/V_cnt_9_s1/CLK

MPW8

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: syn_gen_inst/V_cnt_1_s1

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF syn_gen_inst/V_cnt_1_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR syn_gen_inst/V_cnt_1_s1/CLK

MPW9

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_0_s0/CLK

MPW10

MPW Summary:

Slack: 3.552
Actual Width: 4.552
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
4.630 0.000 active clock edge time
4.630 0.000 O_adv7513_clk
4.630 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
4.891 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
9.259 0.000 active clock edge time
9.259 0.000 O_adv7513_clk
9.259 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
9.443 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
3192 dma_clk 4.593 0.261
1797 I_clk_d 7.426 0.261
266 n14_11 9.097 1.583
198 eye_calib_start_r 7.076 1.958
192 hfifo_objrpt[0] 16.476 1.417
165 O_adv7513_clk_d 2.714 0.427
155 next_state.ST_IFF0_WRITE_DDR 6.563 1.725
149 dqsts1 10.968 1.376
148 dqs_reg 10.752 1.322
144 n28_3 10.001 1.508

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R32C41 90.28%
R12C18 88.89%
R22C19 87.50%
R29C2 87.50%
R45C35 87.50%
R7C50 86.11%
R13C17 86.11%
R22C21 86.11%
R38C38 86.11%
R39C50 86.11%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name dma_clk -period 13.333 -waveform {0 6.667} [get_nets {dma_clk}] -add
TC_CLOCK Actived create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add
TC_CLOCK Actived create_clock -name memory_clk -period 3.333 -waveform {0 1.667} [get_nets {memory_clk}] -add
TC_CLOCK Actived create_clock -name O_adv7513_clk -period 9.259 -waveform {0 4.63} [get_ports {O_adv7513_clk}] -add
TC_FALSE_PATH Actived set_false_path -from [get_clocks {O_adv7513_clk}] -to [get_clocks {dma_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {dma_clk}] -to [get_clocks {O_adv7513_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {dma_clk}] -group [get_clocks {I_clk}] -group [get_clocks {memory_clk}]