Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\SCALER\data\scaler_wrapper.v
C:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\SCALER\data\static_macro_define.v
C:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\SCALER\data\scaler_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-6
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Mon Oct 30 16:11:14 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Scaler_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.43s, Peak memory usage = 45.090MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 45.090MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 45.090MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 45.090MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 45.090MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 45.090MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 45.090MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 45.090MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 45.090MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 45.090MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 45.090MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 45.090MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 59.867MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 59.867MB
Generate output files:
    CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 59.867MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 59.867MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 181
I/O Buf 181
    IBUF 130
    OBUF 51
Register 1056
    DFF 27
    DFFR 3
    DFFC 250
    DFFCE 776
LUT 874
    LUT2 156
    LUT3 400
    LUT4 318
ALU 360
    ALU 360
SSRAM 7
    RAM16S4 5
    RAM16SDP1 2
INV 32
    INV 32
DSP
    MULT18X18 12
BSRAM 12
    SDPB 12

Resource Utilization Summary

Resource Usage Utilization
Logic 1308(906 LUT, 360 ALU, 7 RAM16) / 20736 7%
Register 1056 / 16509 7%
  --Register as Latch 0 / 16509 0%
  --Register as FF 1056 / 16509 7%
BSRAM 12 / 46 27%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_vin_clk Base 10.000 100.0 0.000 5.000 I_vin_clk_ibuf/I
I_sysclk Base 10.000 100.0 0.000 5.000 I_sysclk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_vin_clk 100.0(MHz) 224.0(MHz) 6 TOP
2 I_sysclk 100.0(MHz) 194.5(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.858
Data Arrival Time 5.970
Data Required Time 10.828
From scaler_wrapper_inst/scaler_core_inst/vout_vsize_sysclk_1_s0
To scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/framevsdone_s1
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 1011 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/vout_vsize_sysclk_1_s0/CLK
1.095 0.232 tC2Q RF 5 scaler_wrapper_inst/scaler_core_inst/vout_vsize_sysclk_1_s0/Q
1.332 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s36/I1
1.887 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s36/F
2.124 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s28/I1
2.679 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s28/F
2.916 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s14/I1
3.471 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s14/F
3.708 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s6/I0
4.225 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s6/F
4.462 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s3/I0
4.979 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s3/F
5.216 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s2/I0
5.733 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/n255_s2/F
5.970 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/framevsdone_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 1011 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/framevsdone_s1/CLK
10.828 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_coord_trans_inst/framevsdone_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.216, 62.972%; route: 1.659, 32.485%; tC2Q: 0.232, 4.543%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.858
Data Arrival Time 5.970
Data Required Time 10.828
From scaler_wrapper_inst/scaler_core_inst/vin_hsize_sysclk_1_s0
To scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_rightedge_s0
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 1011 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/vin_hsize_sysclk_1_s0/CLK
1.095 0.232 tC2Q RF 6 scaler_wrapper_inst/scaler_core_inst/vin_hsize_sysclk_1_s0/Q
1.332 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s35/I1
1.887 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s35/F
2.124 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s25/I1
2.679 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s25/F
2.916 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s15/I1
3.471 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s15/F
3.708 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s6/I0
4.225 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s6/F
4.462 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s2/I0
4.979 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s2/F
5.216 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s1/I0
5.733 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n301_s1/F
5.970 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_rightedge_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 1011 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_rightedge_s0/CLK
10.828 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_rightedge_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.216, 62.972%; route: 1.659, 32.485%; tC2Q: 0.232, 4.543%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 4.884
Data Arrival Time 5.944
Data Required Time 10.828
From scaler_wrapper_inst/scaler_core_inst/vout_hsize_sysclk_2_s0
To scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framededone_s1
Launch Clk I_sysclk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_sysclk
0.000 0.000 tCL RR 1 I_sysclk_ibuf/I
0.683 0.683 tINS RR 1011 I_sysclk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/vout_hsize_sysclk_2_s0/CLK
1.095 0.232 tC2Q RF 6 scaler_wrapper_inst/scaler_core_inst/vout_hsize_sysclk_2_s0/Q
1.332 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s31/I1
1.887 0.555 tINS FF 5 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s31/F
2.124 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s34/I1
2.679 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s34/F
2.916 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s26/I2
3.369 0.453 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s26/F
3.606 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s11/I1
4.161 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s11/F
4.398 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s4/I0
4.915 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s4/F
5.152 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s2/I1
5.707 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/n262_s2/F
5.944 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framededone_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 1011 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framededone_s1/CLK
10.828 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framededone_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.190, 62.783%; route: 1.659, 32.651%; tC2Q: 0.232, 4.566%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 4.989
Data Arrival Time 5.804
Data Required Time 10.793
From scaler_wrapper_inst/scaler_core_inst/vin_vsize_vinclk_5_s0
To scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_8_s0
Launch Clk I_vin_clk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vin_clk
0.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
0.683 0.683 tINS RR 88 I_vin_clk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/vin_vsize_vinclk_5_s0/CLK
1.095 0.232 tC2Q RF 5 scaler_wrapper_inst/scaler_core_inst/vin_vsize_vinclk_5_s0/Q
1.332 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s72/I1
1.887 0.555 tINS FF 3 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s72/F
2.124 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s63/I1
2.679 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s63/F
2.916 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s57/I2
3.369 0.453 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s57/F
3.606 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s55/I0
4.123 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s55/F
4.360 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s54/I0
4.877 0.517 tINS FF 24 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s54/F
5.114 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n945_s35/I2
5.567 0.453 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n945_s35/F
5.804 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 1011 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_8_s0/CLK
10.828 -0.035 tUnc scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_8_s0
10.793 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.050, 61.729%; route: 1.659, 33.576%; tC2Q: 0.232, 4.695%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 4.989
Data Arrival Time 5.804
Data Required Time 10.793
From scaler_wrapper_inst/scaler_core_inst/vin_vsize_vinclk_5_s0
To scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_9_s0
Launch Clk I_vin_clk[R]
Latch Clk I_sysclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vin_clk
0.000 0.000 tCL RR 1 I_vin_clk_ibuf/I
0.683 0.683 tINS RR 88 I_vin_clk_ibuf/O
0.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/vin_vsize_vinclk_5_s0/CLK
1.095 0.232 tC2Q RF 5 scaler_wrapper_inst/scaler_core_inst/vin_vsize_vinclk_5_s0/Q
1.332 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s72/I1
1.887 0.555 tINS FF 3 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s72/F
2.124 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s63/I1
2.679 0.555 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s63/F
2.916 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s57/I2
3.369 0.453 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s57/F
3.606 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s55/I0
4.123 0.517 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s55/F
4.360 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s54/I0
4.877 0.517 tINS FF 24 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n628_s54/F
5.114 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n944_s35/I2
5.567 0.453 tINS FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/n944_s35/F
5.804 0.237 tNET FF 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_sysclk
10.000 0.000 tCL RR 1 I_sysclk_ibuf/I
10.682 0.683 tINS RR 1011 I_sysclk_ibuf/O
10.863 0.180 tNET RR 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_9_s0/CLK
10.828 -0.035 tUnc scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_9_s0
10.793 -0.035 tSu 1 scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data2_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.050, 61.729%; route: 1.659, 33.576%; tC2Q: 0.232, 4.695%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%