Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\proj\Gowin_Scaler_Live_RefDesign\project\src\line_buffer\fifo_top\fifo_top\temp\FIFO\fifo_define.v D:\proj\Gowin_Scaler_Live_RefDesign\project\src\line_buffer\fifo_top\fifo_top\temp\FIFO\fifo_parameter.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\FIFO\data\edc.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\FIFO\data\fifo.v D:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\FIFO\data\fifo_top.v |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.8.01 |
Part Number | GW2A-LV18PG484C8/I7 |
Device | GW2A-18C |
Created Time | Fri Nov 12 09:23:37 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | fifo_read |
Synthesis Process | Running parser: CPU time = 0h 0m 0.561s, Elapsed time = 0h 0m 0.831s, Peak memory usage = 55.348MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 55.348MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 55.348MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 55.348MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 55.348MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 55.348MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 55.348MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 55.348MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 55.348MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 55.348MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 55.348MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 55.348MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.202s, Elapsed time = 0h 0m 0.201s, Peak memory usage = 60.824MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 60.824MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 60.824MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.823s, Elapsed time = 0h 0m 1s, Peak memory usage = 60.824MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 55 |
I/O Buf | 55 |
    IBUF | 29 |
    OBUF | 26 |
Register | 79 |
    DFF | 1 |
    DFFP | 1 |
    DFFC | 71 |
    DFFCE | 2 |
    DFFNP | 4 |
LUT | 48 |
    LUT2 | 24 |
    LUT3 | 18 |
    LUT4 | 6 |
ALU | 35 |
    ALU | 35 |
SSRAM | 3 |
    RAM16S4 | 3 |
INV | 1 |
    INV | 1 |
BSRAM | 3 |
    SDPX9B | 3 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 102(49 LUTs, 35 ALUs, 3 SSRAMs) / 20736 | 1% |
Register | 79 / 16509 | 1% |
  --Register as Latch | 0 / 16509 | 0% |
  --Register as FF | 79 / 16509 | 1% |
BSRAM | 3 / 46 | 7% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
RdClk | Base | 10.000 | 100.0 | 0.000 | 5.000 | RdClk_ibuf/I | ||
WrClk | Base | 10.000 | 100.0 | 0.000 | 5.000 | WrClk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | RdClk | 100.0(MHz) | 194.0(MHz) | 9 | TOP |
2 | WrClk | 100.0(MHz) | 192.8(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.813 |
Data Arrival Time | 6.015 |
Data Required Time | 10.828 |
From | fifo_inst/Full_s0 |
To | fifo_inst/Full_s0 |
Launch Clk | WrClk[R] |
Latch Clk | WrClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | WrClk | |||
0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
0.683 | 0.683 | tINS | RR | 53 | WrClk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | fifo_inst/Full_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | fifo_inst/n30_s1/I0 |
1.849 | 0.517 | tINS | FF | 4 | fifo_inst/n30_s1/F |
2.086 | 0.237 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_0_s/I1 |
2.655 | 0.570 | tINS | FR | 1 | fifo_inst/Equal.wbinnext_0_s/COUT |
2.655 | 0.000 | tNET | RR | 2 | fifo_inst/Equal.wbinnext_1_s/CIN |
2.691 | 0.035 | tINS | RF | 1 | fifo_inst/Equal.wbinnext_1_s/COUT |
2.691 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_2_s/CIN |
2.726 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_2_s/COUT |
2.726 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_3_s/CIN |
2.761 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_3_s/COUT |
2.761 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_4_s/CIN |
2.796 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_4_s/COUT |
2.796 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_5_s/CIN |
2.832 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_5_s/COUT |
2.832 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_6_s/CIN |
2.867 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_6_s/COUT |
2.867 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_7_s/CIN |
2.902 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_7_s/COUT |
2.902 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_8_s/CIN |
2.937 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_8_s/COUT |
2.937 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_9_s/CIN |
2.972 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_9_s/COUT |
2.972 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_10_s/CIN |
3.008 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_10_s/COUT |
3.008 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_11_s/CIN |
3.478 | 0.470 | tINS | FF | 3 | fifo_inst/Equal.wbinnext_11_s/SUM |
3.715 | 0.237 | tNET | FF | 1 | fifo_inst/wfull_val_s5/I1 |
4.270 | 0.555 | tINS | FF | 1 | fifo_inst/wfull_val_s5/F |
4.507 | 0.237 | tNET | FF | 1 | fifo_inst/wfull_val_s1/I0 |
5.024 | 0.517 | tINS | FF | 1 | fifo_inst/wfull_val_s1/F |
5.261 | 0.237 | tNET | FF | 1 | fifo_inst/wfull_val_s0/I0 |
5.778 | 0.517 | tINS | FF | 1 | fifo_inst/wfull_val_s0/F |
6.015 | 0.237 | tNET | FF | 1 | fifo_inst/Full_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | WrClk | |||
10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
10.682 | 0.683 | tINS | RR | 53 | WrClk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK |
10.828 | -0.035 | tSu | 1 | fifo_inst/Full_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.498, 67.896%; route: 1.422, 27.601%; tC2Q: 0.232, 4.503% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 4.845 |
Data Arrival Time | 5.983 |
Data Required Time | 10.828 |
From | fifo_inst/Empty_s0 |
To | fifo_inst/Empty_s0 |
Launch Clk | RdClk[R] |
Latch Clk | RdClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | RdClk | |||
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
0.683 | 0.683 | tINS | RR | 35 | RdClk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | fifo_inst/Empty_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | fifo_inst/n34_s0/I0 |
1.849 | 0.517 | tINS | FF | 4 | fifo_inst/n34_s0/F |
2.086 | 0.237 | tNET | FF | 2 | fifo_inst/rbin_num_next_0_s/I1 |
2.655 | 0.570 | tINS | FR | 1 | fifo_inst/rbin_num_next_0_s/COUT |
2.655 | 0.000 | tNET | RR | 2 | fifo_inst/rbin_num_next_1_s/CIN |
2.691 | 0.035 | tINS | RF | 1 | fifo_inst/rbin_num_next_1_s/COUT |
2.691 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_2_s/CIN |
2.726 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_2_s/COUT |
2.726 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_3_s/CIN |
2.761 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_3_s/COUT |
2.761 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_4_s/CIN |
2.796 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_4_s/COUT |
2.796 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_5_s/CIN |
2.832 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_5_s/COUT |
2.832 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_6_s/CIN |
2.867 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_6_s/COUT |
2.867 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_7_s/CIN |
2.902 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_7_s/COUT |
2.902 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_8_s/CIN |
2.937 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_8_s/COUT |
2.937 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_9_s/CIN |
2.972 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_9_s/COUT |
2.972 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_10_s/CIN |
3.442 | 0.470 | tINS | FF | 3 | fifo_inst/rbin_num_next_10_s/SUM |
3.679 | 0.237 | tNET | FF | 1 | fifo_inst/Equal.rgraynext_9_s0/I1 |
4.234 | 0.555 | tINS | FF | 2 | fifo_inst/Equal.rgraynext_9_s0/F |
4.471 | 0.237 | tNET | FF | 2 | fifo_inst/n178_s0/I0 |
5.020 | 0.549 | tINS | FR | 1 | fifo_inst/n178_s0/COUT |
5.020 | 0.000 | tNET | RR | 2 | fifo_inst/n179_s0/CIN |
5.056 | 0.035 | tINS | RF | 1 | fifo_inst/n179_s0/COUT |
5.293 | 0.237 | tNET | FF | 1 | fifo_inst/rempty_val_s1/I2 |
5.746 | 0.453 | tINS | FF | 1 | fifo_inst/rempty_val_s1/F |
5.983 | 0.237 | tNET | FF | 1 | fifo_inst/Empty_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | RdClk | |||
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
10.682 | 0.683 | tINS | RR | 35 | RdClk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
10.828 | -0.035 | tSu | 1 | fifo_inst/Empty_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.466, 67.696%; route: 1.422, 27.773%; tC2Q: 0.232, 4.531% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 6.321 |
Data Arrival Time | 4.507 |
Data Required Time | 10.828 |
From | fifo_inst/Full_s0 |
To | fifo_inst/Equal.wptr_10_s0 |
Launch Clk | WrClk[R] |
Latch Clk | WrClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | WrClk | |||
0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
0.683 | 0.683 | tINS | RR | 53 | WrClk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | fifo_inst/Full_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | fifo_inst/n30_s1/I0 |
1.849 | 0.517 | tINS | FF | 4 | fifo_inst/n30_s1/F |
2.086 | 0.237 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_0_s/I1 |
2.655 | 0.570 | tINS | FR | 1 | fifo_inst/Equal.wbinnext_0_s/COUT |
2.655 | 0.000 | tNET | RR | 2 | fifo_inst/Equal.wbinnext_1_s/CIN |
2.691 | 0.035 | tINS | RF | 1 | fifo_inst/Equal.wbinnext_1_s/COUT |
2.691 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_2_s/CIN |
2.726 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_2_s/COUT |
2.726 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_3_s/CIN |
2.761 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_3_s/COUT |
2.761 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_4_s/CIN |
2.796 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_4_s/COUT |
2.796 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_5_s/CIN |
2.832 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_5_s/COUT |
2.832 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_6_s/CIN |
2.867 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_6_s/COUT |
2.867 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_7_s/CIN |
2.902 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_7_s/COUT |
2.902 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_8_s/CIN |
2.937 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_8_s/COUT |
2.937 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_9_s/CIN |
2.972 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_9_s/COUT |
2.972 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_10_s/CIN |
3.008 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_10_s/COUT |
3.008 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_11_s/CIN |
3.478 | 0.470 | tINS | FF | 3 | fifo_inst/Equal.wbinnext_11_s/SUM |
3.715 | 0.237 | tNET | FF | 1 | fifo_inst/Equal.wgraynext_10_s0/I1 |
4.270 | 0.555 | tINS | FF | 1 | fifo_inst/Equal.wgraynext_10_s0/F |
4.507 | 0.237 | tNET | FF | 1 | fifo_inst/Equal.wptr_10_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | WrClk | |||
10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
10.682 | 0.683 | tINS | RR | 53 | WrClk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wptr_10_s0/CLK |
10.828 | -0.035 | tSu | 1 | fifo_inst/Equal.wptr_10_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.464, 67.618%; route: 0.948, 26.015%; tC2Q: 0.232, 6.367% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 6.321 |
Data Arrival Time | 4.507 |
Data Required Time | 10.828 |
From | fifo_inst/Empty_s0 |
To | fifo_inst/Equal.rptr_10_s0 |
Launch Clk | RdClk[R] |
Latch Clk | RdClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | RdClk | |||
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
0.683 | 0.683 | tINS | RR | 35 | RdClk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | fifo_inst/Empty_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | fifo_inst/n34_s0/I0 |
1.849 | 0.517 | tINS | FF | 4 | fifo_inst/n34_s0/F |
2.086 | 0.237 | tNET | FF | 2 | fifo_inst/rbin_num_next_0_s/I1 |
2.655 | 0.570 | tINS | FR | 1 | fifo_inst/rbin_num_next_0_s/COUT |
2.655 | 0.000 | tNET | RR | 2 | fifo_inst/rbin_num_next_1_s/CIN |
2.691 | 0.035 | tINS | RF | 1 | fifo_inst/rbin_num_next_1_s/COUT |
2.691 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_2_s/CIN |
2.726 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_2_s/COUT |
2.726 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_3_s/CIN |
2.761 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_3_s/COUT |
2.761 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_4_s/CIN |
2.796 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_4_s/COUT |
2.796 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_5_s/CIN |
2.832 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_5_s/COUT |
2.832 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_6_s/CIN |
2.867 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_6_s/COUT |
2.867 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_7_s/CIN |
2.902 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_7_s/COUT |
2.902 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_8_s/CIN |
2.937 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_8_s/COUT |
2.937 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_9_s/CIN |
2.972 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_9_s/COUT |
2.972 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_10_s/CIN |
3.008 | 0.035 | tINS | FF | 1 | fifo_inst/rbin_num_next_10_s/COUT |
3.008 | 0.000 | tNET | FF | 2 | fifo_inst/rbin_num_next_11_s/CIN |
3.478 | 0.470 | tINS | FF | 3 | fifo_inst/rbin_num_next_11_s/SUM |
3.715 | 0.237 | tNET | FF | 1 | fifo_inst/Equal.rgraynext_10_s0/I1 |
4.270 | 0.555 | tINS | FF | 2 | fifo_inst/Equal.rgraynext_10_s0/F |
4.507 | 0.237 | tNET | FF | 1 | fifo_inst/Equal.rptr_10_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | RdClk | |||
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
10.682 | 0.683 | tINS | RR | 35 | RdClk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rptr_10_s0/CLK |
10.828 | -0.035 | tSu | 1 | fifo_inst/Equal.rptr_10_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.464, 67.618%; route: 0.948, 26.015%; tC2Q: 0.232, 6.367% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 6.356 |
Data Arrival Time | 4.471 |
Data Required Time | 10.828 |
From | fifo_inst/Full_s0 |
To | fifo_inst/Equal.wptr_9_s0 |
Launch Clk | WrClk[R] |
Latch Clk | WrClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | WrClk | |||
0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
0.683 | 0.683 | tINS | RR | 53 | WrClk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 2 | fifo_inst/Full_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | fifo_inst/n30_s1/I0 |
1.849 | 0.517 | tINS | FF | 4 | fifo_inst/n30_s1/F |
2.086 | 0.237 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_0_s/I1 |
2.655 | 0.570 | tINS | FR | 1 | fifo_inst/Equal.wbinnext_0_s/COUT |
2.655 | 0.000 | tNET | RR | 2 | fifo_inst/Equal.wbinnext_1_s/CIN |
2.691 | 0.035 | tINS | RF | 1 | fifo_inst/Equal.wbinnext_1_s/COUT |
2.691 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_2_s/CIN |
2.726 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_2_s/COUT |
2.726 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_3_s/CIN |
2.761 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_3_s/COUT |
2.761 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_4_s/CIN |
2.796 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_4_s/COUT |
2.796 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_5_s/CIN |
2.832 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_5_s/COUT |
2.832 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_6_s/CIN |
2.867 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_6_s/COUT |
2.867 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_7_s/CIN |
2.902 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_7_s/COUT |
2.902 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_8_s/CIN |
2.937 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_8_s/COUT |
2.937 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_9_s/CIN |
2.972 | 0.035 | tINS | FF | 1 | fifo_inst/Equal.wbinnext_9_s/COUT |
2.972 | 0.000 | tNET | FF | 2 | fifo_inst/Equal.wbinnext_10_s/CIN |
3.442 | 0.470 | tINS | FF | 4 | fifo_inst/Equal.wbinnext_10_s/SUM |
3.679 | 0.237 | tNET | FF | 1 | fifo_inst/Equal.wgraynext_9_s0/I1 |
4.234 | 0.555 | tINS | FF | 2 | fifo_inst/Equal.wgraynext_9_s0/F |
4.471 | 0.237 | tNET | FF | 1 | fifo_inst/Equal.wptr_9_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | WrClk | |||
10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
10.682 | 0.683 | tINS | RR | 53 | WrClk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wptr_9_s0/CLK |
10.828 | -0.035 | tSu | 1 | fifo_inst/Equal.wptr_9_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.429, 67.302%; route: 0.948, 26.269%; tC2Q: 0.232, 6.429% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |