Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\Gowin_Scaler_Memory_RefDesign\project\impl\gwsynthesis\scaler_ref_design_memory.vg
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\Gowin_Scaler_Memory_RefDesign\project\src\scaler_test_top.cst
Timing Constraint File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\Gowin_Scaler_Memory_RefDesign\project\src\scaler_ref_design_memory.sdc
Version V1.9.9 Beta-6
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Tue Oct 31 13:47:14 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C C8/I7
Hold Delay Model Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed 14614
Numbers of Endpoints Analyzed 14952
Numbers of Falling Endpoints 8
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk_x4i Base 3.333 300.030 0.000 1.667 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/clk_x4i
I_clk Base 20.000 50.000 0.000 10.000 I_clk
O_adv7513_clk Base 7.246 138.007 0.000 3.623 O_adv7513_clk O_adv7513_clk_d
dma_clk Base 13.333 75.002 0.000 6.667 dma_clk
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 7.222 138.462 0.000 3.611 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTP
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 14.444 69.231 0.000 7.222 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTD
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 21.667 46.154 0.000 10.833 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTD3
ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk Generated 3.333 300.000 0.000 1.667 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUT
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 3.333 300.000 0.000 1.667 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTP
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 6.667 150.000 0.000 3.333 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTD
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 10.000 100.000 0.000 5.000 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_x4i 300.030(MHz) 2016.129(MHz) 1 TOP
2 I_clk 50.000(MHz) 176.699(MHz) 5 TOP
3 O_adv7513_clk 138.007(MHz) 142.905(MHz) 4 TOP
4 dma_clk 75.002(MHz) 96.027(MHz) 9 TOP

No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk_x4i Setup 0.000 0
clk_x4i Hold 0.000 0
I_clk Setup 0.000 0
I_clk Hold 0.000 0
O_adv7513_clk Setup 0.000 0
O_adv7513_clk Hold 0.000 0
dma_clk Setup 0.000 0
dma_clk Hold 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.248 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_52_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.963
2 0.248 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.963
3 0.250 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_44_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.961
4 0.282 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_51_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.929
5 0.289 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_48_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.922
6 0.289 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_49_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.922
7 0.289 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_51_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.922
8 0.289 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_53_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.922
9 0.296 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_49_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.915
10 0.315 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_de_32b_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.896
11 0.319 Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/Q Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_11_s1/D O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.892
12 0.340 Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/Q Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_10_s1/D O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.871
13 0.346 Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/Q Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_3_s1/D O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.865
14 0.388 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_62_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.823
15 0.392 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.819
16 0.394 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_54_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.817
17 0.416 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_53_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.795
18 0.421 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_59_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.790
19 0.421 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_59_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.790
20 0.421 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_60_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.790
21 0.421 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_61_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.790
22 0.424 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_43_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.787
23 0.424 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_45_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.787
24 0.425 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_58_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.786
25 0.439 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_54_s1/CE O_adv7513_clk:[R] O_adv7513_clk:[R] 7.246 0.000 6.772

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_47_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[15] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
2 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_35_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[3] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
3 0.204 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_0_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1/DI[0] O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.453
4 0.211 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/ADA[7] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
5 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[23] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
6 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_53_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[21] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
7 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_48_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[16] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
8 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_7_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[7] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
9 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_6_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[6] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
10 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[0] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
11 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_23_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[23] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
12 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[22] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
13 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
14 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[19] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
15 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[17] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
16 0.215 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_6_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[6] O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.464
17 0.216 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_3_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1/DI[3] O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.465
18 0.217 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_0_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[0] O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.466
19 0.219 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_7_s0/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[7] O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.468
20 0.222 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wraddr_0_s3/Q Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1/ADA[3] O_adv7513_clk:[R] O_adv7513_clk:[R] 0.000 0.000 0.340
21 0.225 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_29_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s/DI[5] I_clk:[R] I_clk:[R] 0.000 0.000 0.474
22 0.225 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.474
23 0.225 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[19] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.474
24 0.225 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_47_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[15] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.474
25 0.225 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[13] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.474

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.159 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.008
2 1.159 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.008
3 1.159 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.008
4 1.159 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.008
5 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
6 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
7 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_3_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
8 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_7_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
9 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_8_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
10 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
11 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_2_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
12 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
13 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
14 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
15 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_6_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
16 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
17 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
18 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
19 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
20 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
21 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_5_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
22 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_6_s1/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
23 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
24 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024
25 1.546 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_7_s0/CLEAR O_adv7513_clk:[F] O_adv7513_clk:[R] 3.623 0.018 2.024

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.406 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.417
2 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/sda_chk_s3/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
3 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SDA_OEN_s1/PRESET I_clk:[R] I_clk:[R] 0.000 0.000 1.533
4 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SCL_OEN_s1/PRESET I_clk:[R] I_clk:[R] 0.000 0.000 1.533
5 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_0_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
6 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_1_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
7 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_2_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
8 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_3_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
9 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_4_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
10 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_5_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
11 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_6_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
12 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_7_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
13 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_8_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
14 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_9_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
15 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_10_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
16 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_11_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
17 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_12_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
18 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_13_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
19 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_14_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
20 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_15_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
21 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_16_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
22 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_0_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
23 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_1_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
24 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_2_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533
25 1.522 key_debounceN_inst0/key_n_out1_s1/Q I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_3_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.533

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Pout_hs_dn_24_s0
2 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hres_10_s0
3 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1
4 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vout_vsize_sysclk_7_s0
5 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ky_23_s0
6 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ky_7_s0
7 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d1_s0
8 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s6
9 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/state_1_s0
10 2.546 3.546 1.000 Low Pulse Width O_adv7513_clk Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/state_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.248
Data Arrival Time 7.206
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_52_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.206 0.944 tNET RR 1 R21C39[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_52_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R21C39[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_52_s1/CLK
7.454 -0.035 tSu 1 R21C39[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_52_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 20.940%; route: 5.273, 75.728%; tC2Q: 0.232, 3.332%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack 0.248
Data Arrival Time 7.206
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.206 0.944 tNET RR 1 R24C39[2][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R24C39[2][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s1/CLK
7.454 -0.035 tSu 1 R24C39[2][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 20.940%; route: 5.273, 75.728%; tC2Q: 0.232, 3.332%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack 0.250
Data Arrival Time 7.205
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_44_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s3/I3
6.262 0.570 tINS FR 24 R31C44[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s3/F
7.205 0.943 tNET RR 1 R22C38[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_44_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R22C38[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_44_s1/CLK
7.454 -0.035 tSu 1 R22C38[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_44_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 20.944%; route: 5.271, 75.723%; tC2Q: 0.232, 3.333%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack 0.282
Data Arrival Time 7.172
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_51_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.172 0.911 tNET RR 1 R21C41[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_51_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R21C41[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_51_s1/CLK
7.454 -0.035 tSu 1 R21C41[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_51_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.043%; route: 5.239, 75.609%; tC2Q: 0.232, 3.348%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack 0.289
Data Arrival Time 7.165
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_48_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.165 0.904 tNET RR 1 R26C46[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_48_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R26C46[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_48_s1/CLK
7.454 -0.035 tSu 1 R26C46[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_48_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.063%; route: 5.232, 75.585%; tC2Q: 0.232, 3.352%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack 0.289
Data Arrival Time 7.165
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_49_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.165 0.904 tNET RR 1 R26C46[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_49_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R26C46[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_49_s1/CLK
7.454 -0.035 tSu 1 R26C46[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_49_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.063%; route: 5.232, 75.585%; tC2Q: 0.232, 3.352%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack 0.289
Data Arrival Time 7.165
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_51_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.165 0.904 tNET RR 1 R24C41[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_51_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R24C41[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_51_s1/CLK
7.454 -0.035 tSu 1 R24C41[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_51_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.064%; route: 5.232, 75.584%; tC2Q: 0.232, 3.352%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack 0.289
Data Arrival Time 7.165
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_53_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.165 0.904 tNET RR 1 R26C43[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_53_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R26C43[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_53_s1/CLK
7.454 -0.035 tSu 1 R26C43[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_53_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.064%; route: 5.232, 75.584%; tC2Q: 0.232, 3.352%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack 0.296
Data Arrival Time 7.159
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_49_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.159 0.897 tNET RR 1 R22C42[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_49_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R22C42[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_49_s1/CLK
7.454 -0.035 tSu 1 R22C42[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_49_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.084%; route: 5.225, 75.562%; tC2Q: 0.232, 3.355%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack 0.315
Data Arrival Time 7.140
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_de_32b_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R34C36[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_de_32b_s0/CLK
0.475 0.232 tC2Q RF 22 R34C36[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_24b/dma_de_32b_s0/Q
1.260 0.785 tNET FF 1 R40C34[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s5/I3
1.631 0.371 tINS FF 8 R40C34[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s5/F
2.079 0.448 tNET FF 1 R40C36[3][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_6_s4/I0
2.649 0.570 tINS FR 2 R40C36[3][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_6_s4/F
2.825 0.176 tNET RR 1 R40C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_6_s2/I1
3.380 0.555 tINS RF 6 R40C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_6_s2/F
3.815 0.435 tNET FF 1 R39C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_7_s0/I1
4.370 0.555 tINS FF 2 R39C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_7_s0/F
5.030 0.660 tNET FF 2 R42C39[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n653_s0/I0
5.579 0.549 tINS FR 1 R42C39[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n653_s0/COUT
5.579 0.000 tNET RR 2 R42C39[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n654_s0/CIN
5.615 0.035 tINS RF 1 R42C39[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n654_s0/COUT
6.769 1.154 tNET FF 1 R41C34[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2
7.140 0.371 tINS FF 1 R41C34[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F
7.140 0.000 tNET FF 1 R41C34[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R41C34[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK
7.454 -0.035 tSu 1 R41C34[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.006, 43.592%; route: 3.658, 53.044%; tC2Q: 0.232, 3.364%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack 0.319
Data Arrival Time 7.135
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1
To Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_11_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R29C30[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/CLK
0.475 0.232 tC2Q RF 5 R29C30[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/Q
1.408 0.932 tNET FF 2 R22C31[2][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n362_s28/I1
1.779 0.371 tINS FF 1 R22C31[2][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n362_s28/COUT
2.419 0.640 tNET FF 1 R22C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n441_s17/I2
2.974 0.555 tINS FF 2 R22C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n441_s17/F
3.634 0.660 tNET FF 1 R27C30[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s11/I2
4.183 0.549 tINS FR 1 R27C30[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s11/F
4.185 0.001 tNET RR 1 R27C30[3][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s8/I2
4.734 0.549 tINS RR 1 R27C30[3][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s8/F
4.735 0.001 tNET RR 1 R27C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s6/I1
5.188 0.453 tINS RF 1 R27C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s6/F
5.585 0.397 tNET FF 1 R29C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s3/I2
6.102 0.517 tINS FF 13 R29C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s3/F
6.565 0.463 tNET FF 1 R27C31[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n391_s2/I0
7.135 0.570 tINS FR 1 R27C31[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n391_s2/F
7.135 0.000 tNET RR 1 R27C31[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R27C31[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_11_s1/CLK
7.454 -0.035 tSu 1 R27C31[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.564, 51.713%; route: 3.096, 44.921%; tC2Q: 0.232, 3.366%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack 0.340
Data Arrival Time 7.114
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1
To Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_10_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R29C30[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/CLK
0.475 0.232 tC2Q RF 5 R29C30[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/Q
1.408 0.932 tNET FF 2 R22C31[2][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n362_s28/I1
1.779 0.371 tINS FF 1 R22C31[2][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n362_s28/COUT
2.419 0.640 tNET FF 1 R22C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n441_s17/I2
2.974 0.555 tINS FF 2 R22C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n441_s17/F
3.634 0.660 tNET FF 1 R27C30[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s11/I2
4.183 0.549 tINS FR 1 R27C30[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s11/F
4.185 0.001 tNET RR 1 R27C30[3][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s8/I2
4.734 0.549 tINS RR 1 R27C30[3][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s8/F
4.735 0.001 tNET RR 1 R27C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s6/I1
5.188 0.453 tINS RF 1 R27C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s6/F
5.585 0.397 tNET FF 1 R29C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s3/I2
6.102 0.517 tINS FF 13 R29C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s3/F
6.565 0.463 tNET FF 1 R27C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n392_s2/I0
7.114 0.549 tINS FR 1 R27C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n392_s2/F
7.114 0.000 tNET RR 1 R27C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R27C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_10_s1/CLK
7.454 -0.035 tSu 1 R27C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.543, 51.565%; route: 3.096, 45.058%; tC2Q: 0.232, 3.377%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack 0.346
Data Arrival Time 7.108
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1
To Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_3_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R29C30[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/CLK
0.475 0.232 tC2Q RF 5 R29C30[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_4_s1/Q
1.408 0.932 tNET FF 2 R22C31[2][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n362_s28/I1
1.779 0.371 tINS FF 1 R22C31[2][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n362_s28/COUT
2.419 0.640 tNET FF 1 R22C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n441_s17/I2
2.974 0.555 tINS FF 2 R22C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n441_s17/F
3.634 0.660 tNET FF 1 R27C30[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s11/I2
4.183 0.549 tINS FR 1 R27C30[2][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s11/F
4.185 0.001 tNET RR 1 R27C30[3][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s8/I2
4.734 0.549 tINS RR 1 R27C30[3][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s8/F
4.735 0.001 tNET RR 1 R27C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s6/I1
5.188 0.453 tINS RF 1 R27C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s6/F
5.585 0.397 tNET FF 1 R29C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s3/I2
6.102 0.517 tINS FF 13 R29C30[3][B] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n402_s3/F
6.559 0.458 tNET FF 1 R30C31[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n399_s2/I0
7.108 0.549 tINS FR 1 R30C31[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/n399_s2/F
7.108 0.000 tNET RR 1 R30C31[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R30C31[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_3_s1/CLK
7.454 -0.035 tSu 1 R30C31[1][A] Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.543, 51.608%; route: 3.090, 45.012%; tC2Q: 0.232, 3.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack 0.388
Data Arrival Time 7.067
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_62_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/F
7.067 0.805 tNET RR 1 R23C38[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_62_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R23C38[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_62_s1/CLK
7.454 -0.035 tSu 1 R23C38[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_62_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.368%; route: 5.133, 75.232%; tC2Q: 0.232, 3.400%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack 0.392
Data Arrival Time 7.062
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s3/I3
6.262 0.570 tINS FR 24 R31C44[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s3/F
7.062 0.801 tNET RR 1 R23C40[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R23C40[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s1/CLK
7.454 -0.035 tSu 1 R23C40[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.382%; route: 5.129, 75.216%; tC2Q: 0.232, 3.402%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack 0.394
Data Arrival Time 7.060
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_54_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.060 0.798 tNET RR 1 R23C39[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_54_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R23C39[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_54_s1/CLK
7.454 -0.035 tSu 1 R23C39[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_54_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.389%; route: 5.127, 75.208%; tC2Q: 0.232, 3.403%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack 0.416
Data Arrival Time 7.039
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_53_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.039 0.777 tNET RR 1 R25C41[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_53_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R25C41[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_53_s1/CLK
7.454 -0.035 tSu 1 R25C41[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_53_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.456%; route: 5.105, 75.130%; tC2Q: 0.232, 3.414%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack 0.421
Data Arrival Time 7.033
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_59_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/F
7.033 0.771 tNET RR 1 R24C40[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_59_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R24C40[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_59_s1/CLK
7.454 -0.035 tSu 1 R24C40[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_59_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.474%; route: 5.100, 75.109%; tC2Q: 0.232, 3.417%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack 0.421
Data Arrival Time 7.033
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_59_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/F
7.033 0.771 tNET RR 1 R22C40[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_59_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R22C40[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_59_s1/CLK
7.454 -0.035 tSu 1 R22C40[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_59_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.474%; route: 5.100, 75.109%; tC2Q: 0.232, 3.417%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack 0.421
Data Arrival Time 7.033
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_60_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/F
7.033 0.771 tNET RR 1 R22C40[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_60_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R22C40[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_60_s1/CLK
7.454 -0.035 tSu 1 R22C40[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_60_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.474%; route: 5.100, 75.109%; tC2Q: 0.232, 3.417%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack 0.421
Data Arrival Time 7.033
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_61_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/F
7.033 0.771 tNET RR 1 R25C40[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_61_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R25C40[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_61_s1/CLK
7.454 -0.035 tSu 1 R25C40[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_61_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.474%; route: 5.100, 75.109%; tC2Q: 0.232, 3.417%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack 0.424
Data Arrival Time 7.030
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_43_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s3/I3
6.262 0.570 tINS FR 24 R31C44[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s3/F
7.030 0.769 tNET RR 1 R24C41[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_43_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R24C41[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_43_s1/CLK
7.454 -0.035 tSu 1 R24C41[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo2_43_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.483%; route: 5.097, 75.099%; tC2Q: 0.232, 3.418%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack 0.424
Data Arrival Time 7.030
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_45_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s3/I3
6.262 0.570 tINS FR 24 R31C44[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_47_s3/F
7.030 0.769 tNET RR 1 R26C41[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_45_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R26C41[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_45_s1/CLK
7.454 -0.035 tSu 1 R26C41[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_45_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.483%; route: 5.097, 75.099%; tC2Q: 0.232, 3.418%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack 0.425
Data Arrival Time 7.030
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_58_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_63_s3/F
7.030 0.768 tNET RR 1 R25C46[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_58_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R25C46[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_58_s1/CLK
7.454 -0.035 tSu 1 R25C46[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_58_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.485%; route: 5.096, 75.097%; tC2Q: 0.232, 3.419%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack 0.439
Data Arrival Time 7.016
Data Required Time 7.454
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_54_s1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.243 0.243 tNET RR 1 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/CLK
0.475 0.232 tC2Q RF 18 R14C31[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/q_r[0]_0_s2/Q
0.900 0.425 tNET FF 1 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/RAD[0]
1.417 0.517 tINS FF 51 R14C32 Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s9/DO
2.276 0.859 tNET FF 1 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/I3
2.647 0.371 tINS FF 119 R20C32[3][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc_27_s5/F
5.692 3.045 tNET FF 1 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/I3
6.262 0.570 tINS FR 24 R31C44[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_55_s3/F
7.016 0.754 tNET RR 1 R23C42[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_54_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R23C42[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_54_s1/CLK
7.454 -0.035 tSu 1 R23C42[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_54_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.246
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 1.458, 21.528%; route: 5.082, 75.046%; tC2Q: 0.232, 3.426%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_47_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C7[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_47_s0/CLK
0.386 0.202 tC2Q RR 1 R26C7[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_47_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_35_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C6[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_35_s0/CLK
0.386 0.202 tC2Q RR 1 R26C6[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_35_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack 0.204
Data Arrival Time 0.637
Data Required Time 0.433
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_0_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 R12C49[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_0_s0/CLK
0.386 0.202 tC2Q RR 4 R12C49[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_0_s0/Q
0.637 0.251 tNET RR 1 BSRAM_R10[14] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R10[14] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1/CLKA
0.433 0.249 tHld 1 BSRAM_R10[14] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.251, 55.376%; tC2Q: 0.202, 44.624%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack 0.211
Data Arrival Time 0.514
Data Required Time 0.302
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C5[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLK
0.385 0.201 tC2Q RF 4 R29C5[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/Q
0.514 0.128 tNET FF 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.302 0.118 tHld 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.990%; tC2Q: 0.201, 61.010%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C8[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0/CLK
0.386 0.202 tC2Q RR 1 R26C8[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_55_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[23]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path6

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_53_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C8[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_53_s0/CLK
0.386 0.202 tC2Q RR 1 R26C8[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_53_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[21]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path7

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_48_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C8[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_48_s0/CLK
0.386 0.202 tC2Q RR 1 R26C8[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_48_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[16]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_7_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R27C3[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_7_s0/CLK
0.386 0.202 tC2Q RR 1 R27C3[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_7_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_6_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R27C4[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_6_s0/CLK
0.386 0.202 tC2Q RR 1 R27C4[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_6_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R27C4[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/CLK
0.386 0.202 tC2Q RR 1 R27C4[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_0_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_23_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C10[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_23_s0/CLK
0.386 0.202 tC2Q RR 1 R29C10[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_23_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[23]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C10[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/CLK
0.386 0.202 tC2Q RR 1 R29C10[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_22_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[22]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C10[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/CLK
0.386 0.202 tC2Q RR 1 R29C10[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C11[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/CLK
0.386 0.202 tC2Q RR 1 R29C11[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[19]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C11[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/CLK
0.386 0.202 tC2Q RR 1 R29C11[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_17_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[17]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[3] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack 0.215
Data Arrival Time 0.648
Data Required Time 0.433
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_6_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 R12C49[2][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_6_s0/CLK
0.386 0.202 tC2Q RR 4 R12C49[2][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_6_s0/Q
0.648 0.262 tNET RR 1 BSRAM_R10[15] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R10[15] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/CLKA
0.433 0.249 tHld 1 BSRAM_R10[15] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.262, 56.424%; tC2Q: 0.202, 43.576%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack 0.216
Data Arrival Time 0.649
Data Required Time 0.433
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_3_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 R11C49[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_3_s0/CLK
0.386 0.202 tC2Q RR 4 R11C49[0][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_3_s0/Q
0.649 0.263 tNET RR 1 BSRAM_R10[14] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R10[14] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1/CLKA
0.433 0.249 tHld 1 BSRAM_R10[14] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.263, 56.538%; tC2Q: 0.202, 43.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack 0.217
Data Arrival Time 0.650
Data Required Time 0.433
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_0_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 R13C50[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_0_s0/CLK
0.386 0.202 tC2Q RR 4 R13C50[0][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_0_s0/Q
0.650 0.264 tNET RR 1 BSRAM_R10[15] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R10[15] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/CLKA
0.433 0.249 tHld 1 BSRAM_R10[15] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.264, 56.658%; tC2Q: 0.202, 43.342%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack 0.219
Data Arrival Time 0.652
Data Required Time 0.433
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_7_s0
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 R12C49[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_7_s0/CLK
0.386 0.202 tC2Q RR 4 R12C49[1][B] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_7_s0/Q
0.652 0.266 tNET RR 1 BSRAM_R10[15] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R10[15] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2/CLKA
0.433 0.249 tHld 1 BSRAM_R10[15] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.266, 56.822%; tC2Q: 0.202, 43.178%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack 0.222
Data Arrival Time 0.524
Data Required Time 0.302
From Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wraddr_0_s3
To Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1
Launch Clk O_adv7513_clk:[R]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 R12C48[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wraddr_0_s3/CLK
0.386 0.202 tC2Q RR 17 R12C48[1][A] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wraddr_0_s3/Q
0.524 0.138 tNET RR 1 BSRAM_R10[14] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1/ADA[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 O_adv7513_clk
0.000 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R10[14] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1/CLKA
0.302 0.118 tHld 1 BSRAM_R10[14] Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst/sdpb_inst_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.138, 40.549%; tC2Q: 0.202, 59.451%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path21

Path Summary:

Slack 0.225
Data Arrival Time 1.334
Data Required Time 1.109
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_29_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R42C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_29_s0/CLK
1.062 0.202 tC2Q RR 1 R42C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_29_s0/Q
1.334 0.272 tNET RR 1 BSRAM_R46[14] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R46[14] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s/CLKA
1.109 0.249 tHld 1 BSRAM_R46[14] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack 0.225
Data Arrival Time 0.659
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C3[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/CLK
0.386 0.202 tC2Q RR 1 R26C3[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_20_s0/Q
0.659 0.272 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[20]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack 0.225
Data Arrival Time 0.659
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C3[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/CLK
0.386 0.202 tC2Q RR 1 R26C3[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_19_s0/Q
0.659 0.272 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[19]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack 0.225
Data Arrival Time 0.659
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_47_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C11[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_47_s0/CLK
0.386 0.202 tC2Q RR 1 R30C11[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_47_s0/Q
0.659 0.272 tNET RR 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path25

Path Summary:

Slack 0.225
Data Arrival Time 0.659
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R30C11[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/CLK
0.386 0.202 tC2Q RR 1 R30C11[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_45_s0/Q
0.659 0.272 tNET RR 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.159
Data Arrival Time 5.893
Data Required Time 7.051
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.893 1.776 tNET FF 32 BSRAM_R46[12] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 BSRAM_R46[12] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
7.051 -0.438 tSu 1 BSRAM_R46[12] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.776, 88.448%; tC2Q: 0.232, 11.552%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack 1.159
Data Arrival Time 5.893
Data Required Time 7.051
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.893 1.776 tNET FF 32 BSRAM_R46[11] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 BSRAM_R46[11] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/CLKB
7.051 -0.438 tSu 1 BSRAM_R46[11] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.776, 88.448%; tC2Q: 0.232, 11.552%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack 1.159
Data Arrival Time 5.893
Data Required Time 7.051
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.893 1.776 tNET FF 32 BSRAM_R46[10] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 BSRAM_R46[10] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/CLKB
7.051 -0.438 tSu 1 BSRAM_R46[10] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.776, 88.448%; tC2Q: 0.232, 11.552%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack 1.159
Data Arrival Time 5.893
Data Required Time 7.051
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.893 1.776 tNET FF 32 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB
7.051 -0.438 tSu 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.776, 88.448%; tC2Q: 0.232, 11.552%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R39C38[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R39C38[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0/CLK
7.454 -0.035 tSu 1 R39C38[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/raddr_num_dly_10_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R38C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R38C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1/CLK
7.454 -0.035 tSu 1 R38C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_3_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R40C39[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R40C39[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_3_s1/CLK
7.454 -0.035 tSu 1 R40C39[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_3_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_7_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R40C39[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R40C39[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_7_s1/CLK
7.454 -0.035 tSu 1 R40C39[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_7_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_8_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R38C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R38C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_8_s1/CLK
7.454 -0.035 tSu 1 R38C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_8_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R41C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R41C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1/CLK
7.454 -0.035 tSu 1 R41C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_0_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_2_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R41C38[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R41C38[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_2_s1/CLK
7.454 -0.035 tSu 1 R41C38[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_2_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R41C38[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R41C38[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1/CLK
7.454 -0.035 tSu 1 R41C38[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_3_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R42C41[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R42C41[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1/CLK
7.454 -0.035 tSu 1 R42C41[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_4_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R42C41[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R42C41[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1/CLK
7.454 -0.035 tSu 1 R42C41[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_5_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_6_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R42C41[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R42C41[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_6_s1/CLK
7.454 -0.035 tSu 1 R42C41[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq2_wptr_6_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R40C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R40C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1/CLK
7.454 -0.035 tSu 1 R40C37[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R40C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R40C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1/CLK
7.454 -0.035 tSu 1 R40C38[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R40C37[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R40C37[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1/CLK
7.454 -0.035 tSu 1 R40C37[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R40C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R40C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1/CLK
7.454 -0.035 tSu 1 R40C37[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R42C41[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R42C41[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1/CLK
7.454 -0.035 tSu 1 R42C41[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_5_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R42C41[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R42C41[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_5_s1/CLK
7.454 -0.035 tSu 1 R42C41[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_5_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_6_s1
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R42C41[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R42C41[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_6_s1/CLK
7.454 -0.035 tSu 1 R42C41[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_6_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R41C38[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R41C38[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0/CLK
7.454 -0.035 tSu 1 R41C38[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_3_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R40C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R40C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0/CLK
7.454 -0.035 tSu 1 R40C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_4_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack 1.546
Data Arrival Time 5.908
Data Required Time 7.454
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_7_s0
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.623 3.623 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF 1 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
4.116 0.232 tC2Q FF 55 R38C37[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
5.908 1.792 tNET FF 1 R41C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.246 7.246 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR 1376 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
7.489 0.243 tNET RR 1 R41C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_7_s0/CLK
7.454 -0.035 tSu 1 R41C38[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_7_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 3.623
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.792, 88.538%; tC2Q: 0.232, 11.462%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.406
Data Arrival Time 1.602
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C29[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R44C29[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.823 0.437 tNET RR 1 R36C25[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.207 0.384 tINS RR 60 R36C25[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.602 0.395 tNET RR 1 R34C23[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 3192 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R34C23[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0/CLK
0.195 0.011 tHld 1 R34C23[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 27.091%; route: 0.831, 58.657%; tC2Q: 0.202, 14.251%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/sda_chk_s3
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R9C47[2][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/sda_chk_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R9C47[2][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/sda_chk_s3/CLK
0.871 0.011 tHld 1 R9C47[2][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/sda_chk_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SDA_OEN_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R8C46[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SDA_OEN_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C46[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SDA_OEN_s1/CLK
0.871 0.011 tHld 1 R8C46[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SDA_OEN_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SCL_OEN_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R7C45[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SCL_OEN_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R7C45[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SCL_OEN_s1/CLK
0.871 0.011 tHld 1 R7C45[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/SCL_OEN_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_0_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R8C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_0_s1/CLK
0.871 0.011 tHld 1 R8C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_1_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R8C44[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C44[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_1_s1/CLK
0.871 0.011 tHld 1 R8C44[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_2_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R8C46[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C46[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_2_s1/CLK
0.871 0.011 tHld 1 R8C46[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_3_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R7C45[1][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R7C45[1][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_3_s1/CLK
0.871 0.011 tHld 1 R7C45[1][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_4_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R7C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R7C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_4_s1/CLK
0.871 0.011 tHld 1 R7C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_5_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R9C46[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R9C46[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_5_s1/CLK
0.871 0.011 tHld 1 R9C46[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_6_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R7C45[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R7C45[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_6_s1/CLK
0.871 0.011 tHld 1 R7C45[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_7_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R6C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R6C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_7_s1/CLK
0.871 0.011 tHld 1 R6C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_8_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R7C45[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R7C45[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_8_s1/CLK
0.871 0.011 tHld 1 R7C45[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_9_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R9C44[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R9C44[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_9_s1/CLK
0.871 0.011 tHld 1 R9C44[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_10_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R9C46[2][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R9C46[2][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_10_s1/CLK
0.871 0.011 tHld 1 R9C46[2][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_11_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R9C46[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_11_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R9C46[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_11_s1/CLK
0.871 0.011 tHld 1 R9C46[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_12_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R8C46[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_12_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C46[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_12_s1/CLK
0.871 0.011 tHld 1 R8C46[2][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_12_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_13_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R9C44[1][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_13_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R9C44[1][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_13_s1/CLK
0.871 0.011 tHld 1 R9C44[1][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_13_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_14_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R9C46[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_14_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R9C46[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_14_s1/CLK
0.871 0.011 tHld 1 R9C46[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_14_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_15_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R9C45[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_15_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R9C45[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_15_s1/CLK
0.871 0.011 tHld 1 R9C45[0][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_15_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_16_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R9C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_16_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R9C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_16_s1/CLK
0.871 0.011 tHld 1 R9C45[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/c_state_16_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_0_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R7C44[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R7C44[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_0_s1/CLK
0.871 0.011 tHld 1 R7C44[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_1_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R8C44[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C44[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_1_s1/CLK
0.871 0.011 tHld 1 R8C44[0][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_2_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R8C44[1][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C44[1][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_2_s1/CLK
0.871 0.011 tHld 1 R8C44[1][B] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack 1.522
Data Arrival Time 2.393
Data Required Time 0.871
From key_debounceN_inst0/key_n_out1_s1
To I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_3_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/CLK
1.062 0.202 tC2Q RR 106 R8C50[1][A] key_debounceN_inst0/key_n_out1_s1/Q
2.393 1.331 tNET RR 1 R8C44[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 542 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R8C44[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_3_s1/CLK
0.871 0.011 tHld 1 R8C44[1][A] I2C_MASTER_Top_inst/u_i2c_master/bit_controller/cnt_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.331, 86.821%; tC2Q: 0.202, 13.179%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Pout_hs_dn_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Pout_hs_dn_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Pout_hs_dn_24_s0/CLK

MPW2

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hres_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hres_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hres_10_s0/CLK

MPW3

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_0_s1/CLK

MPW4

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vout_vsize_sysclk_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vout_vsize_sysclk_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vout_vsize_sysclk_7_s0/CLK

MPW5

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ky_23_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ky_23_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ky_23_s0/CLK

MPW6

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ky_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ky_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ky_7_s0/CLK

MPW7

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d1_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d1_s0/CLK

MPW8

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s6

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s6/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/srl_16_inst00/q_r[0]_0_s6/CLK

MPW9

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/state_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/state_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/state_1_s0/CLK

MPW10

MPW Summary:

Slack: 2.546
Actual Width: 3.546
Required Width: 1.000
Type: Low Pulse Width
Clock: O_adv7513_clk
Objects: Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/state_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.623 0.000 active clock edge time
3.623 0.000 O_adv7513_clk
3.623 0.000 tCL FF pix_rpll_inst/rpll_inst/CLKOUT
3.884 0.261 tNET FF Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/state_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
7.246 0.000 active clock edge time
7.246 0.000 O_adv7513_clk
7.246 0.000 tCL RR pix_rpll_inst/rpll_inst/CLKOUT
7.430 0.184 tNET RR Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/state_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
3192 dma_clk 2.919 0.261
1376 O_adv7513_clk_d 0.248 0.427
542 I_clk_d 9.061 0.261
266 n14_11 9.252 1.854
198 eye_calib_start_r 7.322 3.275
192 hfifo_objrpt[0] 2.644 1.881
155 next_state.ST_IFF0_WRITE_DDR 5.369 2.350
149 dqsts1 9.861 2.743
148 dqs_reg 10.525 1.992
144 n28_3 9.970 2.065

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R12C48 87.50%
R13C23 87.50%
R12C41 86.11%
R26C3 86.11%
R11C24 84.72%
R13C32 84.72%
R13C35 84.72%
R13C36 84.72%
R11C35 84.72%
R12C49 84.72%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk_x4i -period 3.333 -waveform {0 1.667} [get_nets {DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/clk_x4i}] -add
TC_CLOCK Actived create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add
TC_CLOCK Actived create_clock -name O_adv7513_clk -period 7.246 -waveform {0 3.623} [get_ports {O_adv7513_clk}] -add
TC_CLOCK Actived create_clock -name dma_clk -period 13.333 -waveform {0 6.667} [get_nets {dma_clk}] -add
TC_FALSE_PATH Actived set_false_path -from [get_clocks {O_adv7513_clk}] -to [get_clocks {dma_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {dma_clk}] -to [get_clocks {O_adv7513_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {I_clk}] -to [get_clocks {O_adv7513_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {O_adv7513_clk}] -to [get_clocks {I_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {dma_clk}] -group [get_clocks {clk_x4i}] -group [get_clocks {I_clk}]