#OPTIONS:"|-layerid|0|-orig_srs|D:\\proj\\scaler_example_design_live\\project\\src\\i2c_master\\temp\\I2C_MASTER\\rev_1\\synwork\\i2c_master_comp.srs|-prodtype|synplify_pro|-primux|-fixsmult|-sdff_counter|-nram|-divnmod|-nostructver|-gowin|-infer_seqShift|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-I|D:\\Gowin\\Gowin_V1.9.2.01Beta\\IDE\\ipcore\\I2CMASTER\\data|-I|D:\\proj\\scaler_example_design_live\\project\\src\\i2c_master\\temp\\I2C_MASTER|-I|D:\\proj\\scaler_example_design_live\\project\\src\\i2c_master\\temp\\I2C_MASTER\\|-I|D:\\Gowin\\Gowin_V1.9.2.01Beta\\SynplifyPro\\lib|-sysv|-devicelib|D:\\Gowin\\Gowin_V1.9.2.01Beta\\SynplifyPro\\lib\\generic\\gw2a.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work"
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\SynplifyPro\\bin64\\c_ver.exe":1569428574
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\SynplifyPro\\lib\\generic\\gw2a.v":1569433954
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\SynplifyPro\\lib\\vlog\\hypermods.v":1569428306
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\SynplifyPro\\lib\\vlog\\umr_capim.v":1569428306
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1569428306
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1569428306
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\IDE\\ipcore\\I2CMASTER\\data\\I2C_MASTER_TOP.v":1571204864
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\i2c_master\\temp\\I2C_MASTER\\top_define.vh":1575857336
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\IDE\\ipcore\\I2CMASTER\\data\\static_macro_define.vh":1571204864
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\IDE\\ipcore\\I2CMASTER\\data\\I2C_MASTER.vp":1571204864
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\i2c_master\\temp\\I2C_MASTER\\top_define.vh":1575857336
#CUR:"D:\\Gowin\\Gowin_V1.9.2.01Beta\\IDE\\ipcore\\I2CMASTER\\data\\static_macro_define.vh":1571204864
0			"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v" verilog
1		*	"D:\proj\scaler_example_design_live\project\src\i2c_master\temp\I2C_MASTER\top_define.vh" verilog
2		*	"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\static_macro_define.vh" verilog
3			"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp" verilog
#Dependency Lists(Uses List)
0 3 2 1
1 1 0 2
2 2 0 1
3 0 2 1
#Dependency Lists(Users Of)
0 3 2 1
1 3 2 1 0
2 3 2 1 0
3 0
#Design Unit to File Association
module work \~I2C_Master_Bit_Ctrl.I2C_MASTER_Top 3
module work \~I2C_Master_Byte_Ctrl.I2C_MASTER_Top 3
module work I2C_MASTER_Top 0
module work \~i2c_master.I2C_MASTER_Top 3
