# Wed Jun 17 14:39:47 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1620R, Built May 18 2020 06:06:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@A: MF827 |No constraint file specified.
@L: D:\proj\scaler_example_design_memory\project\src\scaler\temp\scaler\rev_1\scaler_scck.rpt 
See clock summary report "D:\proj\scaler_example_design_memory\project\src\scaler\temp\scaler\rev_1\scaler_scck.rpt"
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 134MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)

@N: FX493 |Applying initial value "0" on instance vinvs_outclk_d1.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@N: FX493 |Applying initial value "0" on instance vinvs_inclk_d1.
@N: FX493 |Applying initial value "0" on instance vinvs_outclk_d2.
@N: FX493 |Applying initial value "0" on instance vinvs_inclk_d2.
@N: FX493 |Applying initial value "0" on instance vinde_gen.
@N: FX493 |Applying initial value "0" on instance vinvs_inclk_d1.
@N: FX493 |Applying initial value "0" on instance vinde_inclk_d1.
@N: FX493 |Applying initial value "0" on instance vinvs_inclk_d2.
@N: FX493 |Applying initial value "0" on instance vout_de_req_d1.
@N: FX493 |Applying initial value "1" on instance vinvs_outclk_d1.
@N: FX493 |Applying initial value "1" on instance vinvs_outclk_d2.
@N: FX493 |Applying initial value "000000000000" on instance vin_vsize_vinclk[11:0].
@N: FX493 |Applying initial value "0" on instance vinvs_sysclk_d1.
@N: FX493 |Applying initial value "0" on instance vinvs_sysclk_d2.
@N: FX493 |Applying initial value "000000000000" on instance vin_hsize_sysclk[11:0].
@N: FX493 |Applying initial value "000000000000" on instance vin_vsize_sysclk[11:0].
@N: FX493 |Applying initial value "000000000000" on instance vout_hsize_sysclk[11:0].
@N: FX493 |Applying initial value "000000000000" on instance vout_vsize_sysclk[11:0].
@N: FX493 |Applying initial value "000000000000000000000000" on instance kx[23:0].
@N: FX493 |Applying initial value "000000000000000000000000" on instance ky[23:0].
Encoding state machine state[3:0] (in view: work.\\\~hcalc_ctrl_fsm\.Scaler_Top\ (verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
   011 -> 11

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 230MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 230MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 231MB)

@W: BN117 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\scaler\data\scaler_top.v":145:0:145:18|Instance scaler_wrapper_inst of partition view:work.\\\~scaler_wrapper\.Scaler_Top\ _16s_8s_2s_16s(verilog) has no references to its outputs; instance not removed. 
@W: BN117 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\scaler\data\scaler_top.v":145:0:145:18|Instance scaler_wrapper_inst of partition view:work.\\\~scaler_wrapper\.Scaler_Top\ _16s_8s_2s_16s(verilog) has no references to its outputs; instance not removed. 

Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 231MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 230MB peak: 231MB)



Clock Summary
******************

          Start                     Requested     Requested     Clock        Clock                     Clock
Level     Clock                     Frequency     Period        Type         Group                     Load 
------------------------------------------------------------------------------------------------------------
0 -       Scaler_Top|I_sysclk       217.1 MHz     4.607         inferred     Autoconstr_clkgroup_1     1172 
                                                                                                            
0 -       Scaler_Top|I_vout_clk     255.0 MHz     3.922         inferred     Autoconstr_clkgroup_2     164  
                                                                                                            
0 -       Scaler_Top|I_vin_clk      229.4 MHz     4.359         inferred     Autoconstr_clkgroup_0     126  
============================================================================================================



Clock Load Summary
***********************

                          Clock     Source               Clock Pin                                                                     Non-clock Pin     Non-clock Pin
Clock                     Load      Pin                  Seq Example                                                                   Seq Example       Comb Example 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Scaler_Top|I_sysclk       1172      I_sysclk(port)       scaler_wrapper_inst.scaler_core_inst.vinvs_sysclk_d1.C                        -                 -            
                                                                                                                                                                      
Scaler_Top|I_vout_clk     164       I_vout_clk(port)     scaler_wrapper_inst.scaler_core_inst.video_outbuf_inst.oram_rpt_d1[1:0].C     -                 -            
                                                                                                                                                                      
Scaler_Top|I_vin_clk      126       I_vin_clk(port)      scaler_wrapper_inst.scaler_core_inst.vin_vsize_vinclk[0].C                    -                 -            
======================================================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

3 non-gated/non-generated clock tree(s) driving 1462 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       I_sysclk            port                   1172       ENCRYPTED      
@KP:ckid0_1       I_vout_clk          port                   164        ENCRYPTED      
@KP:ckid0_2       I_vin_clk           port                   126        ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\proj\scaler_example_design_memory\project\src\scaler\temp\scaler\rev_1\scaler.sap.

Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB)


Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 232MB peak: 232MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 154MB peak: 234MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Wed Jun 17 14:39:50 2020

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