srcfile:=	../../project/src/scaler/scaler.vo \
			../../project/src/frame_buffer/vfb_top.vo \
			../../project/src/ddr3_memory_interface/ddr3_memory_interface.vo 
			

tbfile:=	../../tb/tb.v \
			../../tb/config/*.v \
			../../tb/driver/*.v \
			../../tb/monitor/*.v \
			../../tb/syn_code/*.v \
			../../tb/ddr3_model/ddr3_model.v

incpath1:=	../../project/src/ddr3_memory_interface/temp/DDR3/ 
incpath2:=	../../project/src/frame_buffer 
incpath3:=	../../tb/ddr3_model 
			

vcs:
	vcs -debug_all -R -full64 -fsdb -sverilog \
	-v ../../tb/prim_sim.v \
	$(tbfile) \
	$(srcfile) \
	+incdir+$(incpath1) \
	+incdir+$(incpath2) \
	+incdir+$(incpath3)

verdi:
	verdi -sverilog	-nologo \
	-v ../../tb/prim_sim.v \
	$(tbfile) \
	$(srcfile) \
	+incdir+$(incpath1) \
	+incdir+$(incpath2) \
	+incdir+$(incpath3) \
	-ssf tb.fsdb \
	&

clean:
	rm -rf compile  *.err *.log csrc  run.do  simv  simv.daidir  ucli.key  vc_hdrs.h  work novas.rc  nWaveLog   vcd2fsdbLog  verilog.vcd  verilog.vcd.fsdb vsim.wlf simv.vdb INCA_libs waves.shm .simvision *.rc cov_work daTaseT.asdb  fcover.acdb  library.cfg elab_file *.ucdb verdiLog inTer.vpd novas.conf wave.ses.png *.fsdb daTa

