//---------------------------------------------------------------------
// File name: syn_code_16.v
// Module name: syn_code_16
// Module Description: used to synchronize the video with system vs signal
// Created by: caojie
// ---------------------------------------------------------------------
// Release history
// VERSION |   Date      | AUTHOR  |    DESCRIPTION
//   1.0   |  7-Sep-2009 | caojie  |      initial
// ---------------------------------------------------------------------


module syn_code_16
(
    // inputs
    input  [15:0] cpu2out_xst_reg   ,
    input  [15:0] cpu2out_xed_reg   ,
    input  [15:0] cpu2out_yst_reg   ,
    input  [15:0] cpu2out_yed_reg   ,
    input  [15:0] cpu2out_hsync_reg ,
    input  [15:0] cpu2out_vsync_reg ,
    input  [15:0] cpu2out_hed_reg   ,
    input  [15:0] cpu2out_ved_reg   ,
    input  [15:0] hor_res0          ,
    input  [15:0] ver_res0          ,
                  
    input         vs_sel            ,
    input         rst_n             ,
    input         pxl_clk           ,
    input         e_vs              ,
                  
    input  [15:0] off0_syn_data     ,
    
    // outputs
    output        syn_off0_re       ,
    output        syn_off0_vs       ,
    output        syn_off0_hs       ,
    output        syn_clip0_vs      ,
    output        syn_clip0_hs      ,
    output        syn_clip0_de      ,
    output [15:0] syn_clip0_data     
);

//==========================================
  // wires
  wire   pout_hs;
  wire   pout_vs;
  
  wire   off0_re;
  
  // regs  
  reg   off0_re_d1;
  reg   off0_re_d2;
  
  reg  [3:0]  vs_dn;
  reg  [3:0]  hs_dn;

//============================================================================
  assign syn_off0_re   = off0_re;
  assign syn_off0_vs   = pout_vs;
  assign syn_off0_hs   = pout_hs;


//============================================================================
//==================== delay ofifo read enable signal ====================
  always@(posedge pxl_clk or negedge rst_n)
  begin
    if(!rst_n) 
      begin
        off0_re_d1 <= 1'b0;
        off0_re_d2 <= 1'b0;
      end
    else 
      begin
        off0_re_d1 <= off0_re;
        off0_re_d2 <= off0_re_d1;
      end
  end

//---------------------------------------------------
always @(posedge pxl_clk or negedge rst_n)
begin
	if(!rst_n)
		begin
			vs_dn <= 4'd0;
			hs_dn <= 4'd0;
		end
	else    
		begin                              
			vs_dn <= {vs_dn[2:0],pout_vs};
			hs_dn <= {hs_dn[2:0],pout_hs};
		end
end

//============================================================================
  assign syn_clip0_de   = off0_re_d1;
  assign syn_clip0_hs   = hs_dn[0] ; 
  assign syn_clip0_vs   = vs_dn[0] ; 
  assign syn_clip0_data = off0_syn_data;

//===================== system signal generate =====================
sync_gen1x sync_gen1x_inst
(
     //-------
     .cpu2out_xst_reg   (cpu2out_xst_reg     ),
     .cpu2out_xed_reg   (cpu2out_xed_reg     ), 
     .cpu2out_yst_reg   (cpu2out_yst_reg     ), 
     .cpu2out_yed_reg   (cpu2out_yed_reg     ),
     .cpu2out_fxed_reg  (16'd0),  
     .cpu2out_fyed_reg  (16'd0), 
     .cpu2out_hsync_reg (cpu2out_hsync_reg   ) ,
     .cpu2out_vsync_reg (cpu2out_vsync_reg   ) , 
     .cpu2out_hed_reg   (cpu2out_hed_reg     ) ,
     .cpu2out_ved_reg   (cpu2out_ved_reg     ) ,
       
     .hor_res0          (hor_res0            ),
     .ver_res0          (ver_res0            ),
     //-------  video   
     .off0_re           (off0_re             ),
             
     .pout_de           (                    ),//unused 
     .pout_hs           (pout_hs             ),
     .pout_vs           (pout_vs             ), 
     .vs_sel            (vs_sel              ),                            
     .e_vs              (e_vs                ),         
     .pxl_clk           (pxl_clk             ),
     .rst_b             (rst_n               )
);

endmodule

