#OPTIONS:"|-layerid|0|-orig_srs|D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\rev_1\\synwork\\ddr3_memory_interface_comp.srs|-prodtype|synplify_pro|-primux|-fixsmult|-sdff_counter|-nram|-divnmod|-nostructver|-gowin|-infer_seqShift|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-y|D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\simlib\\hardware_core\\gw2a\\prim_syn.v|-I|D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3|-I|D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data|-I|D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\|-I|D:\\Gowin\\Gowin_V1.9.6Beta\\SynplifyPro\\lib|-sysv|-devicelib|D:\\Gowin\\Gowin_V1.9.6Beta\\SynplifyPro\\lib\\generic\\gw2a.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work"
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\SynplifyPro\\bin64\\c_ver.exe":1589223566
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\SynplifyPro\\lib\\generic\\gw2a.v":1589223686
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\SynplifyPro\\lib\\vlog\\hypermods.v":1589223772
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\SynplifyPro\\lib\\vlog\\umr_capim.v":1589223772
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1589223772
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1589223772
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\ddr3_1_4code.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\ddr3_name.v":1592386898
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\DDR3_define.v":1592386898
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\ddr3_pll_config.v":1592386898
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\DDR3_TOP.v":1591600886
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\ddr3_name.v":1592386898
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\DDR3_define.v":1592386898
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\ddr3_memory_interface\\temp\\DDR3\\gwmc_param.v":1592386898
#CUR:"D:\\Gowin\\Gowin_V1.9.6Beta\\IDE\\ipcore\\DDR3\\data\\gwmc_local_param.v":1591600886
0			"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v" verilog
1		*	"D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v" verilog
2		*	"D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v" verilog
3		*	"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v" verilog
4		*	"D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v" verilog
5		*	"D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v" verilog
6			"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v" verilog
#Dependency Lists(Uses List)
0 0 5 4 3 2 1
1 1 0 5 4 3 2
2 0 2 5 4 3 1
3 0 3 5 4 2 1
4 4 0 5 3 2 1
5 5 0 4 3 2 1
6 5 0 3 2 4 1
#Dependency Lists(Users Of)
0 5 4 3 2 1 6
1 6 5 4 3 2 0
2 6 5 4 3 2 1 0
3 6 5 4 3 2 1 0
4 6 5 3 2 1 0
5 6 4 3 2 1 0
6 -1
#Design Unit to File Association
module work DDR3_Memory_Interface_Top 6
module work \~gw3_phy_mc.DDR3_Memory_Interface_Top 0
module work \~gwmc_wr_data.DDR3_Memory_Interface_Top 0
module work \~gwmc_top.DDR3_Memory_Interface_Top 0
module work \~gwmc_timing_ctrl.DDR3_Memory_Interface_Top 0
module work \~gwmc_rd_data.DDR3_Memory_Interface_Top 0
module work \~gwmc_rank_ctrl.DDR3_Memory_Interface_Top 0
module work \~gwmc_cmd_buffer.DDR3_Memory_Interface_Top 0
module work \~gwmc_bank_ctrl.DDR3_Memory_Interface_Top 0
module work \~fifo_sc.DDR3_Memory_Interface_Top 0
module work \~ecc_top.DDR3_Memory_Interface_Top 0
module work \~ecc_encoder.DDR3_Memory_Interface_Top 0
module work \~ecc_decoder.DDR3_Memory_Interface_Top 0
module work \~fifo_ctrl.DDR3_Memory_Interface_Top 0
module work \~ddr_phy_wd.DDR3_Memory_Interface_Top 0
module work \~ddr_phy_top.DDR3_Memory_Interface_Top 0
module work \~ddr_phy_reset_gen.DDR3_Memory_Interface_Top 0
module work \~IN_FIFO.DDR3_Memory_Interface_Top 0
module work \~OUT_FIFO.DDR3_Memory_Interface_Top 0
module work \~ddr_phy_data_lane.DDR3_Memory_Interface_Top 0
module work \~ddr_phy_data_io.DDR3_Memory_Interface_Top 0
module work \~ddr_phy_cmd_lane.DDR3_Memory_Interface_Top 0
module work \~ddr_phy_cmd_io.DDR3_Memory_Interface_Top 0
module work \~ddr_memmem_sync.DDR3_Memory_Interface_Top 0
module work \~ddr_init.DDR3_Memory_Interface_Top 0
module work \~CMD_FIFO.DDR3_Memory_Interface_Top 0
