#OPTIONS:"|-layerid|0|-orig_srs|D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO\\rev_1\\synwork\\fifo_dma_write_32_128_comp.srs|-prodtype|synplify_pro|-primux|-fixsmult|-sdff_counter|-nram|-divnmod|-nostructver|-gowin|-infer_seqShift|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-I|D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO|-I|D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO\\|-I|D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\SynplifyPro\\lib|-sysv|-devicelib|D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\SynplifyPro\\lib\\generic\\gw2a.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
#CUR:"D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\SynplifyPro\\bin64\\c_ver.exe":1575393480
#CUR:"D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\SynplifyPro\\lib\\generic\\gw2a.v":1575572956
#CUR:"D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\SynplifyPro\\lib\\vlog\\hypermods.v":1575393232
#CUR:"D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\SynplifyPro\\lib\\vlog\\umr_capim.v":1575393232
#CUR:"D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\SynplifyPro\\lib\\vlog\\scemi_objects.v":1575393232
#CUR:"D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\SynplifyPro\\lib\\vlog\\scemi_pipes.svh":1575393232
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO\\fifo_define.v":1576721266
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO\\fifo_parameter.v":1576721266
#CUR:"D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\IDE\\ipcore\\FIFO\\data\\edc.v":1576572845
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO\\fifo_define.v":1576721266
#CUR:"D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\IDE\\ipcore\\FIFO\\data\\fifo.v":1576572845
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO\\fifo_define.v":1576721266
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO\\fifo_parameter.v":1576721266
#CUR:"D:\\Gowin\\Gowin_V1.9.3Beta_37275_20191218\\IDE\\ipcore\\FIFO\\data\\fifo_top.v":1576572844
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO\\fifo_define.v":1576721266
#CUR:"D:\\proj\\scaler_example_design_live\\project\\src\\frame_buffer\\fifo\\temp\\FIFO\\fifo_parameter.v":1576721266
#numinternalfiles:5
#defaultlanguage:verilog
0			"D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\fifo_define.v" verilog
1			"D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\fifo_parameter.v" verilog
2			"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\ipcore\FIFO\data\edc.v" verilog
3			"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\ipcore\FIFO\data\fifo.v" verilog
4			"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\ipcore\FIFO\data\fifo_top.v" verilog
#Dependency Lists(Uses List)
0 1
1 0 1
2 0 1
3 0 1
4 0 1 3
#Dependency Lists(Users Of)
0 1 2 3 4
1 0 3 4 2
2 -1
3 4
4 -1
#Design Unit to File Association
package work work_D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\fifo_define.v_unit 1
module work \~edc.fifo_dma_write_32_128 2
module work \~fifo.fifo_dma_write_32_128 3
module work fifo_dma_write_32_128 4
