`

    #Build: Synplify Pro (R) P-2019.03G-1-Beta1, Build 387R, Dec  3 2019
    #install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GZAE-AE-CAOJIE

    # Thu Dec 19 10:07:48 2019

    #Implementation: rev_1

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\fifo_define.v" (library work)
    @I::"D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\fifo_parameter.v" (library work)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\ipcore\FIFO\data\edc.v" (library work)
    @W:CG1337 : edc.v(77) | Net Reset is not declared.
    @W:CG1337 : edc.v(91) | Net RPReset is not declared.
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\ipcore\FIFO\data\fifo.v" (library work)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\ipcore\FIFO\data\fifo_top.v" (library work)
    Verilog syntax check successful!
    @N:CG364 : fifo_parameter.v(1) | Synthesizing module work_D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\fifo_define.v_unit in library work.
    Selecting top level module fifo_dma_write_32_128
    Running optimization stage 1 on \~fifo.fifo_dma_write_32_128  .......
    @N:CG364 : fifo_top.v(3) | Synthesizing module fifo_dma_write_32_128 in library work.
    Running optimization stage 1 on fifo_dma_write_32_128 .......
    Running optimization stage 2 on fifo_dma_write_32_128 .......
    Running optimization stage 2 on \~fifo.fifo_dma_write_32_128  .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 124MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Dec 19 10:07:49 2019

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    @N:NF107 : fifo_top.v(3) | Selected library: work cell: fifo_dma_write_32_128 view verilog as top level
    @N:NF107 : fifo_top.v(3) | Selected library: work cell: fifo_dma_write_32_128 view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 88MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Dec 19 10:07:49 2019

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  fifo_dma_write_32_128_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 18MB peak: 19MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Dec 19 10:07:49 2019

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    @N:NF107 : fifo_top.v(3) | Selected library: work cell: fifo_dma_write_32_128 view verilog as top level
    @N:NF107 : fifo_top.v(3) | Selected library: work cell: fifo_dma_write_32_128 view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 88MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Dec 19 10:07:51 2019

    ###########################################################]

`
`

    Premap Report

`
`

    # Thu Dec 19 10:07:51 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  fifo_dma_write_32_128_scck.rpt
    Printing clock  summary report in "D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 220MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)

    Clock Summary
    ******************

              Start                           Requested     Requested     Clock        Clock                     Clock
    Level     Clock                           Frequency     Period        Type         Group                     Load
    ------------------------------------------------------------------------------------------------------------------
    0 -       fifo_dma_write_32_128|RdClk     199.1 MHz     5.024         inferred     Autoconstr_clkgroup_1     189

    0 -       fifo_dma_write_32_128|WrClk     247.1 MHz     4.047         inferred     Autoconstr_clkgroup_0     172
    ==================================================================================================================

    Clock Load Summary
    ***********************

                                    Clock     Source          Clock Pin                          Non-clock Pin     Non-clock Pin
    Clock                           Load      Pin             Seq Example                        Seq Example       Comb Example
    --------------------------------------------------------------------------------------------------------------------------------------------
    fifo_dma_write_32_128|RdClk     189       RdClk(port)     fifo_inst.Big\.rq2_wptr[9:0].C     -                 fifo_inst.un1_RdClk.I[0](inv)

    fifo_dma_write_32_128|WrClk     172       WrClk(port)     fifo_inst.Big\.wq2_rptr[9:0].C     -                 fifo_inst.un1_WrClk.I[0](inv)
    ============================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    2 non-gated/non-generated clock tree(s) driving 237 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       RdClk               port                   189        ENCRYPTED
    ClockId_0_1       WrClk               port                   48         ENCRYPTED
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 225MB)

    Process took 0h:00m:03s realtime, 0h:00m:02s cputime
    # Thu Dec 19 10:07:54 2019

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Thu Dec 19 10:07:54 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 216MB peak: 216MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 222MB peak: 222MB)

    @W:FX107 :  | RAM mem_2_3[19:0] (in view: work.\\\~fifo\.fifo_dma_write_32_128\ (verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
    @W:FX107 :  | RAM mem_2_2[35:0] (in view: work.\\\~fifo\.fifo_dma_write_32_128\ (verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
    @W:FX107 :  | RAM mem_2_1[35:0] (in view: work.\\\~fifo\.fifo_dma_write_32_128\ (verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
    @W:FX107 :  | RAM mem_2_0[35:0] (in view: work.\\\~fifo\.fifo_dma_write_32_128\ (verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.

    Starting factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 225MB peak: 226MB)

    Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 225MB peak: 226MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 225MB peak: 226MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 225MB peak: 226MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 226MB peak: 226MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 226MB peak: 226MB)

    Finished preparing to map (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 226MB peak: 226MB)

    Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 226MB peak: 226MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:04s		    -2.34ns		 251 /       106
       2		0h:00m:04s		    -2.34ns		 251 /       106

       3		0h:00m:04s		    -2.34ns		 251 /       106

       4		0h:00m:04s		    -2.34ns		 251 /       106

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 227MB peak: 227MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 227MB peak: 227MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 155MB peak: 228MB)

    Writing Analyst data base D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synwork\fifo_dma_write_32_128_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 227MB peak: 228MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 227MB peak: 228MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 228MB peak: 228MB)

    Start final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 226MB peak: 228MB)

    @W:MT420 :  | Found inferred clock fifo_dma_write_32_128|WrClk with period 5.20ns. Please declare a user-defined clock on port WrClk.
    @W:MT420 :  | Found inferred clock fifo_dma_write_32_128|RdClk with period 5.31ns. Please declare a user-defined clock on port RdClk.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Thu Dec 19 10:08:02 2019
    #

    Top view:               fifo_dma_write_32_128
    Requested Frequency:    188.5 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -0.936

                                    Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                  Frequency     Frequency     Period        Period        Slack      Type         Group
    -------------------------------------------------------------------------------------------------------------------------------------
    fifo_dma_write_32_128|RdClk     188.5 MHz     160.2 MHz     5.306         6.242         -0.936     inferred     Autoconstr_clkgroup_1
    fifo_dma_write_32_128|WrClk     192.5 MHz     163.6 MHz     5.196         6.113         -0.917     inferred     Autoconstr_clkgroup_0
    System                          150.0 MHz     237.1 MHz     6.667         4.218         2.449      system       system_clkgroup
    =====================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                     Ending                       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -------------------------------------------------------------------------------------------------------------------------------------------------
    System                       fifo_dma_write_32_128|WrClk  |  5.196       4.623   |  No paths    -      |  No paths    -      |  No paths    -
    System                       fifo_dma_write_32_128|RdClk  |  5.306       2.449   |  No paths    -      |  No paths    -      |  No paths    -
    fifo_dma_write_32_128|WrClk  System                       |  5.196       4.418   |  No paths    -      |  No paths    -      |  No paths    -
    fifo_dma_write_32_128|WrClk  fifo_dma_write_32_128|WrClk  |  5.196       -0.917  |  5.196       4.357  |  No paths    -      |  No paths    -
    fifo_dma_write_32_128|WrClk  fifo_dma_write_32_128|RdClk  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    fifo_dma_write_32_128|RdClk  System                       |  5.306       4.467   |  No paths    -      |  No paths    -      |  No paths    -
    fifo_dma_write_32_128|RdClk  fifo_dma_write_32_128|WrClk  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    fifo_dma_write_32_128|RdClk  fifo_dma_write_32_128|RdClk  |  5.306       -0.936  |  5.306       4.467  |  No paths    -      |  2.653       1.814
    =================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: fifo_dma_write_32_128|RdClk
    ====================================

    Starting Points with Worst Slack
    ********************************

                                   Starting                                                              Arrival
    Instance                       Reference                       Type     Pin     Net                  Time        Slack
                                   Clock
    -----------------------------------------------------------------------------------------------------------------------
    fifo_inst.Big\.rq2_wptr[6]     fifo_dma_write_32_128|RdClk     DFFC     Q       Big\.rq2_wptr[6]     0.243       -0.936
    fifo_inst.Big\.rq2_wptr[5]     fifo_dma_write_32_128|RdClk     DFFC     Q       Big\.rq2_wptr[5]     0.243       -0.854
    fifo_inst.Empty                fifo_dma_write_32_128|RdClk     DFFP     Q       Empty                0.243       -0.403
    fifo_inst.Big\.rq2_wptr[4]     fifo_dma_write_32_128|RdClk     DFFC     Q       Big\.rq2_wptr[4]     0.243       -0.289
    fifo_inst.Big\.rq2_wptr[3]     fifo_dma_write_32_128|RdClk     DFFC     Q       Big\.rq2_wptr[3]     0.243       -0.207
    fifo_inst.Big\.rq2_wptr[2]     fifo_dma_write_32_128|RdClk     DFFC     Q       Big\.rq2_wptr[2]     0.243       0.052
    fifo_inst.rbin_num[3]          fifo_dma_write_32_128|RdClk     DFFC     Q       rbin_num[3]          0.243       0.221
    fifo_inst.Big\.rq2_wptr[1]     fifo_dma_write_32_128|RdClk     DFFC     Q       Big\.rq2_wptr[1]     0.243       0.283
    fifo_inst.rbin_num[0]          fifo_dma_write_32_128|RdClk     DFFC     Q       rbin_num[0]          0.243       0.494
    fifo_inst.rbin_num[1]          fifo_dma_write_32_128|RdClk     DFFC     Q       rbin_num[1]          0.243       0.529
    =======================================================================================================================

    Ending Points with Worst Slack
    ******************************

                          Starting                                                             Required
    Instance              Reference                       Type     Pin     Net                 Time         Slack
                          Clock
    --------------------------------------------------------------------------------------------------------------
    fifo_inst.Rnum[9]     fifo_dma_write_32_128|RdClk     DFFC     D       rcnt_sub[9]         5.245        -0.936
    fifo_inst.Rnum[8]     fifo_dma_write_32_128|RdClk     DFFC     D       rcnt_sub[8]         5.245        -0.901
    fifo_inst.Rnum[7]     fifo_dma_write_32_128|RdClk     DFFC     D       rcnt_sub[7]         5.245        -0.866
    fifo_inst.Rnum[6]     fifo_dma_write_32_128|RdClk     DFFC     D       rcnt_sub[6]         5.245        -0.831
    fifo_inst.Rnum[5]     fifo_dma_write_32_128|RdClk     DFFC     D       rcnt_sub[5]         5.245        -0.796
    fifo_inst.Rnum[4]     fifo_dma_write_32_128|RdClk     DFFC     D       rcnt_sub[4]         5.245        -0.761
    fifo_inst.Rnum[3]     fifo_dma_write_32_128|RdClk     DFFC     D       rcnt_sub[3]         5.245        -0.726
    fifo_inst.Empty       fifo_dma_write_32_128|RdClk     DFFP     D       rempty_val_NE_i     5.245        -0.403
    fifo_inst.Rnum[2]     fifo_dma_write_32_128|RdClk     DFFC     D       rcnt_sub[2]         5.245        -0.256
    fifo_inst.Rnum[1]     fifo_dma_write_32_128|RdClk     DFFC     D       rcnt_sub[1]         5.245        -0.009
    ==============================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      6.181
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -0.936

        Number of logic level(s):                12
        Starting point:                          fifo_inst.Big\.rq2_wptr[6] / Q
        Ending point:                            fifo_inst.Rnum[9] / D
        The start point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    fifo_inst.Big\.rq2_wptr[6]          DFFC     Q        Out     0.243     0.243       -
    Big\.rq2_wptr[6]                    Net      -        -       0.596     -           12
    fifo_inst.rcnt_sub_v_0_i_o3[5]      LUT2     I1       In      -         0.839       -
    fifo_inst.rcnt_sub_v_0_i_o3[5]      LUT2     F        Out     0.570     1.409       -
    rcnt_sub_b_D0_0[5]                  Net      -        -       0.535     -           4
    fifo_inst.rcnt_sub_v_0_0_a2[2]      LUT4     I3       In      -         1.944       -
    fifo_inst.rcnt_sub_v_0_0_a2[2]      LUT4     F        Out     0.371     2.315       -
    rcnt_sub_b_D0_0[2]                  Net      -        -       0.535     -           2
    fifo_inst.rcnt_sub_0_axb_2_lofx     LUT4     I2       In      -         2.850       -
    fifo_inst.rcnt_sub_0_axb_2_lofx     LUT4     F        Out     0.462     3.312       -
    rcnt_sub_0_axb_2_lofx               Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_0_cry_2_0        ALU      I0       In      -         3.847       -
    fifo_inst.rcnt_sub_0_cry_2_0        ALU      COUT     Out     0.549     4.396       -
    rcnt_sub_0_cry_2                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_3_0        ALU      CIN      In      -         4.396       -
    fifo_inst.rcnt_sub_0_cry_3_0        ALU      COUT     Out     0.035     4.431       -
    rcnt_sub_0_cry_3                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_4_0        ALU      CIN      In      -         4.431       -
    fifo_inst.rcnt_sub_0_cry_4_0        ALU      COUT     Out     0.035     4.466       -
    rcnt_sub_0_cry_4                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_5_0        ALU      CIN      In      -         4.466       -
    fifo_inst.rcnt_sub_0_cry_5_0        ALU      COUT     Out     0.035     4.501       -
    rcnt_sub_0_cry_5                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_6_0        ALU      CIN      In      -         4.501       -
    fifo_inst.rcnt_sub_0_cry_6_0        ALU      COUT     Out     0.035     4.536       -
    rcnt_sub_0_cry_6                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_7_0        ALU      CIN      In      -         4.536       -
    fifo_inst.rcnt_sub_0_cry_7_0        ALU      COUT     Out     0.035     4.571       -
    rcnt_sub_0_cry_7                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_8_0        ALU      CIN      In      -         4.571       -
    fifo_inst.rcnt_sub_0_cry_8_0        ALU      COUT     Out     0.035     4.606       -
    rcnt_sub_0_cry_8                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_s_9_0          ALU      CIN      In      -         4.606       -
    fifo_inst.rcnt_sub_0_s_9_0          ALU      SUM      Out     0.470     5.076       -
    rcnt_sub0[9]                        Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_m[9]             LUT4     I1       In      -         5.611       -
    fifo_inst.rcnt_sub_m[9]             LUT4     F        Out     0.570     6.181       -
    rcnt_sub[9]                         Net      -        -       0.000     -           1
    fifo_inst.Rnum[9]                   DFFC     D        In      -         6.181       -
    ==============================================================================================
    Total path delay (propagation time + setup) of 6.242 is 3.506(56.2%) logic and 2.736(43.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      5.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      6.146
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.901

        Number of logic level(s):                11
        Starting point:                          fifo_inst.Big\.rq2_wptr[6] / Q
        Ending point:                            fifo_inst.Rnum[8] / D
        The start point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    fifo_inst.Big\.rq2_wptr[6]          DFFC     Q        Out     0.243     0.243       -
    Big\.rq2_wptr[6]                    Net      -        -       0.596     -           12
    fifo_inst.rcnt_sub_v_0_i_o3[5]      LUT2     I1       In      -         0.839       -
    fifo_inst.rcnt_sub_v_0_i_o3[5]      LUT2     F        Out     0.570     1.409       -
    rcnt_sub_b_D0_0[5]                  Net      -        -       0.535     -           4
    fifo_inst.rcnt_sub_v_0_0_a2[2]      LUT4     I3       In      -         1.944       -
    fifo_inst.rcnt_sub_v_0_0_a2[2]      LUT4     F        Out     0.371     2.315       -
    rcnt_sub_b_D0_0[2]                  Net      -        -       0.535     -           2
    fifo_inst.rcnt_sub_0_axb_2_lofx     LUT4     I2       In      -         2.850       -
    fifo_inst.rcnt_sub_0_axb_2_lofx     LUT4     F        Out     0.462     3.312       -
    rcnt_sub_0_axb_2_lofx               Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_0_cry_2_0        ALU      I0       In      -         3.847       -
    fifo_inst.rcnt_sub_0_cry_2_0        ALU      COUT     Out     0.549     4.396       -
    rcnt_sub_0_cry_2                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_3_0        ALU      CIN      In      -         4.396       -
    fifo_inst.rcnt_sub_0_cry_3_0        ALU      COUT     Out     0.035     4.431       -
    rcnt_sub_0_cry_3                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_4_0        ALU      CIN      In      -         4.431       -
    fifo_inst.rcnt_sub_0_cry_4_0        ALU      COUT     Out     0.035     4.466       -
    rcnt_sub_0_cry_4                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_5_0        ALU      CIN      In      -         4.466       -
    fifo_inst.rcnt_sub_0_cry_5_0        ALU      COUT     Out     0.035     4.501       -
    rcnt_sub_0_cry_5                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_6_0        ALU      CIN      In      -         4.501       -
    fifo_inst.rcnt_sub_0_cry_6_0        ALU      COUT     Out     0.035     4.536       -
    rcnt_sub_0_cry_6                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_7_0        ALU      CIN      In      -         4.536       -
    fifo_inst.rcnt_sub_0_cry_7_0        ALU      COUT     Out     0.035     4.571       -
    rcnt_sub_0_cry_7                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_8_0        ALU      CIN      In      -         4.571       -
    fifo_inst.rcnt_sub_0_cry_8_0        ALU      SUM      Out     0.470     5.041       -
    rcnt_sub0[8]                        Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_m[8]             LUT4     I1       In      -         5.576       -
    fifo_inst.rcnt_sub_m[8]             LUT4     F        Out     0.570     6.146       -
    rcnt_sub[8]                         Net      -        -       0.000     -           1
    fifo_inst.Rnum[8]                   DFFC     D        In      -         6.146       -
    ==============================================================================================
    Total path delay (propagation time + setup) of 6.207 is 3.471(55.9%) logic and 2.736(44.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      5.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      6.111
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.866

        Number of logic level(s):                10
        Starting point:                          fifo_inst.Big\.rq2_wptr[6] / Q
        Ending point:                            fifo_inst.Rnum[7] / D
        The start point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    fifo_inst.Big\.rq2_wptr[6]          DFFC     Q        Out     0.243     0.243       -
    Big\.rq2_wptr[6]                    Net      -        -       0.596     -           12
    fifo_inst.rcnt_sub_v_0_i_o3[5]      LUT2     I1       In      -         0.839       -
    fifo_inst.rcnt_sub_v_0_i_o3[5]      LUT2     F        Out     0.570     1.409       -
    rcnt_sub_b_D0_0[5]                  Net      -        -       0.535     -           4
    fifo_inst.rcnt_sub_v_0_0_a2[2]      LUT4     I3       In      -         1.944       -
    fifo_inst.rcnt_sub_v_0_0_a2[2]      LUT4     F        Out     0.371     2.315       -
    rcnt_sub_b_D0_0[2]                  Net      -        -       0.535     -           2
    fifo_inst.rcnt_sub_0_axb_2_lofx     LUT4     I2       In      -         2.850       -
    fifo_inst.rcnt_sub_0_axb_2_lofx     LUT4     F        Out     0.462     3.312       -
    rcnt_sub_0_axb_2_lofx               Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_0_cry_2_0        ALU      I0       In      -         3.847       -
    fifo_inst.rcnt_sub_0_cry_2_0        ALU      COUT     Out     0.549     4.396       -
    rcnt_sub_0_cry_2                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_3_0        ALU      CIN      In      -         4.396       -
    fifo_inst.rcnt_sub_0_cry_3_0        ALU      COUT     Out     0.035     4.431       -
    rcnt_sub_0_cry_3                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_4_0        ALU      CIN      In      -         4.431       -
    fifo_inst.rcnt_sub_0_cry_4_0        ALU      COUT     Out     0.035     4.466       -
    rcnt_sub_0_cry_4                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_5_0        ALU      CIN      In      -         4.466       -
    fifo_inst.rcnt_sub_0_cry_5_0        ALU      COUT     Out     0.035     4.501       -
    rcnt_sub_0_cry_5                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_6_0        ALU      CIN      In      -         4.501       -
    fifo_inst.rcnt_sub_0_cry_6_0        ALU      COUT     Out     0.035     4.536       -
    rcnt_sub_0_cry_6                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_7_0        ALU      CIN      In      -         4.536       -
    fifo_inst.rcnt_sub_0_cry_7_0        ALU      SUM      Out     0.470     5.006       -
    rcnt_sub0[7]                        Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_m[7]             LUT4     I1       In      -         5.541       -
    fifo_inst.rcnt_sub_m[7]             LUT4     F        Out     0.570     6.111       -
    rcnt_sub[7]                         Net      -        -       0.000     -           1
    fifo_inst.Rnum[7]                   DFFC     D        In      -         6.111       -
    ==============================================================================================
    Total path delay (propagation time + setup) of 6.172 is 3.436(55.7%) logic and 2.736(44.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      5.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      6.099
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.854

        Number of logic level(s):                11
        Starting point:                          fifo_inst.Big\.rq2_wptr[6] / Q
        Ending point:                            fifo_inst.Rnum[9] / D
        The start point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK

    Instance / Net                                Pin      Pin               Arrival     No. of
    Name                                 Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------
    fifo_inst.Big\.rq2_wptr[6]           DFFC     Q        Out     0.243     0.243       -
    Big\.rq2_wptr[6]                     Net      -        -       0.596     -           12
    fifo_inst.rcnt_sub_v_0_i_o3[5]       LUT2     I1       In      -         0.839       -
    fifo_inst.rcnt_sub_v_0_i_o3[5]       LUT2     F        Out     0.570     1.409       -
    rcnt_sub_b_D0_0[5]                   Net      -        -       0.535     -           4
    fifo_inst.rcnt_sub_0_axb_3           LUT4     I3       In      -         1.944       -
    fifo_inst.rcnt_sub_0_axb_3           LUT4     F        Out     0.371     2.315       -
    rcnt_sub_0_axb_3                     Net      -        -       0.401     -           1
    fifo_inst.rcnt_sub_0_cry_3_0_RNO     LUT2     I0       In      -         2.716       -
    fifo_inst.rcnt_sub_0_cry_3_0_RNO     LUT2     F        Out     0.549     3.265       -
    rcnt_sub_0_cry_3_0_RNO               Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_0_cry_3_0         ALU      I0       In      -         3.800       -
    fifo_inst.rcnt_sub_0_cry_3_0         ALU      COUT     Out     0.549     4.349       -
    rcnt_sub_0_cry_3                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_4_0         ALU      CIN      In      -         4.349       -
    fifo_inst.rcnt_sub_0_cry_4_0         ALU      COUT     Out     0.035     4.384       -
    rcnt_sub_0_cry_4                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_5_0         ALU      CIN      In      -         4.384       -
    fifo_inst.rcnt_sub_0_cry_5_0         ALU      COUT     Out     0.035     4.419       -
    rcnt_sub_0_cry_5                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_6_0         ALU      CIN      In      -         4.419       -
    fifo_inst.rcnt_sub_0_cry_6_0         ALU      COUT     Out     0.035     4.454       -
    rcnt_sub_0_cry_6                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_7_0         ALU      CIN      In      -         4.454       -
    fifo_inst.rcnt_sub_0_cry_7_0         ALU      COUT     Out     0.035     4.489       -
    rcnt_sub_0_cry_7                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_8_0         ALU      CIN      In      -         4.489       -
    fifo_inst.rcnt_sub_0_cry_8_0         ALU      COUT     Out     0.035     4.524       -
    rcnt_sub_0_cry_8                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_s_9_0           ALU      CIN      In      -         4.524       -
    fifo_inst.rcnt_sub_0_s_9_0           ALU      SUM      Out     0.470     4.994       -
    rcnt_sub0[9]                         Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_m[9]              LUT4     I1       In      -         5.529       -
    fifo_inst.rcnt_sub_m[9]              LUT4     F        Out     0.570     6.099       -
    rcnt_sub[9]                          Net      -        -       0.000     -           1
    fifo_inst.Rnum[9]                    DFFC     D        In      -         6.099       -
    ===============================================================================================
    Total path delay (propagation time + setup) of 6.160 is 3.558(57.8%) logic and 2.602(42.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      5.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      6.099
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.854

        Number of logic level(s):                12
        Starting point:                          fifo_inst.Big\.rq2_wptr[5] / Q
        Ending point:                            fifo_inst.Rnum[9] / D
        The start point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    fifo_inst.Big\.rq2_wptr[5]          DFFC     Q        Out     0.243     0.243       -
    Big\.rq2_wptr[5]                    Net      -        -       0.535     -           10
    fifo_inst.rcnt_sub_v_0_i_o3[5]      LUT2     I0       In      -         0.778       -
    fifo_inst.rcnt_sub_v_0_i_o3[5]      LUT2     F        Out     0.549     1.327       -
    rcnt_sub_b_D0_0[5]                  Net      -        -       0.535     -           4
    fifo_inst.rcnt_sub_v_0_0_a2[2]      LUT4     I3       In      -         1.862       -
    fifo_inst.rcnt_sub_v_0_0_a2[2]      LUT4     F        Out     0.371     2.233       -
    rcnt_sub_b_D0_0[2]                  Net      -        -       0.535     -           2
    fifo_inst.rcnt_sub_0_axb_2_lofx     LUT4     I2       In      -         2.768       -
    fifo_inst.rcnt_sub_0_axb_2_lofx     LUT4     F        Out     0.462     3.230       -
    rcnt_sub_0_axb_2_lofx               Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_0_cry_2_0        ALU      I0       In      -         3.765       -
    fifo_inst.rcnt_sub_0_cry_2_0        ALU      COUT     Out     0.549     4.314       -
    rcnt_sub_0_cry_2                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_3_0        ALU      CIN      In      -         4.314       -
    fifo_inst.rcnt_sub_0_cry_3_0        ALU      COUT     Out     0.035     4.349       -
    rcnt_sub_0_cry_3                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_4_0        ALU      CIN      In      -         4.349       -
    fifo_inst.rcnt_sub_0_cry_4_0        ALU      COUT     Out     0.035     4.384       -
    rcnt_sub_0_cry_4                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_5_0        ALU      CIN      In      -         4.384       -
    fifo_inst.rcnt_sub_0_cry_5_0        ALU      COUT     Out     0.035     4.419       -
    rcnt_sub_0_cry_5                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_6_0        ALU      CIN      In      -         4.419       -
    fifo_inst.rcnt_sub_0_cry_6_0        ALU      COUT     Out     0.035     4.454       -
    rcnt_sub_0_cry_6                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_7_0        ALU      CIN      In      -         4.454       -
    fifo_inst.rcnt_sub_0_cry_7_0        ALU      COUT     Out     0.035     4.489       -
    rcnt_sub_0_cry_7                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_cry_8_0        ALU      CIN      In      -         4.489       -
    fifo_inst.rcnt_sub_0_cry_8_0        ALU      COUT     Out     0.035     4.524       -
    rcnt_sub_0_cry_8                    Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_0_s_9_0          ALU      CIN      In      -         4.524       -
    fifo_inst.rcnt_sub_0_s_9_0          ALU      SUM      Out     0.470     4.994       -
    rcnt_sub0[9]                        Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_m[9]             LUT4     I1       In      -         5.529       -
    fifo_inst.rcnt_sub_m[9]             LUT4     F        Out     0.570     6.099       -
    rcnt_sub[9]                         Net      -        -       0.000     -           1
    fifo_inst.Rnum[9]                   DFFC     D        In      -         6.099       -
    ==============================================================================================
    Total path delay (propagation time + setup) of 6.160 is 3.485(56.6%) logic and 2.675(43.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: fifo_dma_write_32_128|WrClk
    ====================================

    Starting Points with Worst Slack
    ********************************

                               Starting                                                          Arrival
    Instance                   Reference                       Type     Pin     Net              Time        Slack
                               Clock
    ---------------------------------------------------------------------------------------------------------------
    fifo_inst.Full             fifo_dma_write_32_128|WrClk     DFFC     Q       Full             0.243       -0.917
    fifo_inst.Big\.wbin[0]     fifo_dma_write_32_128|WrClk     DFFC     Q       Big\.wbin[0]     0.243       -0.020
    fifo_inst.Big\.wbin[1]     fifo_dma_write_32_128|WrClk     DFFC     Q       Big\.wbin[1]     0.243       0.015
    fifo_inst.Big\.wbin[2]     fifo_dma_write_32_128|WrClk     DFFC     Q       Big\.wbin[2]     0.243       0.050
    fifo_inst.Big\.wbin[3]     fifo_dma_write_32_128|WrClk     DFFC     Q       Big\.wbin[3]     0.243       0.085
    fifo_inst.Big\.wbin[4]     fifo_dma_write_32_128|WrClk     DFFC     Q       Big\.wbin[4]     0.243       0.120
    fifo_inst.Big\.wbin[5]     fifo_dma_write_32_128|WrClk     DFFC     Q       Big\.wbin[5]     0.243       0.211
    fifo_inst.Big\.wbin[6]     fifo_dma_write_32_128|WrClk     DFFC     Q       Big\.wbin[6]     0.243       0.319
    fifo_inst.Big\.wbin[7]     fifo_dma_write_32_128|WrClk     DFFC     Q       Big\.wbin[7]     0.243       0.631
    fifo_inst.Big\.wbin[8]     fifo_dma_write_32_128|WrClk     DFFC     Q       Big\.wbin[8]     0.243       1.101
    ===============================================================================================================

    Ending Points with Worst Slack
    ******************************

                               Starting                                                            Required
    Instance                   Reference                       Type     Pin     Net                Time         Slack
                               Clock
    ------------------------------------------------------------------------------------------------------------------
    fifo_inst.Full             fifo_dma_write_32_128|WrClk     DFFC     D       wfull_val_NE_i     5.135        -0.917
    fifo_inst.Big\.wptr[8]     fifo_dma_write_32_128|WrClk     DFFC     D       wgraynext[8]       5.135        0.986
    fifo_inst.Big\.wptr[7]     fifo_dma_write_32_128|WrClk     DFFC     D       wgraynext[7]       5.135        1.021
    fifo_inst.Big\.wptr[6]     fifo_dma_write_32_128|WrClk     DFFC     D       wgraynext[6]       5.135        1.056
    fifo_inst.Big\.wptr[5]     fifo_dma_write_32_128|WrClk     DFFC     D       wgraynext[5]       5.135        1.091
    fifo_inst.Big\.wptr[4]     fifo_dma_write_32_128|WrClk     DFFC     D       wgraynext[4]       5.135        1.126
    fifo_inst.Big\.wptr[3]     fifo_dma_write_32_128|WrClk     DFFC     D       wgraynext[3]       5.135        1.161
    fifo_inst.Big\.wptr[2]     fifo_dma_write_32_128|WrClk     DFFC     D       wgraynext[2]       5.135        1.196
    fifo_inst.Big\.wptr[1]     fifo_dma_write_32_128|WrClk     DFFC     D       wgraynext[1]       5.135        1.231
    fifo_inst.Big\.wptr[0]     fifo_dma_write_32_128|WrClk     DFFC     D       wgraynext[0]       5.135        1.266
    ==================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.196
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.135

        - Propagation time:                      6.052
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.917

        Number of logic level(s):                12
        Starting point:                          fifo_inst.Full / Q
        Ending point:                            fifo_inst.Full / D
        The start point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    fifo_inst.Full                      DFFC          Q        Out     0.243     0.243       -
    Full                                Net           -        -       0.535     -           3
    fifo_inst.Big\.un1_WrEn             LUT2          I0       In      -         0.778       -
    fifo_inst.Big\.un1_WrEn             LUT2          F        Out     0.549     1.327       -
    Big\.un1_WrEn                       Net           -        -       0.862     -           1
    fifo_inst.wbin_num_next_cry_0_0     ALU           CIN      In      -         2.189       -
    fifo_inst.wbin_num_next_cry_0_0     ALU           COUT     Out     0.035     2.224       -
    wbin_num_next_cry_0                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_1_0     ALU           CIN      In      -         2.224       -
    fifo_inst.wbin_num_next_cry_1_0     ALU           COUT     Out     0.035     2.259       -
    wbin_num_next_cry_1                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_2_0     ALU           CIN      In      -         2.259       -
    fifo_inst.wbin_num_next_cry_2_0     ALU           COUT     Out     0.035     2.294       -
    wbin_num_next_cry_2                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_3_0     ALU           CIN      In      -         2.294       -
    fifo_inst.wbin_num_next_cry_3_0     ALU           COUT     Out     0.035     2.329       -
    wbin_num_next_cry_3                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_4_0     ALU           CIN      In      -         2.329       -
    fifo_inst.wbin_num_next_cry_4_0     ALU           COUT     Out     0.035     2.364       -
    wbin_num_next_cry_4                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_5_0     ALU           CIN      In      -         2.364       -
    fifo_inst.wbin_num_next_cry_5_0     ALU           SUM      Out     0.470     2.834       -
    wbin_num_next[5]                    Net           -        -       0.535     -           5
    fifo_inst.wfull_val_3               LUT3          I1       In      -         3.369       -
    fifo_inst.wfull_val_3               LUT3          F        Out     0.570     3.939       -
    wfull_val_3                         Net           -        -       0.535     -           4
    fifo_inst.wfull_val_NE_6_0_0        LUT4          I2       In      -         4.474       -
    fifo_inst.wfull_val_NE_6_0_0        LUT4          F        Out     0.462     4.936       -
    wfull_val_NE_6_0_0                  Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6_0          MUX2_LUT5     I0       In      -         4.936       -
    fifo_inst.wfull_val_NE_6_0          MUX2_LUT5     O        Out     0.105     5.041       -
    wfull_val_NE_6_0                    Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     I0       In      -         5.041       -
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     O        Out     0.105     5.146       -
    wfull_val_NE_6                      Net           -        -       0.535     -           1
    fifo_inst.wfull_val_NE_i            LUT4          I3       In      -         5.681       -
    fifo_inst.wfull_val_NE_i            LUT4          F        Out     0.371     6.052       -
    wfull_val_NE_i                      Net           -        -       0.000     -           1
    fifo_inst.Full                      DFFC          D        In      -         6.052       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 6.113 is 3.111(50.9%) logic and 3.002(49.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      5.196
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.135

        - Propagation time:                      6.052
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.917

        Number of logic level(s):                12
        Starting point:                          fifo_inst.Full / Q
        Ending point:                            fifo_inst.Full / D
        The start point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    fifo_inst.Full                      DFFC          Q        Out     0.243     0.243       -
    Full                                Net           -        -       0.535     -           3
    fifo_inst.Big\.un1_WrEn             LUT2          I0       In      -         0.778       -
    fifo_inst.Big\.un1_WrEn             LUT2          F        Out     0.549     1.327       -
    Big\.un1_WrEn                       Net           -        -       0.862     -           1
    fifo_inst.wbin_num_next_cry_0_0     ALU           CIN      In      -         2.189       -
    fifo_inst.wbin_num_next_cry_0_0     ALU           COUT     Out     0.035     2.224       -
    wbin_num_next_cry_0                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_1_0     ALU           CIN      In      -         2.224       -
    fifo_inst.wbin_num_next_cry_1_0     ALU           COUT     Out     0.035     2.259       -
    wbin_num_next_cry_1                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_2_0     ALU           CIN      In      -         2.259       -
    fifo_inst.wbin_num_next_cry_2_0     ALU           COUT     Out     0.035     2.294       -
    wbin_num_next_cry_2                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_3_0     ALU           CIN      In      -         2.294       -
    fifo_inst.wbin_num_next_cry_3_0     ALU           COUT     Out     0.035     2.329       -
    wbin_num_next_cry_3                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_4_0     ALU           CIN      In      -         2.329       -
    fifo_inst.wbin_num_next_cry_4_0     ALU           COUT     Out     0.035     2.364       -
    wbin_num_next_cry_4                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_5_0     ALU           CIN      In      -         2.364       -
    fifo_inst.wbin_num_next_cry_5_0     ALU           SUM      Out     0.470     2.834       -
    wbin_num_next[5]                    Net           -        -       0.535     -           5
    fifo_inst.wfull_val_3               LUT3          I1       In      -         3.369       -
    fifo_inst.wfull_val_3               LUT3          F        Out     0.570     3.939       -
    wfull_val_3                         Net           -        -       0.535     -           4
    fifo_inst.wfull_val_NE_6_0_1        LUT4          I2       In      -         4.474       -
    fifo_inst.wfull_val_NE_6_0_1        LUT4          F        Out     0.462     4.936       -
    wfull_val_NE_6_0_1                  Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6_0          MUX2_LUT5     I1       In      -         4.936       -
    fifo_inst.wfull_val_NE_6_0          MUX2_LUT5     O        Out     0.105     5.041       -
    wfull_val_NE_6_0                    Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     I0       In      -         5.041       -
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     O        Out     0.105     5.146       -
    wfull_val_NE_6                      Net           -        -       0.535     -           1
    fifo_inst.wfull_val_NE_i            LUT4          I3       In      -         5.681       -
    fifo_inst.wfull_val_NE_i            LUT4          F        Out     0.371     6.052       -
    wfull_val_NE_i                      Net           -        -       0.000     -           1
    fifo_inst.Full                      DFFC          D        In      -         6.052       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 6.113 is 3.111(50.9%) logic and 3.002(49.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      5.196
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.135

        - Propagation time:                      6.052
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.917

        Number of logic level(s):                12
        Starting point:                          fifo_inst.Full / Q
        Ending point:                            fifo_inst.Full / D
        The start point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    fifo_inst.Full                      DFFC          Q        Out     0.243     0.243       -
    Full                                Net           -        -       0.535     -           3
    fifo_inst.Big\.un1_WrEn             LUT2          I0       In      -         0.778       -
    fifo_inst.Big\.un1_WrEn             LUT2          F        Out     0.549     1.327       -
    Big\.un1_WrEn                       Net           -        -       0.862     -           1
    fifo_inst.wbin_num_next_cry_0_0     ALU           CIN      In      -         2.189       -
    fifo_inst.wbin_num_next_cry_0_0     ALU           COUT     Out     0.035     2.224       -
    wbin_num_next_cry_0                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_1_0     ALU           CIN      In      -         2.224       -
    fifo_inst.wbin_num_next_cry_1_0     ALU           COUT     Out     0.035     2.259       -
    wbin_num_next_cry_1                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_2_0     ALU           CIN      In      -         2.259       -
    fifo_inst.wbin_num_next_cry_2_0     ALU           COUT     Out     0.035     2.294       -
    wbin_num_next_cry_2                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_3_0     ALU           CIN      In      -         2.294       -
    fifo_inst.wbin_num_next_cry_3_0     ALU           COUT     Out     0.035     2.329       -
    wbin_num_next_cry_3                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_4_0     ALU           CIN      In      -         2.329       -
    fifo_inst.wbin_num_next_cry_4_0     ALU           COUT     Out     0.035     2.364       -
    wbin_num_next_cry_4                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_5_0     ALU           CIN      In      -         2.364       -
    fifo_inst.wbin_num_next_cry_5_0     ALU           SUM      Out     0.470     2.834       -
    wbin_num_next[5]                    Net           -        -       0.535     -           5
    fifo_inst.wfull_val_3               LUT3          I1       In      -         3.369       -
    fifo_inst.wfull_val_3               LUT3          F        Out     0.570     3.939       -
    wfull_val_3                         Net           -        -       0.535     -           4
    fifo_inst.wfull_val_NE_6_1_1        LUT4          I2       In      -         4.474       -
    fifo_inst.wfull_val_NE_6_1_1        LUT4          F        Out     0.462     4.936       -
    wfull_val_NE_6_1_1                  Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6_1          MUX2_LUT5     I1       In      -         4.936       -
    fifo_inst.wfull_val_NE_6_1          MUX2_LUT5     O        Out     0.105     5.041       -
    wfull_val_NE_6_1                    Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     I1       In      -         5.041       -
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     O        Out     0.105     5.146       -
    wfull_val_NE_6                      Net           -        -       0.535     -           1
    fifo_inst.wfull_val_NE_i            LUT4          I3       In      -         5.681       -
    fifo_inst.wfull_val_NE_i            LUT4          F        Out     0.371     6.052       -
    wfull_val_NE_i                      Net           -        -       0.000     -           1
    fifo_inst.Full                      DFFC          D        In      -         6.052       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 6.113 is 3.111(50.9%) logic and 3.002(49.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      5.196
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.135

        - Propagation time:                      6.052
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.917

        Number of logic level(s):                12
        Starting point:                          fifo_inst.Full / Q
        Ending point:                            fifo_inst.Full / D
        The start point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    fifo_inst.Full                      DFFC          Q        Out     0.243     0.243       -
    Full                                Net           -        -       0.535     -           3
    fifo_inst.Big\.un1_WrEn             LUT2          I0       In      -         0.778       -
    fifo_inst.Big\.un1_WrEn             LUT2          F        Out     0.549     1.327       -
    Big\.un1_WrEn                       Net           -        -       0.862     -           1
    fifo_inst.wbin_num_next_cry_0_0     ALU           CIN      In      -         2.189       -
    fifo_inst.wbin_num_next_cry_0_0     ALU           COUT     Out     0.035     2.224       -
    wbin_num_next_cry_0                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_1_0     ALU           CIN      In      -         2.224       -
    fifo_inst.wbin_num_next_cry_1_0     ALU           COUT     Out     0.035     2.259       -
    wbin_num_next_cry_1                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_2_0     ALU           CIN      In      -         2.259       -
    fifo_inst.wbin_num_next_cry_2_0     ALU           COUT     Out     0.035     2.294       -
    wbin_num_next_cry_2                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_3_0     ALU           CIN      In      -         2.294       -
    fifo_inst.wbin_num_next_cry_3_0     ALU           COUT     Out     0.035     2.329       -
    wbin_num_next_cry_3                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_4_0     ALU           CIN      In      -         2.329       -
    fifo_inst.wbin_num_next_cry_4_0     ALU           COUT     Out     0.035     2.364       -
    wbin_num_next_cry_4                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_5_0     ALU           CIN      In      -         2.364       -
    fifo_inst.wbin_num_next_cry_5_0     ALU           SUM      Out     0.470     2.834       -
    wbin_num_next[5]                    Net           -        -       0.535     -           5
    fifo_inst.wfull_val_3               LUT3          I1       In      -         3.369       -
    fifo_inst.wfull_val_3               LUT3          F        Out     0.570     3.939       -
    wfull_val_3                         Net           -        -       0.535     -           4
    fifo_inst.wfull_val_NE_6_1_0        LUT4          I2       In      -         4.474       -
    fifo_inst.wfull_val_NE_6_1_0        LUT4          F        Out     0.462     4.936       -
    wfull_val_NE_6_1_0                  Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6_1          MUX2_LUT5     I0       In      -         4.936       -
    fifo_inst.wfull_val_NE_6_1          MUX2_LUT5     O        Out     0.105     5.041       -
    wfull_val_NE_6_1                    Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     I1       In      -         5.041       -
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     O        Out     0.105     5.146       -
    wfull_val_NE_6                      Net           -        -       0.535     -           1
    fifo_inst.wfull_val_NE_i            LUT4          I3       In      -         5.681       -
    fifo_inst.wfull_val_NE_i            LUT4          F        Out     0.371     6.052       -
    wfull_val_NE_i                      Net           -        -       0.000     -           1
    fifo_inst.Full                      DFFC          D        In      -         6.052       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 6.113 is 3.111(50.9%) logic and 3.002(49.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      5.196
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.135

        - Propagation time:                      5.996
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.861

        Number of logic level(s):                13
        Starting point:                          fifo_inst.Full / Q
        Ending point:                            fifo_inst.Full / D
        The start point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK
        The end   point is clocked by            fifo_dma_write_32_128|WrClk [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    fifo_inst.Full                      DFFC          Q        Out     0.243     0.243       -
    Full                                Net           -        -       0.535     -           3
    fifo_inst.Big\.un1_WrEn             LUT2          I0       In      -         0.778       -
    fifo_inst.Big\.un1_WrEn             LUT2          F        Out     0.549     1.327       -
    Big\.un1_WrEn                       Net           -        -       0.862     -           1
    fifo_inst.wbin_num_next_cry_0_0     ALU           CIN      In      -         2.189       -
    fifo_inst.wbin_num_next_cry_0_0     ALU           COUT     Out     0.035     2.224       -
    wbin_num_next_cry_0                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_1_0     ALU           CIN      In      -         2.224       -
    fifo_inst.wbin_num_next_cry_1_0     ALU           COUT     Out     0.035     2.259       -
    wbin_num_next_cry_1                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_2_0     ALU           CIN      In      -         2.259       -
    fifo_inst.wbin_num_next_cry_2_0     ALU           COUT     Out     0.035     2.294       -
    wbin_num_next_cry_2                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_3_0     ALU           CIN      In      -         2.294       -
    fifo_inst.wbin_num_next_cry_3_0     ALU           COUT     Out     0.035     2.329       -
    wbin_num_next_cry_3                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_4_0     ALU           CIN      In      -         2.329       -
    fifo_inst.wbin_num_next_cry_4_0     ALU           COUT     Out     0.035     2.364       -
    wbin_num_next_cry_4                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_5_0     ALU           CIN      In      -         2.364       -
    fifo_inst.wbin_num_next_cry_5_0     ALU           COUT     Out     0.035     2.399       -
    wbin_num_next_cry_5                 Net           -        -       0.000     -           1
    fifo_inst.wbin_num_next_cry_6_0     ALU           CIN      In      -         2.399       -
    fifo_inst.wbin_num_next_cry_6_0     ALU           SUM      Out     0.470     2.869       -
    wbin_num_next[6]                    Net           -        -       0.535     -           5
    fifo_inst.wfull_val_4               LUT3          I1       In      -         3.404       -
    fifo_inst.wfull_val_4               LUT3          F        Out     0.570     3.974       -
    wfull_val_4                         Net           -        -       0.535     -           4
    fifo_inst.wfull_val_NE_6_0_0        LUT4          I3       In      -         4.509       -
    fifo_inst.wfull_val_NE_6_0_0        LUT4          F        Out     0.371     4.880       -
    wfull_val_NE_6_0_0                  Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6_0          MUX2_LUT5     I0       In      -         4.880       -
    fifo_inst.wfull_val_NE_6_0          MUX2_LUT5     O        Out     0.105     4.985       -
    wfull_val_NE_6_0                    Net           -        -       0.000     -           1
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     I0       In      -         4.985       -
    fifo_inst.wfull_val_NE_6            MUX2_LUT6     O        Out     0.105     5.090       -
    wfull_val_NE_6                      Net           -        -       0.535     -           1
    fifo_inst.wfull_val_NE_i            LUT4          I3       In      -         5.625       -
    fifo_inst.wfull_val_NE_i            LUT4          F        Out     0.371     5.996       -
    wfull_val_NE_i                      Net           -        -       0.000     -           1
    fifo_inst.Full                      DFFC          D        In      -         5.996       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 6.057 is 3.055(50.4%) logic and 3.002(49.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                           Starting                                                    Arrival
    Instance                               Reference     Type     Pin     Net                          Time        Slack
                                           Clock
    --------------------------------------------------------------------------------------------------------------------
    fifo_inst.rcnt_sub_1_cry_1_0_RNO       System        INV      O       rbin_num_i[1]                0.000       2.449
    fifo_inst.rcnt_sub_1_cry_3_0_RNO       System        INV      O       rbin_num_i[3]                0.000       2.519
    fifo_inst.rcnt_sub_1_cry_4_0_RNO       System        INV      O       rbin_num_i[4]                0.000       2.554
    fifo_inst.rcnt_sub_1_cry_5_0_RNO       System        INV      O       rbin_num_i[5]                0.000       2.589
    fifo_inst.rcnt_sub_1_cry_6_0_RNO       System        INV      O       Big\.rq2_wptr_i[6]           0.000       2.624
    fifo_inst.rcnt_sub_1_cry_3_0_RNO_1     System        INV      O       rcnt_sub_1_cry_3_0_RNO_1     0.000       2.697
    fifo_inst.Full_RNIJKO                  System        INV      O       Full_i                       0.000       4.623
    fifo_inst.Big\.wdata_q_rst_RNO         System        INV      O       Empty_i                      0.000       4.710
    ====================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                      Starting                                        Required
    Instance                          Reference     Type      Pin     Net             Time         Slack
                                      Clock
    ----------------------------------------------------------------------------------------------------
    fifo_inst.Rnum[9]                 System        DFFC      D       rcnt_sub[9]     5.245        2.449
    fifo_inst.Rnum[8]                 System        DFFC      D       rcnt_sub[8]     5.245        2.484
    fifo_inst.Rnum[7]                 System        DFFC      D       rcnt_sub[7]     5.245        2.519
    fifo_inst.Rnum[6]                 System        DFFC      D       rcnt_sub[6]     5.245        2.554
    fifo_inst.Rnum[5]                 System        DFFC      D       rcnt_sub[5]     5.245        2.589
    fifo_inst.Rnum[4]                 System        DFFC      D       rcnt_sub[4]     5.245        2.624
    fifo_inst.Rnum[3]                 System        DFFC      D       rcnt_sub[3]     5.245        2.659
    fifo_inst.Rnum[2]                 System        DFFC      D       rcnt_sub[2]     5.245        2.694
    fifo_inst.Rnum[1]                 System        DFFC      D       rcnt_sub[1]     5.245        3.164
    fifo_inst.mem_2_0_mem_2_0_0_0     System        SDPX9     CEA     Full_i          5.158        4.623
    ====================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.245

        - Propagation time:                      2.796
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 2.449

        Number of logic level(s):                10
        Starting point:                          fifo_inst.rcnt_sub_1_cry_1_0_RNO / O
        Ending point:                            fifo_inst.Rnum[9] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            fifo_dma_write_32_128|RdClk [rising] on pin CLK

    Instance / Net                                Pin      Pin               Arrival     No. of
    Name                                 Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------
    fifo_inst.rcnt_sub_1_cry_1_0_RNO     INV      O        Out     0.000     0.000       -
    rbin_num_i[1]                        Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_1_cry_1_0         ALU      I0       In      -         0.535       -
    fifo_inst.rcnt_sub_1_cry_1_0         ALU      COUT     Out     0.549     1.084       -
    rcnt_sub_1_cry_1                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_1_cry_2_0         ALU      CIN      In      -         1.084       -
    fifo_inst.rcnt_sub_1_cry_2_0         ALU      COUT     Out     0.035     1.119       -
    rcnt_sub_1_cry_2                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_1_cry_3_0         ALU      CIN      In      -         1.119       -
    fifo_inst.rcnt_sub_1_cry_3_0         ALU      COUT     Out     0.035     1.154       -
    rcnt_sub_1_cry_3                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_1_cry_4_0         ALU      CIN      In      -         1.154       -
    fifo_inst.rcnt_sub_1_cry_4_0         ALU      COUT     Out     0.035     1.189       -
    rcnt_sub_1_cry_4                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_1_cry_5_0         ALU      CIN      In      -         1.189       -
    fifo_inst.rcnt_sub_1_cry_5_0         ALU      COUT     Out     0.035     1.224       -
    rcnt_sub_1_cry_5                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_1_cry_6_0         ALU      CIN      In      -         1.224       -
    fifo_inst.rcnt_sub_1_cry_6_0         ALU      COUT     Out     0.035     1.259       -
    rcnt_sub_1_cry_6                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_1_cry_7_0         ALU      CIN      In      -         1.259       -
    fifo_inst.rcnt_sub_1_cry_7_0         ALU      COUT     Out     0.035     1.294       -
    rcnt_sub_1_cry_7                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_1_cry_8_0         ALU      CIN      In      -         1.294       -
    fifo_inst.rcnt_sub_1_cry_8_0         ALU      COUT     Out     0.035     1.329       -
    rcnt_sub_1_cry_8                     Net      -        -       0.000     -           1
    fifo_inst.rcnt_sub_1_s_9_0           ALU      CIN      In      -         1.329       -
    fifo_inst.rcnt_sub_1_s_9_0           ALU      SUM      Out     0.470     1.799       -
    rcnt_sub1[9]                         Net      -        -       0.535     -           1
    fifo_inst.rcnt_sub_m[9]              LUT4     I2       In      -         2.334       -
    fifo_inst.rcnt_sub_m[9]              LUT4     F        Out     0.462     2.796       -
    rcnt_sub[9]                          Net      -        -       0.000     -           1
    fifo_inst.Rnum[9]                    DFFC     D        In      -         2.796       -
    ===============================================================================================
    Total path delay (propagation time + setup) of 2.857 is 1.787(62.5%) logic and 1.070(37.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 227MB peak: 228MB)

    Finished timing report (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 227MB peak: 228MB)

    ---------------------------------------
    Resource Usage Report for fifo_dma_write_32_128

    Mapping to part: gw2a_18pbga256-8
    Cell usage:
    ALU             42 uses
    DFFC            91 uses
    DFFCE           10 uses
    DFFNP           4 uses
    DFFP            1 use
    GSR             1 use
    INV             8 uses
    MUX2_LUT5       5 uses
    MUX2_LUT6       2 uses
    SDP             1 use
    SDPX9           3 uses
    LUT2            39 uses
    LUT3            17 uses
    LUT4            33 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   106 of 15552 (0%)

    RAM/ROM usage summary
    Block Rams : 4 of 46 (8%)

    Total load per clock:
       fifo_dma_write_32_128|WrClk: 48
       fifo_dma_write_32_128|RdClk: 66

    @S |Mapping Summary:
    Total  LUTs: 89 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 75MB peak: 228MB)

    Process took 0h:00m:08s realtime, 0h:00m:07s cputime
    # Thu Dec 19 10:08:03 2019

    ###########################################################]

`