D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\bin64\m_generic.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1   -part GW2A_18  -package PBGA256  -grade -8    -maxfan 10000 -RWCheckOnRam 0 -block -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synlog\report\fifo_dma_write_32_128_fpga_mapper.xml -merge_inferred_clocks 0  -implementation  rev_1  -flow mapping  -multisrs  -ovm  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128.vm   -autoconstraint  -freq 150.000   D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synwork\fifo_dma_write_32_128_prem.srd  -sap  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128.sap  -otap  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128.tap  -omap  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128.map  -devicelib  D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\generic\gw2a.v  -ologparam  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\syntmp\fifo_dma_write_32_128.plg  -osyn  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128.srm  -prjdir  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\  -prjname  FIFO  -log  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synlog\fifo_dma_write_32_128_fpga_mapper.srr  -sn  2019.03  -jobname  "fpga_mapper" 
relcom:..\..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\rev_1 -part GW2A_18 -package PBGA256 -grade -8 -maxfan 10000 -RWCheckOnRam 0 -block -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile ..\synlog\report\fifo_dma_write_32_128_fpga_mapper.xml -merge_inferred_clocks 0 -implementation rev_1 -flow mapping -multisrs -ovm ..\fifo_dma_write_32_128.vm -autoconstraint -freq 150.000 ..\synwork\fifo_dma_write_32_128_prem.srd -sap ..\fifo_dma_write_32_128.sap -otap ..\fifo_dma_write_32_128.tap -omap ..\fifo_dma_write_32_128.map -devicelib ..\..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\generic\gw2a.v -ologparam fifo_dma_write_32_128.plg -osyn ..\fifo_dma_write_32_128.srm -prjdir ..\..\ -prjname FIFO -log ..\synlog\fifo_dma_write_32_128_fpga_mapper.srr -sn 2019.03 -jobname "fpga_mapper"
rc:1 success:1 runtime:9
file:..\fifo_dma_write_32_128.vm|io:o|time:1576721282|size:65121|exec:0|csum:
file:..\synwork\fifo_dma_write_32_128_prem.srd|io:i|time:1576721273|size:46220|exec:0|csum:F8965881F9002CF1DDB3547980FB248B
file:..\fifo_dma_write_32_128.sap|io:o|time:1576721274|size:237|exec:0|csum:
file:..\fifo_dma_write_32_128.tap|io:o|time:0|size:-1|exec:0|csum:
file:..\fifo_dma_write_32_128.map|io:o|time:1576721283|size:28|exec:0|csum:
file:..\..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\generic\gw2a.v|io:i|time:1575572956|size:163815|exec:0|csum:9E2600B864B99F5A90D449698CC6DFCB
file:fifo_dma_write_32_128.plg|io:o|time:1576721283|size:1146|exec:0|csum:
file:..\fifo_dma_write_32_128.srm|io:o|time:1576721281|size:5290|exec:0|csum:
file:..\synlog\fifo_dma_write_32_128_fpga_mapper.srr|io:o|time:1576721283|size:79223|exec:0|csum:
file:..\..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\bin64\m_generic.exe|io:i|time:1575571358|size:39936512|exec:1|csum:350A231ED38336BB11E83024B56EB85B
