
#Begin clock constraint
define_clock -name {_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock} {n:_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock} -period 6.306 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 3.153 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {DDR3_Memory_Interface_Top|clk} {p:DDR3_Memory_Interface_Top|clk} -period 3.424 -clockgroup Autoconstr_clkgroup_1 -rise 0.000 -fall 1.712 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock} {n:_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock} -period 66667.000 -clockgroup Autoconstr_clkgroup_2 -rise 0.000 -fall 33333.500 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock} {n:_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock} -period 66667.000 -clockgroup Autoconstr_clkgroup_3 -rise 0.000 -fall 33333.500 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock} {n:_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock} -period 66667.000 -clockgroup Autoconstr_clkgroup_4 -rise 0.000 -fall 33333.500 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock} {n:_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock} -period 66667.000 -clockgroup Autoconstr_clkgroup_5 -rise 0.000 -fall 33333.500 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock} {n:_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock} -period 66667.000 -clockgroup Autoconstr_clkgroup_6 -rise 0.000 -fall 33333.500 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock} {n:_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock} -period 66667.000 -clockgroup Autoconstr_clkgroup_7 -rise 0.000 -fall 33333.500 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock} {n:_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock} -period 66667.000 -clockgroup Autoconstr_clkgroup_8 -rise 0.000 -fall 33333.500 -route 0.000 
#End clock constraint
