Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | E:\IP_verify\1.9.6\IP_web\Gowin_Scaler_RefDesign_DDR300MHz\Gowin_Scaler_RefDesign_DDR300MHz\scaler_example_design_live\project\impl\synthesize\rev_1\scaler_ref_design_live.vm
Physical Constraints File | E:\IP_verify\1.9.6\IP_web\Gowin_Scaler_RefDesign_DDR300MHz\Gowin_Scaler_RefDesign_DDR300MHz\scaler_example_design_live\project\src\scaler_test_top.cst
Timing Constraint File | E:\IP_verify\1.9.6\IP_web\Gowin_Scaler_RefDesign_DDR300MHz\Gowin_Scaler_RefDesign_DDR300MHz\scaler_example_design_live\project\src\scaler_ref_design_live.sdc
GOWIN version | V1.9.6Beta
Part Number | GW2A-LV18PG484C8/I7
Created Time | Wed Jul 01 18:05:55 2020
Legal Announcement | Copyright (C)2014-2020 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 0.95V 85C
Hold Delay Model | Fast 1.05V 0C
Numbers of Paths Analyzed | 12219
Numbers of Endpoints Analyzed | 12573
Numbers of Falling Endpoints | 8
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
clk_x4 | Base | 3.333 | 300.030 | 0.000 | 1.667 |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4
clk_x4i | Base | 3.333 | 300.030 | 0.000 | 1.667 |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4i
dma_clk | Base | 13.333 | 75.002 | 0.000 | 6.667 |  |  | dma_clk
I_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  | I_clk
gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.667 | 150.000 | 0.000 | 3.333 | I_clk_ibuf/I | I_clk | gw_pll_inst/rpll_inst/CLKOUT
gw_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.667 | 150.000 | 0.000 | 3.333 | I_clk_ibuf/I | I_clk | gw_pll_inst/rpll_inst/CLKOUTP
gw_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 13.333 | 75.000 | 0.000 | 6.667 | I_clk_ibuf/I | I_clk | gw_pll_inst/rpll_inst/CLKOUTD
gw_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | I_clk_ibuf/I | I_clk | gw_pll_inst/rpll_inst/CLKOUTD3
pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.667 | 150.000 | 0.000 | 3.333 | I_clk_ibuf/I | I_clk | pix_pll_inst/rpll_inst/CLKOUT
pix_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.667 | 150.000 | 0.000 | 3.333 | I_clk_ibuf/I | I_clk | pix_pll_inst/rpll_inst/CLKOUTP
pix_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 13.333 | 75.000 | 0.000 | 6.667 | I_clk_ibuf/I | I_clk | pix_pll_inst/rpll_inst/CLKOUTD
pix_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | I_clk_ibuf/I | I_clk | pix_pll_inst/rpll_inst/CLKOUTD3
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP.default_gen_clk | Generated | 3.333 | 300.000 | 1.667 | 0.000 | I_clk_ibuf/I | I_clk | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD.default_gen_clk | Generated | 6.667 | 150.000 | 0.000 | 3.333 | I_clk_ibuf/I | I_clk | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | I_clk_ibuf/I | I_clk | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | clk_x4i | 300.030(MHz) | 1436.782(MHz) | 1 | TOP
2 | dma_clk | 75.002(MHz) | 109.222(MHz) | 8 | TOP
3 | I_clk | 50.000(MHz) | 155.372(MHz) | 6 | TOP
4 | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | 150.000(MHz) | 172.075(MHz) | 9 | TOP
5 | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk | 150.000(MHz) | 179.573(MHz) | 8 | TOP

#### No timing paths to get frequency of clk_x4!

#### No timing paths to get frequency of gw_pll_inst/rpll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of gw_pll_inst/rpll_inst/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of gw_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

#### No timing paths to get frequency of pix_pll_inst/rpll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of pix_pll_inst/rpll_inst/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of pix_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

#### No timing paths to get frequency of DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3.default_gen_clk!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
clk_x4 | Setup | 0.000 | 0
clk_x4 | Hold | 0.000 | 0
clk_x4i | Setup | 0.000 | 0
clk_x4i | Hold | 0.000 | 0
dma_clk | Setup | 0.000 | 0
dma_clk | Hold | 0.000 | 0
I_clk | Setup | 0.000 | 0
I_clk | Hold | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.855 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_de_32b/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Full_Z/D | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.576
2 | 1.098 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/D | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.334
3 | 1.112 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[0]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.319
4 | 1.187 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hor_wrdot_Z[3]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[2]/D | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.244
5 | 1.187 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hor_wrdot_Z[3]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[0]/D | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.244
6 | 1.292 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[8]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.139
7 | 1.292 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[5]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.139
8 | 1.292 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[3]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.139
9 | 1.292 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[4]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.139
10 | 1.292 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[0]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.139
11 | 1.292 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[7]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.139
12 | 1.292 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[6]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.139
13 | 1.296 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.136
14 | 1.296 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[1]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.136
15 | 1.376 | testpattern_inst/V_cnt_Z[5]/Q | testpattern_inst/V_cnt_Z[11]/D | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.055
16 | 1.412 | testpattern_inst/V_cnt_Z[5]/Q | testpattern_inst/V_cnt_Z[10]/D | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 5.020
17 | 1.447 | testpattern_inst/V_cnt_Z[5]/Q | testpattern_inst/V_cnt_Z[9]/D | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 4.985
18 | 1.480 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[7]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 4.952
19 | 1.480 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[6]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 4.952
20 | 1.480 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[5]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 4.952
21 | 1.480 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[4]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 4.952
22 | 1.480 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[9]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 4.952
23 | 1.480 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[8]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 4.952
24 | 1.482 | testpattern_inst/V_cnt_Z[5]/Q | testpattern_inst/V_cnt_Z[8]/D | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 4.950
25 | 1.483 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[1]/CE | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 6.667 | 0.000 | 4.948

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.080 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[7]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/DI7 | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.329
2 | 0.086 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[6]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0/DI6 | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.335
3 | 0.194 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/WREA | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
4 | 0.194 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/WREA | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
5 | 0.194 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/WREA | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
6 | 0.194 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/WREA | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
7 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3/WREB | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.335
8 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0/WREB | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
9 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1/WREB | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.335
10 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2/WREB | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.335
11 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0/WREB | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
12 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0/WREB | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
13 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0/WREB | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
14 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0/WREB | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.335
15 | 0.201 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[1]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/DI1 | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.450
16 | 0.206 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[5]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0/DI5 | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.455
17 | 0.206 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[5]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/DI5 | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.455
18 | 0.216 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[2]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/DI2 | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.465
19 | 0.233 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[80]/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[20].u_cmd_gen/D0 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.328
20 | 0.234 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[15]/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen/D6 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329
21 | 0.234 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[14]/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen/D4 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329
22 | 0.234 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[39]/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/D6 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329
23 | 0.234 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[38]/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/D4 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329
24 | 0.234 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[37]/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/D2 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329
25 | 0.234 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[36]/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/D0 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.736 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[0]_Z/CLEAR | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.334
2 | 1.736 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[0]_Z/CLEAR | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.334
3 | 1.751 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.320
4 | 1.751 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.320
5 | 1.751 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[0]_Z/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.320
6 | 1.751 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.320
7 | 1.751 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[0]_Z/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.320
8 | 1.768 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[9]/CLEAR | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.303
9 | 1.768 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[3]_Z/CLEAR | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.303
10 | 1.768 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[2]_Z/CLEAR | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.303
11 | 1.768 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[2]_Z/CLEAR | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.303
12 | 1.768 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[4]_Z/CLEAR | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.303
13 | 1.768 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[3]_Z/CLEAR | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.303
14 | 1.823 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/PRESET | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 3.333 | -0.028 | 1.303
15 | 1.823 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[0]/PRESET | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | 3.333 | -0.028 | 1.303
16 | 1.894 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[8]_Z/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.176
17 | 1.894 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[8]_Z/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.176
18 | 1.906 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[8]/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.165
19 | 1.906 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[9]/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.165
20 | 1.906 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.165
21 | 1.906 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[8]/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.165
22 | 1.906 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.165
23 | 1.917 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[7]_Z/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.153
24 | 1.917 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.153
25 | 1.917 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z/CLEAR | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F] | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | 0.028 | 1.153

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
2 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[23]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
3 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[24]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
4 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
5 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[22]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
6 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_Z/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
7 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_fast/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
8 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
9 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
10 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
11 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_wr_grant/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
12 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
13 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[25]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
14 | 1.598 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.609
15 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
16 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[4]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
17 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[5]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
18 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[4]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
19 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
20 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[3]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
21 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[6]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
22 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[5]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
23 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[2]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
24 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[0]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614
25 | 1.603 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[0]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.614

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | cnt_vs_Z[9]
2 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | cnt_vs_Z[7]
3 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | cnt_vs_Z[3]
4 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | testpattern_inst/De_hcnt_Z[9]
5 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | testpattern_inst/De_vcnt_Z[5]
6 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | testpattern_inst/Color_bar_Z[0]
7 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | testpattern_inst/Gray_d1_Z[3]
8 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/kx_Z[20]
9 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].iram_rddata0[2][6]
10 | 2.007 | 3.007 | 1.000 | Low Pulse Width | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/loop[2].q_r[2][3]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.855
Data Arrival Time | 6.777
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_de_32b
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Full_Z
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R21C39[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_de_32b/CLK
1.433 | 0.232 | tC2Q | RF | 1 | R21C39[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/dma_de_32b/Q
1.586 | 0.153 | tNET | FF | 1 | R21C39[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_32b_cZ/I0
2.141 | 0.555 | tINS | FF | 5 | R21C39[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_32b_cZ/F
2.672 | 0.531 | tNET | FF | 1 | R20C35[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.un1_WrEn_cZ/I1
3.242 | 0.570 | tINS | FR | 1 | R20C35[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.un1_WrEn_cZ/F
3.386 | 0.144 | tNET | RR | 2 | R20C35[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_0_0/I1
3.757 | 0.371 | tINS | RF | 1 | R20C35[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_0_0/COUT
3.757 | 0.000 | tNET | FF | 2 | R20C35[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_1_0/CIN
3.792 | 0.035 | tINS | FF | 1 | R20C35[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_1_0/COUT
3.792 | 0.000 | tNET | FF | 2 | R20C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_2_0/CIN
3.828 | 0.035 | tINS | FF | 1 | R20C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_2_0/COUT
3.828 | 0.000 | tNET | FF | 2 | R20C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_3_0/CIN
3.863 | 0.035 | tINS | FF | 1 | R20C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_3_0/COUT
3.863 | 0.000 | tNET | FF | 2 | R20C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_4_0/CIN
3.898 | 0.035 | tINS | FF | 1 | R20C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_4_0/COUT
3.898 | 0.000 | tNET | FF | 2 | R20C36[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_5_0/CIN
4.368 | 0.470 | tINS | FF | 5 | R20C36[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wbin_num_next_cry_5_0/SUM
4.625 | 0.257 | tNET | FF | 1 | R20C38[3][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_3_cZ/I1
5.180 | 0.555 | tINS | FF | 4 | R20C38[3][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_3_cZ/F
5.378 | 0.198 | tNET | FF | 1 | R20C37[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_NE_6_0_0_cZ/I2
5.840 | 0.462 | tINS | FR | 1 | R20C37[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_NE_6_0_0_cZ/F
5.840 | 0.000 | tNET | RR | 1 | R20C37[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_NE_6_0_cZ/I0
5.945 | 0.105 | tINS | RR | 1 | R20C37[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_NE_6_0_cZ/O
5.945 | 0.000 | tNET | RR | 1 | R20C37[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_NE_6_cZ/I0
6.050 | 0.105 | tINS | RR | 1 | R20C37[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_NE_6_cZ/O
6.228 | 0.178 | tNET | RR | 1 | R20C37[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_NE_i_cZ/I3
6.777 | 0.549 | tINS | RR | 1 | R20C37[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/wfull_val_NE_i_cZ/F
6.777 | 0.000 | tNET | RR | 1 | R20C37[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Full_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C37[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Full_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Full_Z
7.632 | -0.035 | tSu |  | 1 | R20C37[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Full_Z

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 9
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 3.883, 69.629%; route: 1.462, 26.211%; tC2Q: 0.232, 4.160%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path2

Path Summary:

Slack | 1.098
Data Arrival Time | 6.534
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R16C42[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b/CLK
1.433 | 0.232 | tC2Q | RF | 23 | R16C42[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b/Q
1.897 | 0.465 | tNET | FF | 1 | R18C43[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata14_cZ/I1
2.350 | 0.453 | tINS | FF | 2 | R18C43[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata14_cZ/F
2.509 | 0.159 | tNET | FF | 2 | R18C43[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_0_0/I1
2.880 | 0.371 | tINS | FF | 1 | R18C43[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_0_0/COUT
2.880 | 0.000 | tNET | FF | 2 | R18C43[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_1_0/CIN
2.915 | 0.035 | tINS | FF | 1 | R18C43[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_1_0/COUT
2.915 | 0.000 | tNET | FF | 2 | R18C43[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_2_0/CIN
2.950 | 0.035 | tINS | FF | 1 | R18C43[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_2_0/COUT
2.950 | 0.000 | tNET | FF | 2 | R18C43[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_3_0/CIN
2.986 | 0.035 | tINS | FF | 1 | R18C43[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_3_0/COUT
2.986 | 0.000 | tNET | FF | 2 | R18C44[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_4_0/CIN
3.021 | 0.035 | tINS | FF | 1 | R18C44[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_4_0/COUT
3.021 | 0.000 | tNET | FF | 2 | R18C44[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_5_0/CIN
3.491 | 0.470 | tINS | FF | 5 | R18C44[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_5_0/SUM
3.998 | 0.507 | tNET | FF | 1 | R20C42[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_3_cZ/I1
4.553 | 0.555 | tINS | FF | 4 | R20C42[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_3_cZ/F
4.983 | 0.430 | tNET | FF | 1 | R21C41[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_0_0_cZ/I2
5.538 | 0.555 | tINS | FF | 1 | R21C41[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_0_0_cZ/F
5.538 | 0.000 | tNET | FF | 1 | R21C41[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_0_cZ/I0
5.641 | 0.103 | tINS | FF | 1 | R21C41[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_0_cZ/O
5.641 | 0.000 | tNET | FF | 1 | R21C41[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_cZ/I0
5.744 | 0.103 | tINS | FF | 1 | R21C41[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_cZ/O
6.163 | 0.419 | tNET | FF | 1 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_i_cZ/I3
6.534 | 0.371 | tINS | FF | 1 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_i_cZ/F
6.534 | 0.000 | tNET | FF | 1 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
7.632 | -0.035 | tSu |  | 1 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 8
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 3.122, 58.529%; route: 1.980, 37.121%; tC2Q: 0.232, 4.350%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path3

Path Summary:

Slack | 1.112
Data Arrival Time | 6.520
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[0]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.520 | 1.381 | tNET | RR | 1 | R26C27[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[0]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R26C27[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[0]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[0]
7.632 | -0.035 | tSu |  | 1 | R26C27[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 15.660%; route: 4.254, 79.978%; tC2Q: 0.232, 4.362%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path4

Path Summary:

Slack | 1.187
Data Arrival Time | 6.445
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hor_wrdot_Z[3]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[2]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R29C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hor_wrdot_Z[3]/CLK
1.433 | 0.232 | tC2Q | RF | 3 | R29C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hor_wrdot_Z[3]/Q
2.323 | 0.890 | tNET | FF | 2 | R26C37[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_3_0/I0
2.872 | 0.549 | tINS | FR | 1 | R26C37[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_3_0/COUT
2.872 | 0.000 | tNET | RR | 2 | R26C38[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_4_0/CIN
2.907 | 0.035 | tINS | RF | 1 | R26C38[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_4_0/COUT
2.907 | 0.000 | tNET | FF | 2 | R26C38[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_5_0/CIN
2.942 | 0.035 | tINS | FF | 1 | R26C38[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_5_0/COUT
2.942 | 0.000 | tNET | FF | 2 | R26C38[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_6_0/CIN
2.978 | 0.035 | tINS | FF | 1 | R26C38[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_6_0/COUT
2.978 | 0.000 | tNET | FF | 2 | R26C38[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_7_0/CIN
3.013 | 0.035 | tINS | FF | 1 | R26C38[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_7_0/COUT
3.013 | 0.000 | tNET | FF | 2 | R26C38[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_8_0/CIN
3.048 | 0.035 | tINS | FF | 1 | R26C38[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_8_0/COUT
3.048 | 0.000 | tNET | FF | 2 | R26C38[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_9_0/CIN
3.083 | 0.035 | tINS | FF | 1 | R26C38[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_9_0/COUT
3.083 | 0.000 | tNET | FF | 2 | R26C39[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_10_0/CIN
3.118 | 0.035 | tINS | FF | 1 | R26C39[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_10_0/COUT
3.118 | 0.000 | tNET | FF | 2 | R26C39[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_11_0/CIN
3.154 | 0.035 | tINS | FF | 3 | R26C39[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_11_0/COUT
4.316 | 1.163 | tNET | FF | 1 | R35C38[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/hfifo_wren_cZ/I2
4.833 | 0.517 | tINS | FF | 4 | R35C38[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/hfifo_wren_cZ/F
5.875 | 1.042 | tNET | FF | 1 | R41C44[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_4_cZ[2]/I0
6.445 | 0.570 | tINS | FR | 1 | R41C44[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_4_cZ[2]/F
6.445 | 0.000 | tNET | RR | 1 | R41C44[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R41C44[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[2]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[2]
7.632 | -0.035 | tSu |  | 1 | R41C44[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 6
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.918, 36.564%; route: 3.095, 59.012%; tC2Q: 0.232, 4.424%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path5

Path Summary:

Slack | 1.187
Data Arrival Time | 6.445
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hor_wrdot_Z[3]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[0]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R29C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hor_wrdot_Z[3]/CLK
1.433 | 0.232 | tC2Q | RF | 3 | R29C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hor_wrdot_Z[3]/Q
2.323 | 0.890 | tNET | FF | 2 | R26C37[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_3_0/I0
2.872 | 0.549 | tINS | FR | 1 | R26C37[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_3_0/COUT
2.872 | 0.000 | tNET | RR | 2 | R26C38[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_4_0/CIN
2.907 | 0.035 | tINS | RF | 1 | R26C38[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_4_0/COUT
2.907 | 0.000 | tNET | FF | 2 | R26C38[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_5_0/CIN
2.942 | 0.035 | tINS | FF | 1 | R26C38[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_5_0/COUT
2.942 | 0.000 | tNET | FF | 2 | R26C38[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_6_0/CIN
2.978 | 0.035 | tINS | FF | 1 | R26C38[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_6_0/COUT
2.978 | 0.000 | tNET | FF | 2 | R26C38[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_7_0/CIN
3.013 | 0.035 | tINS | FF | 1 | R26C38[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_7_0/COUT
3.013 | 0.000 | tNET | FF | 2 | R26C38[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_8_0/CIN
3.048 | 0.035 | tINS | FF | 1 | R26C38[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_8_0/COUT
3.048 | 0.000 | tNET | FF | 2 | R26C38[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_9_0/CIN
3.083 | 0.035 | tINS | FF | 1 | R26C38[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_9_0/COUT
3.083 | 0.000 | tNET | FF | 2 | R26C39[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_10_0/CIN
3.118 | 0.035 | tINS | FF | 1 | R26C39[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_10_0/COUT
3.118 | 0.000 | tNET | FF | 2 | R26C39[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_11_0/CIN
3.154 | 0.035 | tINS | FF | 3 | R26C39[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_hor_wren_cry_11_0/COUT
4.316 | 1.163 | tNET | FF | 1 | R35C38[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/hfifo_wren_cZ/I2
4.833 | 0.517 | tINS | FF | 4 | R35C38[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/hfifo_wren_cZ/F
5.875 | 1.042 | tNET | FF | 1 | R41C44[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_2_cZ[0]/I0
6.445 | 0.570 | tINS | FR | 1 | R41C44[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_2_cZ[0]/F
6.445 | 0.000 | tNET | RR | 1 | R41C44[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R41C44[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[0]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[0]
7.632 | -0.035 | tSu |  | 1 | R41C44[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_rden_Z[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 6
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.918, 36.564%; route: 3.095, 59.012%; tC2Q: 0.232, 4.424%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path6

Path Summary:

Slack | 1.292
Data Arrival Time | 6.340
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[8]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.340 | 1.201 | tNET | RR | 1 | R34C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[8]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R34C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[8]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[8]
7.632 | -0.035 | tSu |  | 1 | R34C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.209%; route: 4.074, 79.277%; tC2Q: 0.232, 4.514%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path7

Path Summary:

Slack | 1.292
Data Arrival Time | 6.340
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[5]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.340 | 1.201 | tNET | RR | 1 | R34C29[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[5]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R34C29[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[5]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[5]
7.632 | -0.035 | tSu |  | 1 | R34C29[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.209%; route: 4.074, 79.277%; tC2Q: 0.232, 4.514%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path8

Path Summary:

Slack | 1.292
Data Arrival Time | 6.340
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[3]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.340 | 1.201 | tNET | RR | 1 | R33C27[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[3]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R33C27[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[3]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[3]
7.632 | -0.035 | tSu |  | 1 | R33C27[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[3]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.209%; route: 4.074, 79.277%; tC2Q: 0.232, 4.514%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path9

Path Summary:

Slack | 1.292
Data Arrival Time | 6.340
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[4]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.340 | 1.201 | tNET | RR | 1 | R34C29[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[4]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R34C29[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[4]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[4]
7.632 | -0.035 | tSu |  | 1 | R34C29[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.209%; route: 4.074, 79.277%; tC2Q: 0.232, 4.514%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path10

Path Summary:

Slack | 1.292
Data Arrival Time | 6.340
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[0]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.340 | 1.201 | tNET | RR | 1 | R33C27[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[0]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R33C27[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[0]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[0]
7.632 | -0.035 | tSu |  | 1 | R33C27[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[0]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.209%; route: 4.074, 79.277%; tC2Q: 0.232, 4.514%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path11

Path Summary:

Slack | 1.292
Data Arrival Time | 6.340
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[7]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.340 | 1.201 | tNET | RR | 1 | R34C29[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[7]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R34C29[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[7]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[7]
7.632 | -0.035 | tSu |  | 1 | R34C29[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.209%; route: 4.074, 79.277%; tC2Q: 0.232, 4.514%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path12

Path Summary:

Slack | 1.292
Data Arrival Time | 6.340
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[6]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.340 | 1.201 | tNET | RR | 1 | R34C29[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[6]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R34C29[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[6]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[6]
7.632 | -0.035 | tSu |  | 1 | R34C29[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[6]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.209%; route: 4.074, 79.277%; tC2Q: 0.232, 4.514%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path13

Path Summary:

Slack | 1.296
Data Arrival Time | 6.336
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.336 | 1.197 | tNET | RR | 1 | R34C28[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R34C28[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]
7.632 | -0.035 | tSu |  | 1 | R34C28[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.220%; route: 4.071, 79.262%; tC2Q: 0.232, 4.518%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path14

Path Summary:

Slack | 1.296
Data Arrival Time | 6.336
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[1]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.336 | 1.197 | tNET | RR | 1 | R34C28[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[1]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R34C28[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[1]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[1]
7.632 | -0.035 | tSu |  | 1 | R34C28[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.220%; route: 4.071, 79.262%; tC2Q: 0.232, 4.518%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path15

Path Summary:

Slack | 1.376
Data Arrival Time | 6.256
Data Required Time | 7.632
From | testpattern_inst/V_cnt_Z[5]
To | testpattern_inst/V_cnt_Z[11]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R41C48[0][B] | testpattern_inst/V_cnt_Z[5]/CLK
1.433 | 0.232 | tC2Q | RF | 4 | R41C48[0][B] | testpattern_inst/V_cnt_Z[5]/Q
2.111 | 0.679 | tNET | FF | 1 | R44C47[3][A] | testpattern_inst/Pout_de_w_i_a2_1_0_cZ/I0
2.681 | 0.570 | tINS | FR | 2 | R44C47[3][A] | testpattern_inst/Pout_de_w_i_a2_1_0_cZ/F
2.684 | 0.003 | tNET | RR | 1 | R44C47[3][B] | testpattern_inst/Pout_de_w_i_a3_1_cZ/I0
3.146 | 0.462 | tINS | RR | 2 | R44C47[3][B] | testpattern_inst/Pout_de_w_i_a3_1_cZ/F
3.320 | 0.174 | tNET | RR | 1 | R44C48[0][B] | testpattern_inst/Pout_de_w_i_o2_cZ/I0
3.691 | 0.371 | tINS | RF | 12 | R44C48[0][B] | testpattern_inst/Pout_de_w_i_o2_cZ/F
4.121 | 0.431 | tNET | FF | 1 | R42C47[3][A] | testpattern_inst/V_cnt_cry_0_RNO_cZ[0]/I0
4.691 | 0.570 | tINS | FR | 1 | R42C47[3][A] | testpattern_inst/V_cnt_cry_0_RNO_cZ[0]/F
4.864 | 0.172 | tNET | RR | 2 | R41C47[1][A] | testpattern_inst/V_cnt_cry_0[0]/I0
5.434 | 0.570 | tINS | RR | 1 | R41C47[1][A] | testpattern_inst/V_cnt_cry_0[0]/COUT
5.434 | 0.000 | tNET | RR | 2 | R41C47[1][B] | testpattern_inst/V_cnt_cry_0[1]/CIN
5.469 | 0.035 | tINS | RF | 1 | R41C47[1][B] | testpattern_inst/V_cnt_cry_0[1]/COUT
5.469 | 0.000 | tNET | FF | 2 | R41C47[2][A] | testpattern_inst/V_cnt_cry_0[2]/CIN
5.504 | 0.035 | tINS | FF | 1 | R41C47[2][A] | testpattern_inst/V_cnt_cry_0[2]/COUT
5.504 | 0.000 | tNET | FF | 2 | R41C47[2][B] | testpattern_inst/V_cnt_cry_0[3]/CIN
5.540 | 0.035 | tINS | FF | 1 | R41C47[2][B] | testpattern_inst/V_cnt_cry_0[3]/COUT
5.540 | 0.000 | tNET | FF | 2 | R41C48[0][A] | testpattern_inst/V_cnt_cry_0[4]/CIN
5.575 | 0.035 | tINS | FF | 1 | R41C48[0][A] | testpattern_inst/V_cnt_cry_0[4]/COUT
5.575 | 0.000 | tNET | FF | 2 | R41C48[0][B] | testpattern_inst/V_cnt_cry_0[5]/CIN
5.610 | 0.035 | tINS | FF | 1 | R41C48[0][B] | testpattern_inst/V_cnt_cry_0[5]/COUT
5.610 | 0.000 | tNET | FF | 2 | R41C48[1][A] | testpattern_inst/V_cnt_cry_0[6]/CIN
5.645 | 0.035 | tINS | FF | 1 | R41C48[1][A] | testpattern_inst/V_cnt_cry_0[6]/COUT
5.645 | 0.000 | tNET | FF | 2 | R41C48[1][B] | testpattern_inst/V_cnt_cry_0[7]/CIN
5.680 | 0.035 | tINS | FF | 1 | R41C48[1][B] | testpattern_inst/V_cnt_cry_0[7]/COUT
5.680 | 0.000 | tNET | FF | 2 | R41C48[2][A] | testpattern_inst/V_cnt_cry_0[8]/CIN
5.716 | 0.035 | tINS | FF | 1 | R41C48[2][A] | testpattern_inst/V_cnt_cry_0[8]/COUT
5.716 | 0.000 | tNET | FF | 2 | R41C48[2][B] | testpattern_inst/V_cnt_cry_0[9]/CIN
5.751 | 0.035 | tINS | FF | 1 | R41C48[2][B] | testpattern_inst/V_cnt_cry_0[9]/COUT
5.751 | 0.000 | tNET | FF | 2 | R41C49[0][A] | testpattern_inst/V_cnt_cry_0[10]/CIN
5.786 | 0.035 | tINS | FF | 1 | R41C49[0][A] | testpattern_inst/V_cnt_cry_0[10]/COUT
5.786 | 0.000 | tNET | FF | 2 | R41C49[0][B] | testpattern_inst/V_cnt_s_0[11]/CIN
6.256 | 0.470 | tINS | FF | 1 | R41C49[0][B] | testpattern_inst/V_cnt_s_0[11]/SUM
6.256 | 0.000 | tNET | FF | 1 | R41C49[0][B] | testpattern_inst/V_cnt_Z[11]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R41C49[0][B] | testpattern_inst/V_cnt_Z[11]/CLK
7.667 | -0.200 | tUnc |  |  |  | testpattern_inst/V_cnt_Z[11]
7.632 | -0.035 | tSu |  | 1 | R41C49[0][B] | testpattern_inst/V_cnt_Z[11]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 8
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 3.365, 66.564%; route: 1.458, 28.847%; tC2Q: 0.232, 4.589%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path16

Path Summary:

Slack | 1.412
Data Arrival Time | 6.221
Data Required Time | 7.632
From | testpattern_inst/V_cnt_Z[5]
To | testpattern_inst/V_cnt_Z[10]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R41C48[0][B] | testpattern_inst/V_cnt_Z[5]/CLK
1.433 | 0.232 | tC2Q | RF | 4 | R41C48[0][B] | testpattern_inst/V_cnt_Z[5]/Q
2.111 | 0.679 | tNET | FF | 1 | R44C47[3][A] | testpattern_inst/Pout_de_w_i_a2_1_0_cZ/I0
2.681 | 0.570 | tINS | FR | 2 | R44C47[3][A] | testpattern_inst/Pout_de_w_i_a2_1_0_cZ/F
2.684 | 0.003 | tNET | RR | 1 | R44C47[3][B] | testpattern_inst/Pout_de_w_i_a3_1_cZ/I0
3.146 | 0.462 | tINS | RR | 2 | R44C47[3][B] | testpattern_inst/Pout_de_w_i_a3_1_cZ/F
3.320 | 0.174 | tNET | RR | 1 | R44C48[0][B] | testpattern_inst/Pout_de_w_i_o2_cZ/I0
3.691 | 0.371 | tINS | RF | 12 | R44C48[0][B] | testpattern_inst/Pout_de_w_i_o2_cZ/F
4.121 | 0.431 | tNET | FF | 1 | R42C47[3][A] | testpattern_inst/V_cnt_cry_0_RNO_cZ[0]/I0
4.691 | 0.570 | tINS | FR | 1 | R42C47[3][A] | testpattern_inst/V_cnt_cry_0_RNO_cZ[0]/F
4.864 | 0.172 | tNET | RR | 2 | R41C47[1][A] | testpattern_inst/V_cnt_cry_0[0]/I0
5.434 | 0.570 | tINS | RR | 1 | R41C47[1][A] | testpattern_inst/V_cnt_cry_0[0]/COUT
5.434 | 0.000 | tNET | RR | 2 | R41C47[1][B] | testpattern_inst/V_cnt_cry_0[1]/CIN
5.469 | 0.035 | tINS | RF | 1 | R41C47[1][B] | testpattern_inst/V_cnt_cry_0[1]/COUT
5.469 | 0.000 | tNET | FF | 2 | R41C47[2][A] | testpattern_inst/V_cnt_cry_0[2]/CIN
5.504 | 0.035 | tINS | FF | 1 | R41C47[2][A] | testpattern_inst/V_cnt_cry_0[2]/COUT
5.504 | 0.000 | tNET | FF | 2 | R41C47[2][B] | testpattern_inst/V_cnt_cry_0[3]/CIN
5.540 | 0.035 | tINS | FF | 1 | R41C47[2][B] | testpattern_inst/V_cnt_cry_0[3]/COUT
5.540 | 0.000 | tNET | FF | 2 | R41C48[0][A] | testpattern_inst/V_cnt_cry_0[4]/CIN
5.575 | 0.035 | tINS | FF | 1 | R41C48[0][A] | testpattern_inst/V_cnt_cry_0[4]/COUT
5.575 | 0.000 | tNET | FF | 2 | R41C48[0][B] | testpattern_inst/V_cnt_cry_0[5]/CIN
5.610 | 0.035 | tINS | FF | 1 | R41C48[0][B] | testpattern_inst/V_cnt_cry_0[5]/COUT
5.610 | 0.000 | tNET | FF | 2 | R41C48[1][A] | testpattern_inst/V_cnt_cry_0[6]/CIN
5.645 | 0.035 | tINS | FF | 1 | R41C48[1][A] | testpattern_inst/V_cnt_cry_0[6]/COUT
5.645 | 0.000 | tNET | FF | 2 | R41C48[1][B] | testpattern_inst/V_cnt_cry_0[7]/CIN
5.680 | 0.035 | tINS | FF | 1 | R41C48[1][B] | testpattern_inst/V_cnt_cry_0[7]/COUT
5.680 | 0.000 | tNET | FF | 2 | R41C48[2][A] | testpattern_inst/V_cnt_cry_0[8]/CIN
5.716 | 0.035 | tINS | FF | 1 | R41C48[2][A] | testpattern_inst/V_cnt_cry_0[8]/COUT
5.716 | 0.000 | tNET | FF | 2 | R41C48[2][B] | testpattern_inst/V_cnt_cry_0[9]/CIN
5.751 | 0.035 | tINS | FF | 1 | R41C48[2][B] | testpattern_inst/V_cnt_cry_0[9]/COUT
5.751 | 0.000 | tNET | FF | 2 | R41C49[0][A] | testpattern_inst/V_cnt_cry_0[10]/CIN
6.221 | 0.470 | tINS | FF | 1 | R41C49[0][A] | testpattern_inst/V_cnt_cry_0[10]/SUM
6.221 | 0.000 | tNET | FF | 1 | R41C49[0][A] | testpattern_inst/V_cnt_Z[10]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R41C49[0][A] | testpattern_inst/V_cnt_Z[10]/CLK
7.667 | -0.200 | tUnc |  |  |  | testpattern_inst/V_cnt_Z[10]
7.632 | -0.035 | tSu |  | 1 | R41C49[0][A] | testpattern_inst/V_cnt_Z[10]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 8
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 3.330, 66.329%; route: 1.458, 29.050%; tC2Q: 0.232, 4.621%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path17

Path Summary:

Slack | 1.447
Data Arrival Time | 6.186
Data Required Time | 7.632
From | testpattern_inst/V_cnt_Z[5]
To | testpattern_inst/V_cnt_Z[9]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R41C48[0][B] | testpattern_inst/V_cnt_Z[5]/CLK
1.433 | 0.232 | tC2Q | RF | 4 | R41C48[0][B] | testpattern_inst/V_cnt_Z[5]/Q
2.111 | 0.679 | tNET | FF | 1 | R44C47[3][A] | testpattern_inst/Pout_de_w_i_a2_1_0_cZ/I0
2.681 | 0.570 | tINS | FR | 2 | R44C47[3][A] | testpattern_inst/Pout_de_w_i_a2_1_0_cZ/F
2.684 | 0.003 | tNET | RR | 1 | R44C47[3][B] | testpattern_inst/Pout_de_w_i_a3_1_cZ/I0
3.146 | 0.462 | tINS | RR | 2 | R44C47[3][B] | testpattern_inst/Pout_de_w_i_a3_1_cZ/F
3.320 | 0.174 | tNET | RR | 1 | R44C48[0][B] | testpattern_inst/Pout_de_w_i_o2_cZ/I0
3.691 | 0.371 | tINS | RF | 12 | R44C48[0][B] | testpattern_inst/Pout_de_w_i_o2_cZ/F
4.121 | 0.431 | tNET | FF | 1 | R42C47[3][A] | testpattern_inst/V_cnt_cry_0_RNO_cZ[0]/I0
4.691 | 0.570 | tINS | FR | 1 | R42C47[3][A] | testpattern_inst/V_cnt_cry_0_RNO_cZ[0]/F
4.864 | 0.172 | tNET | RR | 2 | R41C47[1][A] | testpattern_inst/V_cnt_cry_0[0]/I0
5.434 | 0.570 | tINS | RR | 1 | R41C47[1][A] | testpattern_inst/V_cnt_cry_0[0]/COUT
5.434 | 0.000 | tNET | RR | 2 | R41C47[1][B] | testpattern_inst/V_cnt_cry_0[1]/CIN
5.469 | 0.035 | tINS | RF | 1 | R41C47[1][B] | testpattern_inst/V_cnt_cry_0[1]/COUT
5.469 | 0.000 | tNET | FF | 2 | R41C47[2][A] | testpattern_inst/V_cnt_cry_0[2]/CIN
5.504 | 0.035 | tINS | FF | 1 | R41C47[2][A] | testpattern_inst/V_cnt_cry_0[2]/COUT
5.504 | 0.000 | tNET | FF | 2 | R41C47[2][B] | testpattern_inst/V_cnt_cry_0[3]/CIN
5.540 | 0.035 | tINS | FF | 1 | R41C47[2][B] | testpattern_inst/V_cnt_cry_0[3]/COUT
5.540 | 0.000 | tNET | FF | 2 | R41C48[0][A] | testpattern_inst/V_cnt_cry_0[4]/CIN
5.575 | 0.035 | tINS | FF | 1 | R41C48[0][A] | testpattern_inst/V_cnt_cry_0[4]/COUT
5.575 | 0.000 | tNET | FF | 2 | R41C48[0][B] | testpattern_inst/V_cnt_cry_0[5]/CIN
5.610 | 0.035 | tINS | FF | 1 | R41C48[0][B] | testpattern_inst/V_cnt_cry_0[5]/COUT
5.610 | 0.000 | tNET | FF | 2 | R41C48[1][A] | testpattern_inst/V_cnt_cry_0[6]/CIN
5.645 | 0.035 | tINS | FF | 1 | R41C48[1][A] | testpattern_inst/V_cnt_cry_0[6]/COUT
5.645 | 0.000 | tNET | FF | 2 | R41C48[1][B] | testpattern_inst/V_cnt_cry_0[7]/CIN
5.680 | 0.035 | tINS | FF | 1 | R41C48[1][B] | testpattern_inst/V_cnt_cry_0[7]/COUT
5.680 | 0.000 | tNET | FF | 2 | R41C48[2][A] | testpattern_inst/V_cnt_cry_0[8]/CIN
5.716 | 0.035 | tINS | FF | 1 | R41C48[2][A] | testpattern_inst/V_cnt_cry_0[8]/COUT
5.716 | 0.000 | tNET | FF | 2 | R41C48[2][B] | testpattern_inst/V_cnt_cry_0[9]/CIN
6.186 | 0.470 | tINS | FF | 1 | R41C48[2][B] | testpattern_inst/V_cnt_cry_0[9]/SUM
6.186 | 0.000 | tNET | FF | 1 | R41C48[2][B] | testpattern_inst/V_cnt_Z[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R41C48[2][B] | testpattern_inst/V_cnt_Z[9]/CLK
7.667 | -0.200 | tUnc |  |  |  | testpattern_inst/V_cnt_Z[9]
7.632 | -0.035 | tSu |  | 1 | R41C48[2][B] | testpattern_inst/V_cnt_Z[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 8
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 3.295, 66.091%; route: 1.458, 29.255%; tC2Q: 0.232, 4.654%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path18

Path Summary:

Slack | 1.480
Data Arrival Time | 6.153
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[7]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.153 | 1.013 | tNET | RR | 1 | R27C29[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[7]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R27C29[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[7]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[7]
7.632 | -0.035 | tSu |  | 1 | R27C29[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[7]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.822%; route: 3.887, 78.493%; tC2Q: 0.232, 4.685%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path19

Path Summary:

Slack | 1.480
Data Arrival Time | 6.153
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[6]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.153 | 1.013 | tNET | RR | 1 | R27C29[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[6]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R27C29[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[6]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[6]
7.632 | -0.035 | tSu |  | 1 | R27C29[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[6]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.822%; route: 3.887, 78.493%; tC2Q: 0.232, 4.685%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path20

Path Summary:

Slack | 1.480
Data Arrival Time | 6.153
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[5]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.153 | 1.013 | tNET | RR | 1 | R25C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[5]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R25C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[5]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[5]
7.632 | -0.035 | tSu |  | 1 | R25C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[5]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.822%; route: 3.887, 78.493%; tC2Q: 0.232, 4.685%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path21

Path Summary:

Slack | 1.480
Data Arrival Time | 6.153
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[4]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.153 | 1.013 | tNET | RR | 1 | R25C29[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[4]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R25C29[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[4]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[4]
7.632 | -0.035 | tSu |  | 1 | R25C29[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[4]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.822%; route: 3.887, 78.493%; tC2Q: 0.232, 4.685%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path22

Path Summary:

Slack | 1.480
Data Arrival Time | 6.153
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[9]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.153 | 1.013 | tNET | RR | 1 | R27C29[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[9]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R27C29[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[9]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[9]
7.632 | -0.035 | tSu |  | 1 | R27C29[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[9]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.822%; route: 3.887, 78.493%; tC2Q: 0.232, 4.685%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path23

Path Summary:

Slack | 1.480
Data Arrival Time | 6.153
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[8]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.153 | 1.013 | tNET | RR | 1 | R27C29[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[8]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R27C29[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[8]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[8]
7.632 | -0.035 | tSu |  | 1 | R27C29[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.822%; route: 3.887, 78.493%; tC2Q: 0.232, 4.685%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path24

Path Summary:

Slack | 1.482
Data Arrival Time | 6.150
Data Required Time | 7.632
From | testpattern_inst/V_cnt_Z[5]
To | testpattern_inst/V_cnt_Z[8]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R41C48[0][B] | testpattern_inst/V_cnt_Z[5]/CLK
1.433 | 0.232 | tC2Q | RF | 4 | R41C48[0][B] | testpattern_inst/V_cnt_Z[5]/Q
2.111 | 0.679 | tNET | FF | 1 | R44C47[3][A] | testpattern_inst/Pout_de_w_i_a2_1_0_cZ/I0
2.681 | 0.570 | tINS | FR | 2 | R44C47[3][A] | testpattern_inst/Pout_de_w_i_a2_1_0_cZ/F
2.684 | 0.003 | tNET | RR | 1 | R44C47[3][B] | testpattern_inst/Pout_de_w_i_a3_1_cZ/I0
3.146 | 0.462 | tINS | RR | 2 | R44C47[3][B] | testpattern_inst/Pout_de_w_i_a3_1_cZ/F
3.320 | 0.174 | tNET | RR | 1 | R44C48[0][B] | testpattern_inst/Pout_de_w_i_o2_cZ/I0
3.691 | 0.371 | tINS | RF | 12 | R44C48[0][B] | testpattern_inst/Pout_de_w_i_o2_cZ/F
4.121 | 0.431 | tNET | FF | 1 | R42C47[3][A] | testpattern_inst/V_cnt_cry_0_RNO_cZ[0]/I0
4.691 | 0.570 | tINS | FR | 1 | R42C47[3][A] | testpattern_inst/V_cnt_cry_0_RNO_cZ[0]/F
4.864 | 0.172 | tNET | RR | 2 | R41C47[1][A] | testpattern_inst/V_cnt_cry_0[0]/I0
5.434 | 0.570 | tINS | RR | 1 | R41C47[1][A] | testpattern_inst/V_cnt_cry_0[0]/COUT
5.434 | 0.000 | tNET | RR | 2 | R41C47[1][B] | testpattern_inst/V_cnt_cry_0[1]/CIN
5.469 | 0.035 | tINS | RF | 1 | R41C47[1][B] | testpattern_inst/V_cnt_cry_0[1]/COUT
5.469 | 0.000 | tNET | FF | 2 | R41C47[2][A] | testpattern_inst/V_cnt_cry_0[2]/CIN
5.504 | 0.035 | tINS | FF | 1 | R41C47[2][A] | testpattern_inst/V_cnt_cry_0[2]/COUT
5.504 | 0.000 | tNET | FF | 2 | R41C47[2][B] | testpattern_inst/V_cnt_cry_0[3]/CIN
5.540 | 0.035 | tINS | FF | 1 | R41C47[2][B] | testpattern_inst/V_cnt_cry_0[3]/COUT
5.540 | 0.000 | tNET | FF | 2 | R41C48[0][A] | testpattern_inst/V_cnt_cry_0[4]/CIN
5.575 | 0.035 | tINS | FF | 1 | R41C48[0][A] | testpattern_inst/V_cnt_cry_0[4]/COUT
5.575 | 0.000 | tNET | FF | 2 | R41C48[0][B] | testpattern_inst/V_cnt_cry_0[5]/CIN
5.610 | 0.035 | tINS | FF | 1 | R41C48[0][B] | testpattern_inst/V_cnt_cry_0[5]/COUT
5.610 | 0.000 | tNET | FF | 2 | R41C48[1][A] | testpattern_inst/V_cnt_cry_0[6]/CIN
5.645 | 0.035 | tINS | FF | 1 | R41C48[1][A] | testpattern_inst/V_cnt_cry_0[6]/COUT
5.645 | 0.000 | tNET | FF | 2 | R41C48[1][B] | testpattern_inst/V_cnt_cry_0[7]/CIN
5.680 | 0.035 | tINS | FF | 1 | R41C48[1][B] | testpattern_inst/V_cnt_cry_0[7]/COUT
5.680 | 0.000 | tNET | FF | 2 | R41C48[2][A] | testpattern_inst/V_cnt_cry_0[8]/CIN
6.150 | 0.470 | tINS | FF | 1 | R41C48[2][A] | testpattern_inst/V_cnt_cry_0[8]/SUM
6.150 | 0.000 | tNET | FF | 1 | R41C48[2][A] | testpattern_inst/V_cnt_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R41C48[2][A] | testpattern_inst/V_cnt_Z[8]/CLK
7.667 | -0.200 | tUnc |  |  |  | testpattern_inst/V_cnt_Z[8]
7.632 | -0.035 | tSu |  | 1 | R41C48[2][A] | testpattern_inst/V_cnt_Z[8]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 8
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 3.259, 65.850%; route: 1.458, 29.463%; tC2Q: 0.232, 4.687%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path25

Path Summary:

Slack | 1.483
Data Arrival Time | 6.149
Data Required Time | 7.632
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[1]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/CLK
1.433 | 0.232 | tC2Q | RF | 7 | R38C29[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hcalc_ctrl_fsm_inst/hcalc_en_fast/Q
2.301 | 0.868 | tNET | FF | 1 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/I1
2.672 | 0.371 | tINS | FF | 201 | R35C36[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_wraddr14/F
4.677 | 2.006 | tNET | FF | 1 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/I3
5.139 | 0.462 | tINS | FR | 41 | R30C32[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecntlde/F
6.149 | 1.010 | tNET | RR | 1 | R25C28[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[1]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R25C28[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[1]/CLK
7.667 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[1]
7.632 | -0.035 | tSu |  | 1 | R25C28[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/hor_kxacc[1]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.667
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.833, 16.834%; route: 3.883, 78.477%; tC2Q: 0.232, 4.689%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.080
Data Arrival Time | 1.231
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[7]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R29C47[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[7]/CLK
1.104 | 0.202 | tC2Q | RR | 4 | R29C47[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[7]/Q
1.231 | 0.127 | tNET | RR | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/DI7

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.127, 38.581%; tC2Q: 0.202, 61.419%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path2

Path Summary:

Slack | 0.086
Data Arrival Time | 1.237
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[6]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R45C47[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[6]/CLK
1.103 | 0.201 | tC2Q | RF | 4 | R45C47[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[6]/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R46[14] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0/DI6

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R46[14] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R46[14] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.013%; tC2Q: 0.201, 59.987%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path3

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R39C17[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/CLK
1.104 | 0.202 | tC2Q | RR | 12 | R39C17[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q
1.237 | 0.133 | tNET | RR | 1 | BSRAM_R28[7] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/WREA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[7] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R28[7] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path4

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R39C17[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/CLK
1.104 | 0.202 | tC2Q | RR | 12 | R39C17[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q
1.237 | 0.133 | tNET | RR | 1 | BSRAM_R28[5] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/WREA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[5] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R28[5] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path5

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R39C17[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/CLK
1.104 | 0.202 | tC2Q | RR | 12 | R39C17[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q
1.237 | 0.133 | tNET | RR | 1 | BSRAM_R28[6] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/WREA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[6] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R28[6] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path6

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R39C17[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/CLK
1.104 | 0.202 | tC2Q | RR | 12 | R39C17[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q
1.237 | 0.133 | tNET | RR | 1 | BSRAM_R28[4] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/WREA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[4] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R28[4] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path7

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 5 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R10[14] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[14] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3
1.043 | 0.141 | tHld |  | 1 | BSRAM_R10[14] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path8

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R18C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R18C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R28[9] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[9] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R28[9] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path9

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 5 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R10[12] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[12] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1
1.043 | 0.141 | tHld |  | 1 | BSRAM_R10[12] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path10

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 5 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R10[11] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[11] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2
1.043 | 0.141 | tHld |  | 1 | BSRAM_R10[11] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path11

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R18C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R18C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R10[10] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[10] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R10[10] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path12

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R18C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R18C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R10[9] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[9] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R10[9] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path13

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R18C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R18C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R28[8] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[8] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R28[8] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path14

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 5 | R20C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R10[13] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[13] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R10[13] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path15

Path Summary:

Slack | 0.201
Data Arrival Time | 1.352
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[1]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R32C47[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[1]/CLK
1.104 | 0.202 | tC2Q | RR | 4 | R32C47[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[1]/Q
1.352 | 0.248 | tNET | RR | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/DI1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.248, 55.078%; tC2Q: 0.202, 44.922%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path16

Path Summary:

Slack | 0.206
Data Arrival Time | 1.357
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[5]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R45C47[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[5]/CLK
1.104 | 0.202 | tC2Q | RR | 4 | R45C47[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[5]/Q
1.357 | 0.253 | tNET | RR | 1 | BSRAM_R46[14] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0/DI5

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R46[14] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R46[14] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[3].bram_inst2/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.253, 55.591%; tC2Q: 0.202, 44.409%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path17

Path Summary:

Slack | 0.206
Data Arrival Time | 1.357
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[5]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R30C47[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[5]/CLK
1.104 | 0.202 | tC2Q | RR | 4 | R30C47[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[5]/Q
1.357 | 0.253 | tNET | RR | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/DI5

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.253, 55.591%; tC2Q: 0.202, 44.409%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path18

Path Summary:

Slack | 0.216
Data Arrival Time | 1.367
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[2]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R29C47[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[2]/CLK
1.104 | 0.202 | tC2Q | RR | 4 | R29C47[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata1_Z[2]/Q
1.367 | 0.263 | tNET | RR | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/DI2

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R28[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].bram_inst1/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.263, 56.544%; tC2Q: 0.202, 43.456%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path19

Path Summary:

Slack | 0.233
Data Arrival Time | 1.230
Data Required Time | 0.997
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[80]
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[20].u_cmd_gen
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R7C2[2][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[80]/CLK
1.104 | 0.202 | tC2Q | RR | 2 | R7C2[2][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[80]/Q
1.230 | 0.126 | tNET | RR | 1 | IOL7[A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[20].u_cmd_gen/D0

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | IOL7[A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[20].u_cmd_gen/PCLK
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[20].u_cmd_gen
0.997 | 0.095 | tHld |  | 1 | IOL7[A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 38.456%; tC2Q: 0.202, 61.544%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path20

Path Summary:

Slack | 0.234
Data Arrival Time | 1.230
Data Required Time | 0.997
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[15]
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R11C2[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[15]/CLK
1.103 | 0.201 | tC2Q | RF | 2 | R11C2[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[15]/Q
1.230 | 0.128 | tNET | FF | 1 | IOL11[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen/D6

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | IOL11[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen/PCLK
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen
0.997 | 0.095 | tHld |  | 1 | IOL11[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path21

Path Summary:

Slack | 0.234
Data Arrival Time | 1.230
Data Required Time | 0.997
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[14]
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R11C2[0][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[14]/CLK
1.103 | 0.201 | tC2Q | RF | 2 | R11C2[0][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[14]/Q
1.230 | 0.128 | tNET | FF | 1 | IOL11[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen/D4

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | IOL11[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen/PCLK
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen
0.997 | 0.095 | tHld |  | 1 | IOL11[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[3].u_cmd_gen

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path22

Path Summary:

Slack | 0.234
Data Arrival Time | 1.230
Data Required Time | 0.997
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[39]
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R2C2[0][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[39]/CLK
1.103 | 0.201 | tC2Q | RF | 2 | R2C2[0][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[39]/Q
1.230 | 0.128 | tNET | FF | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/D6

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/PCLK
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen
0.997 | 0.095 | tHld |  | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path23

Path Summary:

Slack | 0.234
Data Arrival Time | 1.230
Data Required Time | 0.997
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[38]
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R2C2[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[38]/CLK
1.103 | 0.201 | tC2Q | RF | 2 | R2C2[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[38]/Q
1.230 | 0.128 | tNET | FF | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/D4

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/PCLK
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen
0.997 | 0.095 | tHld |  | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path24

Path Summary:

Slack | 0.234
Data Arrival Time | 1.230
Data Required Time | 0.997
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[37]
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R2C2[1][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[37]/CLK
1.103 | 0.201 | tC2Q | RF | 2 | R2C2[1][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[37]/Q
1.230 | 0.128 | tNET | FF | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/D2

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/PCLK
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen
0.997 | 0.095 | tHld |  | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path25

Path Summary:

Slack | 0.234
Data Arrival Time | 1.230
Data Required Time | 0.997
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[36]
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R2C2[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[36]/CLK
1.103 | 0.201 | tC2Q | RF | 2 | R2C2[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[36]/Q
1.230 | 0.128 | tNET | FF | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/D0

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen/PCLK
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen
0.997 | 0.095 | tHld |  | 1 | IOL2[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[9].u_cmd_gen

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.736
Data Arrival Time | 5.896
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[0]_Z
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 42 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q
5.896 | 1.102 | tNET | FF | 1 | R18C38[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[0]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R18C38[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[0]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[0]_Z
7.632 | -0.035 | tSu |  | 1 | R18C38[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[0]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 82.610%; tC2Q: 0.232, 17.390%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path2

Path Summary:

Slack | 1.736
Data Arrival Time | 5.896
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[0]_Z
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 42 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q
5.896 | 1.102 | tNET | FF | 1 | R18C38[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[0]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R18C38[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[0]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[0]_Z
7.632 | -0.035 | tSu |  | 1 | R18C38[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[0]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 82.610%; tC2Q: 0.232, 17.390%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path3

Path Summary:

Slack | 1.751
Data Arrival Time | 5.882
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.882 | 1.088 | tNET | FF | 1 | R20C44[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C44[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]
7.632 | -0.035 | tSu |  | 1 | R20C44[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.088, 82.422%; tC2Q: 0.232, 17.578%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path4

Path Summary:

Slack | 1.751
Data Arrival Time | 5.882
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.882 | 1.088 | tNET | FF | 1 | R20C44[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C44[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z
7.632 | -0.035 | tSu |  | 1 | R20C44[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.088, 82.422%; tC2Q: 0.232, 17.578%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path5

Path Summary:

Slack | 1.751
Data Arrival Time | 5.882
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[0]_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.882 | 1.088 | tNET | FF | 1 | R20C44[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[0]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C44[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[0]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[0]_Z
7.632 | -0.035 | tSu |  | 1 | R20C44[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[0]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.088, 82.422%; tC2Q: 0.232, 17.578%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path6

Path Summary:

Slack | 1.751
Data Arrival Time | 5.882
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.882 | 1.088 | tNET | FF | 1 | R20C44[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C44[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z
7.632 | -0.035 | tSu |  | 1 | R20C44[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.088, 82.422%; tC2Q: 0.232, 17.578%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path7

Path Summary:

Slack | 1.751
Data Arrival Time | 5.882
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[0]_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.882 | 1.088 | tNET | FF | 1 | R20C44[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[0]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C44[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[0]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[0]_Z
7.632 | -0.035 | tSu |  | 1 | R20C44[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[0]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.088, 82.422%; tC2Q: 0.232, 17.578%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path8

Path Summary:

Slack | 1.768
Data Arrival Time | 5.864
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[9]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 42 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q
5.864 | 1.071 | tNET | FF | 1 | R20C38[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C38[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[9]/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[9]
7.632 | -0.035 | tSu |  | 1 | R20C38[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[9]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.071, 82.190%; tC2Q: 0.232, 17.810%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path9

Path Summary:

Slack | 1.768
Data Arrival Time | 5.864
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[3]_Z
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 42 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q
5.864 | 1.071 | tNET | FF | 1 | R20C38[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[3]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C38[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[3]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[3]_Z
7.632 | -0.035 | tSu |  | 1 | R20C38[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[3]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.071, 82.190%; tC2Q: 0.232, 17.810%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path10

Path Summary:

Slack | 1.768
Data Arrival Time | 5.864
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[2]_Z
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 42 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q
5.864 | 1.071 | tNET | FF | 1 | R20C38[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[2]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C38[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[2]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[2]_Z
7.632 | -0.035 | tSu |  | 1 | R20C38[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq1_rptr_Z[2]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.071, 82.190%; tC2Q: 0.232, 17.810%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path11

Path Summary:

Slack | 1.768
Data Arrival Time | 5.864
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[2]_Z
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 42 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q
5.864 | 1.071 | tNET | FF | 1 | R20C38[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[2]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C38[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[2]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[2]_Z
7.632 | -0.035 | tSu |  | 1 | R20C38[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[2]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.071, 82.190%; tC2Q: 0.232, 17.810%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path12

Path Summary:

Slack | 1.768
Data Arrival Time | 5.864
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[4]_Z
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 42 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q
5.864 | 1.071 | tNET | FF | 1 | R20C38[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[4]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C38[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[4]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[4]_Z
7.632 | -0.035 | tSu |  | 1 | R20C38[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[4]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.071, 82.190%; tC2Q: 0.232, 17.810%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path13

Path Summary:

Slack | 1.768
Data Arrival Time | 5.864
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[3]_Z
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 42 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/Q
5.864 | 1.071 | tNET | FF | 1 | R20C38[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[3]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C38[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[3]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[3]_Z
7.632 | -0.035 | tSu |  | 1 | R20C38[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Big.wq2_rptr_Z[3]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.071, 82.190%; tC2Q: 0.232, 17.810%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path14

Path Summary:

Slack | 1.823
Data Arrival Time | 2.504
Data Required Time | 4.327
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R18C39[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_Z/CLK
1.433 | 0.232 | tC2Q | RF | 4 | R18C39[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_Z/Q
2.504 | 1.071 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]/CLK
4.362 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]
4.327 | -0.035 | tSu |  | 1 | R23C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[1]

Path Statistics:

Clock Skew | 0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.071, 82.194%; tC2Q: 0.232, 17.806%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%

### Path15

Path Summary:

Slack | 1.823
Data Arrival Time | 2.504
Data Required Time | 4.327
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[0]
Launch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R18C39[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_Z/CLK
1.433 | 0.232 | tC2Q | RF | 4 | R18C39[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_Z/Q
2.504 | 1.071 | tNET | FF | 1 | R23C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[0]/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 1689 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R23C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[0]/CLK
4.362 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[0]
4.327 | -0.035 | tSu |  | 1 | R23C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/reset_w_Z[0]

Path Statistics:

Clock Skew | 0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.071, 82.194%; tC2Q: 0.232, 17.806%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%

### Path16

Path Summary:

Slack | 1.894
Data Arrival Time | 5.738
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[8]_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.738 | 0.944 | tNET | FF | 1 | R18C46[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[8]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R18C46[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[8]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[8]_Z
7.632 | -0.035 | tSu |  | 1 | R18C46[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[8]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.944, 80.276%; tC2Q: 0.232, 19.724%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path17

Path Summary:

Slack | 1.894
Data Arrival Time | 5.738
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[8]_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.738 | 0.944 | tNET | FF | 1 | R18C46[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[8]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R18C46[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[8]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[8]_Z
7.632 | -0.035 | tSu |  | 1 | R18C46[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[8]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.944, 80.276%; tC2Q: 0.232, 19.724%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path18

Path Summary:

Slack | 1.906
Data Arrival Time | 5.726
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[8]
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.726 | 0.933 | tNET | FF | 1 | R20C45[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C45[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[8]/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[8]
7.632 | -0.035 | tSu |  | 1 | R20C45[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[8]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.933, 80.082%; tC2Q: 0.232, 19.918%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path19

Path Summary:

Slack | 1.906
Data Arrival Time | 5.726
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[9]
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.726 | 0.933 | tNET | FF | 1 | R20C45[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C45[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[9]/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[9]
7.632 | -0.035 | tSu |  | 1 | R20C45[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/raddr_num_dly_Z[9]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.933, 80.082%; tC2Q: 0.232, 19.918%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path20

Path Summary:

Slack | 1.906
Data Arrival Time | 5.726
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.726 | 0.933 | tNET | FF | 1 | R20C45[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C45[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]
7.632 | -0.035 | tSu |  | 1 | R20C45[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.933, 80.082%; tC2Q: 0.232, 19.918%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path21

Path Summary:

Slack | 1.906
Data Arrival Time | 5.726
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[8]
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.726 | 0.933 | tNET | FF | 1 | R20C45[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C45[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[8]/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[8]
7.632 | -0.035 | tSu |  | 1 | R20C45[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[8]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.933, 80.082%; tC2Q: 0.232, 19.918%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path22

Path Summary:

Slack | 1.906
Data Arrival Time | 5.726
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.726 | 0.933 | tNET | FF | 1 | R20C45[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R20C45[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]
7.632 | -0.035 | tSu |  | 1 | R20C45[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.933, 80.082%; tC2Q: 0.232, 19.918%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path23

Path Summary:

Slack | 1.917
Data Arrival Time | 5.715
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[7]_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.715 | 0.921 | tNET | FF | 1 | R21C45[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[7]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R21C45[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[7]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[7]_Z
7.632 | -0.035 | tSu |  | 1 | R21C45[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[7]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.921, 79.884%; tC2Q: 0.232, 20.116%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path24

Path Summary:

Slack | 1.917
Data Arrival Time | 5.715
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.715 | 0.921 | tNET | FF | 1 | R21C44[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R21C44[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z
7.632 | -0.035 | tSu |  | 1 | R21C44[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.921, 79.884%; tC2Q: 0.232, 20.116%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path25

Path Summary:

Slack | 1.917
Data Arrival Time | 5.715
Data Required Time | 7.632
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z
Launch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[F]
Latch Clk | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.333 | 3.333 |  |  |  |  | active clock edge time
3.333 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | 1 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.794 | 0.232 | tC2Q | FF | 54 | R17C41[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.715 | 0.921 | tNET | FF | 1 | R21C44[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.667 | 6.667 |  |  |  |  | active clock edge time
6.667 | 0.000 |  |  |  |  | pix_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | 143 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.867 | 1.201 | tNET | RR | 1 | R21C44[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z/CLK
7.667 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z
7.632 | -0.035 | tSu |  | 1 | R21C44[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.333
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.921, 79.884%; tC2Q: 0.232, 20.116%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R17C33[0][A] | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R17C33[0][A] | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant
0.913 | 0.011 | tHld |  | 1 | R17C33[0][A] | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path2

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[23]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R15C42[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[23]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R15C42[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[23]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[23]
0.913 | 0.011 | tHld |  | 1 | R15C42[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[23]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path3

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[24]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R15C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[24]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R15C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[24]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[24]
0.913 | 0.011 | tHld |  | 1 | R15C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr[24]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path4

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R21C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R21C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o
0.913 | 0.011 | tHld |  | 1 | R21C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path5

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[22]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R23C47[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[22]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R23C47[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[22]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[22]
0.913 | 0.011 | tHld |  | 1 | R23C47[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[22]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path6

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_Z
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R22C45[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_Z/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R22C45[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_Z/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_Z
0.913 | 0.011 | tHld |  | 1 | R22C45[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path7

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_fast
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R21C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_fast/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R21C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_fast/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_fast
0.913 | 0.011 | tHld |  | 1 | R21C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_fast

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path8

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R22C34[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R22C34[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o
0.913 | 0.011 | tHld |  | 1 | R22C34[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path9

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R16C39[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R16C39[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z
0.913 | 0.011 | tHld |  | 1 | R16C39[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path10

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R20C34[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R20C34[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast
0.913 | 0.011 | tHld |  | 1 | R20C34[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path11

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_wr_grant
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R21C32[2][B] | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_wr_grant/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R21C32[2][B] | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_wr_grant/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_wr_grant
0.913 | 0.011 | tHld |  | 1 | R21C32[2][B] | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_wr_grant

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path12

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R22C34[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R22C34[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast
0.913 | 0.011 | tHld |  | 1 | R22C34[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path13

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[25]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R23C47[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[25]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R23C47[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[25]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[25]
0.913 | 0.011 | tHld |  | 1 | R23C47[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[25]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path14

Path Summary:

Slack | 1.598
Data Arrival Time | 2.511
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.511 | 1.407 | tNET | RR | 1 | R20C34[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R20C34[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o
0.913 | 0.011 | tHld |  | 1 | R20C34[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.407, 87.445%; tC2Q: 0.202, 12.555%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path15

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R25C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R25C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]
0.913 | 0.011 | tHld |  | 1 | R25C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path16

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[4]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R25C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R25C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[4]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[4]
0.913 | 0.011 | tHld |  | 1 | R25C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path17

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[5]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R25C36[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R25C36[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[5]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[5]
0.913 | 0.011 | tHld |  | 1 | R25C36[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path18

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[4]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R24C42[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C42[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[4]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[4]
0.913 | 0.011 | tHld |  | 1 | R24C42[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path19

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R25C36[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R25C36[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]
0.913 | 0.011 | tHld |  | 1 | R25C36[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path20

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[3]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R24C41[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C41[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[3]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[3]
0.913 | 0.011 | tHld |  | 1 | R24C41[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path21

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[6]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R24C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[6]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[6]
0.913 | 0.011 | tHld |  | 1 | R24C42[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path22

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[5]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R24C42[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C42[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[5]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[5]
0.913 | 0.011 | tHld |  | 1 | R24C42[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path23

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[2]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R24C34[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C34[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[2]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[2]
0.913 | 0.011 | tHld |  | 1 | R24C34[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path24

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[0]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R24C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[0]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[0]
0.913 | 0.011 | tHld |  | 1 | R24C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path25

Path Summary:

Slack | 1.603
Data Arrival Time | 2.516
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[0]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 480 | R41C24[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.516 | 1.412 | tNET | RR | 1 | R21C46[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R21C46[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[0]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[0]
0.913 | 0.011 | tHld |  | 1 | R21C46[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.412, 87.484%; tC2Q: 0.202, 12.516%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | cnt_vs_Z[9]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | cnt_vs_Z[9]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | cnt_vs_Z[9]/CLK

### MPW2

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | cnt_vs_Z[7]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | cnt_vs_Z[7]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | cnt_vs_Z[7]/CLK

### MPW3

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | cnt_vs_Z[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | cnt_vs_Z[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | cnt_vs_Z[3]/CLK

### MPW4

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | testpattern_inst/De_hcnt_Z[9]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | testpattern_inst/De_hcnt_Z[9]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | testpattern_inst/De_hcnt_Z[9]/CLK

### MPW5

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | testpattern_inst/De_vcnt_Z[5]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | testpattern_inst/De_vcnt_Z[5]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | testpattern_inst/De_vcnt_Z[5]/CLK

### MPW6

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | testpattern_inst/Color_bar_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | testpattern_inst/Color_bar_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | testpattern_inst/Color_bar_Z[0]/CLK

### MPW7

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | testpattern_inst/Gray_d1_Z[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | testpattern_inst/Gray_d1_Z[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | testpattern_inst/Gray_d1_Z[3]/CLK

### MPW8

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/kx_Z[20]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/kx_Z[20]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/kx_Z[20]/CLK

### MPW9

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].iram_rddata0[2][6]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].iram_rddata0[2][6]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[2].iram_rddata0[2][6]/CLK

### MPW10

MPW Summary:

Slack: | 2.007
Actual Width: | 3.007
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
Objects: | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/loop[2].q_r[2][3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.333 | 0.000 |  |  | active clock edge time
3.333 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
3.333 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.562 | 1.228 | tNET | FF | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/loop[2].q_r[2][3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.667 | 0.000 |  |  | active clock edge time
6.667 | 0.000 |  |  | gw_pll_inst/rpll_inst/CLKOUT.default_gen_clk
6.667 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.569 | 0.902 | tNET | RR | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/srld_16_inst1/loop[2].q_r[2][3]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
2134 | dma_clk | 4.177 | 1.228
1689 | clkout | 0.855 | 1.228
480 | init_calib_complete | 4.383 | 2.310
300 | I_clk_c | 13.564 | 1.228
295 | frame_rst | 1.714 | 2.167
283 | rvalid[0] | 9.555 | 2.281
201 | oram_wraddr14 | 1.112 | 2.107
192 | un1_vval_limit_en_1_i_sx_RNII8VE | 1.859 | 2.341
161 | D0_L3 | 6.398 | 2.636
157 | mux_wrdata_en | 7.697 | 2.216

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R29C44 | 80.56%
R15C18 | 75.00%
R24C17 | 72.22%
R23C37 | 69.44%
R29C43 | 69.44%
R29C45 | 69.44%
R40C47 | 68.06%
R23C17 | 68.06%
R13C32 | 68.06%
R16C18 | 66.67%

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---
TC_CLOCK | Actived | create_clock -name clk_x4 -period 3.333 -waveform {0 1.667} [get_nets {DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4}] -add
TC_CLOCK | Actived | create_clock -name clk_x4i -period 3.333 -waveform {0 1.667} [get_nets {DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4i}] -add
TC_CLOCK | Actived | create_clock -name dma_clk -period 13.333 -waveform {0 6.667} [get_nets {dma_clk}] -add
TC_CLOCK | Actived | create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {dma_clk}]
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {I_clk}]
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {clk_x4i}]
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {clk_x4}]