@P:  Worst Slack : -1.996
@P:  DDR3_Memory_Interface_Top|clk - Estimated Frequency : 248.3 MHz
@P:  DDR3_Memory_Interface_Top|clk - Requested Frequency : 292.1 MHz
@P:  DDR3_Memory_Interface_Top|clk - Estimated Period : 4.028
@P:  DDR3_Memory_Interface_Top|clk - Requested Period : 3.424
@P:  DDR3_Memory_Interface_Top|clk - Slack : -0.604
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock - Estimated Frequency : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock - Requested Frequency : 150.0 MHz
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock - Estimated Period : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock - Requested Period : 6.667
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock - Slack : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock - Estimated Frequency : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock - Requested Frequency : 150.0 MHz
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock - Estimated Period : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock - Requested Period : 6.667
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock - Slack : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock - Estimated Frequency : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock - Requested Frequency : 150.0 MHz
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock - Estimated Period : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock - Requested Period : 6.667
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock - Slack : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock - Estimated Frequency : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock - Requested Frequency : 150.0 MHz
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock - Estimated Period : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock - Requested Period : 6.667
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock - Slack : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock - Estimated Frequency : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock - Requested Frequency : 150.0 MHz
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock - Estimated Period : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock - Requested Period : 6.667
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock - Slack : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock - Estimated Frequency : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock - Requested Frequency : 150.0 MHz
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock - Estimated Period : NA
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock - Requested Period : 6.667
@P:  _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock - Slack : NA
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock - Estimated Frequency : 134.8 MHz
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock - Requested Frequency : 158.6 MHz
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock - Estimated Period : 7.419
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock - Requested Period : 6.306
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock - Slack : -1.113
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock - Estimated Frequency : NA
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock - Requested Frequency : 150.0 MHz
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock - Estimated Period : NA
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock - Requested Period : 6.667
@P:  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock - Slack : NA
@P:  System - Estimated Frequency : 617.7 MHz
@P:  System - Requested Frequency : 726.6 MHz
@P:  System - Estimated Period : 1.619
@P:  System - Requested Period : 1.376
@P:  System - Slack : -0.243
@P: DDR3_Memory_Interface_Top Part : gw2a_18pbga484-8
@P: DDR3_Memory_Interface_Top I/O primitives : 45
@P: DDR3_Memory_Interface_Top I/O Register bits : 0
@P: DDR3_Memory_Interface_Top Register bits (Non I/O) : 1788 (11%)
@P: DDR3_Memory_Interface_Top Block Rams : 8 of 46 (17%)
@P: DDR3_Memory_Interface_Top Total Luts : 1767 of 800 (8%)
@P:  CPU Time : 0h:00m:17s
