D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\bin64\m_generic.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1   -part GW2A_18  -package PBGA256  -grade -8    -maxfan 10000 -RWCheckOnRam 0 -block -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synlog\report\fifo_dma_write_32_128_premap.xml -merge_inferred_clocks 0  -implementation  rev_1  -ovm  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128.vm  -conchk_prepass  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128_cck.rpt   -autoconstraint  -freq 150.000   D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synwork\fifo_dma_write_32_128_mult.srs  -flow prepass  -gcc_prepass  -osrd  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synwork\fifo_dma_write_32_128_prem.srd  -qsap  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\fifo_dma_write_32_128.sap  -devicelib  D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\generic\gw2a.v  -ologparam  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\syntmp\fifo_dma_write_32_128.plg  -osyn  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synwork\fifo_dma_write_32_128_prem.srd  -prjdir  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\  -prjname  FIFO  -log  D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synlog\fifo_dma_write_32_128_premap.srr  -sn  2019.03  -jobname  "premap" 
relcom:..\..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\rev_1 -part GW2A_18 -package PBGA256 -grade -8 -maxfan 10000 -RWCheckOnRam 0 -block -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile ..\synlog\report\fifo_dma_write_32_128_premap.xml -merge_inferred_clocks 0 -implementation rev_1 -ovm ..\fifo_dma_write_32_128.vm -conchk_prepass ..\fifo_dma_write_32_128_cck.rpt -autoconstraint -freq 150.000 ..\synwork\fifo_dma_write_32_128_mult.srs -flow prepass -gcc_prepass -osrd ..\synwork\fifo_dma_write_32_128_prem.srd -qsap ..\fifo_dma_write_32_128.sap -devicelib ..\..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\generic\gw2a.v -ologparam fifo_dma_write_32_128.plg -osyn ..\synwork\fifo_dma_write_32_128_prem.srd -prjdir ..\..\ -prjname FIFO -log ..\synlog\fifo_dma_write_32_128_premap.srr -sn 2019.03 -jobname "premap"
rc:0 success:1 runtime:3
file:..\fifo_dma_write_32_128.vm|io:o|time:0|size:-1|exec:0|csum:
file:..\fifo_dma_write_32_128_cck.rpt|io:o|time:1576721274|size:4560|exec:0|csum:
file:..\synwork\fifo_dma_write_32_128_mult.srs|io:i|time:1576721271|size:2542|exec:0|csum:8C82B6A2CA51E0EC981DA09257F355ED
file:..\synwork\fifo_dma_write_32_128_prem.srd|io:o|time:1576721273|size:46220|exec:0|csum:
file:..\fifo_dma_write_32_128.sap|io:o|time:1576721274|size:237|exec:0|csum:
file:..\..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\generic\gw2a.v|io:i|time:1575572956|size:163815|exec:0|csum:9E2600B864B99F5A90D449698CC6DFCB
file:fifo_dma_write_32_128.plg|io:o|time:1576721271|size:0|exec:0|csum:
file:..\synwork\fifo_dma_write_32_128_prem.srd|io:o|time:1576721273|size:46220|exec:0|csum:
file:..\synlog\fifo_dma_write_32_128_premap.srr|io:o|time:1576721274|size:6565|exec:0|csum:
file:..\..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\bin64\m_generic.exe|io:i|time:1575571358|size:39936512|exec:1|csum:350A231ED38336BB11E83024B56EB85B
