Project Status Summary Page

Project Settings
Project Name | FIFO | Device Name | rev_1: GOWIN-GW2A : GW2A_18
Implementation Name | rev_1 | Top Module | [auto]
Pipelining | 1 | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 1 | Disable Sequential Optimizations | 0
Clock Conversion | 1 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 9 | 2 | 0 | - | 00m:01s | - | 2019/12/19 10:07:49
(premap) | Complete | 5 | 0 | 0 | 0m:02s | 0m:03s | 225MB | 2019/12/19 10:07:54
(fpga_mapper) | Complete | 9 | 6 | 0 | 0m:07s | 0m:08s | 228MB | 2019/12/19 10:08:03
Multi-srs Generator | Complete |  |  |  | 00m:01s |  |  | 2019/12/19 10:07:51

Area Summary
Non I/O Register bits (non_io_reg) | 106 (0%) | I/O Register bits (total_io_reg) | 0
Ultra Rams | 0 | Block Rams (v_ram) | 4 (46)
Block Multipliers (dsp_used) | 0 (24) | LUTs (total_luts) | 89 (0%)

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
fifo_dma_write_32_128|RdClk | 188.5 MHz | 160.2 MHz | -0.936
fifo_dma_write_32_128|WrClk | 192.5 MHz | 163.6 MHz | -0.917
System | 150.0 MHz | 237.1 MHz | 2.449

Optimizations Summary
Combined Clock Conversion | 2 / 0 |  |