
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\SCALER\data\scaler_wrapper.vp" (library work)
@I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\SCALER\data\scaler_wrapper.vp":"D:\proj\scaler_example_design_live\project\src\scaler\temp\scaler\top_define.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\SCALER\data\scaler_wrapper.vp":"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\SCALER\data\static_macro_define.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\SCALER\data\scaler_wrapper.vp":"D:\proj\scaler_example_design_live\project\src\scaler\temp\scaler\scaler_defines.v" (library work)
@I::"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\SCALER\data\scaler_top.v" (library work)
Verilog syntax check successful!
Selecting top level module Scaler_Top
Running optimization stage 1 on \~srld_16.Scaler_Top _1s_8_9 .......
Running optimization stage 1 on \~srld_16.Scaler_Top _1s_2_3 .......
Running optimization stage 1 on \~mode_control.Scaler_Top  .......
Running optimization stage 1 on \~hcalc_ctrl_fsm.Scaler_Top  .......
Running optimization stage 1 on \~ver_coord_trans.Scaler_Top  .......
Running optimization stage 1 on SDPB .......
Running optimization stage 1 on \~bram.Scaler_Top _8s .......
Running optimization stage 1 on \~ver_calcdata_gen.Scaler_Top _8s_2s_2_2s_4s .......
Running optimization stage 1 on \~ver_coef_gen.Scaler_Top _16s_2s_16s_2_4s .......
Running optimization stage 1 on \~srld_16.Scaler_Top _1s_3_4 .......
Running optimization stage 1 on MULT18X18 .......
Running optimization stage 1 on \~ver_integrator.Scaler_Top _16s_8s_2s_16s_9s .......
Running optimization stage 1 on \~ver_calc_wrapper.Scaler_Top _16s_8s_2s_16s_2 .......
Running optimization stage 1 on \~hor_coord_trans.Scaler_Top  .......
Running optimization stage 1 on \~srld_16.Scaler_Top _3s_7_8 .......
Running optimization stage 1 on \~srld_16.Scaler_Top _1s_7_8 .......
Running optimization stage 1 on \~hor_calcdata_gen.Scaler_Top _8s_2s_7_7_7_3s_8s .......
Running optimization stage 1 on \~srld_16.Scaler_Top _16s_7_8 .......
Running optimization stage 1 on \~hor_coef_gen.Scaler_Top _16s_2s_16s_7_7_4s .......
Running optimization stage 1 on \~hor_integrator.Scaler_Top _16s_8s_2s_16s_9s .......
Running optimization stage 1 on \~hor_calc_wrapper.Scaler_Top _16s_8s_2s_16s_7_7_7_7 .......
Running optimization stage 1 on \~video_outbuf.Scaler_Top _8s .......
Running optimization stage 1 on \~scaler_core.Scaler_Top _16s_8s_2s_16s_7_7_7_7_7_2 .......
Running optimization stage 1 on \~scaler_wrapper.Scaler_Top _16s_8s_2s_16s .......
@N: CG364 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\SCALER\data\scaler_top.v":31:19:31:19|Synthesizing module Scaler_Top in library work.
Running optimization stage 1 on Scaler_Top .......
Running optimization stage 2 on Scaler_Top .......
Running optimization stage 2 on \~scaler_wrapper.Scaler_Top _16s_8s_2s_16s .......
Running optimization stage 2 on \~scaler_core.Scaler_Top _16s_8s_2s_16s_7_7_7_7_7_2 .......
Running optimization stage 2 on \~video_outbuf.Scaler_Top _8s .......
Running optimization stage 2 on \~hor_calc_wrapper.Scaler_Top _16s_8s_2s_16s_7_7_7_7 .......
Running optimization stage 2 on \~hor_integrator.Scaler_Top _16s_8s_2s_16s_9s .......
Running optimization stage 2 on \~hor_coef_gen.Scaler_Top _16s_2s_16s_7_7_4s .......
Running optimization stage 2 on \~srld_16.Scaler_Top _16s_7_8 .......
Running optimization stage 2 on \~hor_calcdata_gen.Scaler_Top _8s_2s_7_7_7_3s_8s .......
Running optimization stage 2 on \~srld_16.Scaler_Top _1s_7_8 .......
Running optimization stage 2 on \~srld_16.Scaler_Top _3s_7_8 .......
Running optimization stage 2 on \~hor_coord_trans.Scaler_Top  .......
Running optimization stage 2 on \~ver_calc_wrapper.Scaler_Top _16s_8s_2s_16s_2 .......
Running optimization stage 2 on MULT18X18 .......
Running optimization stage 2 on \~ver_integrator.Scaler_Top _16s_8s_2s_16s_9s .......
Running optimization stage 2 on \~srld_16.Scaler_Top _1s_3_4 .......
Running optimization stage 2 on \~ver_coef_gen.Scaler_Top _16s_2s_16s_2_4s .......
Running optimization stage 2 on \~bram.Scaler_Top _8s .......
Running optimization stage 2 on SDPB .......
Running optimization stage 2 on \~ver_calcdata_gen.Scaler_Top _8s_2s_2_2s_4s .......
Running optimization stage 2 on \~ver_coord_trans.Scaler_Top  .......
Running optimization stage 2 on \~hcalc_ctrl_fsm.Scaler_Top  .......
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
Running optimization stage 2 on \~mode_control.Scaler_Top  .......
Running optimization stage 2 on \~srld_16.Scaler_Top _1s_2_3 .......
Running optimization stage 2 on \~srld_16.Scaler_Top _1s_8_9 .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\proj\scaler_example_design_live\project\src\scaler\temp\scaler\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 102MB peak: 108MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 17 14:22:32 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N|Running in 64-bit mode
@N: NF107 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\scaler\data\scaler_top.v":31:19:31:19|Selected library: work cell: Scaler_Top view verilog as top level
@N: NF107 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\scaler\data\scaler_top.v":31:19:31:19|Selected library: work cell: Scaler_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 17 14:22:32 2020

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: D:\proj\scaler_example_design_live\project\src\scaler\temp\scaler\rev_1\synwork\scaler_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 22MB peak: 22MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

Process completed successfully.
# Wed Jun 17 14:22:32 2020

###########################################################]
