@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF578 |Incompatible asynchronous control logic preventing generated clock conversion.
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface.sap.
