
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v" (library work)
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":1056:7:1056:12|Net cke_en is not declared.
@N: CG346 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":1676:34:1676:42|Read full_case directive.
@N: CG347 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":1676:44:1676:56|Read a parallel_case directive.
@W: CG286 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":1676:2:1676:5|Case statement has both a full_case directive and a default clause -- ignoring full_case directive.
@W: CG921 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":2893:5:2893:11|recalib is already declared in this scope.
@W: CG921 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":3288:41:3288:48|ddr_rsti is already declared in this scope.
@I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v" (library work)
@W: CG921 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":3683:25:3683:32|dll_lock is already declared in this scope.
@W: CG921 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":3711:5:3711:9|pause is already declared in this scope.
@W: CG921 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":3711:11:3711:14|stop is already declared in this scope.
@W: CG921 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":3711:41:3711:48|ddr_rsti is already declared in this scope.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6290:9:6290:20|Net act_one_bank is not declared.
@W: CG104 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6775:25:6775:27|Unsized number in concatenation is 32 bits
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6776:9:6776:16|Net sent_col is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6777:9:6777:16|Net sent_row is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6802:9:6802:19|Net send_cs_en0 is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6803:9:6803:19|Net send_cs_en1 is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6804:9:6804:19|Net send_cs_en2 is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6805:9:6805:19|Net send_cs_en3 is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6808:9:6808:21|Net send_cmd0_col is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6809:9:6809:21|Net send_cmd1_col is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6811:9:6811:21|Net send_cmd0_row is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":6812:9:6812:21|Net send_cmd1_row is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":7930:9:7930:16|Net wr_wrbuf is not declared.
@W: CG1337 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":8015:9:8015:10|Net bl is not declared.
@W: CG921 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":8336:35:8336:41|ddr_rst is already declared in this scope.
@I::"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v" (library work)
Verilog syntax check successful!
@N: CG364 :"D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v":1:0:1:8|Synthesizing module work_D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v_unit in library work.
Selecting top level module DDR3_Memory_Interface_Top
@N: CG364 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v":6:23:6:23|Synthesizing module DDR3_Memory_Interface_Top in library work.
Running optimization stage 1 on \~gwmc_cmd_buffer.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_bank_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_timing_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~fifo_sc.DDR3_Memory_Interface_Top _144s_4s_16s_1s_2s_1s_2s_1s_12s_0s .......
Running optimization stage 1 on \~gwmc_wr_data.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_rd_data.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_rank_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_top.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on ELVDS_OBUF .......
Running optimization stage 1 on OBUF .......
Running optimization stage 1 on \~CMD_FIFO.DDR3_Memory_Interface_Top _4s_2s_FALSE_23s_4s .......
Running optimization stage 1 on OSER8 .......
Running optimization stage 1 on \~ddr_phy_cmd_io.DDR3_Memory_Interface_Top _92s .......
Running optimization stage 1 on \~ddr_phy_cmd_lane.DDR3_Memory_Interface_Top _Z1 .......
Running optimization stage 1 on \~fifo_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~ddr_phy_reset_gen.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on DLL .......
Running optimization stage 1 on \~ddr_memmem_sync.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on ELVDS_IOBUF .......
Running optimization stage 1 on IOBUF .......
Running optimization stage 1 on IODELAY .......
Running optimization stage 1 on TBUF .......
Running optimization stage 1 on \~OUT_FIFO.DDR3_Memory_Interface_Top _8s_5s_16s_8s_2s_8s .......
Running optimization stage 1 on \~IN_FIFO.DDR3_Memory_Interface_Top _8s_5s_8s .......
Running optimization stage 1 on OSER8_MEM .......
Running optimization stage 1 on IDES8_MEM .......
Running optimization stage 1 on DQS .......
Running optimization stage 1 on \~ddr_phy_data_io.DDR3_Memory_Interface_Top _16s_8s_2500s_5s_5s .......
Running optimization stage 1 on \~ddr_phy_data_lane.DDR3_Memory_Interface_Top _16s_8s_5s_5s_5s_5s .......
Running optimization stage 1 on \~ddr_phy_wd.DDR3_Memory_Interface_Top _Z2 .......
Running optimization stage 1 on \~ddr_init.DDR3_Memory_Interface_Top _Z3 .......
Running optimization stage 1 on PLL .......
Running optimization stage 1 on DHCEN .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on \~ddr_phy_top.DDR3_Memory_Interface_Top _Z4 .......
Running optimization stage 1 on \~gw3_phy_mc.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on DDR3_Memory_Interface_Top .......
Running optimization stage 2 on \~gw3_phy_mc.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~ddr_phy_top.DDR3_Memory_Interface_Top _Z4 .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on DHCEN .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on \~ddr_init.DDR3_Memory_Interface_Top _Z3 .......
Extracted state machine for register read_cal_state
State machine has 13 reachable states with original encodings of:
   0000000000001
   0000000000010
   0000000000100
   0000000001000
   0000000010000
   0000000100000
   0000001000000
   0000010000000
   0000100000000
   0001000000000
   0010000000000
   0100000000000
   1000000000000
Extracted state machine for register wrlvl_state
State machine has 10 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0001000000
   0010000000
   0100000000
   1000000000
Extracted state machine for register init_state
State machine has 19 reachable states with original encodings of:
   000000000000000000000000001
   000000000000000000000000010
   000000000000000000000000100
   000000000000000100000000000
   000000000000001000000000000
   000000000000010000000000000
   000000000000100000000000000
   000000000001000000000000000
   000000000010000000000000000
   000000000100000000000000000
   000000001000000000000000000
   000000010000000000000000000
   000000100000000000000000000
   000001000000000000000000000
   000010000000000000000000000
   000100000000000000000000000
   001000000000000000000000000
   010000000000000000000000000
   100000000000000000000000000
Running optimization stage 2 on \~ddr_phy_data_lane.DDR3_Memory_Interface_Top _16s_8s_5s_5s_5s_5s .......
Running optimization stage 2 on DQS .......
Running optimization stage 2 on IDES8_MEM .......
Running optimization stage 2 on \~ddr_phy_data_io.DDR3_Memory_Interface_Top _16s_8s_2500s_5s_5s .......
Running optimization stage 2 on OSER8_MEM .......
Running optimization stage 2 on \~IN_FIFO.DDR3_Memory_Interface_Top _8s_5s_8s .......
Running optimization stage 2 on \~OUT_FIFO.DDR3_Memory_Interface_Top _8s_5s_16s_8s_2s_8s .......
Running optimization stage 2 on TBUF .......
Running optimization stage 2 on IODELAY .......
Running optimization stage 2 on IOBUF .......
Running optimization stage 2 on ELVDS_IOBUF .......
Running optimization stage 2 on \~ddr_phy_wd.DDR3_Memory_Interface_Top _Z2 .......
Running optimization stage 2 on \~ddr_memmem_sync.DDR3_Memory_Interface_Top  .......
Extracted state machine for register flag
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Running optimization stage 2 on DLL .......
Running optimization stage 2 on \~ddr_phy_reset_gen.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~fifo_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~ddr_phy_cmd_lane.DDR3_Memory_Interface_Top _Z1 .......
Running optimization stage 2 on \~ddr_phy_cmd_io.DDR3_Memory_Interface_Top _92s .......
Running optimization stage 2 on OSER8 .......
Running optimization stage 2 on \~CMD_FIFO.DDR3_Memory_Interface_Top _4s_2s_FALSE_23s_4s .......
Running optimization stage 2 on OBUF .......
Running optimization stage 2 on ELVDS_OBUF .......
Running optimization stage 2 on \~gwmc_top.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_rank_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_rd_data.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_wr_data.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~fifo_sc.DDR3_Memory_Interface_Top _144s_4s_16s_1s_2s_1s_2s_1s_12s_0s .......
Running optimization stage 2 on \~gwmc_timing_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_bank_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_cmd_buffer.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on DDR3_Memory_Interface_Top .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 114MB peak: 117MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime

Process completed successfully.
# Wed Jun 17 17:41:43 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N|Running in 64-bit mode
@N: NF107 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\ddr3\data\ddr3_top.v":6:23:6:23|Selected library: work cell: DDR3_Memory_Interface_Top view verilog as top level
@N: NF107 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\ddr3\data\ddr3_top.v":6:23:6:23|Selected library: work cell: DDR3_Memory_Interface_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 17 17:41:44 2020

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\rev_1\synwork\ddr3_memory_interface_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 22MB peak: 22MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime

Process completed successfully.
# Wed Jun 17 17:41:44 2020

###########################################################]
