# Written by Synplify Pro version mapgw, Build 1620R. Synopsys Run ID: sid1592386909 
# Top Level Design Parameters 

# Clocks 
create_clock -period 6.306 -waveform {0.000 3.153} -name {_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock} [get_pins {genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT}] 
create_clock -period 3.424 -waveform {0.000 1.712} -name {DDR3_Memory_Interface_Top|clk} [get_ports {clk}] 
create_clock -period 6.667 -waveform {0.000 3.333} -name {_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock} [get_pins {genblk1.gw3mc_top/u_ddr_phy_top/u_dqcen/CLKOUT}] 
create_clock -period 6.667 -waveform {0.000 3.333} -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock} [get_pins {genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/cml5.u_dqs/DQSW0}] 
create_clock -period 6.667 -waveform {0.000 3.333} -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock} [get_pins {genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/cml5.u_dqs/DQSW270}] 
create_clock -period 6.667 -waveform {0.000 3.333} -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock} [get_pins {genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/cml5.u_dqs/DQSR90}] 
create_clock -period 6.667 -waveform {0.000 3.333} -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock} [get_pins {genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/cml5.u_dqs/DQSW0}] 
create_clock -period 6.667 -waveform {0.000 3.333} -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock} [get_pins {genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/cml5.u_dqs/DQSW270}] 
create_clock -period 6.667 -waveform {0.000 3.333} -name {_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock} [get_pins {genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/cml5.u_dqs/DQSR90}] 

# Virtual Clocks 

# Generated Clocks 

# Paths Between Clocks 

# Multicycle Constraints 

# Point-to-point Delay Constraints 

# False Path Constraints 

# Output Load Constraints 

# Driving Cell Constraints 

# Input Delay Constraints 

# Output Delay Constraints 

# Wire Loads 

# Other Constraints 

# syn_hier Attributes 

# set_case Attributes 

# Clock Delay Constraints 
set Autoconstr_clkgroup_0 [list _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock]
set Autoconstr_clkgroup_1 [list DDR3_Memory_Interface_Top|clk]
set Autoconstr_clkgroup_2 [list _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock]
set Autoconstr_clkgroup_3 [list _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock]
set Autoconstr_clkgroup_4 [list _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock]
set Autoconstr_clkgroup_5 [list _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock]
set Autoconstr_clkgroup_6 [list _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock]
set Autoconstr_clkgroup_7 [list _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock]
set Autoconstr_clkgroup_8 [list _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock]
set_clock_groups -asynchronous -group $Autoconstr_clkgroup_0 -group $Autoconstr_clkgroup_1 -group $Autoconstr_clkgroup_2 -group $Autoconstr_clkgroup_3 -group $Autoconstr_clkgroup_4 -group $Autoconstr_clkgroup_5 -group $Autoconstr_clkgroup_6 -group $Autoconstr_clkgroup_7 -group $Autoconstr_clkgroup_8

# syn_mode Attributes 

# Cells 

# Port DRC Rules 

# Input Transition Constraints 

# Unused constraints (intentionally commented out) 


# Non-forward-annotatable constraints (intentionally commented out) 

# Block Path constraints 

