@N: CG364 :"D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v":1:0:1:8|Synthesizing module work_D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v_unit in library work.
Selecting top level module DDR3_Memory_Interface_Top
@N: CG364 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v":6:23:6:23|Synthesizing module DDR3_Memory_Interface_Top in library work.
Running optimization stage 1 on \~gwmc_cmd_buffer.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_bank_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_timing_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~fifo_sc.DDR3_Memory_Interface_Top _144s_4s_16s_1s_2s_1s_2s_1s_12s_0s .......
Running optimization stage 1 on \~gwmc_wr_data.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_rd_data.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_rank_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~gwmc_top.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on ELVDS_OBUF .......
Running optimization stage 1 on OBUF .......
Running optimization stage 1 on \~CMD_FIFO.DDR3_Memory_Interface_Top _4s_2s_FALSE_23s_4s .......
Running optimization stage 1 on OSER8 .......
Running optimization stage 1 on \~ddr_phy_cmd_io.DDR3_Memory_Interface_Top _92s .......
Running optimization stage 1 on \~ddr_phy_cmd_lane.DDR3_Memory_Interface_Top _Z1 .......
Running optimization stage 1 on \~fifo_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on \~ddr_phy_reset_gen.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on DLL .......
Running optimization stage 1 on \~ddr_memmem_sync.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on ELVDS_IOBUF .......
Running optimization stage 1 on IOBUF .......
Running optimization stage 1 on IODELAY .......
Running optimization stage 1 on TBUF .......
Running optimization stage 1 on \~OUT_FIFO.DDR3_Memory_Interface_Top _8s_5s_16s_8s_2s_8s .......
Running optimization stage 1 on \~IN_FIFO.DDR3_Memory_Interface_Top _8s_5s_8s .......
Running optimization stage 1 on OSER8_MEM .......
Running optimization stage 1 on IDES8_MEM .......
Running optimization stage 1 on DQS .......
Running optimization stage 1 on \~ddr_phy_data_io.DDR3_Memory_Interface_Top _16s_8s_2500s_5s_5s .......
Running optimization stage 1 on \~ddr_phy_data_lane.DDR3_Memory_Interface_Top _16s_8s_5s_5s_5s_5s .......
Running optimization stage 1 on \~ddr_phy_wd.DDR3_Memory_Interface_Top _Z2 .......
Running optimization stage 1 on \~ddr_init.DDR3_Memory_Interface_Top _Z3 .......
Running optimization stage 1 on PLL .......
Running optimization stage 1 on DHCEN .......
Running optimization stage 1 on CLKDIV .......
Running optimization stage 1 on \~ddr_phy_top.DDR3_Memory_Interface_Top _Z4 .......
Running optimization stage 1 on \~gw3_phy_mc.DDR3_Memory_Interface_Top  .......
Running optimization stage 1 on DDR3_Memory_Interface_Top .......
Running optimization stage 2 on \~gw3_phy_mc.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~ddr_phy_top.DDR3_Memory_Interface_Top _Z4 .......
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on DHCEN .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on \~ddr_init.DDR3_Memory_Interface_Top _Z3 .......
Extracted state machine for register read_cal_state
State machine has 13 reachable states with original encodings of:
   0000000000001
   0000000000010
   0000000000100
   0000000001000
   0000000010000
   0000000100000
   0000001000000
   0000010000000
   0000100000000
   0001000000000
   0010000000000
   0100000000000
   1000000000000
Extracted state machine for register wrlvl_state
State machine has 10 reachable states with original encodings of:
   0000000001
   0000000010
   0000000100
   0000001000
   0000010000
   0000100000
   0001000000
   0010000000
   0100000000
   1000000000
Extracted state machine for register init_state
State machine has 19 reachable states with original encodings of:
   000000000000000000000000001
   000000000000000000000000010
   000000000000000000000000100
   000000000000000100000000000
   000000000000001000000000000
   000000000000010000000000000
   000000000000100000000000000
   000000000001000000000000000
   000000000010000000000000000
   000000000100000000000000000
   000000001000000000000000000
   000000010000000000000000000
   000000100000000000000000000
   000001000000000000000000000
   000010000000000000000000000
   000100000000000000000000000
   001000000000000000000000000
   010000000000000000000000000
   100000000000000000000000000
Running optimization stage 2 on \~ddr_phy_data_lane.DDR3_Memory_Interface_Top _16s_8s_5s_5s_5s_5s .......
Running optimization stage 2 on DQS .......
Running optimization stage 2 on IDES8_MEM .......
Running optimization stage 2 on \~ddr_phy_data_io.DDR3_Memory_Interface_Top _16s_8s_2500s_5s_5s .......
Running optimization stage 2 on OSER8_MEM .......
Running optimization stage 2 on \~IN_FIFO.DDR3_Memory_Interface_Top _8s_5s_8s .......
Running optimization stage 2 on \~OUT_FIFO.DDR3_Memory_Interface_Top _8s_5s_16s_8s_2s_8s .......
Running optimization stage 2 on TBUF .......
Running optimization stage 2 on IODELAY .......
Running optimization stage 2 on IOBUF .......
Running optimization stage 2 on ELVDS_IOBUF .......
Running optimization stage 2 on \~ddr_phy_wd.DDR3_Memory_Interface_Top _Z2 .......
Running optimization stage 2 on \~ddr_memmem_sync.DDR3_Memory_Interface_Top  .......
Extracted state machine for register flag
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Running optimization stage 2 on DLL .......
Running optimization stage 2 on \~ddr_phy_reset_gen.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~fifo_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~ddr_phy_cmd_lane.DDR3_Memory_Interface_Top _Z1 .......
Running optimization stage 2 on \~ddr_phy_cmd_io.DDR3_Memory_Interface_Top _92s .......
Running optimization stage 2 on OSER8 .......
Running optimization stage 2 on \~CMD_FIFO.DDR3_Memory_Interface_Top _4s_2s_FALSE_23s_4s .......
Running optimization stage 2 on OBUF .......
Running optimization stage 2 on ELVDS_OBUF .......
Running optimization stage 2 on \~gwmc_top.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_rank_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_rd_data.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_wr_data.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~fifo_sc.DDR3_Memory_Interface_Top _144s_4s_16s_1s_2s_1s_2s_1s_12s_0s .......
Running optimization stage 2 on \~gwmc_timing_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_bank_ctrl.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on \~gwmc_cmd_buffer.DDR3_Memory_Interface_Top  .......
Running optimization stage 2 on DDR3_Memory_Interface_Top .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\synwork\layer0.rt.csv

