# Mon Dec  9 10:09:06 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: DESKTOP

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 217MB peak: 217MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 221MB peak: 221MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 222MB peak: 222MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -1.55ns		 195 /       127
   2		0h:00m:01s		    -1.55ns		 190 /       127
   3		0h:00m:01s		    -1.55ns		 191 /       127
Timing driven replication report
Added 8 Registers via timing driven replication
Added 9 LUTs via timing driven replication

   4		0h:00m:01s		    -1.41ns		 205 /       135
   5		0h:00m:01s		    -1.41ns		 205 /       135


   6		0h:00m:01s		    -1.41ns		 204 /       135

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 227MB peak: 227MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to inpure port. Because it's a pure input port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port
@W:|Converting bidirection inout port to output port. Because it's a pure output port

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 228MB peak: 228MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 155MB peak: 228MB)

Writing Analyst data base D:\proj\scaler_example_design_live\project\src\i2c_master\temp\I2C_MASTER\rev_1\synwork\i2c_master_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 228MB peak: 228MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 229MB peak: 229MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 229MB peak: 229MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 227MB peak: 229MB)

@W: MT420 |Found inferred clock I2C_MASTER_Top|I_CLK with period 3.77ns. Please declare a user-defined clock on port I_CLK.


##### START OF TIMING REPORT #####[
# Timing report written on Mon Dec  9 10:09:10 2019
#


Top view:               I2C_MASTER_Top
Requested Frequency:    265.2 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -0.665

                         Requested      Estimated      Requested     Estimated                Clock        Clock                
Starting Clock           Frequency      Frequency      Period        Period        Slack      Type         Group                
--------------------------------------------------------------------------------------------------------------------------------
I2C_MASTER_Top|I_CLK     265.2 MHz      225.5 MHz      3.770         4.435         -0.665     inferred     Autoconstr_clkgroup_0
System                   2198.8 MHz     1869.2 MHz     0.455         0.535         -0.080     system       system_clkgroup      
================================================================================================================================





Clock Relationships
*******************

Clocks                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------
Starting              Ending                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------
System                System                |  0.455       -0.080  |  No paths    -      |  No paths    -      |  No paths    -    
System                I2C_MASTER_Top|I_CLK  |  3.770       3.174   |  No paths    -      |  No paths    -      |  No paths    -    
I2C_MASTER_Top|I_CLK  System                |  3.770       2.992   |  No paths    -      |  No paths    -      |  No paths    -    
I2C_MASTER_Top|I_CLK  I2C_MASTER_Top|I_CLK  |  3.770       -0.665  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: I2C_MASTER_Top|I_CLK
====================================



Starting Points with Worst Slack
********************************

                                            Starting                                                   Arrival           
Instance                                    Reference                Type      Pin     Net             Time        Slack 
                                            Clock                                                                        
-------------------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.c_state[4]      I2C_MASTER_Top|I_CLK     DFFC      Q       c_state[4]      0.243       -0.665
u_i2c_master.bit_controller.c_state[3]      I2C_MASTER_Top|I_CLK     DFFC      Q       c_state[3]      0.243       -0.644
u_i2c_master.bit_controller.c_state[16]     I2C_MASTER_Top|I_CLK     DFFC      Q       c_state[16]     0.243       -0.644
u_i2c_master.bit_controller.c_state[15]     I2C_MASTER_Top|I_CLK     DFFC      Q       c_state[15]     0.243       -0.623
u_i2c_master.bit_controller.cnt[13]         I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[13]         0.243       -0.618
u_i2c_master.bit_controller.cnt[9]          I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[9]          0.243       -0.597
u_i2c_master.bit_controller.cnt[12]         I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[12]         0.243       -0.597
u_i2c_master.bit_controller.cnt[8]          I2C_MASTER_Top|I_CLK     DFFCE     Q       cnt[8]          0.243       -0.576
u_i2c_master.bit_controller.c_state[7]      I2C_MASTER_Top|I_CLK     DFFC      Q       c_state[7]      0.243       -0.557
u_i2c_master.bit_controller.c_state[11]     I2C_MASTER_Top|I_CLK     DFFC      Q       c_state[11]     0.243       -0.557
=========================================================================================================================


Ending Points with Worst Slack
******************************

                                           Starting                                                     Required           
Instance                                   Reference                Type      Pin     Net               Time         Slack 
                                           Clock                                                                           
---------------------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.c_state[0]     I2C_MASTER_Top|I_CLK     DFFP      D       c_state_ns[0]     3.709        -0.665
u_i2c_master.bit_controller.cnt[0]         I2C_MASTER_Top|I_CLK     DFFCE     D       cnt_lm[0]         3.709        -0.618
u_i2c_master.bit_controller.cnt[1]         I2C_MASTER_Top|I_CLK     DFFCE     D       cnt_lm[1]         3.709        -0.618
u_i2c_master.bit_controller.cnt[2]         I2C_MASTER_Top|I_CLK     DFFCE     D       cnt_lm[2]         3.709        -0.618
u_i2c_master.bit_controller.cnt[3]         I2C_MASTER_Top|I_CLK     DFFCE     D       cnt_lm[3]         3.709        -0.618
u_i2c_master.bit_controller.cnt[4]         I2C_MASTER_Top|I_CLK     DFFCE     D       cnt_lm[4]         3.709        -0.618
u_i2c_master.bit_controller.cnt[5]         I2C_MASTER_Top|I_CLK     DFFCE     D       cnt_lm[5]         3.709        -0.618
u_i2c_master.bit_controller.cnt[6]         I2C_MASTER_Top|I_CLK     DFFCE     D       cnt_lm[6]         3.709        -0.618
u_i2c_master.bit_controller.cnt[7]         I2C_MASTER_Top|I_CLK     DFFCE     D       cnt_lm[7]         3.709        -0.618
u_i2c_master.bit_controller.cnt[8]         I2C_MASTER_Top|I_CLK     DFFCE     D       cnt_lm[8]         3.709        -0.618
===========================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      3.770
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.709

    - Propagation time:                      4.374
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.665

    Number of logic level(s):                4
    Starting point:                          u_i2c_master.bit_controller.c_state[4] / Q
    Ending point:                            u_i2c_master.bit_controller.c_state[0] / D
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                                   Pin      Pin               Arrival     No. of    
Name                                                    Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.c_state[4]                  DFFC     Q        Out     0.243     0.243       -         
c_state[4]                                              Net      -        -       0.535     -           3         
u_i2c_master.bit_controller.SDA_OEN_2_sqmuxa_i_a2_0     LUT4     I1       In      -         0.778       -         
u_i2c_master.bit_controller.SDA_OEN_2_sqmuxa_i_a2_0     LUT4     F        Out     0.570     1.348       -         
N_251                                                   Net      -        -       0.535     -           3         
u_i2c_master.bit_controller.c_state_ns_o2_1_4[0]        LUT4     I1       In      -         1.883       -         
u_i2c_master.bit_controller.c_state_ns_o2_1_4[0]        LUT4     F        Out     0.570     2.453       -         
c_state_ns_o2_1_4[0]                                    Net      -        -       0.401     -           1         
u_i2c_master.bit_controller.c_state_ns_o2_1[0]          LUT4     I1       In      -         2.854       -         
u_i2c_master.bit_controller.c_state_ns_o2_1[0]          LUT4     F        Out     0.570     3.424       -         
N_196                                                   Net      -        -       0.401     -           1         
u_i2c_master.bit_controller.c_state_ns[0]               LUT2     I0       In      -         3.825       -         
u_i2c_master.bit_controller.c_state_ns[0]               LUT2     F        Out     0.549     4.374       -         
c_state_ns[0]                                           Net      -        -       0.000     -           1         
u_i2c_master.bit_controller.c_state[0]                  DFFP     D        In      -         4.374       -         
==================================================================================================================
Total path delay (propagation time + setup) of 4.435 is 2.563(57.8%) logic and 1.872(42.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      3.770
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.709

    - Propagation time:                      4.353
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.644

    Number of logic level(s):                4
    Starting point:                          u_i2c_master.bit_controller.c_state[3] / Q
    Ending point:                            u_i2c_master.bit_controller.c_state[0] / D
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                                   Pin      Pin               Arrival     No. of    
Name                                                    Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.c_state[3]                  DFFC     Q        Out     0.243     0.243       -         
c_state[3]                                              Net      -        -       0.535     -           3         
u_i2c_master.bit_controller.SDA_OEN_2_sqmuxa_i_a2_0     LUT4     I0       In      -         0.778       -         
u_i2c_master.bit_controller.SDA_OEN_2_sqmuxa_i_a2_0     LUT4     F        Out     0.549     1.327       -         
N_251                                                   Net      -        -       0.535     -           3         
u_i2c_master.bit_controller.c_state_ns_o2_1_4[0]        LUT4     I1       In      -         1.862       -         
u_i2c_master.bit_controller.c_state_ns_o2_1_4[0]        LUT4     F        Out     0.570     2.432       -         
c_state_ns_o2_1_4[0]                                    Net      -        -       0.401     -           1         
u_i2c_master.bit_controller.c_state_ns_o2_1[0]          LUT4     I1       In      -         2.833       -         
u_i2c_master.bit_controller.c_state_ns_o2_1[0]          LUT4     F        Out     0.570     3.403       -         
N_196                                                   Net      -        -       0.401     -           1         
u_i2c_master.bit_controller.c_state_ns[0]               LUT2     I0       In      -         3.804       -         
u_i2c_master.bit_controller.c_state_ns[0]               LUT2     F        Out     0.549     4.353       -         
c_state_ns[0]                                           Net      -        -       0.000     -           1         
u_i2c_master.bit_controller.c_state[0]                  DFFP     D        In      -         4.353       -         
==================================================================================================================
Total path delay (propagation time + setup) of 4.414 is 2.542(57.6%) logic and 1.872(42.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      3.770
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.709

    - Propagation time:                      4.353
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.644

    Number of logic level(s):                4
    Starting point:                          u_i2c_master.bit_controller.c_state[16] / Q
    Ending point:                            u_i2c_master.bit_controller.c_state[0] / D
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                 Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.c_state[16]              DFFC     Q        Out     0.243     0.243       -         
c_state[16]                                          Net      -        -       0.535     -           4         
u_i2c_master.bit_controller.sda_chk_4_i_a2           LUT2     I1       In      -         0.778       -         
u_i2c_master.bit_controller.sda_chk_4_i_a2           LUT2     F        Out     0.570     1.348       -         
N_218                                                Net      -        -       0.535     -           3         
u_i2c_master.bit_controller.c_state_ns_o2_1_4[0]     LUT4     I0       In      -         1.883       -         
u_i2c_master.bit_controller.c_state_ns_o2_1_4[0]     LUT4     F        Out     0.549     2.432       -         
c_state_ns_o2_1_4[0]                                 Net      -        -       0.401     -           1         
u_i2c_master.bit_controller.c_state_ns_o2_1[0]       LUT4     I1       In      -         2.833       -         
u_i2c_master.bit_controller.c_state_ns_o2_1[0]       LUT4     F        Out     0.570     3.403       -         
N_196                                                Net      -        -       0.401     -           1         
u_i2c_master.bit_controller.c_state_ns[0]            LUT2     I0       In      -         3.804       -         
u_i2c_master.bit_controller.c_state_ns[0]            LUT2     F        Out     0.549     4.353       -         
c_state_ns[0]                                        Net      -        -       0.000     -           1         
u_i2c_master.bit_controller.c_state[0]               DFFP     D        In      -         4.353       -         
===============================================================================================================
Total path delay (propagation time + setup) of 4.414 is 2.542(57.6%) logic and 1.872(42.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      3.770
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.709

    - Propagation time:                      4.332
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.623

    Number of logic level(s):                4
    Starting point:                          u_i2c_master.bit_controller.c_state[15] / Q
    Ending point:                            u_i2c_master.bit_controller.c_state[0] / D
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                 Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.c_state[15]              DFFC     Q        Out     0.243     0.243       -         
c_state[15]                                          Net      -        -       0.535     -           4         
u_i2c_master.bit_controller.sda_chk_4_i_a2           LUT2     I0       In      -         0.778       -         
u_i2c_master.bit_controller.sda_chk_4_i_a2           LUT2     F        Out     0.549     1.327       -         
N_218                                                Net      -        -       0.535     -           3         
u_i2c_master.bit_controller.c_state_ns_o2_1_4[0]     LUT4     I0       In      -         1.862       -         
u_i2c_master.bit_controller.c_state_ns_o2_1_4[0]     LUT4     F        Out     0.549     2.411       -         
c_state_ns_o2_1_4[0]                                 Net      -        -       0.401     -           1         
u_i2c_master.bit_controller.c_state_ns_o2_1[0]       LUT4     I1       In      -         2.812       -         
u_i2c_master.bit_controller.c_state_ns_o2_1[0]       LUT4     F        Out     0.570     3.382       -         
N_196                                                Net      -        -       0.401     -           1         
u_i2c_master.bit_controller.c_state_ns[0]            LUT2     I0       In      -         3.783       -         
u_i2c_master.bit_controller.c_state_ns[0]            LUT2     F        Out     0.549     4.332       -         
c_state_ns[0]                                        Net      -        -       0.000     -           1         
u_i2c_master.bit_controller.c_state[0]               DFFP     D        In      -         4.332       -         
===============================================================================================================
Total path delay (propagation time + setup) of 4.393 is 2.521(57.4%) logic and 1.872(42.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      3.770
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.709

    - Propagation time:                      4.327
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.618

    Number of logic level(s):                4
    Starting point:                          u_i2c_master.bit_controller.cnt[13] / Q
    Ending point:                            u_i2c_master.bit_controller.cnt[0] / D
    The start point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                        Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.cnt[13]         DFFCE     Q        Out     0.243     0.243       -         
cnt[13]                                     Net       -        -       0.535     -           3         
u_i2c_master.bit_controller.un1_cnt_9       LUT4      I1       In      -         0.778       -         
u_i2c_master.bit_controller.un1_cnt_9       LUT4      F        Out     0.570     1.348       -         
un1_cnt_9                                   Net       -        -       0.401     -           1         
u_i2c_master.bit_controller.un1_cnt_12      LUT2      I1       In      -         1.749       -         
u_i2c_master.bit_controller.un1_cnt_12      LUT2      F        Out     0.570     2.319       -         
un1_cnt_12                                  Net       -        -       0.401     -           1         
u_i2c_master.bit_controller.cnt8            LUT4      I2       In      -         2.720       -         
u_i2c_master.bit_controller.cnt8            LUT4      F        Out     0.462     3.182       -         
cnt8                                        Net       -        -       0.596     -           17        
u_i2c_master.bit_controller.cnt_lm_0[0]     LUT3      I0       In      -         3.778       -         
u_i2c_master.bit_controller.cnt_lm_0[0]     LUT3      F        Out     0.549     4.327       -         
cnt_lm[0]                                   Net       -        -       0.000     -           1         
u_i2c_master.bit_controller.cnt[0]          DFFCE     D        In      -         4.327       -         
=======================================================================================================
Total path delay (propagation time + setup) of 4.388 is 2.455(55.9%) logic and 1.933(44.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                Starting                                            Arrival           
Instance                                        Reference     Type     Pin     Net                  Time        Slack 
                                                Clock                                                                 
----------------------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.SCL_OEN_RNIJ002     System        INV      O       un1_scl_padoen_o     0.000       -0.080
u_i2c_master.bit_controller.SDA_OEN_RNI9P6E     System        INV      O       un1_sda_padoen_o     0.000       -0.080
u_i2c_master.I_RESETN_RNIPH41                   System        INV      O       I_RESETN_i           0.000       3.174 
======================================================================================================================


Ending Points with Worst Slack
******************************

                                            Starting                                               Required           
Instance                                    Reference     Type     Pin        Net                  Time         Slack 
                                            Clock                                                                     
----------------------------------------------------------------------------------------------------------------------
un1_SDA_RNO                                 System        INV      I          un1_sda_padoen_o     0.455        -0.080
un2_SCL_RNO                                 System        INV      I          un1_scl_padoen_o     0.455        -0.080
u_i2c_master.bit_controller.c_state[0]      System        DFFP     PRESET     I_RESETN_i           3.709        3.174 
u_i2c_master.byte_controller.c_state[0]     System        DFFP     PRESET     I_RESETN_i           3.709        3.174 
u_i2c_master.bit_controller.clk_en          System        DFFP     PRESET     I_RESETN_i           3.709        3.174 
u_i2c_master.bit_controller.dSCL            System        DFFP     PRESET     I_RESETN_i           3.709        3.174 
u_i2c_master.bit_controller.dSDA            System        DFFP     PRESET     I_RESETN_i           3.709        3.174 
u_i2c_master.bit_controller.sSCL            System        DFFP     PRESET     I_RESETN_i           3.709        3.174 
u_i2c_master.bit_controller.sSDA            System        DFFP     PRESET     I_RESETN_i           3.709        3.174 
======================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      0.455
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         0.455

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.080

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.bit_controller.SCL_OEN_RNIJ002 / O
    Ending point:                            un2_SCL_RNO / I
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                            Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.SCL_OEN_RNIJ002     INV      O        Out     0.000     0.000       -         
un1_scl_padoen_o                                Net      -        -       0.535     -           1         
un2_SCL_RNO                                     INV      I        In      -         0.535       -         
==========================================================================================================
Total path delay (propagation time + setup) of 0.535 is 0.000(0.0%) logic and 0.535(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      0.455
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         0.455

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.080

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.bit_controller.SDA_OEN_RNI9P6E / O
    Ending point:                            un1_SDA_RNO / I
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                            Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
u_i2c_master.bit_controller.SDA_OEN_RNI9P6E     INV      O        Out     0.000     0.000       -         
un1_sda_padoen_o                                Net      -        -       0.535     -           1         
un1_SDA_RNO                                     INV      I        In      -         0.535       -         
==========================================================================================================
Total path delay (propagation time + setup) of 0.535 is 0.000(0.0%) logic and 0.535(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      3.770
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.709

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.174

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.I_RESETN_RNIPH41 / O
    Ending point:                            u_i2c_master.bit_controller.c_state[0] / PRESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                      Pin        Pin               Arrival     No. of    
Name                                       Type     Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
u_i2c_master.I_RESETN_RNIPH41              INV      O          Out     0.000     0.000       -         
I_RESETN_i                                 Net      -          -       0.535     -           134       
u_i2c_master.bit_controller.c_state[0]     DFFP     PRESET     In      -         0.535       -         
=======================================================================================================
Total path delay (propagation time + setup) of 0.596 is 0.061(10.2%) logic and 0.535(89.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      3.770
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.709

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.174

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.I_RESETN_RNIPH41 / O
    Ending point:                            u_i2c_master.bit_controller.clk_en / PRESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                  Pin        Pin               Arrival     No. of    
Name                                   Type     Name       Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
u_i2c_master.I_RESETN_RNIPH41          INV      O          Out     0.000     0.000       -         
I_RESETN_i                             Net      -          -       0.535     -           134       
u_i2c_master.bit_controller.clk_en     DFFP     PRESET     In      -         0.535       -         
===================================================================================================
Total path delay (propagation time + setup) of 0.596 is 0.061(10.2%) logic and 0.535(89.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      3.770
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.709

    - Propagation time:                      0.535
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.174

    Number of logic level(s):                0
    Starting point:                          u_i2c_master.I_RESETN_RNIPH41 / O
    Ending point:                            u_i2c_master.bit_controller.dSCL / PRESET
    The start point is clocked by            System [rising]
    The end   point is clocked by            I2C_MASTER_Top|I_CLK [rising] on pin CLK

Instance / Net                                Pin        Pin               Arrival     No. of    
Name                                 Type     Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
u_i2c_master.I_RESETN_RNIPH41        INV      O          Out     0.000     0.000       -         
I_RESETN_i                           Net      -          -       0.535     -           134       
u_i2c_master.bit_controller.dSCL     DFFP     PRESET     In      -         0.535       -         
=================================================================================================
Total path delay (propagation time + setup) of 0.596 is 0.061(10.2%) logic and 0.535(89.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 228MB peak: 229MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 228MB peak: 229MB)

---------------------------------------
Resource Usage Report for I2C_MASTER_Top 

Mapping to part: gw2ar_18lqfp176-8
Cell usage:
ALU             16 uses
DFF             1 use
DFFC            44 uses
DFFCE           81 uses
DFFP            7 uses
DFFPE           2 uses
GSR             1 use
INV             5 uses
MUX2_LUT5       8 uses
LUT2            19 uses
LUT3            55 uses
LUT4            110 uses

I/O ports: 29
I/O primitives: 2
IOBUF          2 uses

I/O Register bits:                  0
Register bits not including I/Os:   135 of 15552 (0%)
Total load per clock:
   I2C_MASTER_Top|I_CLK: 135

@S |Mapping Summary:
Total  LUTs: 184 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 74MB peak: 229MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Mon Dec  9 10:09:10 2019

###########################################################]
