D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\bin64\m_generic.exe  -prodtype  synplify_pro   -encrypt  -pro  -rundir  D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1   -part GW2A_18  -package PBGA484  -grade -8    -maxfan 10000 -RWCheckOnRam 1 -block -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -gcc_allow_lat_combloops 0 -gcc_convert_lats_to_regs 0 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\synlog\report\ddr3_memory_interface_fpga_mapper.xml -merge_inferred_clocks 0  -implementation  rev_1  -flow mapping  -multisrs  -ovm  D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface.vm   -autoconstraint  -freq 150.000   D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\synwork\ddr3_memory_interface_prem.srd  -sap  D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface.sap  -otap  D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface.tap  -omap  D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface.map  -devicelib  D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\generic\gw2a.v  -ologparam  D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\syntmp\ddr3_memory_interface.plg  -osyn  D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface.srm  -prjdir  D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\  -prjname  DDR3  -log  D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\synlog\ddr3_memory_interface_fpga_mapper.srr  -sn  2020.03  -jobname  "fpga_mapper" 
relcom:..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.6Beta\SynplifyPro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\rev_1 -part GW2A_18 -package PBGA484 -grade -8 -maxfan 10000 -RWCheckOnRam 1 -block -pipe -fixgatedclocks 1 -fixgeneratedclocks 1 -gcc_allow_lat_combloops 0 -gcc_convert_lats_to_regs 0 -csa_carry_chain_maxlen 0 -infer_seqShift -enable_gcc_in_premap -preserve_slash_names -summaryfile ..\synlog\report\ddr3_memory_interface_fpga_mapper.xml -merge_inferred_clocks 0 -implementation rev_1 -flow mapping -multisrs -ovm ..\ddr3_memory_interface.vm -autoconstraint -freq 150.000 ..\synwork\ddr3_memory_interface_prem.srd -sap ..\ddr3_memory_interface.sap -otap ..\ddr3_memory_interface.tap -omap ..\ddr3_memory_interface.map -devicelib ..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\generic\gw2a.v -ologparam ddr3_memory_interface.plg -osyn ..\ddr3_memory_interface.srm -prjdir ..\..\ -prjname DDR3 -log ..\synlog\ddr3_memory_interface_fpga_mapper.srr -sn 2020.03 -jobname "fpga_mapper"
rc:1 success:1 runtime:20
file:..\ddr3_memory_interface.vm|io:o|time:1592387439|size:1024033|exec:0|csum:
file:..\synwork\ddr3_memory_interface_prem.srd|io:i|time:1592387420|size:1309590|exec:0|csum:419708421F302DAE45D92276ED20562A
file:..\ddr3_memory_interface.sap|io:o|time:1592387421|size:306|exec:0|csum:
file:..\ddr3_memory_interface.tap|io:o|time:0|size:-1|exec:0|csum:
file:..\ddr3_memory_interface.map|io:o|time:1592387440|size:28|exec:0|csum:
file:..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\generic\gw2a.v|io:i|time:1589223686|size:163815|exec:0|csum:9E2600B864B99F5A90D449698CC6DFCB
file:ddr3_memory_interface.plg|io:o|time:1592387440|size:5483|exec:0|csum:
file:..\ddr3_memory_interface.srm|io:o|time:1592387437|size:14359|exec:0|csum:
file:..\synlog\ddr3_memory_interface_fpga_mapper.srr|io:o|time:1592387440|size:111025|exec:0|csum:
file:..\..\..\..\..\..\..\..\..\Gowin\Gowin_V1.9.6Beta\SynplifyPro\bin64\m_generic.exe|io:i|time:1589872814|size:42754560|exec:1|csum:8A5C66A99D1A39CA6F46967D21D4CCBB
