@W: MT246 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\ddr3\data\ddr3_1_4code.v":3506:7:3506:12|Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\ddr3\data\ddr3_1_4code.v":3499:6:3499:12|Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\ddr3\data\ddr3_1_4code.v":3427:4:3427:8|Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\ddr3\data\ddr3_1_4code.v":4165:2:4165:6|Blackbox DLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\ddr3\data\ddr3_1_4code.v":2785:2:2785:6|Blackbox DQS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock with period 6.31ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.clk_out.
@W: MT420 |Found inferred clock DDR3_Memory_Interface_Top|clk with period 3.42ns. Please declare a user-defined clock on port clk.
@W: MT420 |Found inferred clock _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.clk_x4i.
@W: MT420 |Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsw0.
@W: MT420 |Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsw270.
@W: MT420 |Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsr90.
@W: MT420 |Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsw0.
@W: MT420 |Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsw270.
@W: MT420 |Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsr90.
