i RdClk
m 0 0
u 9 189
p {p:RdClk}{t:fifo_inst.RdClk}{p:ENCRYPTED}{t:ENCRYPTED}
e ckid0_0 {t:ENCRYPTED} <ENCRYPTED>
c ckid0_0 {p:RdClk} port Unsupported/too complex instance on clock path
i WrClk
m 0 0
u 10 48
p {p:WrClk}{t:fifo_inst.WrClk}{p:ENCRYPTED}{t:ENCRYPTED}
e ckid0_1 {t:ENCRYPTED} <ENCRYPTED>
c ckid0_1 {p:WrClk} port Unsupported/too complex instance on clock path
l 0 0 0 0 0
r 0 0 0 0 0 0 0 0
