<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\rev_1\synlog\fifo_dma_write_32_128_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>fifo_dma_write_32_128|RdClk</data>
<data>188.5 MHz</data>
<data>160.2 MHz</data>
<data>-0.936</data>
</row>
<row>
<data>fifo_dma_write_32_128|WrClk</data>
<data>192.5 MHz</data>
<data>163.6 MHz</data>
<data>-0.917</data>
</row>
<row>
<data>System</data>
<data>150.0 MHz</data>
<data>237.1 MHz</data>
<data>2.449</data>
</row>
</report_table>
