@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG346 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":1676:34:1676:42|Read full_case directive.
@N: CG347 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":1676:44:1676:56|Read a parallel_case directive.
@N: CG364 :"D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v":1:0:1:8|Synthesizing module work_D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v_unit in library work.
@N: CG364 :"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v":6:23:6:23|Synthesizing module DDR3_Memory_Interface_Top in library work.
@N|Running in 64-bit mode
@N: NF107 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\ddr3\data\ddr3_top.v":6:23:6:23|Selected library: work cell: DDR3_Memory_Interface_Top view verilog as top level
@N: NF107 :"d:\gowin\gowin_v1.9.6beta\ide\ipcore\ddr3\data\ddr3_top.v":6:23:6:23|Selected library: work cell: DDR3_Memory_Interface_Top view verilog as top level

