`

    #Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020
    #install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GZAE-AE-CAOJIE

    # Wed Jun 17 17:50:12 2020

    #Implementation: rev_1

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v" (library work)
    @I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v" (library work)
    @I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v" (library work)
    @I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v" (library work)
    @I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v" (library work)
    @W:CG1337 : ddr3_1_4code.v(1056) | Net cke_en is not declared.
    @N:CG346 : ddr3_1_4code.v(1676) | Read full_case directive.
    @N:CG347 : ddr3_1_4code.v(1676) | Read a parallel_case directive.
    @W:CG286 : ddr3_1_4code.v(1676) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive.
    @W:CG921 : ddr3_1_4code.v(2893) | recalib is already declared in this scope.
    @W:CG921 : ddr3_1_4code.v(3288) | ddr_rsti is already declared in this scope.
    @I:"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v":"D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v" (library work)
    @W:CG921 : ddr3_1_4code.v(3683) | dll_lock is already declared in this scope.
    @W:CG921 : ddr3_1_4code.v(3711) | pause is already declared in this scope.
    @W:CG921 : ddr3_1_4code.v(3711) | stop is already declared in this scope.
    @W:CG921 : ddr3_1_4code.v(3711) | ddr_rsti is already declared in this scope.
    @W:CG1337 : ddr3_1_4code.v(6290) | Net act_one_bank is not declared.
    @W:CG104 : ddr3_1_4code.v(6775) | Unsized number in concatenation is 32 bits
    @W:CG1337 : ddr3_1_4code.v(6776) | Net sent_col is not declared.
    @W:CG1337 : ddr3_1_4code.v(6777) | Net sent_row is not declared.
    @W:CG1337 : ddr3_1_4code.v(6802) | Net send_cs_en0 is not declared.
    @W:CG1337 : ddr3_1_4code.v(6803) | Net send_cs_en1 is not declared.
    @W:CG1337 : ddr3_1_4code.v(6804) | Net send_cs_en2 is not declared.
    @W:CG1337 : ddr3_1_4code.v(6805) | Net send_cs_en3 is not declared.
    @W:CG1337 : ddr3_1_4code.v(6808) | Net send_cmd0_col is not declared.
    @W:CG1337 : ddr3_1_4code.v(6809) | Net send_cmd1_col is not declared.
    @W:CG1337 : ddr3_1_4code.v(6811) | Net send_cmd0_row is not declared.
    @W:CG1337 : ddr3_1_4code.v(6812) | Net send_cmd1_row is not declared.
    @W:CG1337 : ddr3_1_4code.v(7930) | Net wr_wrbuf is not declared.
    @W:CG1337 : ddr3_1_4code.v(8015) | Net bl is not declared.
    @W:CG921 : ddr3_1_4code.v(8336) | ddr_rst is already declared in this scope.
    @I::"D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v" (library work)
    Verilog syntax check successful!
    @N:CG364 : gwmc_param.v(1) | Synthesizing module work_D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v_unit in library work.
    Selecting top level module DDR3_Memory_Interface_Top
    @N:CG364 : DDR3_TOP.v(6) | Synthesizing module DDR3_Memory_Interface_Top in library work.
    Running optimization stage 1 on \~gwmc_cmd_buffer.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on \~gwmc_bank_ctrl.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on \~gwmc_timing_ctrl.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on \~fifo_sc.DDR3_Memory_Interface_Top _144s_4s_16s_1s_2s_1s_2s_1s_12s_0s .......
    Running optimization stage 1 on \~gwmc_wr_data.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on \~gwmc_rd_data.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on \~gwmc_rank_ctrl.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on \~gwmc_top.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on ELVDS_OBUF .......
    Running optimization stage 1 on OBUF .......
    Running optimization stage 1 on \~CMD_FIFO.DDR3_Memory_Interface_Top _4s_2s_FALSE_23s_4s .......
    Running optimization stage 1 on OSER8 .......
    Running optimization stage 1 on \~ddr_phy_cmd_io.DDR3_Memory_Interface_Top _92s .......
    Running optimization stage 1 on \~ddr_phy_cmd_lane.DDR3_Memory_Interface_Top _Z1 .......
    Running optimization stage 1 on \~fifo_ctrl.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on \~ddr_phy_reset_gen.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on DLL .......
    Running optimization stage 1 on \~ddr_memmem_sync.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on ELVDS_IOBUF .......
    Running optimization stage 1 on IOBUF .......
    Running optimization stage 1 on IODELAY .......
    Running optimization stage 1 on TBUF .......
    Running optimization stage 1 on \~OUT_FIFO.DDR3_Memory_Interface_Top _8s_5s_16s_8s_2s_8s .......
    Running optimization stage 1 on \~IN_FIFO.DDR3_Memory_Interface_Top _8s_5s_8s .......
    Running optimization stage 1 on OSER8_MEM .......
    Running optimization stage 1 on IDES8_MEM .......
    Running optimization stage 1 on DQS .......
    Running optimization stage 1 on \~ddr_phy_data_io.DDR3_Memory_Interface_Top _16s_8s_2500s_5s_5s .......
    Running optimization stage 1 on \~ddr_phy_data_lane.DDR3_Memory_Interface_Top _16s_8s_5s_5s_5s_5s .......
    Running optimization stage 1 on \~ddr_phy_wd.DDR3_Memory_Interface_Top _Z2 .......
    Running optimization stage 1 on \~ddr_init.DDR3_Memory_Interface_Top _Z3 .......
    Running optimization stage 1 on PLL .......
    Running optimization stage 1 on DHCEN .......
    Running optimization stage 1 on CLKDIV .......
    Running optimization stage 1 on \~ddr_phy_top.DDR3_Memory_Interface_Top _Z4 .......
    Running optimization stage 1 on \~gw3_phy_mc.DDR3_Memory_Interface_Top  .......
    Running optimization stage 1 on DDR3_Memory_Interface_Top .......
    Running optimization stage 2 on \~gw3_phy_mc.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on \~ddr_phy_top.DDR3_Memory_Interface_Top _Z4 .......
    Running optimization stage 2 on CLKDIV .......
    Running optimization stage 2 on DHCEN .......
    Running optimization stage 2 on PLL .......
    Running optimization stage 2 on \~ddr_init.DDR3_Memory_Interface_Top _Z3 .......
    Extracted state machine for register read_cal_state
    State machine has 13 reachable states with original encodings of:
       0000000000001
       0000000000010
       0000000000100
       0000000001000
       0000000010000
       0000000100000
       0000001000000
       0000010000000
       0000100000000
       0001000000000
       0010000000000
       0100000000000
       1000000000000
    Extracted state machine for register wrlvl_state
    State machine has 10 reachable states with original encodings of:
       0000000001
       0000000010
       0000000100
       0000001000
       0000010000
       0000100000
       0001000000
       0010000000
       0100000000
       1000000000
    Extracted state machine for register init_state
    State machine has 19 reachable states with original encodings of:
       000000000000000000000000001
       000000000000000000000000010
       000000000000000000000000100
       000000000000000100000000000
       000000000000001000000000000
       000000000000010000000000000
       000000000000100000000000000
       000000000001000000000000000
       000000000010000000000000000
       000000000100000000000000000
       000000001000000000000000000
       000000010000000000000000000
       000000100000000000000000000
       000001000000000000000000000
       000010000000000000000000000
       000100000000000000000000000
       001000000000000000000000000
       010000000000000000000000000
       100000000000000000000000000
    Running optimization stage 2 on \~ddr_phy_data_lane.DDR3_Memory_Interface_Top _16s_8s_5s_5s_5s_5s .......
    Running optimization stage 2 on DQS .......
    Running optimization stage 2 on IDES8_MEM .......
    Running optimization stage 2 on \~ddr_phy_data_io.DDR3_Memory_Interface_Top _16s_8s_2500s_5s_5s .......
    Running optimization stage 2 on OSER8_MEM .......
    Running optimization stage 2 on \~IN_FIFO.DDR3_Memory_Interface_Top _8s_5s_8s .......
    Running optimization stage 2 on \~OUT_FIFO.DDR3_Memory_Interface_Top _8s_5s_16s_8s_2s_8s .......
    Running optimization stage 2 on TBUF .......
    Running optimization stage 2 on IODELAY .......
    Running optimization stage 2 on IOBUF .......
    Running optimization stage 2 on ELVDS_IOBUF .......
    Running optimization stage 2 on \~ddr_phy_wd.DDR3_Memory_Interface_Top _Z2 .......
    Running optimization stage 2 on \~ddr_memmem_sync.DDR3_Memory_Interface_Top  .......
    Extracted state machine for register flag
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    Running optimization stage 2 on DLL .......
    Running optimization stage 2 on \~ddr_phy_reset_gen.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on \~fifo_ctrl.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on \~ddr_phy_cmd_lane.DDR3_Memory_Interface_Top _Z1 .......
    Running optimization stage 2 on \~ddr_phy_cmd_io.DDR3_Memory_Interface_Top _92s .......
    Running optimization stage 2 on OSER8 .......
    Running optimization stage 2 on \~CMD_FIFO.DDR3_Memory_Interface_Top _4s_2s_FALSE_23s_4s .......
    Running optimization stage 2 on OBUF .......
    Running optimization stage 2 on ELVDS_OBUF .......
    Running optimization stage 2 on \~gwmc_top.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on \~gwmc_rank_ctrl.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on \~gwmc_rd_data.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on \~gwmc_wr_data.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on \~fifo_sc.DDR3_Memory_Interface_Top _144s_4s_16s_1s_2s_1s_2s_1s_12s_0s .......
    Running optimization stage 2 on \~gwmc_timing_ctrl.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on \~gwmc_bank_ctrl.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on \~gwmc_cmd_buffer.DDR3_Memory_Interface_Top  .......
    Running optimization stage 2 on DDR3_Memory_Interface_Top .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 114MB peak: 118MB)

    Process took 0h:00m:03s realtime, 0h:00m:03s cputime

    Process completed successfully.
    # Wed Jun 17 17:50:16 2020

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode
    @N:NF107 : ddr3_top.v(6) | Selected library: work cell: DDR3_Memory_Interface_Top view verilog as top level
    @N:NF107 : ddr3_top.v(6) | Selected library: work cell: DDR3_Memory_Interface_Top view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Jun 17 17:50:16 2020

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  ddr3_memory_interface_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 22MB peak: 22MB)

    Process took 0h:00m:03s realtime, 0h:00m:03s cputime

    Process completed successfully.
    # Wed Jun 17 17:50:16 2020

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

    @N: :  | Running in 64-bit mode
    @N:NF107 : ddr3_top.v(6) | Selected library: work cell: DDR3_Memory_Interface_Top view verilog as top level
    @N:NF107 : ddr3_top.v(6) | Selected library: work cell: DDR3_Memory_Interface_Top view verilog as top level

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Jun 17 17:50:18 2020

    ###########################################################]

`
`

    Premap Report

`
`

    # Wed Jun 17 17:50:18 2020

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1620R, Built May 18 2020 06:06:53, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  ddr3_memory_interface_scck.rpt
    See clock summary report "D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface_scck.rpt"
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 140MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 151MB peak: 153MB)

    Encoding state machine flag[2:0] (in view: work.\\\~ddr_memmem_sync\.DDR3_Memory_Interface_Top\ (verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine init_state[18:0] (in view: work.\\\~ddr_init\.DDR3_Memory_Interface_Top\ _Z3(verilog))
    original code -> new code
       000000000000000000000000001 -> 0000000000000000001
       000000000000000000000000010 -> 0000000000000000010
       000000000000000000000000100 -> 0000000000000000100
       000000000000000100000000000 -> 0000000000000001000
       000000000000001000000000000 -> 0000000000000010000
       000000000000010000000000000 -> 0000000000000100000
       000000000000100000000000000 -> 0000000000001000000
       000000000001000000000000000 -> 0000000000010000000
       000000000010000000000000000 -> 0000000000100000000
       000000000100000000000000000 -> 0000000001000000000
       000000001000000000000000000 -> 0000000010000000000
       000000010000000000000000000 -> 0000000100000000000
       000000100000000000000000000 -> 0000001000000000000
       000001000000000000000000000 -> 0000010000000000000
       000010000000000000000000000 -> 0000100000000000000
       000100000000000000000000000 -> 0001000000000000000
       001000000000000000000000000 -> 0010000000000000000
       010000000000000000000000000 -> 0100000000000000000
       100000000000000000000000000 -> 1000000000000000000
    Encoding state machine read_cal_state[12:0] (in view: work.\\\~ddr_init\.DDR3_Memory_Interface_Top\ _Z3(verilog))
    original code -> new code
       0000000000001 -> 0000000000001
       0000000000010 -> 0000000000010
       0000000000100 -> 0000000000100
       0000000001000 -> 0000000001000
       0000000010000 -> 0000000010000
       0000000100000 -> 0000000100000
       0000001000000 -> 0000001000000
       0000010000000 -> 0000010000000
       0000100000000 -> 0000100000000
       0001000000000 -> 0001000000000
       0010000000000 -> 0010000000000
       0100000000000 -> 0100000000000
       1000000000000 -> 1000000000000
    Encoding state machine wrlvl_state[9:0] (in view: work.\\\~ddr_init\.DDR3_Memory_Interface_Top\ _Z3(verilog))
    original code -> new code
       0000000001 -> 0000000001
       0000000010 -> 0000000010
       0000000100 -> 0000000100
       0000001000 -> 0000001000
       0000010000 -> 0000010000
       0000100000 -> 0000100000
       0001000000 -> 0001000000
       0010000000 -> 0010000000
       0100000000 -> 0100000000
       1000000000 -> 1000000000

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 239MB peak: 239MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB)

    @N:MF578 :  | Incompatible asynchronous control logic preventing generated clock conversion.

    Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB)

    Clock Summary
    ******************

              Start                                                                                        Requested     Requested     Clock        Clock                     Clock
    Level     Clock                                                                                        Frequency     Period        Type         Group                     Load
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    0 -       System                                                                                       150.0 MHz     6.667         system       system_clkgroup           0

    0 -       _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                            162.3 MHz     6.160         inferred     Autoconstr_clkgroup_0     2739

    0 -       _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                           150.0 MHz     6.667         inferred     Autoconstr_clkgroup_2     60

    0 -       DDR3_Memory_Interface_Top|clk                                                                302.5 MHz     3.306         inferred     Autoconstr_clkgroup_1     33

    0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_7     9

    0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_4     9

    0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock      150.0 MHz     6.667         inferred     Autoconstr_clkgroup_8     8

    0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock      150.0 MHz     6.667         inferred     Autoconstr_clkgroup_5     8

    0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock       150.0 MHz     6.667         inferred     Autoconstr_clkgroup_6     1

    0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock       150.0 MHz     6.667         inferred     Autoconstr_clkgroup_3     1
    ===============================================================================================================================================================================

    Clock Load Summary
    ***********************

                                                                                                 Clock     Source                                                                                                                               Clock Pin                                                                                                                                      Non-clock Pin                                                                                                                                  Non-clock Pin
    Clock                                                                                        Load      Pin                                                                                                                                  Seq Example                                                                                                                                    Seq Example                                                                                                                                    Comb Example
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                                                                       0         -                                                                                                                                    -                                                                                                                                              -                                                                                                                                              -

    _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                            2739      genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv.CLKOUT(CLKDIV)                                                                               genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.read_cmd0.C                                                                                        genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem.PCLK     -

    _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                           60        genblk1\.gw3mc_top.u_ddr_phy_top.u_dqcen.CLKOUT(DHCEN)                                                                               genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_ddr_phy_cmd_lane.u_ddr_phy_cmd_io.mcd_oserdes_gen\[15\]\.u_cmd_gen.FCLK                        -                                                                                                                                              -

    DDR3_Memory_Interface_Top|clk                                                                33        clk(port)                                                                                                                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.recalib_s[1:0].C                                                                      -                                                                                                                                              -

    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock     9         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW270(DQS)     genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.oserdes_gen\[5\]\.u_oser8_mem.TCLK     -                                                                                                                                              -

    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock     9         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW270(DQS)     genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.oserdes_gen\[5\]\.u_oser8_mem.TCLK     -                                                                                                                                              -

    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock      8         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSR90(DQS)      genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem.ICLK     -                                                                                                                                              -

    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock      8         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSR90(DQS)      genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem.ICLK     -                                                                                                                                              -

    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock       1         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW0(DQS)       genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.u_dqs_gen.TCLK                         -                                                                                                                                              -

    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock       1         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW0(DQS)       genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.u_dqs_gen.TCLK                         -                                                                                                                                              -
    =======================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    9 non-gated/non-generated clock tree(s) driving 2362 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           CLKDIV                 2233       ENCRYPTED
    ClockId_0_1       clk                 port                   33         ENCRYPTED
    ClockId_0_2       ENCRYPTED           DHCEN                  60         ENCRYPTED
    ClockId_0_3       ENCRYPTED           DQS                    8          ENCRYPTED
    ClockId_0_4       ENCRYPTED           DQS                    9          ENCRYPTED
    ClockId_0_5       ENCRYPTED           DQS                    1          ENCRYPTED
    ClockId_0_6       ENCRYPTED           DQS                    8          ENCRYPTED
    ClockId_0_7       ENCRYPTED           DQS                    9          ENCRYPTED
    ClockId_0_8       ENCRYPTED           DQS                    1          ENCRYPTED
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB)

    Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 242MB peak: 242MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 242MB)

    Process took 0h:00m:03s realtime, 0h:00m:03s cputime
    # Wed Jun 17 17:50:21 2020

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Wed Jun 17 17:50:22 2020

    Copyright (C) 1994-2020 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: Q-2020.03G-Beta1
    Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1620R, Built May 18 2020 06:06:53, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 234MB)

    Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 245MB peak: 245MB)

    Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 251MB peak: 251MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 258MB peak: 258MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 258MB peak: 258MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 258MB peak: 258MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 258MB peak: 258MB)

    Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 258MB peak: 258MB)

    Finished technology mapping (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 290MB peak: 290MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:09s		    -4.38ns		1803 /      1788
       2		0h:00m:09s		    -4.38ns		1795 /      1788
       3		0h:00m:09s		    -4.38ns		1795 /      1788
       4		0h:00m:09s		    -4.38ns		1795 /      1788
       5		0h:00m:09s		    -4.38ns		1795 /      1788

       6		0h:00m:11s		    -4.38ns		1795 /      1788
       7		0h:00m:11s		    -4.38ns		1802 /      1788
       8		0h:00m:11s		    -4.38ns		1803 /      1788
       9		0h:00m:11s		    -4.38ns		1803 /      1788
      10		0h:00m:11s		    -4.38ns		1804 /      1788

      11		0h:00m:12s		    -3.43ns		1817 /      1788
      12		0h:00m:12s		    -3.43ns		1818 /      1788
      13		0h:00m:12s		    -3.43ns		1817 /      1788
      14		0h:00m:12s		    -3.43ns		1818 /      1788

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 292MB peak: 292MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 292MB peak: 292MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 210MB peak: 293MB)

    Writing Analyst data base D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\synwork\ddr3_memory_interface_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 286MB peak: 293MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 287MB peak: 293MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 287MB peak: 293MB)

    Start final timing analysis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 281MB peak: 293MB)

    @W:MT246 : ddr3_1_4code.v(3506) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : ddr3_1_4code.v(3499) | Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : ddr3_1_4code.v(3427) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : ddr3_1_4code.v(4165) | Blackbox DLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : ddr3_1_4code.v(2785) | Blackbox DQS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock with period 6.31ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.clk_out.
    @W:MT420 :  | Found inferred clock DDR3_Memory_Interface_Top|clk with period 3.42ns. Please declare a user-defined clock on port clk.
    @W:MT420 :  | Found inferred clock _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.clk_x4i.
    @W:MT420 :  | Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsw0.
    @W:MT420 :  | Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsw270.
    @W:MT420 :  | Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsr90.
    @W:MT420 :  | Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsw0.
    @W:MT420 :  | Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsw270.
    @W:MT420 :  | Found inferred clock _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock with period 6.67ns. Please declare a user-defined clock on net genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.dqsr90.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Wed Jun 17 17:50:40 2020
    #

    Top view:               DDR3_Memory_Interface_Top
    Requested Frequency:    150.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.996

                                                                                                 Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock                                                                               Frequency     Frequency     Period        Period        Slack      Type         Group
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    DDR3_Memory_Interface_Top|clk                                                                292.1 MHz     248.3 MHz     3.424         4.028         -0.604     inferred     Autoconstr_clkgroup_1
    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock      150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_8
    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock       150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_6
    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_7
    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock      150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_5
    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock       150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_3
    _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_4
    _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                            158.6 MHz     134.8 MHz     6.306         7.419         -1.113     inferred     Autoconstr_clkgroup_0
    _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                           150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_2
    System                                                                                       726.6 MHz     617.7 MHz     1.376         1.619         -0.243     system       system_clkgroup
    ==================================================================================================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks                                                                                                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                                           Ending                                                                                   |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                                             System                                                                                   |  1.376       -0.243  |  No paths    -      |  No paths    -      |  No paths    -
    System                                                             _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                        |  6.306       -1.996  |  No paths    -      |  No paths    -      |  No paths    -
    System                                                             DDR3_Memory_Interface_Top|clk                                                            |  3.424       2.258   |  No paths    -      |  No paths    -      |  No paths    -
    System                                                             _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                       |  6.667       6.071   |  No paths    -      |  No paths    -      |  No paths    -
    System                                                             _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock  |  No paths    -       |  No paths    -      |  6.667       6.071  |  No paths    -
    System                                                             _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock  |  No paths    -       |  No paths    -      |  6.667       6.071  |  No paths    -
    _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock  System                                                                                   |  6.306       0.158   |  No paths    -      |  No paths    -      |  No paths    -
    _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                        |  6.306       -1.113  |  No paths    -      |  No paths    -      |  No paths    -
    _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock  DDR3_Memory_Interface_Top|clk                                                            |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    DDR3_Memory_Interface_Top|clk                                      System                                                                                   |  3.424       -0.770  |  No paths    -      |  No paths    -      |  No paths    -
    DDR3_Memory_Interface_Top|clk                                      _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                        |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    DDR3_Memory_Interface_Top|clk                                      DDR3_Memory_Interface_Top|clk                                                            |  3.424       -0.604  |  No paths    -      |  No paths    -      |  No paths    -
    ===================================================================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: DDR3_Memory_Interface_Top|clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                               Starting                                                              Arrival
    Instance                                                                   Reference                         Type      Pin     Net               Time        Slack
                                                                               Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.cs_memsync[3]     DDR3_Memory_Interface_Top|clk     DFFCE     Q       cs_memsync[3]     0.243       -0.770
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.dll_rst           DDR3_Memory_Interface_Top|clk     DFFP      Q       dll_rsti          0.243       -0.688
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_syn[1]       DDR3_Memory_Interface_Top|clk     DFFC      Q       lock_cnt          0.243       -0.604
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[0]       DDR3_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[0]       0.243       -0.564
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[1]       DDR3_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[1]       0.243       -0.529
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[2]       DDR3_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[2]       0.243       -0.494
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[3]       DDR3_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[3]       0.243       -0.459
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[4]       DDR3_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[4]       0.243       -0.424
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[5]       DDR3_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[5]       0.243       -0.389
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[6]       DDR3_Memory_Interface_Top|clk     DFFCE     Q       lock_cnt[6]       0.243       -0.354
    ===================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                                                                            Starting                                                                Required
    Instance                                                                                                                Reference                         Type      Pin      Net                Time         Slack
                                                                                                                            Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs     DDR3_Memory_Interface_Top|clk     DQS       HOLD     pause_en           3.424        -0.770
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs     DDR3_Memory_Interface_Top|clk     DQS       HOLD     pause_en           3.424        -0.770
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[15]                                                   DDR3_Memory_Interface_Top|clk     DFFCE     D        lock_cnt_s[15]     3.363        -0.604
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[14]                                                   DDR3_Memory_Interface_Top|clk     DFFCE     D        lock_cnt_s[14]     3.363        -0.569
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[13]                                                   DDR3_Memory_Interface_Top|clk     DFFCE     D        lock_cnt_s[13]     3.363        -0.534
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[12]                                                   DDR3_Memory_Interface_Top|clk     DFFCE     D        lock_cnt_s[12]     3.363        -0.499
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[11]                                                   DDR3_Memory_Interface_Top|clk     DFFCE     D        lock_cnt_s[11]     3.363        -0.464
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[10]                                                   DDR3_Memory_Interface_Top|clk     DFFCE     D        lock_cnt_s[10]     3.363        -0.429
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[9]                                                    DDR3_Memory_Interface_Top|clk     DFFCE     D        lock_cnt_s[9]      3.363        -0.394
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[8]                                                    DDR3_Memory_Interface_Top|clk     DFFCE     D        lock_cnt_s[8]      3.363        -0.359
    ===================================================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      3.424
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         3.424

        - Propagation time:                      4.194
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.770

        Number of logic level(s):                3
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.cs_memsync[3] / Q
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs / HOLD
        The start point is clocked by            DDR3_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK
        The end   point is clocked by            System [rising]

    Instance / Net                                                                                                                    Pin      Pin               Arrival     No. of
    Name                                                                                                                    Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.cs_memsync[3]                                                  DFFCE     Q        Out     0.243     0.243 r     -
    cs_memsync[3]                                                                                                           Net       -        -       0.596     -           11
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_tz_0                                       LUT2      I1       In      -         0.839 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_tz_0                                       LUT2      F        Out     0.570     1.409 r     -
    ddr_rst_i_1                                                                                                             Net       -        -       0.596     -           15
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_mb_mb_mb                                   LUT4      I0       In      -         2.005 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_mb_mb_mb                                   LUT4      F        Out     0.549     2.554 r     -
    hold_reg_1_sqmuxa_0_a2_i_d_d_0_2                                                                                        Net       -        -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.pause_en        LUT4      I1       In      -         3.089 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.pause_en        LUT4      F        Out     0.570     3.659 r     -
    pause_en                                                                                                                Net       -        -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs     DQS       HOLD     In      -         4.194 r     -
    ===================================================================================================================================================================================
    Total path delay (propagation time + setup) of 4.194 is 1.932(46.1%) logic and 2.262(53.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      3.424
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         3.424

        - Propagation time:                      4.194
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.770

        Number of logic level(s):                3
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.cs_memsync[3] / Q
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs / HOLD
        The start point is clocked by            DDR3_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK
        The end   point is clocked by            System [rising]

    Instance / Net                                                                                                                    Pin      Pin               Arrival     No. of
    Name                                                                                                                    Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.cs_memsync[3]                                                  DFFCE     Q        Out     0.243     0.243 r     -
    cs_memsync[3]                                                                                                           Net       -        -       0.596     -           11
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_tz_0                                       LUT2      I1       In      -         0.839 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_tz_0                                       LUT2      F        Out     0.570     1.409 r     -
    ddr_rst_i_1                                                                                                             Net       -        -       0.596     -           15
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_mb_mb_mb                                   LUT4      I0       In      -         2.005 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_mb_mb_mb                                   LUT4      F        Out     0.549     2.554 r     -
    hold_reg_1_sqmuxa_0_a2_i_d_d_0_2                                                                                        Net       -        -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.pause_en        LUT4      I1       In      -         3.089 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.pause_en        LUT4      F        Out     0.570     3.659 r     -
    pause_en                                                                                                                Net       -        -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs     DQS       HOLD     In      -         4.194 r     -
    ===================================================================================================================================================================================
    Total path delay (propagation time + setup) of 4.194 is 1.932(46.1%) logic and 2.262(53.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      3.424
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         3.424

        - Propagation time:                      4.112
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.688

        Number of logic level(s):                3
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.dll_rst / Q
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs / HOLD
        The start point is clocked by            DDR3_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK
        The end   point is clocked by            System [rising]

    Instance / Net                                                                                                                   Pin      Pin               Arrival     No. of
    Name                                                                                                                    Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.dll_rst                                                        DFFP     Q        Out     0.243     0.243 r     -
    dll_rsti                                                                                                                Net      -        -       0.535     -           6
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_tz_0                                       LUT2     I0       In      -         0.778 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_tz_0                                       LUT2     F        Out     0.549     1.327 r     -
    ddr_rst_i_1                                                                                                             Net      -        -       0.596     -           15
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_mb_mb_mb                                   LUT4     I0       In      -         1.923 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_mb_mb_mb                                   LUT4     F        Out     0.549     2.472 r     -
    hold_reg_1_sqmuxa_0_a2_i_d_d_0_2                                                                                        Net      -        -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.pause_en        LUT4     I1       In      -         3.007 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.pause_en        LUT4     F        Out     0.570     3.577 r     -
    pause_en                                                                                                                Net      -        -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs     DQS      HOLD     In      -         4.112 r     -
    ==================================================================================================================================================================================
    Total path delay (propagation time + setup) of 4.112 is 1.911(46.5%) logic and 2.201(53.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      3.424
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         3.424

        - Propagation time:                      4.112
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.688

        Number of logic level(s):                3
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.dll_rst / Q
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs / HOLD
        The start point is clocked by            DDR3_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK
        The end   point is clocked by            System [rising]

    Instance / Net                                                                                                                   Pin      Pin               Arrival     No. of
    Name                                                                                                                    Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.dll_rst                                                        DFFP     Q        Out     0.243     0.243 r     -
    dll_rsti                                                                                                                Net      -        -       0.535     -           6
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_tz_0                                       LUT2     I0       In      -         0.778 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_tz_0                                       LUT2     F        Out     0.549     1.327 r     -
    ddr_rst_i_1                                                                                                             Net      -        -       0.596     -           15
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_mb_mb_mb                                   LUT4     I0       In      -         1.923 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.hold_reg_1_sqmuxa_0_a2_i_d_d_0_2_mb_mb_mb                                   LUT4     F        Out     0.549     2.472 r     -
    hold_reg_1_sqmuxa_0_a2_i_d_d_0_2                                                                                        Net      -        -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.pause_en        LUT4     I1       In      -         3.007 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.pause_en        LUT4     F        Out     0.570     3.577 r     -
    pause_en                                                                                                                Net      -        -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs     DQS      HOLD     In      -         4.112 r     -
    ==================================================================================================================================================================================
    Total path delay (propagation time + setup) of 4.112 is 1.911(46.5%) logic and 2.201(53.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      3.424
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         3.363

        - Propagation time:                      3.967
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.604

        Number of logic level(s):                17
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_syn[1] / Q
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[15] / D
        The start point is clocked by            DDR3_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK
        The end   point is clocked by            DDR3_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK

    Instance / Net                                                                               Pin      Pin               Arrival     No. of
    Name                                                                               Type      Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_syn[1]               DFFC      Q        Out     0.243     0.243 r     -
    lock_cnt                                                                           Net       -        -       0.596     -           18
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0_RNO[0]     LUT2      I0       In      -         0.839 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0_RNO[0]     LUT2      F        Out     0.549     1.388 r     -
    lock_cnt_cry_0_RNO[0]                                                              Net       -        -       0.535     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[0]         ALU       I0       In      -         1.923 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[0]         ALU       COUT     Out     0.549     2.472 r     -
    lock_cnt_cry[0]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[1]         ALU       CIN      In      -         2.472 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[1]         ALU       COUT     Out     0.035     2.507 r     -
    lock_cnt_cry[1]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[2]         ALU       CIN      In      -         2.507 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[2]         ALU       COUT     Out     0.035     2.542 r     -
    lock_cnt_cry[2]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[3]         ALU       CIN      In      -         2.542 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[3]         ALU       COUT     Out     0.035     2.577 r     -
    lock_cnt_cry[3]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[4]         ALU       CIN      In      -         2.577 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[4]         ALU       COUT     Out     0.035     2.612 r     -
    lock_cnt_cry[4]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[5]         ALU       CIN      In      -         2.612 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[5]         ALU       COUT     Out     0.035     2.647 r     -
    lock_cnt_cry[5]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[6]         ALU       CIN      In      -         2.647 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[6]         ALU       COUT     Out     0.035     2.682 r     -
    lock_cnt_cry[6]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[7]         ALU       CIN      In      -         2.682 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[7]         ALU       COUT     Out     0.035     2.717 r     -
    lock_cnt_cry[7]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[8]         ALU       CIN      In      -         2.717 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[8]         ALU       COUT     Out     0.035     2.752 r     -
    lock_cnt_cry[8]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[9]         ALU       CIN      In      -         2.752 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[9]         ALU       COUT     Out     0.035     2.787 r     -
    lock_cnt_cry[9]                                                                    Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[10]        ALU       CIN      In      -         2.787 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[10]        ALU       COUT     Out     0.035     2.822 r     -
    lock_cnt_cry[10]                                                                   Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[11]        ALU       CIN      In      -         2.822 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[11]        ALU       COUT     Out     0.035     2.857 r     -
    lock_cnt_cry[11]                                                                   Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[12]        ALU       CIN      In      -         2.857 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[12]        ALU       COUT     Out     0.035     2.892 r     -
    lock_cnt_cry[12]                                                                   Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[13]        ALU       CIN      In      -         2.892 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[13]        ALU       COUT     Out     0.035     2.927 r     -
    lock_cnt_cry[13]                                                                   Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[14]        ALU       CIN      In      -         2.927 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_cry_0[14]        ALU       COUT     Out     0.035     2.962 r     -
    lock_cnt_cry[14]                                                                   Net       -        -       0.000     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_s_0[15]          ALU       CIN      In      -         2.962 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt_s_0[15]          ALU       SUM      Out     0.470     3.432 f     -
    lock_cnt_s[15]                                                                     Net       -        -       0.535     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.lock_cnt[15]              DFFCE     D        In      -         3.967 f     -
    ==============================================================================================================================================
    Total path delay (propagation time + setup) of 4.028 is 2.362(58.6%) logic and 1.666(41.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                     Starting                                                                                                     Arrival
    Instance                                                         Reference                                                             Type      Pin     Net                  Time        Slack
                                                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[30]           _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFCE     Q       cmd_buf_dout[30]     0.243       -1.113
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_pstate[26]     _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC      Q       gwmc_pstate[26]      0.243       -1.101
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.accept                     _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC      Q       accept               0.243       -1.092
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_timing_ctrl.refresh_req       _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFCE     Q       refresh_req          0.243       -1.063
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_timing_ctrl.ref_accepted      _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC      Q       ref_ack              0.243       -1.042
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRAS_cnt[1]         _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC      Q       tRAS_cnt[1]          0.243       -1.038
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_timing_ctrl.sre_accepted      _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFCE     Q       sr_act               0.243       -1.019
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRAS_cnt[0]         _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC      Q       tRAS_cnt[0]          0.243       -1.018
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[31]           _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFCE     Q       cmd_buf_dout[31]     0.243       -1.005
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_pstate[8]      _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC      Q       gwmc_pstate[8]       0.243       -0.971
    ================================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                              Starting                                                                                                      Required
    Instance                                                                  Reference                                                             Type     Pin     Net                    Time         Slack
                                                                              Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2]                  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       tRFC_cnt_3[2]          6.245        -1.113
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.idle                         _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       idle_2                 6.245        -1.038
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[3]                  _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       tRFC_cnt_3[3]          6.245        -0.846
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_fifo_ctrl.of_Full_reg     _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       of_wfull_val_NE_i      6.245        -0.655
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.loop_en                      _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       loop_en5               6.245        -0.610
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_pstate[2]               _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       gwmc_nstate_27[2]      6.245        -0.567
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_pstate[12]              _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       gwmc_nstate_27[12]     6.245        -0.567
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_pstate[23]              _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       gwmc_nstate_27[23]     6.245        -0.297
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_pstate[18]              _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       gwmc_nstate_27[18]     6.245        -0.280
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_pstate[19]              _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DFFC     D       gwmc_nstate_27[19]     6.245        -0.280
    ===========================================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      6.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.245

        - Propagation time:                      7.358
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.113

        Number of logic level(s):                8
        Starting point:                          genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[30] / Q
        Ending point:                            genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2] / D
        The start point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK

    Instance / Net                                                                                  Pin      Pin               Arrival     No. of
    Name                                                                              Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[30]                            DFFCE         Q        Out     0.243     0.243 r     -
    cmd_buf_dout[30]                                                                  Net           -        -       0.535     -           2
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.un1_cmd_read_0_a2                           LUT4          I1       In      -         0.778 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.un1_cmd_read_0_a2                           LUT4          F        Out     0.570     1.348 r     -
    BL_CNT8                                                                           Net           -        -       0.657     -           22
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m3_e                             LUT3          I0       In      -         2.005 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m3_e                             LUT3          F        Out     0.549     2.554 r     -
    un1_m3_e                                                                          Net           -        -       0.535     -           7
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m4                               LUT4          I0       In      -         3.089 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m4                               LUT4          F        Out     0.549     3.638 r     -
    un1_N_8_mux                                                                       Net           -        -       0.657     -           26
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0_1[24]     LUT4          I3       In      -         4.295 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0_1[24]     LUT4          F        Out     0.371     4.666 f     -
    gwmc_nstate_27_1_iv_5_0_a0_1[24]                                                  Net           -        -       0.401     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0[24]       LUT4          I0       In      -         5.067 f     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0[24]       LUT4          F        Out     0.549     5.616 r     -
    tRFC_cnt_3_1_0[2]                                                                 Net           -        -       0.535     -           5
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_0_0[2]                    LUT4          I2       In      -         6.151 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_0_0[2]                    LUT4          F        Out     0.462     6.613 r     -
    tRFC_cnt_3_0_0[2]                                                                 Net           -        -       0.000     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_0[2]                      MUX2_LUT5     I0       In      -         6.613 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_0[2]                      MUX2_LUT5     O        Out     0.105     6.718 r     -
    tRFC_cnt_3_0[2]                                                                   Net           -        -       0.000     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                        MUX2_LUT6     I0       In      -         6.718 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                        MUX2_LUT6     O        Out     0.105     6.823 r     -
    tRFC_cnt_3[2]                                                                     Net           -        -       0.535     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2]                          DFFC          D        In      -         7.358 r     -
    =================================================================================================================================================
    Total path delay (propagation time + setup) of 7.419 is 3.564(48.0%) logic and 3.855(52.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      6.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.245

        - Propagation time:                      7.358
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.113

        Number of logic level(s):                8
        Starting point:                          genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[30] / Q
        Ending point:                            genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2] / D
        The start point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK

    Instance / Net                                                                                  Pin      Pin               Arrival     No. of
    Name                                                                              Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[30]                            DFFCE         Q        Out     0.243     0.243 r     -
    cmd_buf_dout[30]                                                                  Net           -        -       0.535     -           2
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.un1_cmd_read_0_a2                           LUT4          I1       In      -         0.778 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.un1_cmd_read_0_a2                           LUT4          F        Out     0.570     1.348 r     -
    BL_CNT8                                                                           Net           -        -       0.657     -           22
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m3_e                             LUT3          I0       In      -         2.005 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m3_e                             LUT3          F        Out     0.549     2.554 r     -
    un1_m3_e                                                                          Net           -        -       0.535     -           7
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m4                               LUT4          I0       In      -         3.089 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m4                               LUT4          F        Out     0.549     3.638 r     -
    un1_N_8_mux                                                                       Net           -        -       0.657     -           26
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0_1[24]     LUT4          I3       In      -         4.295 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0_1[24]     LUT4          F        Out     0.371     4.666 f     -
    gwmc_nstate_27_1_iv_5_0_a0_1[24]                                                  Net           -        -       0.401     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0[24]       LUT4          I0       In      -         5.067 f     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0[24]       LUT4          F        Out     0.549     5.616 r     -
    tRFC_cnt_3_1_0[2]                                                                 Net           -        -       0.535     -           5
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_0_1[2]                    LUT4          I2       In      -         6.151 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_0_1[2]                    LUT4          F        Out     0.462     6.613 r     -
    tRFC_cnt_3_0_1[2]                                                                 Net           -        -       0.000     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_0[2]                      MUX2_LUT5     I1       In      -         6.613 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_0[2]                      MUX2_LUT5     O        Out     0.105     6.718 r     -
    tRFC_cnt_3_0[2]                                                                   Net           -        -       0.000     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                        MUX2_LUT6     I0       In      -         6.718 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                        MUX2_LUT6     O        Out     0.105     6.823 r     -
    tRFC_cnt_3[2]                                                                     Net           -        -       0.535     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2]                          DFFC          D        In      -         7.358 r     -
    =================================================================================================================================================
    Total path delay (propagation time + setup) of 7.419 is 3.564(48.0%) logic and 3.855(52.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      6.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.245

        - Propagation time:                      7.358
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.113

        Number of logic level(s):                8
        Starting point:                          genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[30] / Q
        Ending point:                            genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2] / D
        The start point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK

    Instance / Net                                                                                  Pin      Pin               Arrival     No. of
    Name                                                                              Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[30]                            DFFCE         Q        Out     0.243     0.243 r     -
    cmd_buf_dout[30]                                                                  Net           -        -       0.535     -           2
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.un1_cmd_read_0_a2                           LUT4          I1       In      -         0.778 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.un1_cmd_read_0_a2                           LUT4          F        Out     0.570     1.348 r     -
    BL_CNT8                                                                           Net           -        -       0.657     -           22
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m3_e                             LUT3          I0       In      -         2.005 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m3_e                             LUT3          F        Out     0.549     2.554 r     -
    un1_m3_e                                                                          Net           -        -       0.535     -           7
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m4                               LUT4          I0       In      -         3.089 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m4                               LUT4          F        Out     0.549     3.638 r     -
    un1_N_8_mux                                                                       Net           -        -       0.657     -           26
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0_1[24]     LUT4          I3       In      -         4.295 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0_1[24]     LUT4          F        Out     0.371     4.666 f     -
    gwmc_nstate_27_1_iv_5_0_a0_1[24]                                                  Net           -        -       0.401     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0[24]       LUT4          I0       In      -         5.067 f     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0[24]       LUT4          F        Out     0.549     5.616 r     -
    tRFC_cnt_3_1_0[2]                                                                 Net           -        -       0.535     -           5
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_1_1[2]                    LUT4          I2       In      -         6.151 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_1_1[2]                    LUT4          F        Out     0.462     6.613 r     -
    tRFC_cnt_3_1_1[2]                                                                 Net           -        -       0.000     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_1[2]                      MUX2_LUT5     I1       In      -         6.613 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_1[2]                      MUX2_LUT5     O        Out     0.105     6.718 r     -
    tRFC_cnt_3_1[2]                                                                   Net           -        -       0.000     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                        MUX2_LUT6     I1       In      -         6.718 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                        MUX2_LUT6     O        Out     0.105     6.823 r     -
    tRFC_cnt_3[2]                                                                     Net           -        -       0.535     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2]                          DFFC          D        In      -         7.358 r     -
    =================================================================================================================================================
    Total path delay (propagation time + setup) of 7.419 is 3.564(48.0%) logic and 3.855(52.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      6.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.245

        - Propagation time:                      7.358
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.113

        Number of logic level(s):                8
        Starting point:                          genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[30] / Q
        Ending point:                            genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2] / D
        The start point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK

    Instance / Net                                                                                  Pin      Pin               Arrival     No. of
    Name                                                                              Type          Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.cmd_buf_dout[30]                            DFFCE         Q        Out     0.243     0.243 r     -
    cmd_buf_dout[30]                                                                  Net           -        -       0.535     -           2
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.un1_cmd_read_0_a2                           LUT4          I1       In      -         0.778 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gw_cmd0.un1_cmd_read_0_a2                           LUT4          F        Out     0.570     1.348 r     -
    BL_CNT8                                                                           Net           -        -       0.657     -           22
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m3_e                             LUT3          I0       In      -         2.005 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m3_e                             LUT3          F        Out     0.549     2.554 r     -
    un1_m3_e                                                                          Net           -        -       0.535     -           7
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m4                               LUT4          I0       In      -         3.089 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.un1_m4                               LUT4          F        Out     0.549     3.638 r     -
    un1_N_8_mux                                                                       Net           -        -       0.657     -           26
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0_1[24]     LUT4          I3       In      -         4.295 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0_1[24]     LUT4          F        Out     0.371     4.666 f     -
    gwmc_nstate_27_1_iv_5_0_a0_1[24]                                                  Net           -        -       0.401     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0[24]       LUT4          I0       In      -         5.067 f     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_5_0_a0[24]       LUT4          F        Out     0.549     5.616 r     -
    tRFC_cnt_3_1_0[2]                                                                 Net           -        -       0.535     -           5
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_1_0[2]                    LUT4          I2       In      -         6.151 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_1_0[2]                    LUT4          F        Out     0.462     6.613 r     -
    tRFC_cnt_3_1_0_0[2]                                                               Net           -        -       0.000     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_1[2]                      MUX2_LUT5     I0       In      -         6.613 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3_1[2]                      MUX2_LUT5     O        Out     0.105     6.718 r     -
    tRFC_cnt_3_1[2]                                                                   Net           -        -       0.000     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                        MUX2_LUT6     I1       In      -         6.718 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                        MUX2_LUT6     O        Out     0.105     6.823 r     -
    tRFC_cnt_3[2]                                                                     Net           -        -       0.535     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2]                          DFFC          D        In      -         7.358 r     -
    =================================================================================================================================================
    Total path delay (propagation time + setup) of 7.419 is 3.564(48.0%) logic and 3.855(52.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      6.306
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.245

        - Propagation time:                      7.346
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.101

        Number of logic level(s):                7
        Starting point:                          genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_pstate[26] / Q
        Ending point:                            genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2] / D
        The start point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLK

    Instance / Net                                                                               Pin      Pin               Arrival     No. of
    Name                                                                           Type          Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_pstate[26]                   DFFC          Q        Out     0.243     0.243 r     -
    gwmc_pstate[26]                                                                Net           -        -       0.596     -           11
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_1_sqmuxa_6_c          LUT2          I1       In      -         0.839 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_1_sqmuxa_6_c          LUT2          F        Out     0.570     1.409 r     -
    gwmc_nstate_1_sqmuxa_6_c                                                       Net           -        -       0.401     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_cnst_m_a0_1[23]       LUT4          I1       In      -         1.810 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_cnst_m_a0_1[23]       LUT4          F        Out     0.570     2.380 r     -
    gwmc_nstate_cnst_m_a0_1[23]                                                    Net           -        -       0.401     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_cnst_m_a0_5_1[23]     LUT4          I2       In      -         2.781 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_cnst_m_a0_5_1[23]     LUT4          F        Out     0.462     3.243 r     -
    gwmc_nstate_cnst_m_a0_5_1[23]                                                  Net           -        -       0.401     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_cnst_m_a0_5[23]       LUT4          I0       In      -         3.645 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_cnst_m_a0_5[23]       LUT4          F        Out     0.549     4.194 r     -
    gwmc_nstate_cnst_m_a0_5[23]                                                    Net           -        -       0.401     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_N_4L5         LUT3          I0       In      -         4.595 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv_N_4L5         LUT3          F        Out     0.549     5.144 r     -
    gwmc_nstate_27_1_iv_N_4L5                                                      Net           -        -       0.401     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv[23]           LUT4          I2       In      -         5.545 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.gwmc_nstate_27_1_iv[23]           LUT4          F        Out     0.462     6.007 r     -
    gwmc_nstate_27[23]                                                             Net           -        -       0.535     -           3
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                     MUX2_LUT6     S0       In      -         6.542 r     -
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt_3[2]                     MUX2_LUT6     O        Out     0.269     6.811 r     -
    tRFC_cnt_3[2]                                                                  Net           -        -       0.535     -           1
    genblk1\.gw3mc_top.u_gwmc_top.gwmc_bank_ctrl.tRFC_cnt[2]                       DFFC          D        In      -         7.346 r     -
    ==============================================================================================================================================
    Total path delay (propagation time + setup) of 7.407 is 3.735(50.4%) logic and 3.672(49.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                            Starting                                             Arrival
    Instance                                                Reference     Type       Pin         Net             Time        Slack
                                                            Clock
    -------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv                 System        CLKDIV     CLKOUT      clk_x1_i        0.000       -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_PLL                  System        PLL        LOCK        pll_lock        0.000       -0.243
    genblk1\.gw3mc_top.u_ddr_phy_top.u_dqcen                System        DHCEN      CLKOUT      clk_x4i_i       0.000       0.475
    genblk1\.gw3mc_top.u_ddr_phy_top.u_PLL                  System        PLL        CLKOUT      clk_x4          0.000       0.841
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_dll     System        DLL        STEP[0]     dll_step[0]     0.000       0.841
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_dll     System        DLL        STEP[1]     dll_step[1]     0.000       0.841
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_dll     System        DLL        STEP[2]     dll_step[2]     0.000       0.841
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_dll     System        DLL        STEP[3]     dll_step[3]     0.000       0.841
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_dll     System        DLL        STEP[4]     dll_step[4]     0.000       0.841
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_dll     System        DLL        STEP[5]     dll_step[5]     0.000       0.841
    ===============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                                                                      Starting                                       Required
    Instance                                                                                                          Reference     Type     Pin       Net           Time         Slack
                                                                                                                      Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[0]     D3_L_3[0]     6.268        -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[1]     D3_L_3[1]     6.268        -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[2]     D3_L_3[2]     6.268        -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[3]     D3_L_3[3]     6.268        -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[4]     D3_L_3[4]     6.268        -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[5]     D3_L_3[5]     6.268        -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[6]     D3_L_3[6]     6.268        -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[7]     D3_L_3[7]     6.268        -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[8]     D2_L_3[0]     6.268        -1.996
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0     System        SDP      DI[9]     D2_L_3[1]     6.268        -1.996
    ====================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      6.306
        - Setup time:                            0.038
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.268

        - Propagation time:                      8.264
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -1.996

        Number of logic level(s):                2
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv / CLKOUT
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0 / DI[31]
        The start point is clocked by            System [rising]
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLKA

    Instance / Net                                                                                                                                          Pin        Pin               Arrival     No. of
    Name                                                                                                                                      Type          Name       Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv                                                                                                   CLKDIV        CLKOUT     Out     0.000     0.000 r     -
    clk_x1_i                                                                                                                                  Net           -          -       6.459     -           1913
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[0\]\.u_ides8_mem     IDES8_MEM     PCLK       In      -         6.459 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[0\]\.u_ides8_mem     IDES8_MEM     Q7         Out     0.165     6.624 r     -
    iserdes_dq[7]                                                                                                                             Net           -          -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D0_L_3[7]                                 LUT3          I1         In      -         7.159 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D0_L_3[7]                                 LUT3          F          Out     0.570     7.729 r     -
    D0_L_3[7]                                                                                                                                 Net           -          -       0.535     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem3_mem3_0_0                             SDP           DI[31]     In      -         8.264 r     -
    ===========================================================================================================================================================================================================
    Total path delay (propagation time + setup) of 8.302 is 0.773(9.3%) logic and 7.529(90.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      6.306
        - Setup time:                            0.038
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.268

        - Propagation time:                      8.264
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -1.996

        Number of logic level(s):                2
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv / CLKOUT
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem7_mem7_0_0 / DI[15]
        The start point is clocked by            System [rising]
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLKA

    Instance / Net                                                                                                                                          Pin        Pin               Arrival     No. of
    Name                                                                                                                                      Type          Name       Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv                                                                                                   CLKDIV        CLKOUT     Out     0.000     0.000 r     -
    clk_x1_i                                                                                                                                  Net           -          -       6.459     -           1913
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem     IDES8_MEM     PCLK       In      -         6.459 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem     IDES8_MEM     Q7         Out     0.165     6.624 r     -
    iserdes_dq[55]                                                                                                                            Net           -          -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D6_L_3[7]                                 LUT3          I1         In      -         7.159 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D6_L_3[7]                                 LUT3          F          Out     0.570     7.729 r     -
    D6_L_3[7]                                                                                                                                 Net           -          -       0.535     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem7_mem7_0_0                             SDP           DI[15]     In      -         8.264 r     -
    ===========================================================================================================================================================================================================
    Total path delay (propagation time + setup) of 8.302 is 0.773(9.3%) logic and 7.529(90.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      6.306
        - Setup time:                            0.038
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.268

        - Propagation time:                      8.264
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -1.996

        Number of logic level(s):                2
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv / CLKOUT
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem7_mem7_0_0 / DI[23]
        The start point is clocked by            System [rising]
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLKA

    Instance / Net                                                                                                                                          Pin        Pin               Arrival     No. of
    Name                                                                                                                                      Type          Name       Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv                                                                                                   CLKDIV        CLKOUT     Out     0.000     0.000 r     -
    clk_x1_i                                                                                                                                  Net           -          -       6.459     -           1913
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[5\]\.u_ides8_mem     IDES8_MEM     PCLK       In      -         6.459 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[5\]\.u_ides8_mem     IDES8_MEM     Q7         Out     0.165     6.624 r     -
    iserdes_dq[47]                                                                                                                            Net           -          -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D5_L_3[7]                                 LUT3          I1         In      -         7.159 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D5_L_3[7]                                 LUT3          F          Out     0.570     7.729 r     -
    D5_L_3[7]                                                                                                                                 Net           -          -       0.535     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem7_mem7_0_0                             SDP           DI[23]     In      -         8.264 r     -
    ===========================================================================================================================================================================================================
    Total path delay (propagation time + setup) of 8.302 is 0.773(9.3%) logic and 7.529(90.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      6.306
        - Setup time:                            0.038
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.268

        - Propagation time:                      8.264
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -1.996

        Number of logic level(s):                2
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv / CLKOUT
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem7_mem7_0_0 / DI[7]
        The start point is clocked by            System [rising]
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLKA

    Instance / Net                                                                                                                                          Pin        Pin               Arrival     No. of
    Name                                                                                                                                      Type          Name       Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv                                                                                                   CLKDIV        CLKOUT     Out     0.000     0.000 r     -
    clk_x1_i                                                                                                                                  Net           -          -       6.459     -           1913
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[7\]\.u_ides8_mem     IDES8_MEM     PCLK       In      -         6.459 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[7\]\.u_ides8_mem     IDES8_MEM     Q7         Out     0.165     6.624 r     -
    iserdes_dq[63]                                                                                                                            Net           -          -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D7_L_3[7]                                 LUT3          I1         In      -         7.159 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D7_L_3[7]                                 LUT3          F          Out     0.570     7.729 r     -
    D7_L_3[7]                                                                                                                                 Net           -          -       0.535     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem7_mem7_0_0                             SDP           DI[7]      In      -         8.264 r     -
    ===========================================================================================================================================================================================================
    Total path delay (propagation time + setup) of 8.302 is 0.773(9.3%) logic and 7.529(90.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      6.306
        - Setup time:                            0.038
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.268

        - Propagation time:                      8.264
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     -1.996

        Number of logic level(s):                2
        Starting point:                          genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv / CLKOUT
        Ending point:                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem7_mem7_0_0 / DI[31]
        The start point is clocked by            System [rising]
        The end   point is clocked by            _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock [rising] (rise=0.000 fall=3.153 period=6.306) on pin CLKA

    Instance / Net                                                                                                                                          Pin        Pin               Arrival     No. of
    Name                                                                                                                                      Type          Name       Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv                                                                                                   CLKDIV        CLKOUT     Out     0.000     0.000 r     -
    clk_x1_i                                                                                                                                  Net           -          -       6.459     -           1913
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[4\]\.u_ides8_mem     IDES8_MEM     PCLK       In      -         6.459 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[4\]\.u_ides8_mem     IDES8_MEM     Q7         Out     0.165     6.624 r     -
    iserdes_dq[39]                                                                                                                            Net           -          -       0.535     -           2
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D4_L_3[7]                                 LUT3          I1         In      -         7.159 r     -
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.D4_L_3[7]                                 LUT3          F          Out     0.570     7.729 r     -
    D4_L_3[7]                                                                                                                                 Net           -          -       0.535     -           1
    genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_in_fifo.mem7_mem7_0_0                             SDP           DI[31]     In      -         8.264 r     -
    ===========================================================================================================================================================================================================
    Total path delay (propagation time + setup) of 8.302 is 0.773(9.3%) logic and 7.529(90.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 283MB peak: 293MB)

    Finished timing report (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 283MB peak: 293MB)

    ---------------------------------------
    Resource Usage Report for DDR3_Memory_Interface_Top

    Mapping to part: gw2a_18pbga484-8
    Cell usage:
    ALU             137 uses
    CLKDIV          1 use
    DFF             207 uses
    DFFC            875 uses
    DFFCE           173 uses
    DFFE            454 uses
    DFFP            40 uses
    DFFPE           7 uses
    DFFR            25 uses
    DFFS            7 uses
    DHCEN           1 use
    DLL             1 use
    DQS             2 uses
    GSR             1 use
    IDES8_MEM       16 uses
    INV             19 uses
    IODELAY         16 uses
    MUX2_LUT5       9 uses
    MUX2_LUT6       2 uses
    OSER8           24 uses
    OSER8_MEM       20 uses
    PLL             1 use
    RAM16SDP4       79 uses
    SDP             8 uses
    LUT2            737 uses
    LUT3            486 uses
    LUT4            544 uses

    I/O ports: 374
    I/O primitives: 45
    ELVDS_IOBUF    2 uses
    ELVDS_OBUF     1 use
    IOBUF          16 uses
    OBUF           24 uses
    TBUF           2 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   1788 of 15552 (11%)

    RAM/ROM usage summary
    Block Rams : 8 of 46 (17%)

    Total load per clock:
       _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock: 1913
       DDR3_Memory_Interface_Top|clk: 34
       _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock: 63
       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock: 1
       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock: 9
       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock: 8
       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock: 1
       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock: 9
       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock: 8

    @S |Mapping Summary:
    Total  LUTs: 1767

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 92MB peak: 293MB)

    Process took 0h:00m:18s realtime, 0h:00m:18s cputime
    # Wed Jun 17 17:50:40 2020

    ###########################################################]

`