`

    #Build: Synplify Pro (R) P-2019.03G-1-Beta1, Build 387R, Dec  3 2019
    #install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: GZAE-AE-CAOJIE

    # Fri Dec 20 16:21:55 2019

    #Implementation: rev_1

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\generic\gw2a.v" (library work)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"D:\proj\scaler_example_design_live\project\temp\gao\ao_0\gw_ao_parameter.v" (library work)
    @I::"D:\proj\scaler_example_design_live\project\temp\gao\ao_0\gw_ao_top_define.v" (library work)
    @I::"D:\proj\scaler_example_design_live\project\temp\gao\ao_0\gw_ao_expression.v" (library work)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
    @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
    @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
    @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
    @I::"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
    @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
    @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
    @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
    @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
    @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
    @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
    @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
    @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
    @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
    @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
    @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
    @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
    @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
    @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
    @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
    @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
    @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
    @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
    @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
    @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
    @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
    Verilog syntax check successful!
    @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_D:\proj\scaler_example_design_live\project\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
    Selecting top level module ao_top_0
    Running optimization stage 1 on ao_mem_ctrl_0_2048s_19s_11s .......
    Running optimization stage 1 on ao_crc32_0 .......
    Running optimization stage 1 on ao_match_0_0s_1s_19s_1_1_0_1_2_3_4 .......
    Running optimization stage 1 on ao_top_0 .......
    Running optimization stage 2 on ao_match_0_0s_1s_19s_1_1_0_1_2_3_4 .......
    Running optimization stage 2 on ao_top_0 .......
    Extracted state machine for register module_state
    State machine has 11 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
       0110
       0111
       1001
       1010
       1011
    Running optimization stage 2 on ao_crc32_0 .......
    Running optimization stage 2 on ao_mem_ctrl_0_2048s_19s_11s .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 107MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Dec 20 16:21:57 2019

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 88MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Dec 20 16:21:57 2019

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  ao_0_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 18MB peak: 19MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Dec 20 16:21:57 2019

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 391R, Built Dec  3 2019 09:16:34

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 89MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Dec 20 16:21:58 2019

    ###########################################################]

`
`

    Premap Report

`
`

    # Fri Dec 20 16:21:59 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  ao_0_scck.rpt
    Printing clock  summary report in "D:\proj\scaler_example_design_live\project\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    @N:BN133 :  | Ignoring syn_hier=hard property on top-level design.

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

    Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
    original code -> new code
       0000 -> 00000000001
       0001 -> 00000000010
       0010 -> 00000000100
       0011 -> 00000001000
       0100 -> 00000010000
       0101 -> 00000100000
       0110 -> 00001000000
       0111 -> 00010000000
       1001 -> 00100000000
       1010 -> 01000000000
       1011 -> 10000000000

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

    Clock Summary
    ******************

              Start                   Requested     Requested     Clock        Clock                     Clock
    Level     Clock                   Frequency     Period        Type         Group                     Load
    ----------------------------------------------------------------------------------------------------------
    0 -       ao_top_0|control[0]     186.5 MHz     5.362         inferred     Autoconstr_clkgroup_1     263

    0 -       ao_top_0|clk_i          237.7 MHz     4.207         inferred     Autoconstr_clkgroup_0     82
    ==========================================================================================================

    Clock Load Summary
    ***********************

                            Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin
    Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example
    --------------------------------------------------------------------------------------------------------------------------------------
    ao_top_0|control[0]     263       control[0](port)     data_register[39:0].C                    -                 -

    ao_top_0|clk_i          82        clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
    ======================================================================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    2 non-gated/non-generated clock tree(s) driving 327 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       ENCRYPTED           IO_port                263        ENCRYPTED
    ClockId_0_1       ENCRYPTED           port                   64         ENCRYPTED
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file D:\proj\scaler_example_design_live\project\temp\gao\ao_0\rev_1\ao_0.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 224MB)

    Process took 0h:00m:02s realtime, 0h:00m:01s cputime
    # Fri Dec 20 16:22:01 2019

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Fri Dec 20 16:22:01 2019

    Copyright (C) 1994-2019 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: P-2019.03G-1-Beta1
    Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
    OS: Windows 6.1

    Hostname: GZAE-AE-CAOJIE

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw2019q1p1, Build 007R, Built Dec  5 2019 10:27:23

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 121MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 217MB peak: 217MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 221MB peak: 221MB)

    Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 225MB peak: 225MB)

    Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 228MB peak: 228MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 229MB peak: 229MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 229MB peak: 229MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 230MB peak: 230MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 230MB peak: 230MB)

    Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 230MB peak: 230MB)

    Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 251MB peak: 251MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:02s		    -2.47ns		 439 /       302
       2		0h:00m:02s		    -2.47ns		 442 /       302
       3		0h:00m:02s		    -2.58ns		 442 /       302
    Timing driven replication report
    Added 2 Registers via timing driven replication
    Added 2 LUTs via timing driven replication

       4		0h:00m:02s		    -2.45ns		 448 /       304
       5		0h:00m:02s		    -2.58ns		 448 /       304

       6		0h:00m:02s		    -2.45ns		 447 /       304

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 251MB peak: 251MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 251MB peak: 251MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 252MB)

    Writing Analyst data base D:\proj\scaler_example_design_live\project\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 253MB peak: 253MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 254MB peak: 254MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 254MB peak: 254MB)

    Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 250MB peak: 254MB)

    @W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 4.62ns. Please declare a user-defined clock on port clk_i.
    @W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 5.74ns. Please declare a user-defined clock on port control[0].

    ##### START OF TIMING REPORT #####[
    # Timing report written on Fri Dec 20 16:22:07 2019
    #

    Top view:               ao_top_0
    Requested Frequency:    174.1 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.014

                            Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group
    -----------------------------------------------------------------------------------------------------------------------------
    ao_top_0|clk_i          216.4 MHz     183.9 MHz     4.622         5.437         -0.816     inferred     Autoconstr_clkgroup_0
    ao_top_0|control[0]     174.1 MHz     148.0 MHz     5.744         6.758         -1.014     inferred     Autoconstr_clkgroup_1
    System                  150.0 MHz     238.8 MHz     6.667         4.187         2.480      system       system_clkgroup
    =============================================================================================================================

    Clock Relationships
    *******************

    Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ---------------------------------------------------------------------------------------------------------------------------------
    Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ---------------------------------------------------------------------------------------------------------------------------------
    System               ao_top_0|clk_i       |  4.622       2.480   |  No paths    -      |  No paths    -      |  No paths    -
    System               ao_top_0|control[0]  |  5.744       3.793   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|clk_i       System               |  4.622       3.844   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|clk_i       ao_top_0|clk_i       |  4.622       -0.816  |  4.622       3.783  |  No paths    -      |  2.311       1.472
    ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  System               |  5.744       4.966   |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    ao_top_0|control[0]  ao_top_0|control[0]  |  5.744       -1.014  |  No paths    -      |  No paths    -      |  No paths    -
    =================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: ao_top_0|clk_i
    ====================================

    Starting Points with Worst Slack
    ********************************

                                         Starting                                                                 Arrival
    Instance                             Reference          Type     Pin     Net                                  Time        Slack
                                         Clock
    --------------------------------------------------------------------------------------------------------------------------------
    genblk1\.u_ao_match_0.match_sep      ao_top_0|clk_i     DFFC     Q       match                                0.243       -0.816
    internal_reg_force_triger_syn[1]     ao_top_0|clk_i     DFFC     Q       internal_reg_force_triger_syn[1]     0.243       -0.795
    triger_level_cnt[0]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[0]                  0.243       -0.708
    triger_level_cnt[3]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[3]                  0.243       -0.617
    capture_window_sel[1]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[1]                0.243       -0.616
    capture_window_sel[0]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[0]                0.243       -0.595
    u_ao_mem_ctrl.capture_length[0]      ao_top_0|clk_i     DFFC     Q       capture_length[0]                    0.243       -0.131
    u_ao_mem_ctrl.capture_length[1]      ao_top_0|clk_i     DFFC     Q       capture_length[1]                    0.243       -0.096
    u_ao_mem_ctrl.capture_length[2]      ao_top_0|clk_i     DFFC     Q       capture_length[2]                    0.243       -0.061
    u_ao_mem_ctrl.capture_length[3]      ao_top_0|clk_i     DFFP     Q       capture_length[3]                    0.243       -0.026
    ================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                        Starting                                                         Required
    Instance                            Reference          Type      Pin     Net                         Time         Slack
                                        Clock
    ------------------------------------------------------------------------------------------------------------------------
    triger_level_cnt[3]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]       4.561        -0.816
    triger_level_cnt[1]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]       4.561        -0.725
    triger_level_cnt[2]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]       4.561        -0.725
    u_ao_mem_ctrl.capture_mem_wr        ao_top_0|clk_i     DFFCE     CE      g0                          4.561        -0.673
    u_ao_mem_ctrl.mem_addr_inc_en       ao_top_0|clk_i     DFFCE     CE      un1_capture_length_zero     4.561        -0.673
    u_ao_mem_ctrl.mem_addr_inc_en       ao_top_0|clk_i     DFFCE     D       mem_addr_inc_en7            4.561        0.099
    triger_level_cnt[0]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[0]       4.561        0.160
    trigger_seq_start                   ao_top_0|clk_i     DFFCE     CE      un2_start_reg_0             4.561        0.181
    u_ao_mem_ctrl.capture_length[0]     ao_top_0|clk_i     DFFC      D       capture_length_5[0]         4.561        0.207
    u_ao_mem_ctrl.capture_length[1]     ao_top_0|clk_i     DFFC      D       capture_length_5[1]         4.561        0.207
    ========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.622
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.561

        - Propagation time:                      5.376
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.816

        Number of logic level(s):                5
        Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
        Ending point:                            triger_level_cnt[3] / D
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    genblk1\.u_ao_match_0.match_sep     DFFC     Q        Out     0.243     0.243       -
    match                               Net      -        -       0.535     -           1
    un1_triger_level_cnt12_0_o2_3       LUT4     I1       In      -         0.778       -
    un1_triger_level_cnt12_0_o2_3       LUT4     F        Out     0.570     1.348       -
    un1_triger_level_cnt12_0_o2_3       Net      -        -       0.401     -           1
    un1_triger_level_cnt12_0_o2         LUT3     I2       In      -         1.749       -
    un1_triger_level_cnt12_0_o2         LUT3     F        Out     0.462     2.211       -
    N_56                                Net      -        -       0.535     -           3
    un1_triger_level_cnt12_0_a2         LUT4     I0       In      -         2.746       -
    un1_triger_level_cnt12_0_a2         LUT4     F        Out     0.549     3.295       -
    N_119                               Net      -        -       0.535     -           4
    un1_triger_level_cnt12_0            LUT2     I0       In      -         3.830       -
    un1_triger_level_cnt12_0            LUT2     F        Out     0.549     4.379       -
    un1_triger_level_cnt12              Net      -        -       0.535     -           2
    triger_level_cnt_4[3]               LUT4     I2       In      -         4.914       -
    triger_level_cnt_4[3]               LUT4     F        Out     0.462     5.376       -
    triger_level_cnt_4[3]               Net      -        -       0.000     -           1
    triger_level_cnt[3]                 DFFC     D        In      -         5.376       -
    ==============================================================================================
    Total path delay (propagation time + setup) of 5.437 is 2.896(53.3%) logic and 2.541(46.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      4.622
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.561

        - Propagation time:                      5.355
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.795

        Number of logic level(s):                5
        Starting point:                          internal_reg_force_triger_syn[1] / Q
        Ending point:                            triger_level_cnt[3] / D
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                Pin      Pin               Arrival     No. of
    Name                                 Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------
    internal_reg_force_triger_syn[1]     DFFC     Q        Out     0.243     0.243       -
    internal_reg_force_triger_syn[1]     Net      -        -       0.535     -           1
    un1_triger_level_cnt12_0_o2_3        LUT4     I0       In      -         0.778       -
    un1_triger_level_cnt12_0_o2_3        LUT4     F        Out     0.549     1.327       -
    un1_triger_level_cnt12_0_o2_3        Net      -        -       0.401     -           1
    un1_triger_level_cnt12_0_o2          LUT3     I2       In      -         1.728       -
    un1_triger_level_cnt12_0_o2          LUT3     F        Out     0.462     2.190       -
    N_56                                 Net      -        -       0.535     -           3
    un1_triger_level_cnt12_0_a2          LUT4     I0       In      -         2.725       -
    un1_triger_level_cnt12_0_a2          LUT4     F        Out     0.549     3.274       -
    N_119                                Net      -        -       0.535     -           4
    un1_triger_level_cnt12_0             LUT2     I0       In      -         3.809       -
    un1_triger_level_cnt12_0             LUT2     F        Out     0.549     4.358       -
    un1_triger_level_cnt12               Net      -        -       0.535     -           2
    triger_level_cnt_4[3]                LUT4     I2       In      -         4.893       -
    triger_level_cnt_4[3]                LUT4     F        Out     0.462     5.355       -
    triger_level_cnt_4[3]                Net      -        -       0.000     -           1
    triger_level_cnt[3]                  DFFC     D        In      -         5.355       -
    ===============================================================================================
    Total path delay (propagation time + setup) of 5.416 is 2.875(53.1%) logic and 2.541(46.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      4.622
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.561

        - Propagation time:                      5.285
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.725

        Number of logic level(s):                5
        Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
        Ending point:                            triger_level_cnt[2] / D
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    genblk1\.u_ao_match_0.match_sep     DFFC     Q        Out     0.243     0.243       -
    match                               Net      -        -       0.535     -           1
    un1_triger_level_cnt12_0_o2_3       LUT4     I1       In      -         0.778       -
    un1_triger_level_cnt12_0_o2_3       LUT4     F        Out     0.570     1.348       -
    un1_triger_level_cnt12_0_o2_3       Net      -        -       0.401     -           1
    un1_triger_level_cnt12_0_o2         LUT3     I2       In      -         1.749       -
    un1_triger_level_cnt12_0_o2         LUT3     F        Out     0.462     2.211       -
    N_56                                Net      -        -       0.535     -           3
    triger_level_cnt13_i                LUT3     I0       In      -         2.746       -
    triger_level_cnt13_i                LUT3     F        Out     0.549     3.295       -
    triger_level_cnt13_i                Net      -        -       0.535     -           3
    un1_triger_level_cnt_ac0_1          LUT3     I0       In      -         3.830       -
    un1_triger_level_cnt_ac0_1          LUT3     F        Out     0.549     4.379       -
    un1_triger_level_cnt_c2             Net      -        -       0.535     -           2
    triger_level_cnt_4[2]               LUT4     I3       In      -         4.914       -
    triger_level_cnt_4[2]               LUT4     F        Out     0.371     5.285       -
    triger_level_cnt_4[2]               Net      -        -       0.000     -           1
    triger_level_cnt[2]                 DFFC     D        In      -         5.285       -
    ==============================================================================================
    Total path delay (propagation time + setup) of 5.346 is 2.805(52.5%) logic and 2.541(47.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      4.622
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.561

        - Propagation time:                      5.285
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.725

        Number of logic level(s):                5
        Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
        Ending point:                            triger_level_cnt[1] / D
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    genblk1\.u_ao_match_0.match_sep     DFFC     Q        Out     0.243     0.243       -
    match                               Net      -        -       0.535     -           1
    un1_triger_level_cnt12_0_o2_3       LUT4     I1       In      -         0.778       -
    un1_triger_level_cnt12_0_o2_3       LUT4     F        Out     0.570     1.348       -
    un1_triger_level_cnt12_0_o2_3       Net      -        -       0.401     -           1
    un1_triger_level_cnt12_0_o2         LUT3     I2       In      -         1.749       -
    un1_triger_level_cnt12_0_o2         LUT3     F        Out     0.462     2.211       -
    N_56                                Net      -        -       0.535     -           3
    un1_triger_level_cnt12_0_a2         LUT4     I0       In      -         2.746       -
    un1_triger_level_cnt12_0_a2         LUT4     F        Out     0.549     3.295       -
    N_119                               Net      -        -       0.535     -           4
    un1_triger_level_cnt12_0            LUT2     I0       In      -         3.830       -
    un1_triger_level_cnt12_0            LUT2     F        Out     0.549     4.379       -
    un1_triger_level_cnt12              Net      -        -       0.535     -           2
    triger_level_cnt_4[1]               LUT4     I3       In      -         4.914       -
    triger_level_cnt_4[1]               LUT4     F        Out     0.371     5.285       -
    triger_level_cnt_4[1]               Net      -        -       0.000     -           1
    triger_level_cnt[1]                 DFFC     D        In      -         5.285       -
    ==============================================================================================
    Total path delay (propagation time + setup) of 5.346 is 2.805(52.5%) logic and 2.541(47.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      4.622
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.561

        - Propagation time:                      5.285
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.725

        Number of logic level(s):                5
        Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
        Ending point:                            triger_level_cnt[3] / D
        The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    genblk1\.u_ao_match_0.match_sep     DFFC     Q        Out     0.243     0.243       -
    match                               Net      -        -       0.535     -           1
    un1_triger_level_cnt12_0_o2_3       LUT4     I1       In      -         0.778       -
    un1_triger_level_cnt12_0_o2_3       LUT4     F        Out     0.570     1.348       -
    un1_triger_level_cnt12_0_o2_3       Net      -        -       0.401     -           1
    un1_triger_level_cnt12_0_o2         LUT3     I2       In      -         1.749       -
    un1_triger_level_cnt12_0_o2         LUT3     F        Out     0.462     2.211       -
    N_56                                Net      -        -       0.535     -           3
    triger_level_cnt13_i                LUT3     I0       In      -         2.746       -
    triger_level_cnt13_i                LUT3     F        Out     0.549     3.295       -
    triger_level_cnt13_i                Net      -        -       0.535     -           3
    un1_triger_level_cnt_ac0_1          LUT3     I0       In      -         3.830       -
    un1_triger_level_cnt_ac0_1          LUT3     F        Out     0.549     4.379       -
    un1_triger_level_cnt_c2             Net      -        -       0.535     -           2
    triger_level_cnt_4[3]               LUT4     I3       In      -         4.914       -
    triger_level_cnt_4[3]               LUT4     F        Out     0.371     5.285       -
    triger_level_cnt_4[3]               Net      -        -       0.000     -           1
    triger_level_cnt[3]                 DFFC     D        In      -         5.285       -
    ==============================================================================================
    Total path delay (propagation time + setup) of 5.346 is 2.805(52.5%) logic and 2.541(47.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: ao_top_0|control[0]
    ====================================

    Starting Points with Worst Slack
    ********************************

                                     Starting                                                                   Arrival
    Instance                         Reference               Type      Pin     Net                              Time        Slack
                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------
    data_register[39]                ao_top_0|control[0]     DFFCE     Q       data_register[39]                0.243       -1.014
    data_register[38]                ao_top_0|control[0]     DFFCE     Q       data_register[38]                0.243       -0.880
    data_register[36]                ao_top_0|control[0]     DFFCE     Q       data_register[36]                0.243       -0.859
    internal_register_select[3]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[3]      0.243       -0.772
    internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.243       -0.767
    internal_register_select[2]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[2]      0.243       -0.751
    internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.243       -0.746
    internal_register_select[13]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[13]     0.243       -0.746
    internal_register_select[12]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[12]     0.243       -0.725
    internal_register_select[6]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[6]      0.243       -0.664
    ==============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                       Starting                                                                        Required
    Instance                           Reference               Type      Pin     Net                                   Time         Slack
                                       Clock
    --------------------------------------------------------------------------------------------------------------------------------------
    capture_windows_num[0]             ao_top_0|control[0]     DFFC      D       capture_windows_nume_0[0]             5.683        -1.014
    capture_windows_num[1]             ao_top_0|control[0]     DFFC      D       capture_windows_nume_0[1]             5.683        -1.014
    capture_windows_num[2]             ao_top_0|control[0]     DFFC      D       capture_windows_nume_0[2]             5.683        -1.014
    internal_reg_trig_level_max[0]     ao_top_0|control[0]     DFFC      D       internal_reg_trig_level_maxe_0[0]     5.683        -0.906
    internal_reg_trig_level_max[1]     ao_top_0|control[0]     DFFC      D       internal_reg_trig_level_maxe_0[1]     5.683        -0.906
    internal_reg_trig_level_max[2]     ao_top_0|control[0]     DFFC      D       internal_reg_trig_level_maxe_0[2]     5.683        -0.906
    internal_reg_trig_level_max[3]     ao_top_0|control[0]     DFFC      D       internal_reg_trig_level_maxe_0[3]     5.683        -0.906
    data_out_shift_reg[2]              ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[2]               5.683        -0.772
    data_out_shift_reg[0]              ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[0]               5.683        -0.698
    data_out_shift_reg[3]              ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[3]               5.683        -0.681
    ======================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.744
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.683

        - Propagation time:                      6.697
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.014

        Number of logic level(s):                6
        Starting point:                          data_register[39] / Q
        Ending point:                            capture_windows_num[0] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                          Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    data_register[39]             DFFCE     Q        Out     0.243     0.243       -
    data_register[39]             Net       -        -       0.535     -           6
    m23_e_1                       LUT3      I2       In      -         0.778       -
    m23_e_1                       LUT3      F        Out     0.462     1.240       -
    m23_e_1                       Net       -        -       0.535     -           3
    m39                           LUT4      I1       In      -         1.775       -
    m39                           LUT4      F        Out     0.570     2.345       -
    regsel_ld_en_0_sqmuxa         Net       -        -       0.596     -           18
    data_register_RNIPQHG[37]     LUT2      I1       In      -         2.941       -
    data_register_RNIPQHG[37]     LUT2      F        Out     0.570     3.511       -
    intreg_ld_en_0_sqmuxa_1       Net       -        -       0.535     -           5
    m42                           LUT4      I2       In      -         4.046       -
    m42                           LUT4      F        Out     0.462     4.508       -
    N_87_mux                      Net       -        -       0.535     -           4
    m44                           LUT3      I0       In      -         5.043       -
    m44                           LUT3      F        Out     0.549     5.592       -
    capture_windows_num_wr        Net       -        -       0.535     -           3
    capture_windows_nume[0]       LUT3      I1       In      -         6.127       -
    capture_windows_nume[0]       LUT3      F        Out     0.570     6.697       -
    capture_windows_nume_0[0]     Net       -        -       0.000     -           1
    capture_windows_num[0]        DFFC      D        In      -         6.697       -
    =========================================================================================
    Total path delay (propagation time + setup) of 6.758 is 3.487(51.6%) logic and 3.271(48.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      5.744
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.683

        - Propagation time:                      6.697
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.014

        Number of logic level(s):                6
        Starting point:                          data_register[39] / Q
        Ending point:                            capture_windows_num[2] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                          Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    data_register[39]             DFFCE     Q        Out     0.243     0.243       -
    data_register[39]             Net       -        -       0.535     -           6
    m23_e_1                       LUT3      I2       In      -         0.778       -
    m23_e_1                       LUT3      F        Out     0.462     1.240       -
    m23_e_1                       Net       -        -       0.535     -           3
    m39                           LUT4      I1       In      -         1.775       -
    m39                           LUT4      F        Out     0.570     2.345       -
    regsel_ld_en_0_sqmuxa         Net       -        -       0.596     -           18
    data_register_RNIPQHG[37]     LUT2      I1       In      -         2.941       -
    data_register_RNIPQHG[37]     LUT2      F        Out     0.570     3.511       -
    intreg_ld_en_0_sqmuxa_1       Net       -        -       0.535     -           5
    m42                           LUT4      I2       In      -         4.046       -
    m42                           LUT4      F        Out     0.462     4.508       -
    N_87_mux                      Net       -        -       0.535     -           4
    m44                           LUT3      I0       In      -         5.043       -
    m44                           LUT3      F        Out     0.549     5.592       -
    capture_windows_num_wr        Net       -        -       0.535     -           3
    capture_windows_nume[2]       LUT3      I1       In      -         6.127       -
    capture_windows_nume[2]       LUT3      F        Out     0.570     6.697       -
    capture_windows_nume_0[2]     Net       -        -       0.000     -           1
    capture_windows_num[2]        DFFC      D        In      -         6.697       -
    =========================================================================================
    Total path delay (propagation time + setup) of 6.758 is 3.487(51.6%) logic and 3.271(48.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      5.744
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.683

        - Propagation time:                      6.697
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.014

        Number of logic level(s):                6
        Starting point:                          data_register[39] / Q
        Ending point:                            capture_windows_num[1] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                          Type      Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    data_register[39]             DFFCE     Q        Out     0.243     0.243       -
    data_register[39]             Net       -        -       0.535     -           6
    m23_e_1                       LUT3      I2       In      -         0.778       -
    m23_e_1                       LUT3      F        Out     0.462     1.240       -
    m23_e_1                       Net       -        -       0.535     -           3
    m39                           LUT4      I1       In      -         1.775       -
    m39                           LUT4      F        Out     0.570     2.345       -
    regsel_ld_en_0_sqmuxa         Net       -        -       0.596     -           18
    data_register_RNIPQHG[37]     LUT2      I1       In      -         2.941       -
    data_register_RNIPQHG[37]     LUT2      F        Out     0.570     3.511       -
    intreg_ld_en_0_sqmuxa_1       Net       -        -       0.535     -           5
    m42                           LUT4      I2       In      -         4.046       -
    m42                           LUT4      F        Out     0.462     4.508       -
    N_87_mux                      Net       -        -       0.535     -           4
    m44                           LUT3      I0       In      -         5.043       -
    m44                           LUT3      F        Out     0.549     5.592       -
    capture_windows_num_wr        Net       -        -       0.535     -           3
    capture_windows_nume[1]       LUT3      I1       In      -         6.127       -
    capture_windows_nume[1]       LUT3      F        Out     0.570     6.697       -
    capture_windows_nume_0[1]     Net       -        -       0.000     -           1
    capture_windows_num[1]        DFFC      D        In      -         6.697       -
    =========================================================================================
    Total path delay (propagation time + setup) of 6.758 is 3.487(51.6%) logic and 3.271(48.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      5.744
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.683

        - Propagation time:                      6.589
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.906

        Number of logic level(s):                6
        Starting point:                          data_register[39] / Q
        Ending point:                            internal_reg_trig_level_max[0] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                  Pin      Pin               Arrival     No. of
    Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    data_register[39]                     DFFCE     Q        Out     0.243     0.243       -
    data_register[39]                     Net       -        -       0.535     -           6
    m23_e_1                               LUT3      I2       In      -         0.778       -
    m23_e_1                               LUT3      F        Out     0.462     1.240       -
    m23_e_1                               Net       -        -       0.535     -           3
    m39                                   LUT4      I1       In      -         1.775       -
    m39                                   LUT4      F        Out     0.570     2.345       -
    regsel_ld_en_0_sqmuxa                 Net       -        -       0.596     -           18
    data_register_RNIPQHG[37]             LUT2      I1       In      -         2.941       -
    data_register_RNIPQHG[37]             LUT2      F        Out     0.570     3.511       -
    intreg_ld_en_0_sqmuxa_1               Net       -        -       0.535     -           5
    m42                                   LUT4      I2       In      -         4.046       -
    m42                                   LUT4      F        Out     0.462     4.508       -
    N_87_mux                              Net       -        -       0.535     -           4
    m48                                   LUT3      I0       In      -         5.043       -
    m48                                   LUT3      F        Out     0.549     5.592       -
    trig_level_max_reg_wr                 Net       -        -       0.535     -           4
    internal_reg_trig_level_maxe[0]       LUT3      I2       In      -         6.127       -
    internal_reg_trig_level_maxe[0]       LUT3      F        Out     0.462     6.589       -
    internal_reg_trig_level_maxe_0[0]     Net       -        -       0.000     -           1
    internal_reg_trig_level_max[0]        DFFC      D        In      -         6.589       -
    =================================================================================================
    Total path delay (propagation time + setup) of 6.650 is 3.379(50.8%) logic and 3.271(49.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      5.744
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         5.683

        - Propagation time:                      6.589
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -0.906

        Number of logic level(s):                6
        Starting point:                          data_register[39] / Q
        Ending point:                            internal_reg_trig_level_max[2] / D
        The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
        The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

    Instance / Net                                  Pin      Pin               Arrival     No. of
    Name                                  Type      Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    data_register[39]                     DFFCE     Q        Out     0.243     0.243       -
    data_register[39]                     Net       -        -       0.535     -           6
    m23_e_1                               LUT3      I2       In      -         0.778       -
    m23_e_1                               LUT3      F        Out     0.462     1.240       -
    m23_e_1                               Net       -        -       0.535     -           3
    m39                                   LUT4      I1       In      -         1.775       -
    m39                                   LUT4      F        Out     0.570     2.345       -
    regsel_ld_en_0_sqmuxa                 Net       -        -       0.596     -           18
    data_register_RNIPQHG[37]             LUT2      I1       In      -         2.941       -
    data_register_RNIPQHG[37]             LUT2      F        Out     0.570     3.511       -
    intreg_ld_en_0_sqmuxa_1               Net       -        -       0.535     -           5
    m42                                   LUT4      I2       In      -         4.046       -
    m42                                   LUT4      F        Out     0.462     4.508       -
    N_87_mux                              Net       -        -       0.535     -           4
    m48                                   LUT3      I0       In      -         5.043       -
    m48                                   LUT3      F        Out     0.549     5.592       -
    trig_level_max_reg_wr                 Net       -        -       0.535     -           4
    internal_reg_trig_level_maxe[2]       LUT3      I2       In      -         6.127       -
    internal_reg_trig_level_maxe[2]       LUT3      F        Out     0.462     6.589       -
    internal_reg_trig_level_maxe_0[2]     Net       -        -       0.000     -           1
    internal_reg_trig_level_max[2]        DFFC      D        In      -         6.589       -
    =================================================================================================
    Total path delay (propagation time + setup) of 6.650 is 3.379(50.8%) logic and 3.271(49.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                             Starting                                           Arrival
    Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                             Clock
    -------------------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       2.480
    address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       3.793
    =============================================================================================================

    Ending Points with Worst Slack
    ******************************

                                  Starting                                                        Required
    Instance                      Reference     Type      Pin     Net                             Time         Slack
                                  Clock
    ----------------------------------------------------------------------------------------------------------------
    capture_window_sel[2]         System        DFFC      D       capture_window_sel_3[2]         4.561        2.480
    capture_window_sel[3]         System        DFFC      D       capture_window_sel_3[3]         4.561        2.480
    capture_window_sel[1]         System        DFFC      D       capture_window_sel_3[1]         4.561        2.704
    capture_window_sel[0]         System        DFFC      D       capture_window_sel_3[0]         4.561        3.477
    internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]     4.561        3.477
    address_counter[10]           System        DFFCE     D       address_counter_s[10]           5.683        3.793
    address_counter[9]            System        DFFCE     D       address_counter_s[9]            5.683        3.828
    address_counter[8]            System        DFFCE     D       address_counter_s[8]            5.683        3.863
    address_counter[7]            System        DFFCE     D       address_counter_s[7]            5.683        3.898
    address_counter[6]            System        DFFCE     D       address_counter_s[6]            5.683        3.933
    ================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      4.622
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.561

        - Propagation time:                      2.081
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 2.480

        Number of logic level(s):                2
        Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
        Ending point:                            capture_window_sel[2] / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     INV      O        Out     0.000     0.000       -
    capture_end                              Net      -        -       0.535     -           6
    un1_capture_window_sel_ac0_1             LUT4     I0       In      -         0.535       -
    un1_capture_window_sel_ac0_1             LUT4     F        Out     0.549     1.084       -
    un1_capture_window_sel_c2                Net      -        -       0.535     -           2
    capture_window_sel_3[2]                  LUT3     I2       In      -         1.619       -
    capture_window_sel_3[2]                  LUT3     F        Out     0.462     2.081       -
    capture_window_sel_3[2]                  Net      -        -       0.000     -           1
    capture_window_sel[2]                    DFFC     D        In      -         2.081       -
    ===================================================================================================
    Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 251MB peak: 254MB)

    Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 251MB peak: 254MB)

    ---------------------------------------
    Resource Usage Report for ao_top_0

    Mapping to part: gw2a_18pbga484-8
    Cell usage:
    ALU             73 uses
    DFF             18 uses
    DFFC            47 uses
    DFFCE           200 uses
    DFFNP           2 uses
    DFFP            5 uses
    DFFPE           32 uses
    GSR             1 use
    INV             2 uses
    MUX2_LUT5       5 uses
    SDPX9           3 uses
    LUT2            57 uses
    LUT3            103 uses
    LUT4            234 uses

    I/O ports: 31
    I/O primitives: 30
    IBUF           28 uses
    OBUF           2 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   304 of 15552 (1%)

    RAM/ROM usage summary
    Block Rams : 3 of 46 (6%)

    Total load per clock:
       ao_top_0|clk_i: 1
       ao_top_0|control[0]: 244

    @S |Mapping Summary:
    Total  LUTs: 394 (1%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 79MB peak: 254MB)

    Process took 0h:00m:06s realtime, 0h:00m:05s cputime
    # Fri Dec 20 16:22:08 2019

    ###########################################################]

`