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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G-1-Beta1
Install: D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1

# Written on Thu Dec 19 10:07:51 2019

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                           Requested     Requested     Clock        Clock                     Clock
Level     Clock                           Frequency     Period        Type         Group                     Load 
------------------------------------------------------------------------------------------------------------------
0 -       fifo_dma_write_32_128|RdClk     199.1 MHz     5.024         inferred     Autoconstr_clkgroup_1     189  
                                                                                                                  
0 -       fifo_dma_write_32_128|WrClk     247.1 MHz     4.047         inferred     Autoconstr_clkgroup_0     172  
==================================================================================================================


Clock Load Summary
******************

                                Clock     Source          Clock Pin                          Non-clock Pin     Non-clock Pin                
Clock                           Load      Pin             Seq Example                        Seq Example       Comb Example                 
--------------------------------------------------------------------------------------------------------------------------------------------
fifo_dma_write_32_128|RdClk     189       RdClk(port)     fifo_inst.Big\.rq2_wptr[9:0].C     -                 fifo_inst.un1_RdClk.I[0](inv)
                                                                                                                                            
fifo_dma_write_32_128|WrClk     172       WrClk(port)     fifo_inst.Big\.wq2_rptr[9:0].C     -                 fifo_inst.un1_WrClk.I[0](inv)
============================================================================================================================================
