# project files
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/ddr3_memory_interface/ddr3_memory_interface.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/frame_buffer/vfb_defines.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/frame_buffer/vfb_top.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/gw_pll/gw_pll.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/gw_pll/pix_pll.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/i2c_master/i2c_master.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/syn_code/syn_gen.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/adv7513_iic_init.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/key_debounceN.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/scaler_test_top.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/testpattern.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/frame_buffer/vfb_wrapper.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/frame_buffer/fifo/fifo_dma_read_128_32.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/frame_buffer/fifo/fifo_dma_write_32_128.v"
add_file -verilog "E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/scaler/scaler.v"

# implementation: "rev_1"
impl -add rev_1 -type fpga

# device options
set_option -technology GOWIN-GW2A
set_option -part GW2A_18C
set_option -package PBGA484
set_option -speed_grade -8

set_option -frequency auto
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -update_models_cp 0
set_option -rw_check_on_ram 1
set_option -run_prop_extract 1
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -pipe 1
set_option -retiming 0
set_option -write_apr_constraint 1
set_option -vlog_std sysv
set_option -compiler_compatible 0
set_option -multi_file_compilation_unit 1
set_option -looplimit 2000
set_option -fix_gated_and_generated_clocks 1
set_option -top_module scaler_test_top
set_option -include_path {E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/frame_buffer;E:/IP_verify/1.9.6/IP_web/Gowin_Scaler_RefDesign_DDR300MHz/Gowin_Scaler_RefDesign_DDR300MHz/scaler_example_design_memory/project/src/scaler}
set_option -library_path C:/Gowin/Gowin_V1.9.6Beta/IDE/simlib/hardware_core/gw2a/prim_syn.v
# set result format/file
project -result_file "scaler_ref_design_memory.vm"
impl -active "rev_1"
project -run -clean

