# Mon Dec  9 10:09:03 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: DESKTOP

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1450R, Built Sep 25 2019 09:35:08


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

@A: MF827 |No constraint file specified.
@L: D:\proj\scaler_example_design_live\project\src\i2c_master\temp\I2C_MASTER\rev_1\i2c_master_scck.rpt 
Printing clock  summary report in "D:\proj\scaler_example_design_live\project\src\i2c_master\temp\I2C_MASTER\rev_1\i2c_master_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 126MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 126MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)

Encoding state machine c_state[5:0] (in view: work.\\\~I2C_Master_Byte_Ctrl\.I2C_MASTER_Top\ (verilog))
original code -> new code
   00000 -> 000001
   00001 -> 000010
   00010 -> 000100
   00100 -> 001000
   01000 -> 010000
   10000 -> 100000
Encoding state machine c_state[17:0] (in view: work.\\\~I2C_Master_Bit_Ctrl\.I2C_MASTER_Top\ (verilog))
original code -> new code
   00000000000000000 -> 000000000000000001
   00000000000000001 -> 000000000000000010
   00000000000000010 -> 000000000000000100
   00000000000000100 -> 000000000000001000
   00000000000001000 -> 000000000000010000
   00000000000010000 -> 000000000000100000
   00000000000100000 -> 000000000001000000
   00000000001000000 -> 000000000010000000
   00000000010000000 -> 000000000100000000
   00000000100000000 -> 000000001000000000
   00000001000000000 -> 000000010000000000
   00000010000000000 -> 000000100000000000
   00000100000000000 -> 000001000000000000
   00001000000000000 -> 000010000000000000
   00010000000000000 -> 000100000000000000
   00100000000000000 -> 001000000000000000
   01000000000000000 -> 010000000000000000
   10000000000000000 -> 100000000000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)



Clock Summary
******************

          Start                    Requested     Requested     Clock        Clock                     Clock
Level     Clock                    Frequency     Period        Type         Group                     Load 
-----------------------------------------------------------------------------------------------------------
0 -       I2C_MASTER_Top|I_CLK     253.9 MHz     3.939         inferred     Autoconstr_clkgroup_0     127  
===========================================================================================================



Clock Load Summary
***********************

                         Clock     Source          Clock Pin                Non-clock Pin     Non-clock Pin
Clock                    Load      Pin             Seq Example              Seq Example       Comb Example 
-----------------------------------------------------------------------------------------------------------
I2C_MASTER_Top|I_CLK     127       I_CLK(port)     u_i2c_master.rxack.C     -                 -            
===========================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 127 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       I_CLK               port                   127        ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\proj\scaler_example_design_live\project\src\i2c_master\temp\I2C_MASTER\rev_1\i2c_master.sap.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 223MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Mon Dec  9 10:09:06 2019

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