//Copyright (C)2014-2020 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//GOWIN Version: 1.9.6 Beta
//Created Time: 2020-07-01 17:56:29
create_clock -name clk_x4 -period 3.333 -waveform {0 1.667} [get_nets {DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4}] -add
create_clock -name clk_x4i -period 3.333 -waveform {0 1.667} [get_nets {DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4i}] -add
create_clock -name dma_clk -period 13.333 -waveform {0 6.667} [get_nets {dma_clk}] -add
create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add
set_clock_groups -exclusive -group [get_clocks {dma_clk}] 
set_clock_groups -exclusive -group [get_clocks {I_clk}] 
set_clock_groups -exclusive -group [get_clocks {clk_x4i}]
set_clock_groups -exclusive -group [get_clocks {clk_x4}]
