
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1

# Written on Wed Jun 17 17:50:21 2020

##### DESIGN INFO #######################################################

Top View:                "DDR3_Memory_Interface_Top"
Constraint File(s):      (none)




##### SUMMARY ############################################################

Found 0 issues in 0 out of 0 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting                                                              Ending                                                                                      |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                                System                                                                                      |     6.667            |     No paths         |     No paths         |     No paths                         
System                                                                _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                           |     6.160            |     No paths         |     No paths         |     No paths                         
System                                                                DDR3_Memory_Interface_Top|clk                                                               |     3.306            |     No paths         |     No paths         |     No paths                         
System                                                                _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                          |     6.667            |     No paths         |     No paths         |     No paths                         
System                                                                _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock     |     No paths         |     No paths         |     6.667            |     No paths                         
System                                                                _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock     |     No paths         |     No paths         |     6.667            |     No paths                         
_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     System                                                                                      |     6.160            |     No paths         |     No paths         |     No paths                         
_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                           |     6.160            |     No paths         |     No paths         |     No paths                         
_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     DDR3_Memory_Interface_Top|clk                                                               |     Diff grp         |     No paths         |     No paths         |     No paths                         
_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock     _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                          |     Diff grp         |     No paths         |     No paths         |     No paths                         
DDR3_Memory_Interface_Top|clk                                         System                                                                                      |     3.306            |     No paths         |     No paths         |     No paths                         
DDR3_Memory_Interface_Top|clk                                         _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                           |     Diff grp         |     No paths         |     No paths         |     No paths                         
DDR3_Memory_Interface_Top|clk                                         DDR3_Memory_Interface_Top|clk                                                               |     3.306            |     No paths         |     No paths         |     No paths                         
=============================================================================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:IO_ddr_dq[0] (bidir end point)
p:IO_ddr_dq[0] (bidir start point)
p:IO_ddr_dq[1] (bidir end point)
p:IO_ddr_dq[1] (bidir start point)
p:IO_ddr_dq[2] (bidir end point)
p:IO_ddr_dq[2] (bidir start point)
p:IO_ddr_dq[3] (bidir end point)
p:IO_ddr_dq[3] (bidir start point)
p:IO_ddr_dq[4] (bidir end point)
p:IO_ddr_dq[4] (bidir start point)
p:IO_ddr_dq[5] (bidir end point)
p:IO_ddr_dq[5] (bidir start point)
p:IO_ddr_dq[6] (bidir end point)
p:IO_ddr_dq[6] (bidir start point)
p:IO_ddr_dq[7] (bidir end point)
p:IO_ddr_dq[7] (bidir start point)
p:IO_ddr_dq[8] (bidir end point)
p:IO_ddr_dq[8] (bidir start point)
p:IO_ddr_dq[9] (bidir end point)
p:IO_ddr_dq[9] (bidir start point)
p:IO_ddr_dq[10] (bidir end point)
p:IO_ddr_dq[10] (bidir start point)
p:IO_ddr_dq[11] (bidir end point)
p:IO_ddr_dq[11] (bidir start point)
p:IO_ddr_dq[12] (bidir end point)
p:IO_ddr_dq[12] (bidir start point)
p:IO_ddr_dq[13] (bidir end point)
p:IO_ddr_dq[13] (bidir start point)
p:IO_ddr_dq[14] (bidir end point)
p:IO_ddr_dq[14] (bidir start point)
p:IO_ddr_dq[15] (bidir end point)
p:IO_ddr_dq[15] (bidir start point)
p:IO_ddr_dqs[0] (bidir end point)
p:IO_ddr_dqs[0] (bidir start point)
p:IO_ddr_dqs[1] (bidir end point)
p:IO_ddr_dqs[1] (bidir start point)
p:IO_ddr_dqs_n[0] (bidir end point)
p:IO_ddr_dqs_n[0] (bidir start point)
p:IO_ddr_dqs_n[1] (bidir end point)
p:IO_ddr_dqs_n[1] (bidir start point)
p:O_ddr_addr[0]
p:O_ddr_addr[1]
p:O_ddr_addr[2]
p:O_ddr_addr[3]
p:O_ddr_addr[4]
p:O_ddr_addr[5]
p:O_ddr_addr[6]
p:O_ddr_addr[7]
p:O_ddr_addr[8]
p:O_ddr_addr[9]
p:O_ddr_addr[10]
p:O_ddr_addr[11]
p:O_ddr_addr[12]
p:O_ddr_addr[13]
p:O_ddr_ba[0]
p:O_ddr_ba[1]
p:O_ddr_ba[2]
p:O_ddr_cas_n
p:O_ddr_cke
p:O_ddr_clk
p:O_ddr_clk_n
p:O_ddr_cs_n
p:O_ddr_dqm[0]
p:O_ddr_dqm[1]
p:O_ddr_odt
p:O_ddr_ras_n
p:O_ddr_reset_n
p:O_ddr_we_n
p:addr[0]
p:addr[1]
p:addr[2]
p:addr[3]
p:addr[4]
p:addr[5]
p:addr[6]
p:addr[7]
p:addr[8]
p:addr[9]
p:addr[10]
p:addr[11]
p:addr[12]
p:addr[13]
p:addr[14]
p:addr[15]
p:addr[16]
p:addr[17]
p:addr[18]
p:addr[19]
p:addr[20]
p:addr[21]
p:addr[22]
p:addr[23]
p:addr[24]
p:addr[25]
p:addr[26]
p:addr[27]
p:app_burst_number[0]
p:app_burst_number[1]
p:app_burst_number[2]
p:app_burst_number[3]
p:app_burst_number[4]
p:app_burst_number[5]
p:burst
p:cmd[0]
p:cmd[1]
p:cmd[2]
p:cmd_en
p:cmd_ready
p:ddr_rst
p:init_calib_complete
p:rd_data[0]
p:rd_data[1]
p:rd_data[2]
p:rd_data[3]
p:rd_data[4]
p:rd_data[5]
p:rd_data[6]
p:rd_data[7]
p:rd_data[8]
p:rd_data[9]
p:rd_data[10]
p:rd_data[11]
p:rd_data[12]
p:rd_data[13]
p:rd_data[14]
p:rd_data[15]
p:rd_data[16]
p:rd_data[17]
p:rd_data[18]
p:rd_data[19]
p:rd_data[20]
p:rd_data[21]
p:rd_data[22]
p:rd_data[23]
p:rd_data[24]
p:rd_data[25]
p:rd_data[26]
p:rd_data[27]
p:rd_data[28]
p:rd_data[29]
p:rd_data[30]
p:rd_data[31]
p:rd_data[32]
p:rd_data[33]
p:rd_data[34]
p:rd_data[35]
p:rd_data[36]
p:rd_data[37]
p:rd_data[38]
p:rd_data[39]
p:rd_data[40]
p:rd_data[41]
p:rd_data[42]
p:rd_data[43]
p:rd_data[44]
p:rd_data[45]
p:rd_data[46]
p:rd_data[47]
p:rd_data[48]
p:rd_data[49]
p:rd_data[50]
p:rd_data[51]
p:rd_data[52]
p:rd_data[53]
p:rd_data[54]
p:rd_data[55]
p:rd_data[56]
p:rd_data[57]
p:rd_data[58]
p:rd_data[59]
p:rd_data[60]
p:rd_data[61]
p:rd_data[62]
p:rd_data[63]
p:rd_data[64]
p:rd_data[65]
p:rd_data[66]
p:rd_data[67]
p:rd_data[68]
p:rd_data[69]
p:rd_data[70]
p:rd_data[71]
p:rd_data[72]
p:rd_data[73]
p:rd_data[74]
p:rd_data[75]
p:rd_data[76]
p:rd_data[77]
p:rd_data[78]
p:rd_data[79]
p:rd_data[80]
p:rd_data[81]
p:rd_data[82]
p:rd_data[83]
p:rd_data[84]
p:rd_data[85]
p:rd_data[86]
p:rd_data[87]
p:rd_data[88]
p:rd_data[89]
p:rd_data[90]
p:rd_data[91]
p:rd_data[92]
p:rd_data[93]
p:rd_data[94]
p:rd_data[95]
p:rd_data[96]
p:rd_data[97]
p:rd_data[98]
p:rd_data[99]
p:rd_data[100]
p:rd_data[101]
p:rd_data[102]
p:rd_data[103]
p:rd_data[104]
p:rd_data[105]
p:rd_data[106]
p:rd_data[107]
p:rd_data[108]
p:rd_data[109]
p:rd_data[110]
p:rd_data[111]
p:rd_data[112]
p:rd_data[113]
p:rd_data[114]
p:rd_data[115]
p:rd_data[116]
p:rd_data[117]
p:rd_data[118]
p:rd_data[119]
p:rd_data[120]
p:rd_data[121]
p:rd_data[122]
p:rd_data[123]
p:rd_data[124]
p:rd_data[125]
p:rd_data[126]
p:rd_data[127]
p:rd_data_end
p:rd_data_valid
p:ref_ack
p:ref_req
p:rst_n
p:sr_ack
p:sr_req
p:wr_data[0]
p:wr_data[1]
p:wr_data[2]
p:wr_data[3]
p:wr_data[4]
p:wr_data[5]
p:wr_data[6]
p:wr_data[7]
p:wr_data[8]
p:wr_data[9]
p:wr_data[10]
p:wr_data[11]
p:wr_data[12]
p:wr_data[13]
p:wr_data[14]
p:wr_data[15]
p:wr_data[16]
p:wr_data[17]
p:wr_data[18]
p:wr_data[19]
p:wr_data[20]
p:wr_data[21]
p:wr_data[22]
p:wr_data[23]
p:wr_data[24]
p:wr_data[25]
p:wr_data[26]
p:wr_data[27]
p:wr_data[28]
p:wr_data[29]
p:wr_data[30]
p:wr_data[31]
p:wr_data[32]
p:wr_data[33]
p:wr_data[34]
p:wr_data[35]
p:wr_data[36]
p:wr_data[37]
p:wr_data[38]
p:wr_data[39]
p:wr_data[40]
p:wr_data[41]
p:wr_data[42]
p:wr_data[43]
p:wr_data[44]
p:wr_data[45]
p:wr_data[46]
p:wr_data[47]
p:wr_data[48]
p:wr_data[49]
p:wr_data[50]
p:wr_data[51]
p:wr_data[52]
p:wr_data[53]
p:wr_data[54]
p:wr_data[55]
p:wr_data[56]
p:wr_data[57]
p:wr_data[58]
p:wr_data[59]
p:wr_data[60]
p:wr_data[61]
p:wr_data[62]
p:wr_data[63]
p:wr_data[64]
p:wr_data[65]
p:wr_data[66]
p:wr_data[67]
p:wr_data[68]
p:wr_data[69]
p:wr_data[70]
p:wr_data[71]
p:wr_data[72]
p:wr_data[73]
p:wr_data[74]
p:wr_data[75]
p:wr_data[76]
p:wr_data[77]
p:wr_data[78]
p:wr_data[79]
p:wr_data[80]
p:wr_data[81]
p:wr_data[82]
p:wr_data[83]
p:wr_data[84]
p:wr_data[85]
p:wr_data[86]
p:wr_data[87]
p:wr_data[88]
p:wr_data[89]
p:wr_data[90]
p:wr_data[91]
p:wr_data[92]
p:wr_data[93]
p:wr_data[94]
p:wr_data[95]
p:wr_data[96]
p:wr_data[97]
p:wr_data[98]
p:wr_data[99]
p:wr_data[100]
p:wr_data[101]
p:wr_data[102]
p:wr_data[103]
p:wr_data[104]
p:wr_data[105]
p:wr_data[106]
p:wr_data[107]
p:wr_data[108]
p:wr_data[109]
p:wr_data[110]
p:wr_data[111]
p:wr_data[112]
p:wr_data[113]
p:wr_data[114]
p:wr_data[115]
p:wr_data[116]
p:wr_data[117]
p:wr_data[118]
p:wr_data[119]
p:wr_data[120]
p:wr_data[121]
p:wr_data[122]
p:wr_data[123]
p:wr_data[124]
p:wr_data[125]
p:wr_data[126]
p:wr_data[127]
p:wr_data_en
p:wr_data_end
p:wr_data_mask[0]
p:wr_data_mask[1]
p:wr_data_mask[2]
p:wr_data_mask[3]
p:wr_data_mask[4]
p:wr_data_mask[5]
p:wr_data_mask[6]
p:wr_data_mask[7]
p:wr_data_mask[8]
p:wr_data_mask[9]
p:wr_data_mask[10]
p:wr_data_mask[11]
p:wr_data_mask[12]
p:wr_data_mask[13]
p:wr_data_mask[14]
p:wr_data_mask[15]
p:wr_data_rdy


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report
