# Wed Jun 17 14:39:51 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1620R, Built May 18 2020 06:06:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 228MB peak: 228MB)


Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 234MB peak: 234MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 238MB peak: 238MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 241MB peak: 241MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 242MB peak: 242MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 242MB peak: 242MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 242MB peak: 242MB)


Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 242MB peak: 242MB)


Finished technology mapping (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 242MB peak: 242MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:08s		    -1.86ns		1503 /      1400
   2		0h:00m:08s		    -1.86ns		1504 /      1400
Timing driven replication report
Added 11 Registers via timing driven replication
Added 3 LUTs via timing driven replication

   3		0h:00m:08s		    -1.87ns		1507 /      1411


   4		0h:00m:09s		    -1.85ns		1508 /      1411

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 243MB peak: 243MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 243MB peak: 243MB)


Start Writing Netlists (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 165MB peak: 243MB)

Writing Analyst data base D:\proj\scaler_example_design_memory\project\src\scaler\temp\scaler\rev_1\synwork\scaler_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 241MB peak: 243MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 242MB peak: 244MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 242MB peak: 244MB)


Start final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 239MB peak: 244MB)

@W: MT420 |Found inferred clock Scaler_Top|I_vin_clk with period 4.21ns. Please declare a user-defined clock on port I_vin_clk.
@W: MT420 |Found inferred clock Scaler_Top|I_sysclk with period 4.04ns. Please declare a user-defined clock on port I_sysclk.
@W: MT420 |Found inferred clock Scaler_Top|I_vout_clk with period 4.21ns. Please declare a user-defined clock on port I_vout_clk.


##### START OF TIMING REPORT #####[
# Timing report written on Wed Jun 17 14:40:07 2020
#


Top view:               Scaler_Top
Requested Frequency:    237.3 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -0.744

                          Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock            Frequency     Frequency     Period        Period        Slack      Type         Group                
-------------------------------------------------------------------------------------------------------------------------------
Scaler_Top|I_sysclk       247.5 MHz     210.4 MHz     4.040         4.753         -0.713     inferred     Autoconstr_clkgroup_1
Scaler_Top|I_vin_clk      237.3 MHz     201.7 MHz     4.214         4.958         -0.744     inferred     Autoconstr_clkgroup_0
Scaler_Top|I_vout_clk     237.3 MHz     201.7 MHz     4.214         4.958         -0.744     inferred     Autoconstr_clkgroup_2
===============================================================================================================================





Clock Relationships
*******************

Clocks                                        |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------
Starting               Ending                 |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------
Scaler_Top|I_vin_clk   Scaler_Top|I_vin_clk   |  4.214       -0.744  |  No paths    -      |  No paths    -      |  No paths    -    
Scaler_Top|I_vin_clk   Scaler_Top|I_sysclk    |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Scaler_Top|I_vin_clk   Scaler_Top|I_vout_clk  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Scaler_Top|I_sysclk    Scaler_Top|I_vin_clk   |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Scaler_Top|I_sysclk    Scaler_Top|I_sysclk    |  4.040       -0.713  |  No paths    -      |  No paths    -      |  No paths    -    
Scaler_Top|I_sysclk    Scaler_Top|I_vout_clk  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Scaler_Top|I_vout_clk  Scaler_Top|I_sysclk    |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Scaler_Top|I_vout_clk  Scaler_Top|I_vout_clk  |  4.214       -0.744  |  No paths    -      |  No paths    -      |  No paths    -    
=====================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Scaler_Top|I_sysclk
====================================



Starting Points with Worst Slack
********************************

                                                                                                  Starting                                                          Arrival           
Instance                                                                                          Reference               Type      Pin     Net                     Time        Slack 
                                                                                                  Clock                                                                               
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[0]                                 Scaler_Top|I_sysclk     DFFC      Q       state[0]                0.243       -0.713
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[1]                                 Scaler_Top|I_sysclk     DFFC      Q       state[1]                0.243       -0.673
scaler_wrapper_inst.scaler_core_inst.vin_hsize_sysclk[0]                                          Scaler_Top|I_sysclk     DFFCE     Q       vin_hsize_sysclk[0]     0.243       -0.261
scaler_wrapper_inst.scaler_core_inst.hor_calc_wrapper_inst.hor_calcdata_gen_inst.hor_wrdot[0]     Scaler_Top|I_sysclk     DFFCE     Q       hor_wrdot[0]            0.243       -0.240
scaler_wrapper_inst.scaler_core_inst.vin_hsize_sysclk[1]                                          Scaler_Top|I_sysclk     DFFCE     Q       vin_hsize_sysclk[1]     0.243       -0.226
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_coord_trans_inst.ver_kyacc[17]     Scaler_Top|I_sysclk     DFFCE     Q       ver_objline[1]          0.243       -0.212
scaler_wrapper_inst.scaler_core_inst.hor_calc_wrapper_inst.hor_calcdata_gen_inst.hor_wrdot[1]     Scaler_Top|I_sysclk     DFFCE     Q       hor_wrdot[1]            0.243       -0.205
scaler_wrapper_inst.scaler_core_inst.vin_hsize_sysclk[2]                                          Scaler_Top|I_sysclk     DFFCE     Q       vin_hsize_sysclk[2]     0.243       -0.191
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_coord_trans_inst.ver_kyacc[16]     Scaler_Top|I_sysclk     DFFCE     Q       ver_objline[0]          0.243       -0.186
scaler_wrapper_inst.scaler_core_inst.hor_calc_wrapper_inst.hor_coef_gen_inst.hcalc_coef_1[16]     Scaler_Top|I_sysclk     DFFCE     Q       hcalc_coef[16]          0.243       -0.180
======================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                   Starting                                                     Required           
Instance                                                                                           Reference               Type      Pin     Net                Time         Slack 
                                                                                                   Clock                                                                           
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[4]                               Scaler_Top|I_sysclk     DFFC      D       denopcnt_s[4]      3.979        -0.713
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[3]                               Scaler_Top|I_sysclk     DFFC      D       denopcnt_s[3]      3.979        -0.678
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[2]                               Scaler_Top|I_sysclk     DFFC      D       denopcnt_s[2]      3.979        -0.643
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.iram_rden[0]      Scaler_Top|I_sysclk     DFFC      D       iram_rden_2[0]     3.979        -0.261
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.iram_rden[1]      Scaler_Top|I_sysclk     DFFC      D       iram_rden_3[1]     3.979        -0.261
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.iram_rden[2]      Scaler_Top|I_sysclk     DFFC      D       iram_rden_4[2]     3.979        -0.261
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.iram_rden[3]      Scaler_Top|I_sysclk     DFFC      D       iram_rden_5[3]     3.979        -0.261
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_rdline[0]     Scaler_Top|I_sysclk     DFFCE     CE      ver_rdlinee        3.979        -0.212
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_rdline[1]     Scaler_Top|I_sysclk     DFFCE     CE      ver_rdlinee        3.979        -0.212
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_rdline[2]     Scaler_Top|I_sysclk     DFFCE     CE      ver_rdlinee        3.979        -0.212
===================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.040
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.979

    - Propagation time:                      4.692
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.713

    Number of logic level(s):                6
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[0] / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[4] / D
    The start point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK
    The end   point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[0]                  DFFC     Q        Out     0.243     0.243 r     -         
state[0]                                                                           Net      -        -       0.657     -           23        
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     I0       In      -         0.900 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     F        Out     0.549     1.449 r     -         
denopcnt                                                                           Net      -        -       0.535     -           5         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[1]     LUT2     I0       In      -         1.984 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[1]     LUT2     F        Out     0.549     2.533 r     -         
denopcnt_cry_0_RNO[1]                                                              Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[1]         ALU      I0       In      -         3.068 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[1]         ALU      COUT     Out     0.549     3.617 r     -         
denopcnt_cry[1]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[2]         ALU      CIN      In      -         3.617 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[2]         ALU      COUT     Out     0.035     3.652 r     -         
denopcnt_cry[2]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      CIN      In      -         3.652 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      COUT     Out     0.035     3.687 r     -         
denopcnt_cry[3]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_s_0[4]           ALU      CIN      In      -         3.687 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_s_0[4]           ALU      SUM      Out     0.470     4.157 f     -         
denopcnt_s[4]                                                                      Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[4]               DFFC     D        In      -         4.692 f     -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 4.753 is 2.491(52.4%) logic and 2.262(47.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.040
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.979

    - Propagation time:                      4.657
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.678

    Number of logic level(s):                5
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[0] / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[4] / D
    The start point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK
    The end   point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[0]                  DFFC     Q        Out     0.243     0.243 r     -         
state[0]                                                                           Net      -        -       0.657     -           23        
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     I0       In      -         0.900 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     F        Out     0.549     1.449 r     -         
denopcnt                                                                           Net      -        -       0.535     -           5         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[2]     LUT2     I0       In      -         1.984 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[2]     LUT2     F        Out     0.549     2.533 r     -         
denopcnt_cry_0_RNO[2]                                                              Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[2]         ALU      I0       In      -         3.068 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[2]         ALU      COUT     Out     0.549     3.617 r     -         
denopcnt_cry[2]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      CIN      In      -         3.617 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      COUT     Out     0.035     3.652 r     -         
denopcnt_cry[3]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_s_0[4]           ALU      CIN      In      -         3.652 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_s_0[4]           ALU      SUM      Out     0.470     4.122 f     -         
denopcnt_s[4]                                                                      Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[4]               DFFC     D        In      -         4.657 f     -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 4.718 is 2.456(52.1%) logic and 2.262(47.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.040
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.979

    - Propagation time:                      4.657
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.678

    Number of logic level(s):                5
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[0] / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[3] / D
    The start point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK
    The end   point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[0]                  DFFC     Q        Out     0.243     0.243 r     -         
state[0]                                                                           Net      -        -       0.657     -           23        
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     I0       In      -         0.900 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     F        Out     0.549     1.449 r     -         
denopcnt                                                                           Net      -        -       0.535     -           5         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[1]     LUT2     I0       In      -         1.984 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[1]     LUT2     F        Out     0.549     2.533 r     -         
denopcnt_cry_0_RNO[1]                                                              Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[1]         ALU      I0       In      -         3.068 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[1]         ALU      COUT     Out     0.549     3.617 r     -         
denopcnt_cry[1]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[2]         ALU      CIN      In      -         3.617 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[2]         ALU      COUT     Out     0.035     3.652 r     -         
denopcnt_cry[2]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      CIN      In      -         3.652 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      SUM      Out     0.470     4.122 f     -         
denopcnt_s[3]                                                                      Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[3]               DFFC     D        In      -         4.657 f     -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 4.718 is 2.456(52.1%) logic and 2.262(47.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.040
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.979

    - Propagation time:                      4.652
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.673

    Number of logic level(s):                6
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[1] / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[4] / D
    The start point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK
    The end   point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[1]                  DFFC     Q        Out     0.243     0.243 r     -         
state[1]                                                                           Net      -        -       0.596     -           11        
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     I1       In      -         0.839 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     F        Out     0.570     1.409 r     -         
denopcnt                                                                           Net      -        -       0.535     -           5         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[1]     LUT2     I0       In      -         1.944 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[1]     LUT2     F        Out     0.549     2.493 r     -         
denopcnt_cry_0_RNO[1]                                                              Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[1]         ALU      I0       In      -         3.028 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[1]         ALU      COUT     Out     0.549     3.577 r     -         
denopcnt_cry[1]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[2]         ALU      CIN      In      -         3.577 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[2]         ALU      COUT     Out     0.035     3.612 r     -         
denopcnt_cry[2]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      CIN      In      -         3.612 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      COUT     Out     0.035     3.647 r     -         
denopcnt_cry[3]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_s_0[4]           ALU      CIN      In      -         3.647 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_s_0[4]           ALU      SUM      Out     0.470     4.117 f     -         
denopcnt_s[4]                                                                      Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[4]               DFFC     D        In      -         4.652 f     -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 4.713 is 2.512(53.3%) logic and 2.201(46.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.040
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         3.979

    - Propagation time:                      4.622
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.643

    Number of logic level(s):                4
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[0] / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[4] / D
    The start point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK
    The end   point is clocked by            Scaler_Top|I_sysclk [rising] (rise=0.000 fall=2.020 period=4.040) on pin CLK

Instance / Net                                                                              Pin      Pin               Arrival     No. of    
Name                                                                               Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state[0]                  DFFC     Q        Out     0.243     0.243 r     -         
state[0]                                                                           Net      -        -       0.657     -           23        
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     I0       In      -         0.900 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.state_s2_0_a2             LUT2     F        Out     0.549     1.449 r     -         
denopcnt                                                                           Net      -        -       0.535     -           5         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[3]     LUT2     I0       In      -         1.984 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0_RNO[3]     LUT2     F        Out     0.549     2.533 r     -         
denopcnt_cry_0_RNO[3]                                                              Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      I0       In      -         3.068 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_cry_0[3]         ALU      COUT     Out     0.549     3.617 r     -         
denopcnt_cry[3]                                                                    Net      -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_s_0[4]           ALU      CIN      In      -         3.617 r     -         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt_s_0[4]           ALU      SUM      Out     0.470     4.087 f     -         
denopcnt_s[4]                                                                      Net      -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.hcalc_ctrl_fsm_inst.denopcnt[4]               DFFC     D        In      -         4.622 f     -         
=============================================================================================================================================
Total path delay (propagation time + setup) of 4.683 is 2.421(51.7%) logic and 2.262(48.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: Scaler_Top|I_vin_clk
====================================



Starting Points with Worst Slack
********************************

                                                                                                                         Starting                                                           Arrival           
Instance                                                                                                                 Reference                Type      Pin     Net                     Time        Slack 
                                                                                                                         Clock                                                                                
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\][8]     Scaler_Top|I_vin_clk     DFF       Q       vinvs_inclk_dn          0.243       -0.744
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.vinvs_inclk_d1                          Scaler_Top|I_vin_clk     DFFC      Q       vinvs_inclk_d1          0.243       -0.723
scaler_wrapper_inst.mode_control_inst.vin_hsize_inclk[7]                                                                 Scaler_Top|I_vin_clk     DFFCE     Q       vin_hsize_inclk[7]      0.243       -0.425
scaler_wrapper_inst.mode_control_inst.vin_hsize_inclk[8]                                                                 Scaler_Top|I_vin_clk     DFFCE     Q       vin_hsize_inclk[8]      0.243       -0.390
scaler_wrapper_inst.mode_control_inst.vin_hsize_inclk[6]                                                                 Scaler_Top|I_vin_clk     DFFCE     Q       vin_hsize_inclk[6]      0.243       -0.378
scaler_wrapper_inst.mode_control_inst.vin_hsize_inclk[9]                                                                 Scaler_Top|I_vin_clk     DFFCE     Q       vin_hsize_inclk[9]      0.243       -0.355
scaler_wrapper_inst.mode_control_inst.vin_hsize_inclk[10]                                                                Scaler_Top|I_vin_clk     DFFCE     Q       vin_hsize_inclk[10]     0.243       -0.320
scaler_wrapper_inst.mode_control_inst.vin_hsize_inclk[11]                                                                Scaler_Top|I_vin_clk     DFFCE     Q       vin_hsize_inclk[11]     0.243       0.150 
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.iram_wraddr[0]                          Scaler_Top|I_vin_clk     DFFCE     Q       iram_wraddr[0]          0.243       0.340 
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.vinde_inclk_d1                          Scaler_Top|I_vin_clk     DFFC      Q       iram_wraddr             0.243       0.361 
==============================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                    Starting                                                        Required           
Instance                                                                                            Reference                Type      Pin     Net                  Time         Slack 
                                                                                                    Clock                                                                              
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[11]     Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[11]     4.153        -0.744
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[10]     Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[10]     4.153        -0.709
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[9]      Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[9]      4.153        -0.674
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[8]      Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[8]      4.153        -0.639
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[7]      Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[7]      4.153        -0.604
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[6]      Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[6]      4.153        -0.569
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[5]      Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[5]      4.153        -0.534
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[4]      Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[4]      4.153        -0.499
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[3]      Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[3]      4.153        -0.464
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[2]      Scaler_Top|I_vin_clk     DFFCE     D       ver_wrline_s[2]      4.153        -0.429
=======================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.897
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.744

    Number of logic level(s):                13
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\][8] / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[11] / D
    The start point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                                                                             Pin      Pin               Arrival     No. of    
Name                                                                                                                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\][8]             DFF       Q        Out     0.243     0.243 r     -         
vinvs_inclk_dn                                                                                                                   Net       -        -       0.535     -           8         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      I1       In      -         0.778 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      F        Out     0.570     1.348 r     -         
ver_wrline                                                                                                                       Net       -        -       0.596     -           12        
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[1]                         LUT2      I0       In      -         1.944 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[1]                         LUT2      F        Out     0.549     2.493 r     -         
ver_wrline_cry_0_RNO[1]                                                                                                          Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[1]                             ALU       I0       In      -         3.028 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[1]                             ALU       COUT     Out     0.549     3.577 r     -         
ver_wrline_cry[1]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       CIN      In      -         3.577 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       COUT     Out     0.035     3.612 r     -         
ver_wrline_cry[2]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       CIN      In      -         3.612 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       COUT     Out     0.035     3.647 r     -         
ver_wrline_cry[3]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       CIN      In      -         3.647 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       COUT     Out     0.035     3.682 r     -         
ver_wrline_cry[4]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       CIN      In      -         3.682 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       COUT     Out     0.035     3.717 r     -         
ver_wrline_cry[5]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       CIN      In      -         3.717 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       COUT     Out     0.035     3.752 r     -         
ver_wrline_cry[6]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       CIN      In      -         3.752 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       COUT     Out     0.035     3.787 r     -         
ver_wrline_cry[7]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       CIN      In      -         3.787 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       COUT     Out     0.035     3.822 r     -         
ver_wrline_cry[8]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       CIN      In      -         3.822 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       COUT     Out     0.035     3.857 r     -         
ver_wrline_cry[9]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       CIN      In      -         3.857 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       COUT     Out     0.035     3.892 r     -         
ver_wrline_cry[10]                                                                                                               Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_s_0[11]                              ALU       CIN      In      -         3.892 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_s_0[11]                              ALU       SUM      Out     0.470     4.362 f     -         
ver_wrline_s[11]                                                                                                                 Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[11]                                  DFFCE     D        In      -         4.897 f     -         
============================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.958 is 2.757(55.6%) logic and 2.201(44.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.876
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.723

    Number of logic level(s):                13
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.vinvs_inclk_d1 / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[11] / D
    The start point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                                                                             Pin      Pin               Arrival     No. of    
Name                                                                                                                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.vinvs_inclk_d1                                  DFFC      Q        Out     0.243     0.243 r     -         
vinvs_inclk_d1                                                                                                                   Net       -        -       0.535     -           9         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      I0       In      -         0.778 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      F        Out     0.549     1.327 r     -         
ver_wrline                                                                                                                       Net       -        -       0.596     -           12        
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[1]                         LUT2      I0       In      -         1.923 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[1]                         LUT2      F        Out     0.549     2.472 r     -         
ver_wrline_cry_0_RNO[1]                                                                                                          Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[1]                             ALU       I0       In      -         3.007 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[1]                             ALU       COUT     Out     0.549     3.556 r     -         
ver_wrline_cry[1]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       CIN      In      -         3.556 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       COUT     Out     0.035     3.591 r     -         
ver_wrline_cry[2]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       CIN      In      -         3.591 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       COUT     Out     0.035     3.626 r     -         
ver_wrline_cry[3]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       CIN      In      -         3.626 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       COUT     Out     0.035     3.661 r     -         
ver_wrline_cry[4]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       CIN      In      -         3.661 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       COUT     Out     0.035     3.696 r     -         
ver_wrline_cry[5]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       CIN      In      -         3.696 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       COUT     Out     0.035     3.731 r     -         
ver_wrline_cry[6]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       CIN      In      -         3.731 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       COUT     Out     0.035     3.766 r     -         
ver_wrline_cry[7]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       CIN      In      -         3.766 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       COUT     Out     0.035     3.801 r     -         
ver_wrline_cry[8]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       CIN      In      -         3.801 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       COUT     Out     0.035     3.836 r     -         
ver_wrline_cry[9]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       CIN      In      -         3.836 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       COUT     Out     0.035     3.871 r     -         
ver_wrline_cry[10]                                                                                                               Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_s_0[11]                              ALU       CIN      In      -         3.871 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_s_0[11]                              ALU       SUM      Out     0.470     4.341 f     -         
ver_wrline_s[11]                                                                                                                 Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[11]                                  DFFCE     D        In      -         4.876 f     -         
============================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.937 is 2.736(55.4%) logic and 2.201(44.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.862
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.709

    Number of logic level(s):                12
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\][8] / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[11] / D
    The start point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                                                                             Pin      Pin               Arrival     No. of    
Name                                                                                                                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\][8]             DFF       Q        Out     0.243     0.243 r     -         
vinvs_inclk_dn                                                                                                                   Net       -        -       0.535     -           8         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      I1       In      -         0.778 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      F        Out     0.570     1.348 r     -         
ver_wrline                                                                                                                       Net       -        -       0.596     -           12        
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[2]                         LUT2      I0       In      -         1.944 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[2]                         LUT2      F        Out     0.549     2.493 r     -         
ver_wrline_cry_0_RNO[2]                                                                                                          Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       I0       In      -         3.028 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       COUT     Out     0.549     3.577 r     -         
ver_wrline_cry[2]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       CIN      In      -         3.577 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       COUT     Out     0.035     3.612 r     -         
ver_wrline_cry[3]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       CIN      In      -         3.612 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       COUT     Out     0.035     3.647 r     -         
ver_wrline_cry[4]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       CIN      In      -         3.647 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       COUT     Out     0.035     3.682 r     -         
ver_wrline_cry[5]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       CIN      In      -         3.682 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       COUT     Out     0.035     3.717 r     -         
ver_wrline_cry[6]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       CIN      In      -         3.717 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       COUT     Out     0.035     3.752 r     -         
ver_wrline_cry[7]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       CIN      In      -         3.752 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       COUT     Out     0.035     3.787 r     -         
ver_wrline_cry[8]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       CIN      In      -         3.787 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       COUT     Out     0.035     3.822 r     -         
ver_wrline_cry[9]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       CIN      In      -         3.822 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       COUT     Out     0.035     3.857 r     -         
ver_wrline_cry[10]                                                                                                               Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_s_0[11]                              ALU       CIN      In      -         3.857 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_s_0[11]                              ALU       SUM      Out     0.470     4.327 f     -         
ver_wrline_s[11]                                                                                                                 Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[11]                                  DFFCE     D        In      -         4.862 f     -         
============================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.923 is 2.722(55.3%) logic and 2.201(44.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.862
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.709

    Number of logic level(s):                12
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\][8] / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[10] / D
    The start point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                                                                             Pin      Pin               Arrival     No. of    
Name                                                                                                                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\][8]             DFF       Q        Out     0.243     0.243 r     -         
vinvs_inclk_dn                                                                                                                   Net       -        -       0.535     -           8         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      I1       In      -         0.778 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      F        Out     0.570     1.348 r     -         
ver_wrline                                                                                                                       Net       -        -       0.596     -           12        
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[1]                         LUT2      I0       In      -         1.944 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[1]                         LUT2      F        Out     0.549     2.493 r     -         
ver_wrline_cry_0_RNO[1]                                                                                                          Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[1]                             ALU       I0       In      -         3.028 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[1]                             ALU       COUT     Out     0.549     3.577 r     -         
ver_wrline_cry[1]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       CIN      In      -         3.577 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       COUT     Out     0.035     3.612 r     -         
ver_wrline_cry[2]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       CIN      In      -         3.612 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       COUT     Out     0.035     3.647 r     -         
ver_wrline_cry[3]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       CIN      In      -         3.647 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       COUT     Out     0.035     3.682 r     -         
ver_wrline_cry[4]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       CIN      In      -         3.682 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       COUT     Out     0.035     3.717 r     -         
ver_wrline_cry[5]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       CIN      In      -         3.717 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       COUT     Out     0.035     3.752 r     -         
ver_wrline_cry[6]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       CIN      In      -         3.752 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       COUT     Out     0.035     3.787 r     -         
ver_wrline_cry[7]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       CIN      In      -         3.787 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       COUT     Out     0.035     3.822 r     -         
ver_wrline_cry[8]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       CIN      In      -         3.822 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       COUT     Out     0.035     3.857 r     -         
ver_wrline_cry[9]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       CIN      In      -         3.857 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       SUM      Out     0.470     4.327 f     -         
ver_wrline_s[10]                                                                                                                 Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[10]                                  DFFCE     D        In      -         4.862 f     -         
============================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.923 is 2.722(55.3%) logic and 2.201(44.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.841
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.688

    Number of logic level(s):                12
    Starting point:                          scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.vinvs_inclk_d1 / Q
    Ending point:                            scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[11] / D
    The start point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vin_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                                                                             Pin      Pin               Arrival     No. of    
Name                                                                                                                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.vinvs_inclk_d1                                  DFFC      Q        Out     0.243     0.243 r     -         
vinvs_inclk_d1                                                                                                                   Net       -        -       0.535     -           9         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      I0       In      -         0.778 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.srl_16_inst0.loop\[0\]\.q_r\[0\]_RNIU6ID[8]     LUT2      F        Out     0.549     1.327 r     -         
ver_wrline                                                                                                                       Net       -        -       0.596     -           12        
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[2]                         LUT2      I0       In      -         1.923 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0_RNO[2]                         LUT2      F        Out     0.549     2.472 r     -         
ver_wrline_cry_0_RNO[2]                                                                                                          Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       I0       In      -         3.007 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[2]                             ALU       COUT     Out     0.549     3.556 r     -         
ver_wrline_cry[2]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       CIN      In      -         3.556 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[3]                             ALU       COUT     Out     0.035     3.591 r     -         
ver_wrline_cry[3]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       CIN      In      -         3.591 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[4]                             ALU       COUT     Out     0.035     3.626 r     -         
ver_wrline_cry[4]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       CIN      In      -         3.626 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[5]                             ALU       COUT     Out     0.035     3.661 r     -         
ver_wrline_cry[5]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       CIN      In      -         3.661 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[6]                             ALU       COUT     Out     0.035     3.696 r     -         
ver_wrline_cry[6]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       CIN      In      -         3.696 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[7]                             ALU       COUT     Out     0.035     3.731 r     -         
ver_wrline_cry[7]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       CIN      In      -         3.731 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[8]                             ALU       COUT     Out     0.035     3.766 r     -         
ver_wrline_cry[8]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       CIN      In      -         3.766 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[9]                             ALU       COUT     Out     0.035     3.801 r     -         
ver_wrline_cry[9]                                                                                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       CIN      In      -         3.801 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_cry_0[10]                            ALU       COUT     Out     0.035     3.836 r     -         
ver_wrline_cry[10]                                                                                                               Net       -        -       0.000     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_s_0[11]                              ALU       CIN      In      -         3.836 r     -         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline_s_0[11]                              ALU       SUM      Out     0.470     4.306 f     -         
ver_wrline_s[11]                                                                                                                 Net       -        -       0.535     -           1         
scaler_wrapper_inst.scaler_core_inst.ver_calc_wrapper_inst.ver_calcdata_gen_inst.ver_wrline[11]                                  DFFCE     D        In      -         4.841 f     -         
============================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.902 is 2.701(55.1%) logic and 2.201(44.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: Scaler_Top|I_vout_clk
====================================



Starting Points with Worst Slack
********************************

                                                                Starting                                                              Arrival           
Instance                                                        Reference                 Type      Pin     Net                       Time        Slack 
                                                                Clock                                                                                   
--------------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1           Scaler_Top|I_vout_clk     DFF       Q       vinvs_outclk_d1           0.243       -0.744
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d2           Scaler_Top|I_vout_clk     DFF       Q       O_vout_vs                 0.243       -0.723
scaler_wrapper_inst.mode_control_inst.vout_hsize_outclk[6]      Scaler_Top|I_vout_clk     DFFCE     Q       vout_decnt_en_0           0.243       -0.460
scaler_wrapper_inst.mode_control_inst.vout_hsize_outclk[7]      Scaler_Top|I_vout_clk     DFFCE     Q       vout_hsize_outclk[7]      0.243       -0.425
scaler_wrapper_inst.mode_control_inst.vout_hsize_outclk[5]      Scaler_Top|I_vout_clk     DFFCE     Q       vout_hsize_outclk[5]      0.243       -0.413
scaler_wrapper_inst.mode_control_inst.vout_hsize_outclk[8]      Scaler_Top|I_vout_clk     DFFCE     Q       vout_hsize_outclk[8]      0.243       -0.390
scaler_wrapper_inst.mode_control_inst.vout_hsize_outclk[9]      Scaler_Top|I_vout_clk     DFFCE     Q       vout_hsize_outclk[9]      0.243       -0.355
scaler_wrapper_inst.mode_control_inst.vout_hsize_outclk[10]     Scaler_Top|I_vout_clk     DFFCE     Q       vout_hsize_outclk[10]     0.243       -0.320
scaler_wrapper_inst.mode_control_inst.vout_hsize_outclk[11]     Scaler_Top|I_vout_clk     DFFCE     Q       vout_hsize_outclk[11]     0.243       0.150 
scaler_wrapper_inst.mode_control_inst.vout_linecnt[1]           Scaler_Top|I_vout_clk     DFFCE     Q       vout_linecnt[1]           0.243       0.401 
========================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                           Starting                                                           Required           
Instance                                                   Reference                 Type      Pin     Net                    Time         Slack 
                                                           Clock                                                                                 
-------------------------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.mode_control_inst.vout_linecnt[11]     Scaler_Top|I_vout_clk     DFFCE     D       vout_linecnt_s[11]     4.153        -0.744
scaler_wrapper_inst.mode_control_inst.vout_linecnt[10]     Scaler_Top|I_vout_clk     DFFCE     D       vout_linecnt_s[10]     4.153        -0.709
scaler_wrapper_inst.mode_control_inst.vout_linecnt[9]      Scaler_Top|I_vout_clk     DFFCE     D       vout_linecnt_s[9]      4.153        -0.674
scaler_wrapper_inst.mode_control_inst.vout_linecnt[8]      Scaler_Top|I_vout_clk     DFFCE     D       vout_linecnt_s[8]      4.153        -0.639
scaler_wrapper_inst.mode_control_inst.vout_linecnt[7]      Scaler_Top|I_vout_clk     DFFCE     D       vout_linecnt_s[7]      4.153        -0.604
scaler_wrapper_inst.mode_control_inst.vout_linecnt[6]      Scaler_Top|I_vout_clk     DFFCE     D       vout_linecnt_s[6]      4.153        -0.569
scaler_wrapper_inst.mode_control_inst.vout_linecnt[5]      Scaler_Top|I_vout_clk     DFFCE     D       vout_linecnt_s[5]      4.153        -0.534
scaler_wrapper_inst.mode_control_inst.vout_linecnt[4]      Scaler_Top|I_vout_clk     DFFCE     D       vout_linecnt_s[4]      4.153        -0.499
scaler_wrapper_inst.mode_control_inst.vout_linecnt[3]      Scaler_Top|I_vout_clk     DFFCE     D       vout_linecnt_s[3]      4.153        -0.464
scaler_wrapper_inst.mode_control_inst.vout_decnt[0]        Scaler_Top|I_vout_clk     DFFC      D       vout_decnt_lm[0]       4.153        -0.460
=================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.897
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.744

    Number of logic level(s):                13
    Starting point:                          scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1 / Q
    Ending point:                            scaler_wrapper_inst.mode_control_inst.vout_linecnt[11] / D
    The start point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                                Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1               DFF       Q        Out     0.243     0.243 r     -         
vinvs_outclk_d1                                                     Net       -        -       0.535     -           5         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      I1       In      -         0.778 r     -         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      F        Out     0.570     1.348 r     -         
vout_linecnt                                                        Net       -        -       0.596     -           12        
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[1]     LUT2      I0       In      -         1.944 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[1]     LUT2      F        Out     0.549     2.493 r     -         
vout_linecnt_cry_0_RNO[1]                                           Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[1]         ALU       I0       In      -         3.028 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[1]         ALU       COUT     Out     0.549     3.577 r     -         
vout_linecnt_cry[1]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       CIN      In      -         3.577 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       COUT     Out     0.035     3.612 r     -         
vout_linecnt_cry[2]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       CIN      In      -         3.612 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       COUT     Out     0.035     3.647 r     -         
vout_linecnt_cry[3]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       CIN      In      -         3.647 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       COUT     Out     0.035     3.682 r     -         
vout_linecnt_cry[4]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       CIN      In      -         3.682 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       COUT     Out     0.035     3.717 r     -         
vout_linecnt_cry[5]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       CIN      In      -         3.717 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       COUT     Out     0.035     3.752 r     -         
vout_linecnt_cry[6]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       CIN      In      -         3.752 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       COUT     Out     0.035     3.787 r     -         
vout_linecnt_cry[7]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       CIN      In      -         3.787 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       COUT     Out     0.035     3.822 r     -         
vout_linecnt_cry[8]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       CIN      In      -         3.822 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       COUT     Out     0.035     3.857 r     -         
vout_linecnt_cry[9]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       CIN      In      -         3.857 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       COUT     Out     0.035     3.892 r     -         
vout_linecnt_cry[10]                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_s_0[11]          ALU       CIN      In      -         3.892 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_s_0[11]          ALU       SUM      Out     0.470     4.362 f     -         
vout_linecnt_s[11]                                                  Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt[11]              DFFCE     D        In      -         4.897 f     -         
===============================================================================================================================
Total path delay (propagation time + setup) of 4.958 is 2.757(55.6%) logic and 2.201(44.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.876
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.723

    Number of logic level(s):                13
    Starting point:                          scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d2 / Q
    Ending point:                            scaler_wrapper_inst.mode_control_inst.vout_linecnt[11] / D
    The start point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                                Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d2               DFF       Q        Out     0.243     0.243 r     -         
O_vout_vs                                                           Net       -        -       0.535     -           5         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      I0       In      -         0.778 r     -         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      F        Out     0.549     1.327 r     -         
vout_linecnt                                                        Net       -        -       0.596     -           12        
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[1]     LUT2      I0       In      -         1.923 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[1]     LUT2      F        Out     0.549     2.472 r     -         
vout_linecnt_cry_0_RNO[1]                                           Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[1]         ALU       I0       In      -         3.007 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[1]         ALU       COUT     Out     0.549     3.556 r     -         
vout_linecnt_cry[1]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       CIN      In      -         3.556 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       COUT     Out     0.035     3.591 r     -         
vout_linecnt_cry[2]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       CIN      In      -         3.591 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       COUT     Out     0.035     3.626 r     -         
vout_linecnt_cry[3]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       CIN      In      -         3.626 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       COUT     Out     0.035     3.661 r     -         
vout_linecnt_cry[4]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       CIN      In      -         3.661 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       COUT     Out     0.035     3.696 r     -         
vout_linecnt_cry[5]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       CIN      In      -         3.696 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       COUT     Out     0.035     3.731 r     -         
vout_linecnt_cry[6]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       CIN      In      -         3.731 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       COUT     Out     0.035     3.766 r     -         
vout_linecnt_cry[7]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       CIN      In      -         3.766 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       COUT     Out     0.035     3.801 r     -         
vout_linecnt_cry[8]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       CIN      In      -         3.801 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       COUT     Out     0.035     3.836 r     -         
vout_linecnt_cry[9]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       CIN      In      -         3.836 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       COUT     Out     0.035     3.871 r     -         
vout_linecnt_cry[10]                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_s_0[11]          ALU       CIN      In      -         3.871 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_s_0[11]          ALU       SUM      Out     0.470     4.341 f     -         
vout_linecnt_s[11]                                                  Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt[11]              DFFCE     D        In      -         4.876 f     -         
===============================================================================================================================
Total path delay (propagation time + setup) of 4.937 is 2.736(55.4%) logic and 2.201(44.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.862
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.709

    Number of logic level(s):                12
    Starting point:                          scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1 / Q
    Ending point:                            scaler_wrapper_inst.mode_control_inst.vout_linecnt[11] / D
    The start point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                                Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1               DFF       Q        Out     0.243     0.243 r     -         
vinvs_outclk_d1                                                     Net       -        -       0.535     -           5         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      I1       In      -         0.778 r     -         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      F        Out     0.570     1.348 r     -         
vout_linecnt                                                        Net       -        -       0.596     -           12        
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[2]     LUT2      I0       In      -         1.944 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[2]     LUT2      F        Out     0.549     2.493 r     -         
vout_linecnt_cry_0_RNO[2]                                           Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       I0       In      -         3.028 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       COUT     Out     0.549     3.577 r     -         
vout_linecnt_cry[2]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       CIN      In      -         3.577 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       COUT     Out     0.035     3.612 r     -         
vout_linecnt_cry[3]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       CIN      In      -         3.612 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       COUT     Out     0.035     3.647 r     -         
vout_linecnt_cry[4]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       CIN      In      -         3.647 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       COUT     Out     0.035     3.682 r     -         
vout_linecnt_cry[5]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       CIN      In      -         3.682 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       COUT     Out     0.035     3.717 r     -         
vout_linecnt_cry[6]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       CIN      In      -         3.717 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       COUT     Out     0.035     3.752 r     -         
vout_linecnt_cry[7]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       CIN      In      -         3.752 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       COUT     Out     0.035     3.787 r     -         
vout_linecnt_cry[8]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       CIN      In      -         3.787 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       COUT     Out     0.035     3.822 r     -         
vout_linecnt_cry[9]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       CIN      In      -         3.822 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       COUT     Out     0.035     3.857 r     -         
vout_linecnt_cry[10]                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_s_0[11]          ALU       CIN      In      -         3.857 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_s_0[11]          ALU       SUM      Out     0.470     4.327 f     -         
vout_linecnt_s[11]                                                  Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt[11]              DFFCE     D        In      -         4.862 f     -         
===============================================================================================================================
Total path delay (propagation time + setup) of 4.923 is 2.722(55.3%) logic and 2.201(44.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.862
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.709

    Number of logic level(s):                12
    Starting point:                          scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1 / Q
    Ending point:                            scaler_wrapper_inst.mode_control_inst.vout_linecnt[10] / D
    The start point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                                Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1               DFF       Q        Out     0.243     0.243 r     -         
vinvs_outclk_d1                                                     Net       -        -       0.535     -           5         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      I1       In      -         0.778 r     -         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      F        Out     0.570     1.348 r     -         
vout_linecnt                                                        Net       -        -       0.596     -           12        
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[1]     LUT2      I0       In      -         1.944 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[1]     LUT2      F        Out     0.549     2.493 r     -         
vout_linecnt_cry_0_RNO[1]                                           Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[1]         ALU       I0       In      -         3.028 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[1]         ALU       COUT     Out     0.549     3.577 r     -         
vout_linecnt_cry[1]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       CIN      In      -         3.577 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       COUT     Out     0.035     3.612 r     -         
vout_linecnt_cry[2]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       CIN      In      -         3.612 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       COUT     Out     0.035     3.647 r     -         
vout_linecnt_cry[3]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       CIN      In      -         3.647 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       COUT     Out     0.035     3.682 r     -         
vout_linecnt_cry[4]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       CIN      In      -         3.682 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       COUT     Out     0.035     3.717 r     -         
vout_linecnt_cry[5]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       CIN      In      -         3.717 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       COUT     Out     0.035     3.752 r     -         
vout_linecnt_cry[6]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       CIN      In      -         3.752 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       COUT     Out     0.035     3.787 r     -         
vout_linecnt_cry[7]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       CIN      In      -         3.787 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       COUT     Out     0.035     3.822 r     -         
vout_linecnt_cry[8]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       CIN      In      -         3.822 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       COUT     Out     0.035     3.857 r     -         
vout_linecnt_cry[9]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       CIN      In      -         3.857 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       SUM      Out     0.470     4.327 f     -         
vout_linecnt_s[10]                                                  Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt[10]              DFFCE     D        In      -         4.862 f     -         
===============================================================================================================================
Total path delay (propagation time + setup) of 4.923 is 2.722(55.3%) logic and 2.201(44.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.214
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.153

    - Propagation time:                      4.841
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.688

    Number of logic level(s):                12
    Starting point:                          scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d2 / Q
    Ending point:                            scaler_wrapper_inst.mode_control_inst.vout_linecnt[11] / D
    The start point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK
    The end   point is clocked by            Scaler_Top|I_vout_clk [rising] (rise=0.000 fall=2.107 period=4.214) on pin CLK

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                                Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d2               DFF       Q        Out     0.243     0.243 r     -         
O_vout_vs                                                           Net       -        -       0.535     -           5         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      I0       In      -         0.778 r     -         
scaler_wrapper_inst.mode_control_inst.vinvs_outclk_d1_RNINE2V       LUT2      F        Out     0.549     1.327 r     -         
vout_linecnt                                                        Net       -        -       0.596     -           12        
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[2]     LUT2      I0       In      -         1.923 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0_RNO[2]     LUT2      F        Out     0.549     2.472 r     -         
vout_linecnt_cry_0_RNO[2]                                           Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       I0       In      -         3.007 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[2]         ALU       COUT     Out     0.549     3.556 r     -         
vout_linecnt_cry[2]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       CIN      In      -         3.556 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[3]         ALU       COUT     Out     0.035     3.591 r     -         
vout_linecnt_cry[3]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       CIN      In      -         3.591 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[4]         ALU       COUT     Out     0.035     3.626 r     -         
vout_linecnt_cry[4]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       CIN      In      -         3.626 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[5]         ALU       COUT     Out     0.035     3.661 r     -         
vout_linecnt_cry[5]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       CIN      In      -         3.661 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[6]         ALU       COUT     Out     0.035     3.696 r     -         
vout_linecnt_cry[6]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       CIN      In      -         3.696 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[7]         ALU       COUT     Out     0.035     3.731 r     -         
vout_linecnt_cry[7]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       CIN      In      -         3.731 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[8]         ALU       COUT     Out     0.035     3.766 r     -         
vout_linecnt_cry[8]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       CIN      In      -         3.766 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[9]         ALU       COUT     Out     0.035     3.801 r     -         
vout_linecnt_cry[9]                                                 Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       CIN      In      -         3.801 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_cry_0[10]        ALU       COUT     Out     0.035     3.836 r     -         
vout_linecnt_cry[10]                                                Net       -        -       0.000     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_s_0[11]          ALU       CIN      In      -         3.836 r     -         
scaler_wrapper_inst.mode_control_inst.vout_linecnt_s_0[11]          ALU       SUM      Out     0.470     4.306 f     -         
vout_linecnt_s[11]                                                  Net       -        -       0.535     -           1         
scaler_wrapper_inst.mode_control_inst.vout_linecnt[11]              DFFCE     D        In      -         4.841 f     -         
===============================================================================================================================
Total path delay (propagation time + setup) of 4.902 is 2.701(55.1%) logic and 2.201(44.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 241MB peak: 244MB)


Finished timing report (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 241MB peak: 244MB)

---------------------------------------
Resource Usage Report for Scaler_Top 

Mapping to part: gw2a_18pbga484-8
Cell usage:
ALU             608 uses
DFF             219 uses
DFFC            350 uses
DFFCE           834 uses
DFFP            5 uses
DFFR            3 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       24 uses
SDPB            18 uses
LUT2            140 uses
LUT3            459 uses
LUT4            349 uses
MULT18X18      12 uses

I/O Register bits:                  0
Register bits not including I/Os:   1411 of 15552 (9%)

RAM/ROM usage summary
Block Rams : 18 of 46 (39%)


Block Multipliers: 6 of 24 (25%)
Total load per clock:
   Scaler_Top|I_vin_clk: 126
   Scaler_Top|I_sysclk: 1172
   Scaler_Top|I_vout_clk: 161

@S |Mapping Summary:
Total  LUTs: 948 

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 85MB peak: 244MB)

Process took 0h:00m:16s realtime, 0h:00m:16s cputime
# Wed Jun 17 14:40:07 2020

###########################################################]
