
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: DESKTOP

Implementation : rev_1

# Written on Mon Dec  9 10:09:04 2019

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                    Requested     Requested     Clock        Clock                     Clock
Level     Clock                    Frequency     Period        Type         Group                     Load 
-----------------------------------------------------------------------------------------------------------
0 -       I2C_MASTER_Top|I_CLK     253.9 MHz     3.939         inferred     Autoconstr_clkgroup_0     127  
===========================================================================================================


Clock Load Summary
******************

                         Clock     Source          Clock Pin                Non-clock Pin     Non-clock Pin
Clock                    Load      Pin             Seq Example              Seq Example       Comb Example 
-----------------------------------------------------------------------------------------------------------
I2C_MASTER_Top|I_CLK     127       I_CLK(port)     u_i2c_master.rxack.C     -                 -            
===========================================================================================================
