# Wed Jun 17 17:41:46 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1620R, Built May 18 2020 06:06:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@A: MF827 |No constraint file specified.
@L: D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface_scck.rpt 
See clock summary report "D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface_scck.rpt"
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 140MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 151MB peak: 153MB)

Encoding state machine flag[2:0] (in view: work.\\\~ddr_memmem_sync\.DDR3_Memory_Interface_Top\ (verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine init_state[18:0] (in view: work.\\\~ddr_init\.DDR3_Memory_Interface_Top\ _Z3(verilog))
original code -> new code
   000000000000000000000000001 -> 0000000000000000001
   000000000000000000000000010 -> 0000000000000000010
   000000000000000000000000100 -> 0000000000000000100
   000000000000000100000000000 -> 0000000000000001000
   000000000000001000000000000 -> 0000000000000010000
   000000000000010000000000000 -> 0000000000000100000
   000000000000100000000000000 -> 0000000000001000000
   000000000001000000000000000 -> 0000000000010000000
   000000000010000000000000000 -> 0000000000100000000
   000000000100000000000000000 -> 0000000001000000000
   000000001000000000000000000 -> 0000000010000000000
   000000010000000000000000000 -> 0000000100000000000
   000000100000000000000000000 -> 0000001000000000000
   000001000000000000000000000 -> 0000010000000000000
   000010000000000000000000000 -> 0000100000000000000
   000100000000000000000000000 -> 0001000000000000000
   001000000000000000000000000 -> 0010000000000000000
   010000000000000000000000000 -> 0100000000000000000
   100000000000000000000000000 -> 1000000000000000000
Encoding state machine read_cal_state[12:0] (in view: work.\\\~ddr_init\.DDR3_Memory_Interface_Top\ _Z3(verilog))
original code -> new code
   0000000000001 -> 0000000000001
   0000000000010 -> 0000000000010
   0000000000100 -> 0000000000100
   0000000001000 -> 0000000001000
   0000000010000 -> 0000000010000
   0000000100000 -> 0000000100000
   0000001000000 -> 0000001000000
   0000010000000 -> 0000010000000
   0000100000000 -> 0000100000000
   0001000000000 -> 0001000000000
   0010000000000 -> 0010000000000
   0100000000000 -> 0100000000000
   1000000000000 -> 1000000000000
Encoding state machine wrlvl_state[9:0] (in view: work.\\\~ddr_init\.DDR3_Memory_Interface_Top\ _Z3(verilog))
original code -> new code
   0000000001 -> 0000000001
   0000000010 -> 0000000010
   0000000100 -> 0000000100
   0000001000 -> 0000001000
   0000010000 -> 0000010000
   0000100000 -> 0000100000
   0001000000 -> 0001000000
   0010000000 -> 0010000000
   0100000000 -> 0100000000
   1000000000 -> 1000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 239MB peak: 239MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB)

@N: MF578 |Incompatible asynchronous control logic preventing generated clock conversion.

Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 241MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 241MB peak: 242MB)



Clock Summary
******************

          Start                                                                                        Requested     Requested     Clock        Clock                     Clock
Level     Clock                                                                                        Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                                                                       150.0 MHz     6.667         system       system_clkgroup           0    
                                                                                                                                                                               
0 -       _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                            162.3 MHz     6.160         inferred     Autoconstr_clkgroup_0     2739 
                                                                                                                                                                               
0 -       _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                           150.0 MHz     6.667         inferred     Autoconstr_clkgroup_2     60   
                                                                                                                                                                               
0 -       DDR3_Memory_Interface_Top|clk                                                                302.5 MHz     3.306         inferred     Autoconstr_clkgroup_1     33   
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_7     9    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_4     9    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock      150.0 MHz     6.667         inferred     Autoconstr_clkgroup_8     8    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock      150.0 MHz     6.667         inferred     Autoconstr_clkgroup_5     8    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock       150.0 MHz     6.667         inferred     Autoconstr_clkgroup_6     1    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock       150.0 MHz     6.667         inferred     Autoconstr_clkgroup_3     1    
===============================================================================================================================================================================



Clock Load Summary
***********************

                                                                                             Clock     Source                                                                                                                               Clock Pin                                                                                                                                      Non-clock Pin                                                                                                                                  Non-clock Pin
Clock                                                                                        Load      Pin                                                                                                                                  Seq Example                                                                                                                                    Seq Example                                                                                                                                    Comb Example 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                                                       0         -                                                                                                                                    -                                                                                                                                              -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                            2739      genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv.CLKOUT(CLKDIV)                                                                               genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.read_cmd0.C                                                                                        genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem.PCLK     -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                           60        genblk1\.gw3mc_top.u_ddr_phy_top.u_dqcen.CLKOUT(DHCEN)                                                                               genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_ddr_phy_cmd_lane.u_ddr_phy_cmd_io.mcd_oserdes_gen\[15\]\.u_cmd_gen.FCLK                        -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
DDR3_Memory_Interface_Top|clk                                                                33        clk(port)                                                                                                                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.recalib_s[1:0].C                                                                      -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock     9         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW270(DQS)     genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.oserdes_gen\[5\]\.u_oser8_mem.TCLK     -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock     9         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW270(DQS)     genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.oserdes_gen\[5\]\.u_oser8_mem.TCLK     -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock      8         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSR90(DQS)      genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem.ICLK     -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock      8         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSR90(DQS)      genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem.ICLK     -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock       1         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW0(DQS)       genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.u_dqs_gen.TCLK                         -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock       1         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW0(DQS)       genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.u_dqs_gen.TCLK                         -                                                                                                                                              -            
=======================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

9 non-gated/non-generated clock tree(s) driving 2362 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       ENCRYPTED           CLKDIV                 2233       ENCRYPTED      
@KP:ckid0_1       clk                 port                   33         ENCRYPTED      
@KP:ckid0_2       ENCRYPTED           DHCEN                  60         ENCRYPTED      
@KP:ckid0_3       ENCRYPTED           DQS                    8          ENCRYPTED      
@KP:ckid0_4       ENCRYPTED           DQS                    9          ENCRYPTED      
@KP:ckid0_5       ENCRYPTED           DQS                    1          ENCRYPTED      
@KP:ckid0_6       ENCRYPTED           DQS                    8          ENCRYPTED      
@KP:ckid0_7       ENCRYPTED           DQS                    9          ENCRYPTED      
@KP:ckid0_8       ENCRYPTED           DQS                    1          ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\temp\DDR3\rev_1\ddr3_memory_interface.sap.

Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB)


Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 242MB peak: 242MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 243MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Wed Jun 17 17:41:49 2020

###########################################################]
