
Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: DESKTOP

Implementation : rev_1
Synopsys HDL Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: DESKTOP

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v":"D:\proj\scaler_example_design_live\project\src\i2c_master\temp\I2C_MASTER\top_define.vh" (library work)
@I:"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v":"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\static_macro_define.vh" (library work)
@I::"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp" (library work)
@N: CG346 :"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp":491:39:491:47|Read full_case directive.
@N: CG347 :"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp":491:49:491:61|Read a parallel_case directive.
@N: CG346 :"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp":495:39:495:47|Read full_case directive.
@N: CG347 :"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp":495:49:495:61|Read a parallel_case directive.
@W: CG286 :"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp":495:13:495:16|Case statement has both a full_case directive and a default clause -- ignoring full_case directive.
@N: CG346 :"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp":804:34:804:42|Read full_case directive.
@N: CG347 :"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp":804:44:804:56|Read a parallel_case directive.
Verilog syntax check successful!
Selecting top level module I2C_MASTER_Top
Running optimization stage 1 on \~I2C_Master_Byte_Ctrl.I2C_MASTER_Top  .......
Running optimization stage 1 on \~I2C_Master_Bit_Ctrl.I2C_MASTER_Top  .......
Running optimization stage 1 on \~i2c_master.I2C_MASTER_Top  .......
@N: CG364 :"D:\Gowin\Gowin_V1.9.2.01Beta\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v":4:19:4:19|Synthesizing module I2C_MASTER_Top in library work.
Running optimization stage 1 on I2C_MASTER_Top .......
Running optimization stage 2 on I2C_MASTER_Top .......
Running optimization stage 2 on \~i2c_master.I2C_MASTER_Top  .......
Running optimization stage 2 on \~I2C_Master_Bit_Ctrl.I2C_MASTER_Top  .......
Extracted state machine for register c_state
State machine has 18 reachable states with original encodings of:
   00000000000000000
   00000000000000001
   00000000000000010
   00000000000000100
   00000000000001000
   00000000000010000
   00000000000100000
   00000000001000000
   00000000010000000
   00000000100000000
   00000001000000000
   00000010000000000
   00000100000000000
   00001000000000000
   00010000000000000
   00100000000000000
   01000000000000000
   10000000000000000
Running optimization stage 2 on \~I2C_Master_Byte_Ctrl.I2C_MASTER_Top  .......
Extracted state machine for register c_state
State machine has 6 reachable states with original encodings of:
   00000
   00001
   00010
   00100
   01000
   10000

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: D:\proj\scaler_example_design_live\project\src\i2c_master\temp\I2C_MASTER\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 93MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Dec  9 10:09:00 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: P-2019.03G
Install: D:\Gowin\Gowin_V1.9.2.01Beta\SynplifyPro
OS: Windows 6.1

Hostname: DESKTOP

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2019q1p1, Build 307R, Built Sep 25 2019 09:21:26

@N|Running in 64-bit mode
@N: NF107 :"d:\gowin\gowin_v1.9.2.01beta\ide\ipcore\i2cmaster\data\i2c_master_top.v":4:19:4:19|Selected library: work cell: I2C_MASTER_Top view verilog as top level
@N: NF107 :"d:\gowin\gowin_v1.9.2.01beta\ide\ipcore\i2cmaster\data\i2c_master_top.v":4:19:4:19|Selected library: work cell: I2C_MASTER_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Dec  9 10:09:01 2019

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: D:\proj\scaler_example_design_live\project\src\i2c_master\temp\I2C_MASTER\rev_1\synwork\i2c_master_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 18MB peak: 19MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Dec  9 10:09:01 2019

###########################################################]
