<!DOCTYPE gowin-synthesis-project>
<Project>
    <Version>Beta</Version>
    <Device id="GW2A-18" package="PBGA484" speed="8" partNumber="GW2A-LV18PG484C8/I7"/>
    <FileList>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\scaler_test_top.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\testpattern.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\syn_code\syn_gen.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\gw_pll\gw_pll.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\gw_pll\pix_pll.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\scaler\scaler.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\ddr3_memory_interface\ddr3_memory_interface.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\dma_16b_32b.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\dma_24b_32b.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\dma_32b_16b.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\dma_32b_24b.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\dma_bus_arbiter.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\dma_frame_buffer.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\dma_frame_ctrl.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\dma_read_ctrl.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\dma_write_ctrl.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\vfb_defines.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\vfb_top.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\fifo_dma_read_128_32.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\fifo_dma_write_32_128.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\adv7513_iic_init.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\key_debounceN.v"/>
        <File type="verilog"  path="D:\proj\scaler_example_design_live\project\src\i2c_master\i2c_master.v"/>
    </FileList>
    <OptionList>
        <Option type="top_module"  value="scaler_test_top"/>
        <Option type="include_path"  value="D:/proj/scaler_example_design_live/project/src/frame_buffer"/>
        <Option type="output_file"  value="D:\proj\scaler_example_design_live\project\impl\gwsynthesis\scaler_ref_design_live.vg"/>
    </OptionList>
</Project>
