@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\fifo_parameter.v":1:0:1:8|Synthesizing module work_D:\proj\scaler_example_design_live\project\src\frame_buffer\fifo\temp\FIFO\fifo_define.v_unit in library work.
@N: CG364 :"D:\Gowin\Gowin_V1.9.3Beta_37275_20191218\IDE\ipcore\FIFO\data\fifo_top.v":3:20:3:20|Synthesizing module fifo_dma_write_32_128 in library work.
@N|Running in 64-bit mode
@N: NF107 :"d:\gowin\gowin_v1.9.3beta_37275_20191218\ide\ipcore\fifo\data\fifo_top.v":3:20:3:20|Selected library: work cell: fifo_dma_write_32_128 view verilog as top level
@N: NF107 :"d:\gowin\gowin_v1.9.3beta_37275_20191218\ide\ipcore\fifo\data\fifo_top.v":3:20:3:20|Selected library: work cell: fifo_dma_write_32_128 view verilog as top level

