
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1

# Written on Wed Jun 17 17:50:19 2020

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start                                                                                        Requested     Requested     Clock        Clock                     Clock
Level     Clock                                                                                        Frequency     Period        Type         Group                     Load 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                                                                       150.0 MHz     6.667         system       system_clkgroup           0    
                                                                                                                                                                               
0 -       _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                            162.3 MHz     6.160         inferred     Autoconstr_clkgroup_0     2739 
                                                                                                                                                                               
0 -       _~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                           150.0 MHz     6.667         inferred     Autoconstr_clkgroup_2     60   
                                                                                                                                                                               
0 -       DDR3_Memory_Interface_Top|clk                                                                302.5 MHz     3.306         inferred     Autoconstr_clkgroup_1     33   
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_7     9    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_4     9    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock      150.0 MHz     6.667         inferred     Autoconstr_clkgroup_8     8    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock      150.0 MHz     6.667         inferred     Autoconstr_clkgroup_5     8    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock       150.0 MHz     6.667         inferred     Autoconstr_clkgroup_6     1    
                                                                                                                                                                               
0 -       _~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock       150.0 MHz     6.667         inferred     Autoconstr_clkgroup_3     1    
===============================================================================================================================================================================


Clock Load Summary
******************

                                                                                             Clock     Source                                                                                                                               Clock Pin                                                                                                                                      Non-clock Pin                                                                                                                                  Non-clock Pin
Clock                                                                                        Load      Pin                                                                                                                                  Seq Example                                                                                                                                    Seq Example                                                                                                                                    Comb Example 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                                                       0         -                                                                                                                                    -                                                                                                                                              -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock                            2739      genblk1\.gw3mc_top.u_ddr_phy_top.clkdiv.CLKOUT(CLKDIV)                                                                               genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_init.read_cmd0.C                                                                                        genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem.PCLK     -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock                           60        genblk1\.gw3mc_top.u_ddr_phy_top.u_dqcen.CLKOUT(DHCEN)                                                                               genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_ddr_phy_cmd_lane.u_ddr_phy_cmd_io.mcd_oserdes_gen\[15\]\.u_cmd_gen.FCLK                        -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
DDR3_Memory_Interface_Top|clk                                                                33        clk(port)                                                                                                                            genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.u_mem_sync.recalib_s[1:0].C                                                                      -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock     9         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW270(DQS)     genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.oserdes_gen\[5\]\.u_oser8_mem.TCLK     -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock     9         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW270(DQS)     genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.oserdes_gen\[5\]\.u_oser8_mem.TCLK     -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock      8         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSR90(DQS)      genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem.ICLK     -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock      8         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSR90(DQS)      genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.iserdes_gen\[6\]\.u_ides8_mem.ICLK     -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock       1         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW0(DQS)       genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[0\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.u_dqs_gen.TCLK                         -                                                                                                                                              -            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock       1         genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.cml5\.u_dqs.DQSW0(DQS)       genblk1\.gw3mc_top.u_ddr_phy_top.u_ddr_phy_wd.data_lane_gen\[1\]\.u_ddr_phy_data_lane.u_ddr_phy_data_io.u_dqs_gen.TCLK                         -                                                                                                                                              -            
=======================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================
