<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW2A-18C" pn="GW2A-LV18PG484C8/I7">gw2a18c-021</Device>
    <FileList>
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        <File path="src/frame_buffer/vfb_defines.v" type="file.verilog" enable="1"/>
        <File path="src/frame_buffer/vfb_top.v" type="file.verilog" enable="1"/>
        <File path="src/gw_pll/gw_pll.v" type="file.verilog" enable="1"/>
        <File path="src/gw_pll/pix_pll.v" type="file.verilog" enable="1"/>
        <File path="src/i2c_master/i2c_master.v" type="file.verilog" enable="1"/>
        <File path="src/syn_code/syn_gen.v" type="file.verilog" enable="1"/>
        <File path="src/adv7513_iic_init.v" type="file.verilog" enable="1"/>
        <File path="src/key_debounceN.v" type="file.verilog" enable="1"/>
        <File path="src/scaler_test_top.v" type="file.verilog" enable="1"/>
        <File path="src/testpattern.v" type="file.verilog" enable="1"/>
        <File path="src/scaler_test_top.cst" type="file.cst" enable="1"/>
        <File path="src/scaler_ref_design_memory.sdc" type="file.sdc" enable="1"/>
        <File path="src/frame_buffer/vfb_wrapper.v" type="file.verilog" enable="1"/>
        <File path="src/frame_buffer/fifo/fifo_dma_read_128_32.v" type="file.verilog" enable="1"/>
        <File path="src/frame_buffer/fifo/fifo_dma_write_32_128.v" type="file.verilog" enable="1"/>
        <File path="src/scaler/scaler.v" type="file.verilog" enable="1"/>
    </FileList>
</Project>
