<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>D:\proj\scaler_example_design_memory\project\src\scaler\temp\scaler\rev_1\synlog\scaler_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>Scaler_Top|I_sysclk</data>
<data>247.5 MHz</data>
<data>210.4 MHz</data>
<data>-0.713</data>
</row>
<row>
<data>Scaler_Top|I_vin_clk</data>
<data>237.3 MHz</data>
<data>201.7 MHz</data>
<data>-0.744</data>
</row>
<row>
<data>Scaler_Top|I_vout_clk</data>
<data>237.3 MHz</data>
<data>201.7 MHz</data>
<data>-0.744</data>
</row>
</report_table>
