Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | E:\IP_verify\1.9.6\IP_web\Gowin_Scaler_RefDesign_DDR300MHz\Gowin_Scaler_RefDesign_DDR300MHz\scaler_example_design_memory\project\impl\synthesize\rev_1\scaler_ref_design_memory.vm
Physical Constraints File | E:\IP_verify\1.9.6\IP_web\Gowin_Scaler_RefDesign_DDR300MHz\Gowin_Scaler_RefDesign_DDR300MHz\scaler_example_design_memory\project\src\scaler_test_top.cst
Timing Constraint File | E:\IP_verify\1.9.6\IP_web\Gowin_Scaler_RefDesign_DDR300MHz\Gowin_Scaler_RefDesign_DDR300MHz\scaler_example_design_memory\project\src\scaler_ref_design_memory.sdc
GOWIN version | V1.9.6Beta
Part Number | GW2A-LV18PG484C8/I7
Created Time | Thu Jul 02 09:08:01 2020
Legal Announcement | Copyright (C)2014-2020 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 0.95V 85C
Hold Delay Model | Fast 1.05V 0C
Numbers of Paths Analyzed | 12301
Numbers of Endpoints Analyzed | 12597
Numbers of Falling Endpoints | 8
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
I_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  | I_clk
pixel_clk | Base | 6.734 | 148.500 | 0.000 | 3.367 |  |  | pixel_clk
dma_clk | Base | 13.333 | 75.002 | 0.000 | 6.667 |  |  | dma_clk
gw_pll | Base | 6.734 | 148.500 | 0.000 | 3.367 |  |  | clkout
clk_x4 | Base | 3.333 | 300.030 | 0.000 | 1.667 |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4
clk_x4i | Base | 3.333 | 300.030 | 0.000 | 1.667 |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4i
gw_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.667 | 150.000 | 0.000 | 3.333 | I_clk_ibuf/I | I_clk | gw_pll_inst/rpll_inst/CLKOUTP
gw_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 13.333 | 75.000 | 0.000 | 6.667 | I_clk_ibuf/I | I_clk | gw_pll_inst/rpll_inst/CLKOUTD
gw_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | I_clk_ibuf/I | I_clk | gw_pll_inst/rpll_inst/CLKOUTD3
pix_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.667 | 150.000 | 0.000 | 3.333 | I_clk_ibuf/I | I_clk | pix_pll_inst/rpll_inst/CLKOUTP
pix_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 13.333 | 75.000 | 0.000 | 6.667 | I_clk_ibuf/I | I_clk | pix_pll_inst/rpll_inst/CLKOUTD
pix_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | I_clk_ibuf/I | I_clk | pix_pll_inst/rpll_inst/CLKOUTD3
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP.default_gen_clk | Generated | 3.333 | 300.000 | 1.667 | 0.000 | I_clk_ibuf/I | I_clk | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD.default_gen_clk | Generated | 6.667 | 150.000 | 0.000 | 3.333 | I_clk_ibuf/I | I_clk | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | I_clk_ibuf/I | I_clk | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | I_clk | 50.000(MHz) | 143.232(MHz) | 7 | TOP
2 | pixel_clk | 148.500(MHz) | 154.561(MHz) | 8 | TOP
3 | dma_clk | 75.002(MHz) | 95.246(MHz) | 8 | TOP
4 | gw_pll | 148.500(MHz) | 172.584(MHz) | 3 | TOP
5 | clk_x4i | 300.030(MHz) | 1436.782(MHz) | 1 | TOP
6 | gw_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | 75.000(MHz) | 135.137(MHz) | 9 | TOP

#### No timing paths to get frequency of clk_x4!

#### No timing paths to get frequency of gw_pll_inst/rpll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of gw_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

#### No timing paths to get frequency of pix_pll_inst/rpll_inst/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of pix_pll_inst/rpll_inst/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of pix_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

#### No timing paths to get frequency of DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP.default_gen_clk!

#### No timing paths to get frequency of DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD.default_gen_clk!

#### No timing paths to get frequency of DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3.default_gen_clk!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
I_clk | Setup | 0.000 | 0
I_clk | Hold | 0.000 | 0
pixel_clk | Setup | 0.000 | 0
pixel_clk | Hold | 0.000 | 0
dma_clk | Setup | 0.000 | 0
dma_clk | Hold | 0.000 | 0
gw_pll | Setup | 0.000 | 0
gw_pll | Hold | 0.000 | 0
clk_x4 | Setup | 0.000 | 0
clk_x4 | Hold | 0.000 | 0
clk_x4i | Setup | 0.000 | 0
clk_x4i | Hold | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
gw_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
pix_pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP.default_gen_clk | Setup | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTP.default_gen_clk | Hold | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD.default_gen_clk | Setup | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD.default_gen_clk | Hold | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0
DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_PLL/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.264 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/D | pixel_clk:[R] | pixel_clk:[R] | 6.734 | 0.000 | 6.235
2 | 0.940 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[24]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.559
3 | 0.940 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[22]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.559
4 | 0.940 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[21]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.559
5 | 0.940 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[20]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.559
6 | 0.940 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[23]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.559
7 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[61]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
8 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[60]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
9 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[59]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
10 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[58]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
11 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[57]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
12 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[51]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
13 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[50]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
14 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[49]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
15 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[48]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
16 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[47]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
17 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[46]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
18 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[45]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
19 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[44]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
20 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[43]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
21 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[42]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
22 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[41]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
23 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[40]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
24 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[32]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556
25 | 0.943 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[31]/CE | gw_pll:[R] | gw_pll:[R] | 6.734 | 0.000 | 5.556

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.088 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[5]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/B_5 | gw_pll:[R] | gw_pll:[R] | 0.000 | 0.000 | 0.323
2 | 0.194 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/WREA | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
3 | 0.194 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/WREA | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
4 | 0.194 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/WREA | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
5 | 0.194 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/WREA | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
6 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3/WREB | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.335
7 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0/WREB | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
8 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1/WREB | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.335
9 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2/WREB | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.335
10 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0/WREB | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
11 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0/WREB | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
12 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0/WREB | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.335
13 | 0.194 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0/WREB | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.335
14 | 0.211 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_Z[8]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0/ADB11 | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.329
15 | 0.212 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_Z[4]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0/ADB7 | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.330
16 | 0.220 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[11]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[1].mult18x18_inst/B_3 | gw_pll:[R] | gw_pll:[R] | 0.000 | 0.000 | 0.447
17 | 0.224 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[4]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/B_4 | gw_pll:[R] | gw_pll:[R] | 0.000 | 0.000 | 0.451
18 | 0.224 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[3]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/B_3 | gw_pll:[R] | gw_pll:[R] | 0.000 | 0.000 | 0.451
19 | 0.224 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[2]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/B_2 | gw_pll:[R] | gw_pll:[R] | 0.000 | 0.000 | 0.451
20 | 0.228 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[4]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/DI4 | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.477
21 | 0.229 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[5]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/DI5 | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.478
22 | 0.229 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[0]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/DI0 | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.478
23 | 0.230 | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[1]/Q | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/DI1 | pixel_clk:[R] | pixel_clk:[R] | 0.000 | 0.000 | 0.479
24 | 0.234 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[22]/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen/D4 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329
25 | 0.234 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[21]/Q | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen/D2 | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 0.329

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.621 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[1]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.483
2 | 1.621 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[1]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.483
3 | 1.621 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[0]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.483
4 | 1.800 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[6]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.305
5 | 2.020 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata_rst_Z/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.084
6 | 2.020 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[3]_Z/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.084
7 | 2.020 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.084
8 | 2.027 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[0]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.078
9 | 2.027 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[1]_Z/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.078
10 | 2.027 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.078
11 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/PRESET | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
12 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[2]_Z/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
13 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[5]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
14 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[4]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
15 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[3]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
16 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[10]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
17 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
18 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
19 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
20 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[2]_Z/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
21 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[2]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
22 | 2.030 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[7]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.074
23 | 2.031 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.073
24 | 2.031 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[11]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.073
25 | 2.039 | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]/CLEAR | pixel_clk:[F] | pixel_clk:[R] | 3.367 | 0.028 | 1.066

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[5]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
2 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[2]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
3 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
4 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[0]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
5 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
6 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[0]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
7 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
8 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
9 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[2]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
10 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[1]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
11 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[1]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
12 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
13 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_Z/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
14 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[3]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
15 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[8]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
16 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[17]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
17 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[15]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
18 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[7]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
19 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d1_Z/PRESET | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
20 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[4]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
21 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[7]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
22 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[6]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
23 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[20]/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
24 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495
25 | 1.484 | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant/CLEAR | dma_clk:[R] | dma_clk:[R] | 0.000 | 0.000 | 1.495

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 2.041 | 3.041 | 1.000 | Low Pulse Width | pixel_clk | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/video_vs_n_d1_Z
2 | 2.041 | 3.041 | 1.000 | Low Pulse Width | pixel_clk | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_Z
3 | 2.041 | 3.041 | 1.000 | Low Pulse Width | pixel_clk | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b
4 | 2.041 | 3.041 | 1.000 | Low Pulse Width | pixel_clk | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b[3]
5 | 2.041 | 3.041 | 1.000 | Low Pulse Width | pixel_clk | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b[10]
6 | 2.041 | 3.041 | 1.000 | Low Pulse Width | pixel_clk | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z
7 | 2.041 | 3.041 | 1.000 | Low Pulse Width | pixel_clk | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_Z[7]
8 | 2.041 | 3.041 | 1.000 | Low Pulse Width | pixel_clk | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vout_de_gen_d1_Z
9 | 2.041 | 3.041 | 1.000 | Low Pulse Width | gw_pll | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_vres[10]
10 | 2.041 | 3.041 | 1.000 | Low Pulse Width | gw_pll | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.264
Data Arrival Time | 7.436
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
1.433 | 0.232 | tC2Q | RF | 6 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q
2.122 | 0.689 | tNET | FF | 1 | R43C31[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata14_cZ/I0
2.493 | 0.371 | tINS | FF | 2 | R43C31[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata14_cZ/F
2.911 | 0.418 | tNET | FF | 2 | R44C33[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_0_0/I1
3.282 | 0.371 | tINS | FF | 1 | R44C33[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_0_0/COUT
3.282 | 0.000 | tNET | FF | 2 | R44C33[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_1_0/CIN
3.317 | 0.035 | tINS | FF | 1 | R44C33[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_1_0/COUT
3.317 | 0.000 | tNET | FF | 2 | R44C33[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_2_0/CIN
3.352 | 0.035 | tINS | FF | 1 | R44C33[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_2_0/COUT
3.352 | 0.000 | tNET | FF | 2 | R44C33[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_3_0/CIN
3.387 | 0.035 | tINS | FF | 1 | R44C33[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_3_0/COUT
3.387 | 0.000 | tNET | FF | 2 | R44C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_4_0/CIN
3.423 | 0.035 | tINS | FF | 1 | R44C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_4_0/COUT
3.423 | 0.000 | tNET | FF | 2 | R44C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_5_0/CIN
3.893 | 0.470 | tINS | FF | 5 | R44C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_next_cry_5_0/SUM
5.570 | 1.677 | tNET | FF | 1 | R44C36[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_3_cZ/I1
6.023 | 0.453 | tINS | FF | 4 | R44C36[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_3_cZ/F
6.220 | 0.198 | tNET | FF | 1 | R44C35[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_0_0_cZ/I2
6.591 | 0.371 | tINS | FF | 1 | R44C35[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_0_0_cZ/F
6.591 | 0.000 | tNET | FF | 1 | R44C35[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_0_cZ/I0
6.694 | 0.103 | tINS | FF | 1 | R44C35[3][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_0_cZ/O
6.694 | 0.000 | tNET | FF | 1 | R44C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_cZ/I0
6.797 | 0.103 | tINS | FF | 1 | R44C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_6_cZ/O
6.974 | 0.176 | tNET | FF | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_i_cZ/I3
7.436 | 0.462 | tINS | FR | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rempty_val_NE_i_cZ/F
7.436 | 0.000 | tNET | RR | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
7.700 | -0.035 | tSu |  | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 8
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 2.845, 45.627%; route: 3.158, 50.652%; tC2Q: 0.232, 3.721%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path2

Path Summary:

Slack | 0.940
Data Arrival Time | 6.760
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[24]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.760 | 2.490 | tNET | RR | 1 | R20C37[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[24]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C37[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[24]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[24]
7.700 | -0.035 | tSu |  | 1 | R20C37[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[24]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.859%; route: 4.223, 75.968%; tC2Q: 0.232, 4.173%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path3

Path Summary:

Slack | 0.940
Data Arrival Time | 6.760
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[22]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.760 | 2.490 | tNET | RR | 1 | R20C37[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[22]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C37[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[22]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[22]
7.700 | -0.035 | tSu |  | 1 | R20C37[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[22]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.859%; route: 4.223, 75.968%; tC2Q: 0.232, 4.173%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path4

Path Summary:

Slack | 0.940
Data Arrival Time | 6.760
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[21]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.760 | 2.490 | tNET | RR | 1 | R20C37[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[21]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C37[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[21]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[21]
7.700 | -0.035 | tSu |  | 1 | R20C37[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[21]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.859%; route: 4.223, 75.968%; tC2Q: 0.232, 4.173%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path5

Path Summary:

Slack | 0.940
Data Arrival Time | 6.760
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[20]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.760 | 2.490 | tNET | RR | 1 | R20C37[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[20]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C37[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[20]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[20]
7.700 | -0.035 | tSu |  | 1 | R20C37[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[20]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.859%; route: 4.223, 75.968%; tC2Q: 0.232, 4.173%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path6

Path Summary:

Slack | 0.940
Data Arrival Time | 6.760
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[23]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.760 | 2.490 | tNET | RR | 1 | R20C37[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[23]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C37[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[23]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[23]
7.700 | -0.035 | tSu |  | 1 | R20C37[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo1_Z[23]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.859%; route: 4.223, 75.968%; tC2Q: 0.232, 4.173%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path7

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[61]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R14C31[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[61]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R14C31[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[61]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[61]
7.700 | -0.035 | tSu |  | 1 | R14C31[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[61]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path8

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[60]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R14C31[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[60]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R14C31[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[60]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[60]
7.700 | -0.035 | tSu |  | 1 | R14C31[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[60]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path9

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[59]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R14C31[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[59]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R14C31[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[59]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[59]
7.700 | -0.035 | tSu |  | 1 | R14C31[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[59]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path10

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[58]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R14C31[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[58]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R14C31[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[58]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[58]
7.700 | -0.035 | tSu |  | 1 | R14C31[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[58]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path11

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[57]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R14C31[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[57]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R14C31[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[57]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[57]
7.700 | -0.035 | tSu |  | 1 | R14C31[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[57]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path12

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[51]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R18C28[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[51]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R18C28[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[51]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[51]
7.700 | -0.035 | tSu |  | 1 | R18C28[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[51]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path13

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[50]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R18C28[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[50]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R18C28[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[50]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[50]
7.700 | -0.035 | tSu |  | 1 | R18C28[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[50]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path14

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[49]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R18C28[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[49]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R18C28[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[49]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[49]
7.700 | -0.035 | tSu |  | 1 | R18C28[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[49]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path15

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[48]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R18C28[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[48]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R18C28[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[48]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[48]
7.700 | -0.035 | tSu |  | 1 | R18C28[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[48]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path16

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[47]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R18C28[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[47]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R18C28[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[47]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[47]
7.700 | -0.035 | tSu |  | 1 | R18C28[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[47]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path17

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[46]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R18C28[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[46]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R18C28[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[46]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[46]
7.700 | -0.035 | tSu |  | 1 | R18C28[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[46]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path18

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[45]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R20C28[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[45]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C28[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[45]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[45]
7.700 | -0.035 | tSu |  | 1 | R20C28[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[45]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path19

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[44]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R20C28[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[44]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C28[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[44]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[44]
7.700 | -0.035 | tSu |  | 1 | R20C28[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[44]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path20

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[43]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R20C28[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[43]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C28[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[43]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[43]
7.700 | -0.035 | tSu |  | 1 | R20C28[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[43]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path21

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[42]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R20C28[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[42]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C28[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[42]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[42]
7.700 | -0.035 | tSu |  | 1 | R20C28[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[42]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path22

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[41]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R20C28[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[41]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C28[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[41]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[41]
7.700 | -0.035 | tSu |  | 1 | R20C28[2][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[41]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path23

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[40]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R20C28[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[40]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R20C28[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[40]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[40]
7.700 | -0.035 | tSu |  | 1 | R20C28[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[40]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path24

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[32]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R13C29[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[32]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R13C29[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[32]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[32]
7.700 | -0.035 | tSu |  | 1 | R13C29[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[32]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path25

Path Summary:

Slack | 0.943
Data Arrival Time | 6.757
Data Required Time | 7.700
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[31]
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
1.201 | 1.201 | tNET | RR | 1 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/CLK
1.433 | 0.232 | tC2Q | RF | 2 | R27C40[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/vinvs_sysclk_d2_fast_Z/Q
2.558 | 1.126 | tNET | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/I3
3.113 | 0.555 | tINS | FF | 1 | R20C33[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_cZ_cZ/F
3.721 | 0.607 | tNET | FF | 1 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/I0
4.270 | 0.549 | tINS | FR | 192 | R13C34[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/un1_vval_limit_en_1_i_sx_RNII8VE_cZ/F
6.757 | 2.487 | tNET | RR | 1 | R13C29[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[31]/CE

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | gw_pll
6.734 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R13C29[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[31]/CLK
7.735 | -0.200 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[31]
7.700 | -0.035 | tSu |  | 1 | R13C29[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_calcdata_gen_inst/hfifo0_Z[31]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 6.734
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay | cell: 1.104, 19.870%; route: 4.220, 75.954%; tC2Q: 0.232, 4.176%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.088
Data Arrival Time | 1.225
Data Required Time | 1.137
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[5]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R18C47[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[5]/CLK
1.103 | 0.201 | tC2Q | RF | 1 | R18C47[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[5]/Q
1.225 | 0.122 | tNET | FF | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/B_5

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/CLK
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst
1.137 | 0.235 | tHld |  | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path2

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R14C21[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/CLK
1.104 | 0.202 | tC2Q | RR | 12 | R14C21[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q
1.237 | 0.133 | tNET | RR | 1 | BSRAM_R28[7] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/WREA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[7] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R28[7] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path3

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R14C21[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/CLK
1.104 | 0.202 | tC2Q | RR | 12 | R14C21[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q
1.237 | 0.133 | tNET | RR | 1 | BSRAM_R28[6] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/WREA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[6] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R28[6] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path4

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R14C21[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/CLK
1.104 | 0.202 | tC2Q | RR | 12 | R14C21[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q
1.237 | 0.133 | tNET | RR | 1 | BSRAM_R10[7] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/WREA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[7] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R10[7] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path5

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R14C21[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/CLK
1.104 | 0.202 | tC2Q | RR | 12 | R14C21[1][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_fifo_ctrl/of_Full_reg/Q
1.237 | 0.133 | tNET | RR | 1 | BSRAM_R10[6] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/WREA

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[6] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R10[6] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem8_mem8_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path6

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R46[8] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R46[8] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3
1.043 | 0.141 | tHld |  | 1 | BSRAM_R46[8] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_3

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path7

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R39C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R39C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R46[11] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R46[11] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R46[11] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_1_mem_2_1_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path8

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R46[13] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R46[13] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1
1.043 | 0.141 | tHld |  | 1 | BSRAM_R46[13] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path9

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R46[9] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R46[9] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2
1.043 | 0.141 | tHld |  | 1 | BSRAM_R46[9] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path10

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R39C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R39C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R46[12] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R46[12] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R46[12] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_3_mem_2_3_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path11

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R39C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R39C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R28[10] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[10] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R28[10] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_2_mem_2_2_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path12

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R39C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R39C42[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R46[10] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R46[10] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R46[10] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_dma_write_32_128_inst/fifo_inst/mem_2_0_mem_2_0_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path13

Path Summary:

Slack | 0.194
Data Arrival Time | 1.237
Data Required Time | 1.043
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
1.103 | 0.201 | tC2Q | RF | 6 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/Q
1.237 | 0.134 | tNET | FF | 1 | BSRAM_R46[14] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0/WREB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R46[14] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0
1.043 | 0.141 | tHld |  | 1 | BSRAM_R46[14] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/mem_mem_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 40.000%; tC2Q: 0.201, 60.000%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path14

Path Summary:

Slack | 0.211
Data Arrival Time | 1.231
Data Required Time | 1.020
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_Z[8]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R30C44[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_Z[8]/CLK
1.104 | 0.202 | tC2Q | RR | 7 | R30C44[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_Z[8]/Q
1.231 | 0.127 | tNET | RR | 1 | BSRAM_R28[12] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0/ADB11

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[12] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0
1.020 | 0.118 | tHld |  | 1 | BSRAM_R28[12] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.127, 38.581%; tC2Q: 0.202, 61.419%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path15

Path Summary:

Slack | 0.212
Data Arrival Time | 1.232
Data Required Time | 1.020
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_Z[4]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R30C44[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_Z[4]/CLK
1.104 | 0.202 | tC2Q | RR | 7 | R30C44[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/oram_rdaddr_Z[4]/Q
1.232 | 0.128 | tNET | RR | 1 | BSRAM_R28[12] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0/ADB7

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R28[12] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0/CLKB
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0
1.020 | 0.118 | tHld |  | 1 | BSRAM_R28[12] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/video_outbuf_inst/bram_inst1_pp1/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.808%; tC2Q: 0.202, 61.192%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path16

Path Summary:

Slack | 0.220
Data Arrival Time | 1.349
Data Required Time | 1.129
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[11]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[1].mult18x18_inst
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R17C48[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[11]/CLK
1.104 | 0.202 | tC2Q | RR | 1 | R17C48[1][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[11]/Q
1.349 | 0.245 | tNET | RR | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[1].mult18x18_inst/B_3

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[1].mult18x18_inst/CLK
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[1].mult18x18_inst
1.129 | 0.227 | tHld |  | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[1].mult18x18_inst

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path17

Path Summary:

Slack | 0.224
Data Arrival Time | 1.353
Data Required Time | 1.129
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[4]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R17C47[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[4]/CLK
1.104 | 0.202 | tC2Q | RR | 1 | R17C47[2][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[4]/Q
1.353 | 0.249 | tNET | RR | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/B_4

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/CLK
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst
1.129 | 0.227 | tHld |  | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path18

Path Summary:

Slack | 0.224
Data Arrival Time | 1.353
Data Required Time | 1.129
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[3]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R17C47[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[3]/CLK
1.104 | 0.202 | tC2Q | RR | 1 | R17C47[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[3]/Q
1.353 | 0.249 | tNET | RR | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/B_3

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/CLK
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst
1.129 | 0.227 | tHld |  | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path19

Path Summary:

Slack | 0.224
Data Arrival Time | 1.353
Data Required Time | 1.129
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[2]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst
Launch Clk | gw_pll:[R]
Latch Clk | gw_pll:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R17C47[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[2]/CLK
1.104 | 0.202 | tC2Q | RR | 1 | R17C47[1][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/vcalc_data1_Z[2]/Q
1.353 | 0.249 | tNET | RR | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/B_2

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | gw_pll
0.000 | 0.000 | tCL | RR | 1172 | PLL_R[0] | gw_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst/CLK
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst
1.129 | 0.227 | tHld |  | 1 | DSP_R19[5][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_integrator_inst1/loop1[0].mult18x18_inst

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path20

Path Summary:

Slack | 0.228
Data Arrival Time | 1.379
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[4]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R14C45[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[4]/CLK
1.104 | 0.202 | tC2Q | RR | 4 | R14C45[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[4]/Q
1.379 | 0.275 | tNET | RR | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/DI4

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.275, 57.645%; tC2Q: 0.202, 42.355%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path21

Path Summary:

Slack | 0.229
Data Arrival Time | 1.380
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[5]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R14C45[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[5]/CLK
1.104 | 0.202 | tC2Q | RR | 4 | R14C45[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[5]/Q
1.380 | 0.276 | tNET | RR | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/DI5

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.276, 57.736%; tC2Q: 0.202, 42.264%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path22

Path Summary:

Slack | 0.229
Data Arrival Time | 1.380
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[0]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R17C44[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[0]/CLK
1.104 | 0.202 | tC2Q | RR | 4 | R17C44[0][B] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[0]/Q
1.380 | 0.276 | tNET | RR | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/DI0

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.276, 57.753%; tC2Q: 0.202, 42.247%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path23

Path Summary:

Slack | 0.230
Data Arrival Time | 1.381
Data Required Time | 1.151
From | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[1]
To | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0
Launch Clk | pixel_clk:[R]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R17C44[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[1]/CLK
1.104 | 0.202 | tC2Q | RR | 4 | R17C44[0][A] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/iram_wrdata2_Z[1]/Q
1.381 | 0.277 | tNET | RR | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/DI1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pixel_clk
0.000 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0/CLKA
0.902 | 0.000 | tUnc |  |  |  | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0
1.151 | 0.249 | tHld |  | 1 | BSRAM_R10[13] | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/ver_calc_wrapper_inst/ver_calcdata_gen_inst/loop1[0].bram_inst2/bram_sdp_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.277, 57.844%; tC2Q: 0.202, 42.156%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path24

Path Summary:

Slack | 0.234
Data Arrival Time | 1.230
Data Required Time | 0.997
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[22]
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R3C2[0][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[22]/CLK
1.103 | 0.201 | tC2Q | RF | 2 | R3C2[0][B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[22]/Q
1.230 | 0.128 | tNET | FF | 1 | IOL3[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen/D4

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | IOL3[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen/PCLK
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen
0.997 | 0.095 | tHld |  | 1 | IOL3[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path25

Path Summary:

Slack | 0.234
Data Arrival Time | 1.230
Data Required Time | 0.997
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[21]
To | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R3C2[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[21]/CLK
1.103 | 0.201 | tC2Q | RF | 2 | R3C2[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/oserdes_d_reg_Z[21]/Q
1.230 | 0.128 | tNET | FF | 1 | IOL3[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen/D2

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | IOL3[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen/PCLK
0.902 | 0.000 | tUnc |  |  |  | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen
0.997 | 0.095 | tHld |  | 1 | IOL3[B] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_phy_wd/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/mcd_oserdes_gen[5].u_cmd_gen

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.621
Data Arrival Time | 6.078
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[1]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
6.078 | 1.251 | tNET | FF | 1 | R43C32[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R43C32[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[1]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[1]
7.700 | -0.035 | tSu |  | 1 | R43C32[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[1]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.251, 84.354%; tC2Q: 0.232, 15.646%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path2

Path Summary:

Slack | 1.621
Data Arrival Time | 6.078
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[1]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
6.078 | 1.251 | tNET | FF | 1 | R43C32[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R43C32[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[1]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[1]
7.700 | -0.035 | tSu |  | 1 | R43C32[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[1]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.251, 84.354%; tC2Q: 0.232, 15.646%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path3

Path Summary:

Slack | 1.621
Data Arrival Time | 6.078
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[0]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
6.078 | 1.251 | tNET | FF | 1 | R43C32[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R43C32[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[0]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[0]
7.700 | -0.035 | tSu |  | 1 | R43C32[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num[0]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.251, 84.354%; tC2Q: 0.232, 15.646%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path4

Path Summary:

Slack | 1.800
Data Arrival Time | 5.900
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[6]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.900 | 1.073 | tNET | FF | 1 | R43C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R43C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[6]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[6]
7.700 | -0.035 | tSu |  | 1 | R43C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[6]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.073, 82.219%; tC2Q: 0.232, 17.781%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path5

Path Summary:

Slack | 2.020
Data Arrival Time | 5.679
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata_rst_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.679 | 0.852 | tNET | FF | 1 | R43C31[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata_rst_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R43C31[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata_rst_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata_rst_Z
7.700 | -0.035 | tSu |  | 1 | R43C31[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.wdata_rst_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.852, 78.597%; tC2Q: 0.232, 21.403%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path6

Path Summary:

Slack | 2.020
Data Arrival Time | 5.679
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[3]_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.679 | 0.852 | tNET | FF | 1 | R43C31[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[3]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R43C31[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[3]_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[3]_Z
7.700 | -0.035 | tSu |  | 1 | R43C31[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[3]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.852, 78.597%; tC2Q: 0.232, 21.403%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path7

Path Summary:

Slack | 2.020
Data Arrival Time | 5.679
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.679 | 0.852 | tNET | FF | 1 | R43C31[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R43C31[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z
7.700 | -0.035 | tSu |  | 1 | R43C31[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[2]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.852, 78.597%; tC2Q: 0.232, 21.403%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path8

Path Summary:

Slack | 2.027
Data Arrival Time | 5.673
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[0]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.673 | 0.846 | tNET | FF | 1 | R45C33[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R45C33[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[0]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[0]
7.700 | -0.035 | tSu |  | 1 | R45C33[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_fast_Z[0]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.846, 78.473%; tC2Q: 0.232, 21.527%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path9

Path Summary:

Slack | 2.027
Data Arrival Time | 5.673
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[1]_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.673 | 0.846 | tNET | FF | 1 | R45C33[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[1]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R45C33[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[1]_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[1]_Z
7.700 | -0.035 | tSu |  | 1 | R45C33[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[1]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.846, 78.473%; tC2Q: 0.232, 21.527%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path10

Path Summary:

Slack | 2.027
Data Arrival Time | 5.673
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.673 | 0.846 | tNET | FF | 1 | R45C33[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R45C33[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z
7.700 | -0.035 | tSu |  | 1 | R45C33[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[1]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.846, 78.473%; tC2Q: 0.232, 21.527%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path11

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z
7.700 | -0.035 | tSu |  | 1 | R44C36[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Empty_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path12

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[2]_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C37[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[2]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C37[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[2]_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[2]_Z
7.700 | -0.035 | tSu |  | 1 | R44C37[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[2]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path13

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[5]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C36[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C36[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[5]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[5]
7.700 | -0.035 | tSu |  | 1 | R44C36[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[5]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path14

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[4]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C36[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C36[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[4]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[4]
7.700 | -0.035 | tSu |  | 1 | R44C36[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[4]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path15

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[3]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C36[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C36[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[3]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[3]
7.700 | -0.035 | tSu |  | 1 | R44C36[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[3]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path16

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[10]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C37[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C37[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[10]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[10]
7.700 | -0.035 | tSu |  | 1 | R44C37[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[10]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path17

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C36[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C36[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]
7.700 | -0.035 | tSu |  | 1 | R44C36[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[9]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path18

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C37[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C37[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z
7.700 | -0.035 | tSu |  | 1 | R44C37[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path19

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C37[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C37[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]
7.700 | -0.035 | tSu |  | 1 | R44C37[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq1_wptr_Z[5]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path20

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[2]_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C37[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[2]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C37[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[2]_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[2]_Z
7.700 | -0.035 | tSu |  | 1 | R44C37[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[2]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path21

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[2]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C36[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C36[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[2]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[2]
7.700 | -0.035 | tSu |  | 1 | R44C36[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[2]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path22

Path Summary:

Slack | 2.030
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[7]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.842 | tNET | FF | 1 | R44C37[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R44C37[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[7]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[7]
7.700 | -0.035 | tSu |  | 1 | R44C37[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[7]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 78.395%; tC2Q: 0.232, 21.605%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path23

Path Summary:

Slack | 2.031
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.841 | tNET | FF | 1 | R45C35[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R45C35[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z
7.700 | -0.035 | tSu |  | 1 | R45C35[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rptr_Z[4]_Z

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.841, 78.385%; tC2Q: 0.232, 21.615%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path24

Path Summary:

Slack | 2.031
Data Arrival Time | 5.669
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[11]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.669 | 0.841 | tNET | FF | 1 | R45C35[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[11]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R45C35[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[11]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[11]
7.700 | -0.035 | tSu |  | 1 | R45C35[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[11]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.841, 78.385%; tC2Q: 0.232, 21.615%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Path25

Path Summary:

Slack | 2.039
Data Arrival Time | 5.661
Data Required Time | 7.700
From | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]
Launch Clk | pixel_clk:[F]
Latch Clk | pixel_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
3.367 | 3.367 |  |  |  |  | active clock edge time
3.367 | 0.000 |  |  |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | 1 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/CLK
4.827 | 0.232 | tC2Q | FF | 54 | R45C40[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/reset_r_Z[1]/Q
5.661 | 0.834 | tNET | FF | 1 | R43C38[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
6.734 | 6.734 |  |  |  |  | active clock edge time
6.734 | 0.000 |  |  |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | 428 | PLL_R[1] | pix_pll_inst/rpll_inst/CLKOUT
7.935 | 1.201 | tNET | RR | 1 | R43C38[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]/CLK
7.735 | -0.200 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]
7.700 | -0.035 | tSu |  | 1 | R43C38[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/rbin_num_Z[8]

Path Statistics:

Clock Skew | -0.028
Setup Relationship | 3.367
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.834, 78.230%; tC2Q: 0.232, 21.770%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000%

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[5]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R44C40[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R44C40[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[5]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[5]
0.913 | 0.011 | tHld |  | 1 | R44C40[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[5]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path2

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[2]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R44C39[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R44C39[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[2]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[2]
0.913 | 0.011 | tHld |  | 1 | R44C39[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path3

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C36[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C36[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]
0.913 | 0.011 | tHld |  | 1 | R41C36[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path4

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[0]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R44C39[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R44C39[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[0]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[0]
0.913 | 0.011 | tHld |  | 1 | R44C39[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path5

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C37[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C37[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast
0.913 | 0.011 | tHld |  | 1 | R41C37[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_req_o_fast

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path6

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[0]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R42C40[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R42C40[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[0]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[0]
0.913 | 0.011 | tHld |  | 1 | R42C40[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path7

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C37[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C37[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast
0.913 | 0.011 | tHld |  | 1 | R41C37[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_fast

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path8

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]
0.913 | 0.011 | tHld |  | 1 | R41C35[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path9

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[2]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[2]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[2]
0.913 | 0.011 | tHld |  | 1 | R41C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path10

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[1]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C35[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C35[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[1]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[1]
0.913 | 0.011 | tHld |  | 1 | R41C35[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path11

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[1]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R42C28[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R42C28[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[1]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[1]
0.913 | 0.011 | tHld |  | 1 | R42C28[1][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path12

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C34[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C34[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z
0.913 | 0.011 | tHld |  | 1 | R41C34[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path13

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_Z
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C34[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_Z/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C34[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_Z/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_Z
0.913 | 0.011 | tHld |  | 1 | R41C34[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path14

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[3]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[3]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[3]
0.913 | 0.011 | tHld |  | 1 | R41C34[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path15

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[8]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R43C30[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R43C30[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[8]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[8]
0.913 | 0.011 | tHld |  | 1 | R43C30[0][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path16

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[17]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R39C33[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[17]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R39C33[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[17]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[17]
0.913 | 0.011 | tHld |  | 1 | R39C33[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[17]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path17

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[15]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R40C34[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[15]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R40C34[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[15]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[15]
0.913 | 0.011 | tHld |  | 1 | R40C34[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[15]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path18

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[7]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R47C30[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R47C30[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[7]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[7]
0.913 | 0.011 | tHld |  | 1 | R47C30[2][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path19

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d1_Z
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R45C30[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d1_Z/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R45C30[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d1_Z/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d1_Z
0.913 | 0.011 | tHld |  | 1 | R45C30[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d1_Z

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path20

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[4]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[4]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[4]
0.913 | 0.011 | tHld |  | 1 | R41C34[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path21

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[7]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R40C33[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R40C33[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[7]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[7]
0.913 | 0.011 | tHld |  | 1 | R40C33[0][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[7]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path22

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[6]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R41C34[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R41C34[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[6]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[6]
0.913 | 0.011 | tHld |  | 1 | R41C34[1][B] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path23

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[20]
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R44C30[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[20]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R44C30[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[20]/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[20]
0.913 | 0.011 | tHld |  | 1 | R44C30[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr[20]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path24

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R43C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R43C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o
0.913 | 0.011 | tHld |  | 1 | R43C35[2][A] | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

### Path25

Path Summary:

Slack | 1.484
Data Arrival Time | 2.397
Data Required Time | 0.913
From | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]
To | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant
Launch Clk | dma_clk:[R]
Latch Clk | dma_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/CLK
1.104 | 0.202 | tC2Q | RR | 610 | R24C15[0][A] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_0[3]/Q
2.397 | 1.293 | tNET | RR | 1 | R42C29[1][B] | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | dma_clk
0.000 | 0.000 | tCL | RR | 2134 | LEFTSIDE[0] | DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clkdiv/CLKOUT
0.902 | 0.902 | tNET | RR | 1 | R42C29[1][B] | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant/CLK
0.902 | 0.000 | tUnc |  |  |  | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant
0.913 | 0.011 | tHld |  | 1 | R42C29[1][B] | vfb_top_inst/vfb_wrapper_inst/u_dma_bus_arbiter/dma0_rd_grant

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.293, 86.489%; tC2Q: 0.202, 13.511%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000%

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | pixel_clk
Objects: | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/video_vs_n_d1_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/video_vs_n_d1_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | pix_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/video_vs_n_d1_Z/CLK

### MPW2

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | pixel_clk
Objects: | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | pix_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_Z/CLK

### MPW3

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | pixel_clk
Objects: | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | pix_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_32b/CLK

### MPW4

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | pixel_clk
Objects: | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | pix_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b[3]/CLK

### MPW5

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | pixel_clk
Objects: | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b[10]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b[10]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | pix_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b[10]/CLK

### MPW6

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | pixel_clk
Objects: | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | pix_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | vfb_top_inst/vfb_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_dma_read_128_32_inst/fifo_inst/Small.rq2_wptr_Z[5]_Z/CLK

### MPW7

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | pixel_clk
Objects: | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_Z[7]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_Z[7]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | pix_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_hs_cnt_Z[7]/CLK

### MPW8

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | pixel_clk
Objects: | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vout_de_gen_d1_Z

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | pixel_clk
3.367 | 0.000 | tCL | FF | pix_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vout_de_gen_d1_Z/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | pixel_clk
6.734 | 0.000 | tCL | RR | pix_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vout_de_gen_d1_Z/CLK

### MPW9

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll
Objects: | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_vres[10]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | gw_pll
3.367 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_vres[10]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | gw_pll
6.734 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | Scaler_Top_inst/scaler_wrapper_inst/mode_control_inst/vin_vres[10]/CLK

### MPW10

MPW Summary:

Slack: | 2.041
Actual Width: | 3.041
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | gw_pll
Objects: | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
3.367 | 0.000 |  |  | active clock edge time
3.367 | 0.000 |  |  | gw_pll
3.367 | 0.000 | tCL | FF | gw_pll_inst/rpll_inst/CLKOUT
4.595 | 1.228 | tNET | FF | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
6.734 | 0.000 |  |  | active clock edge time
6.734 | 0.000 |  |  | gw_pll
6.734 | 0.000 | tCL | RR | gw_pll_inst/rpll_inst/CLKOUT
7.636 | 0.902 | tNET | RR | Scaler_Top_inst/scaler_wrapper_inst/scaler_core_inst/hor_calc_wrapper_inst/hor_coord_trans_inst/framedecnt_Z[2]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
2134 | dma_clk | 2.834 | 1.228
1172 | clkout | 0.940 | 1.228
610 | init_calib_complete | 2.834 | 2.415
428 | pixel_clk | 0.264 | 1.228
300 | I_clk_c | 13.018 | 1.228
295 | frame_rst | 1.579 | 2.063
283 | rvalid[0] | 8.879 | 2.064
246 | clkoutd | 4.996 | 1.228
201 | oram_wraddr14 | 1.754 | 1.350
192 | un1_vval_limit_en_1_i_sx_RNII8VE | 0.940 | 2.750

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R44C34 | 84.72%
R12C19 | 76.39%
R38C41 | 76.39%
R19C38 | 73.61%
R43C12 | 72.22%
R45C32 | 72.22%
R43C14 | 69.44%
R39C38 | 69.44%
R10C17 | 69.44%
R19C41 | 69.44%

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---
TC_CLOCK | Actived | create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add
TC_CLOCK | Actived | create_clock -name pixel_clk -period 6.734 -waveform {0 3.367} [get_nets {pixel_clk}] -add
TC_CLOCK | Actived | create_clock -name dma_clk -period 13.333 -waveform {0 6.667} [get_nets {dma_clk}] -add
TC_CLOCK | Actived | create_clock -name gw_pll -period 6.734 -waveform {0 3.367} [get_nets {clkout}] -add
TC_CLOCK | Actived | create_clock -name clk_x4 -period 3.333 -waveform {0 1.667} [get_nets {DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4}] -add
TC_CLOCK | Actived | create_clock -name clk_x4i -period 3.333 -waveform {0 1.667} [get_nets {DDR3_Memory_Interface_Top_inst/genblk1.gw3mc_top/u_ddr_phy_top/clk_x4i}] -add
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {dma_clk}]
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {I_clk}]
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {clk_x4i}]
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {clk_x4}]
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {pixel_clk}]
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {gw_pll}]