<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\rev_1\synlog\ddr3_memory_interface_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>DDR3_Memory_Interface_Top|clk</data>
<data>292.1 MHz</data>
<data>248.3 MHz</data>
<data>-0.604</data>
</row>
<row>
<data>_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsr90_inferred_clock</data>
<data>150.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw0_inferred_clock</data>
<data>150.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_0|dqsw270_inferred_clock</data>
<data>150.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsr90_inferred_clock</data>
<data>150.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw0_inferred_clock</data>
<data>150.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>_~ddr_phy_data_io_DDR3_Memory_Interface_Top__16s_8s_2500s_5s_5s_1|dqsw270_inferred_clock</data>
<data>150.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x1_inferred_clock</data>
<data>158.6 MHz</data>
<data>134.8 MHz</data>
<data>-1.113</data>
</row>
<row>
<data>_~ddr_phy_top_DDR3_Memory_Interface_Top__Z4|clk_x4i_inferred_clock</data>
<data>150.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>System</data>
<data>726.6 MHz</data>
<data>617.7 MHz</data>
<data>-0.243</data>
</row>
</report_table>
