
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys HDL compiler and linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

Modified Files: 12
FID:  path (prevtimestamp, timestamp)
0        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26)
1        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26)
2        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26)
3        D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\generic\gw2a.v (N/A, 2020-05-12 03:01:26)
4        D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\hypermods.v (N/A, 2020-05-12 03:02:52)
5        D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\scemi_objects.v (N/A, 2020-05-12 03:02:52)
6        D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\scemi_pipes.svh (N/A, 2020-05-12 03:02:52)
7        D:\Gowin\Gowin_V1.9.6Beta\SynplifyPro\lib\vlog\umr_capim.v (N/A, 2020-05-12 03:02:52)
8        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11)
9        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11)
10       D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11)
11       D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11)

*******************************************************************
Modules that may have changed as a result of file changes: 26
MID:  lib.cell.view
0        work.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
1        work.\~CMD_FIFO.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
2        work.\~IN_FIFO.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
3        work.\~OUT_FIFO.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
4        work.\~ddr_init.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
5        work.\~ddr_memmem_sync.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
6        work.\~ddr_phy_cmd_io.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
7        work.\~ddr_phy_cmd_lane.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
8        work.\~ddr_phy_data_io.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
9        work.\~ddr_phy_data_lane.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
10       work.\~ddr_phy_reset_gen.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
11       work.\~ddr_phy_top.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
12       work.\~ddr_phy_wd.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
13       work.\~ecc_decoder.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
14       work.\~ecc_encoder.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
15       work.\~ecc_top.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
16       work.\~fifo_ctrl.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
17       work.\~fifo_sc.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
18       work.\~gw3_phy_mc.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
19       work.\~gwmc_bank_ctrl.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
20       work.\~gwmc_cmd_buffer.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
21       work.\~gwmc_rank_ctrl.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
22       work.\~gwmc_rd_data.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
23       work.\~gwmc_timing_ctrl.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
24       work.\~gwmc_top.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
25       work.\~gwmc_wr_data.DDR3_Memory_Interface_Top.verilog may have changed because the following files changed:
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\DDR3_TOP.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\ddr3_1_4code.v (N/A, 2020-06-08 15:21:26) <-- (module definition)
                        D:\Gowin\Gowin_V1.9.6Beta\IDE\ipcore\DDR3\data\gwmc_local_param.v (N/A, 2020-06-08 15:21:26) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\DDR3_define.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_name.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\ddr3_pll_config.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)
                        D:\proj\scaler_example_design_memory\project\src\ddr3_memory_interface\temp\DDR3\gwmc_param.v (N/A, 2020-06-17 17:50:11) <-- (may instantiate this module)

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Unmodified files: 0
FID:  path (timestamp)

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Unchanged modules: 0
MID:  lib.cell.view
