Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu.v
D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.8Beta
Part Number GW1NSER-LV4CQN48GC7/I6
Device GW1NSER-4C
Created Time Mon Aug 02 16:21:59 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 40.188MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 40.188MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 40.188MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 40.188MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 40.188MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 40.188MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 40.188MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 40.188MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 40.188MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 40.188MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 40.188MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 40.188MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.433s, Peak memory usage = 54.137MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 54.137MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 54.137MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 54.137MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4
I/O Buf 4
    IBUF 3
    OBUF 1
Register 127
    DFFP 1
    DFFPE 2
    DFFC 49
    DFFCE 59
    DFFNCE 16
LUT 143
    LUT2 31
    LUT3 59
    LUT4 53
INV 2
    INV 2
BSRAM 4
    SP 4
Black Box 1
    EMCU 1
User Flash 1
    FLASH256K 1

Resource Utilization Summary

Resource Usage Utilization
Logic 145(145 LUTs, 0 ALUs) / 4608 3%
Register 127 / 3573 4%
  --Register as Latch 0 / 3573 0%
  --Register as FF 127 / 3573 4%
BSRAM 4 / 10 40%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
sys_clk Base 10.000 100.0 0.000 5.000 sys_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk 100.0(MHz) 90.4(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.534
Data Arrival Time 6.322
Data Required Time 5.789
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 131 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/CLK
1.336 0.340 tC2Q RF 7 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/I1
2.506 0.814 tINS FF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/I1
3.676 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/F
4.032 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/I1
4.846 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/F
5.202 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/I0
5.967 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/F
6.322 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 131 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 5.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.208, 60.231%; route: 1.778, 33.392%; tC2Q: 0.340, 6.377%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 2

Path Summary:
Slack -0.534
Data Arrival Time 6.322
Data Required Time 5.789
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 131 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/CLK
1.336 0.340 tC2Q RF 7 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/I1
2.506 0.814 tINS FF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/I1
3.676 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/F
4.032 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/I1
4.846 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/F
5.202 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/I0
5.967 0.765 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/F
6.322 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 131 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 5.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.208, 60.231%; route: 1.778, 33.392%; tC2Q: 0.340, 6.377%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack -0.378
Data Arrival Time 6.167
Data Required Time 5.789
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 131 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/CLK
1.336 0.340 tC2Q RF 7 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/I1
2.506 0.814 tINS FF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n613_s2/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/I1
3.676 0.814 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/F
4.032 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/I2
4.641 0.609 tINS FF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/F
4.997 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/I1
5.811 0.814 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/F
6.167 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 131 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 5.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.052, 59.034%; route: 1.778, 34.397%; tC2Q: 0.340, 6.569%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack 0.997
Data Arrival Time 4.791
Data Required Time 5.789
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 131 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n95_s1/I1
2.506 0.814 tINS FF 3 Gowin_EMPU_inst/u_flash_wrap/n95_s1/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n77_s1/I2
3.471 0.609 tINS FF 14 Gowin_EMPU_inst/u_flash_wrap/n77_s1/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n157_s0/I2
4.436 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n157_s0/F
4.791 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 131 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_0_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 5.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 2.033, 53.561%; route: 1.423, 37.490%; tC2Q: 0.340, 8.949%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 5

Path Summary:
Slack 0.997
Data Arrival Time 4.791
Data Required Time 5.789
From Gowin_EMPU_inst/u_flash_wrap/hready_out_s1
To Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3
Launch Clk sys_clk[F]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.728 0.728 tINS RR 131 sys_clk_ibuf/O
0.997 0.269 tNET RR 1 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/CLK
1.336 0.340 tC2Q RF 5 Gowin_EMPU_inst/u_flash_wrap/hready_out_s1/Q
1.692 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n95_s1/I1
2.506 0.814 tINS FF 3 Gowin_EMPU_inst/u_flash_wrap/n95_s1/F
2.862 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n77_s1/I2
3.471 0.609 tINS FF 14 Gowin_EMPU_inst/u_flash_wrap/n77_s1/F
3.827 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/n156_s0/I2
4.436 0.609 tINS FF 1 Gowin_EMPU_inst/u_flash_wrap/n156_s0/F
4.791 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 sys_clk
5.000 0.000 tCL FF 1 sys_clk_ibuf/I
5.729 0.729 tINS FF 131 sys_clk_ibuf/O
6.085 0.356 tNET FF 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3/CLK
5.789 -0.296 tSu 1 Gowin_EMPU_inst/u_flash_wrap/rom_addr_1_s3
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 5.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 2.033, 53.561%; route: 1.423, 37.490%; tC2Q: 0.340, 8.949%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%