Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu.v
D:\Gowin\Gowin_V1.9.8Beta\IDE\ipcore\GOWIN_EMPU\data\gowin_empu_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.8Beta
Part Number GW1NSE-UX2CLQ144C5/I4
Device GW1NSE-2C
Created Time Mon Aug 02 15:35:05 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 41.746MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 41.746MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 41.746MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 41.746MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 41.746MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 41.746MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.746MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 41.746MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 41.746MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 41.746MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 41.746MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 41.746MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.979s, Peak memory usage = 55.605MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 55.605MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 55.605MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 55.605MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4
I/O Buf 4
    IBUF 3
    OBUF 1
Register 255
    DFFP 1
    DFFPE 6
    DFFC 53
    DFFCE 192
    DFFNCE 3
LUT 302
    LUT2 32
    LUT3 106
    LUT4 164
ALU 18
    ALU 18
INV 3
    INV 3
BSRAM 4
    SP 4
CLOCK 2
    CLKDIV 1
    DQCE 1
User Flash 1
    FLASH128K 1
MCU 1
ADC 1

Resource Utilization Summary

Resource Usage Utilization
Logic 323(305 LUTs, 18 ALUs) / 1728 19%
Register 255 / 1533 17%
  --Register as Latch 0 / 1533 0%
  --Register as FF 255 / 1533 17%
BSRAM 4 / 4 100%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 DEFAULT_CLK Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk 50.0(MHz) 53.5(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.662
Data Arrival Time 9.892
Data Required Time 10.554
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3
Launch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
0.454 0.454 tCL RR 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
0.908 0.454 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/CLK
1.481 0.573 tC2Q RF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/Q
2.081 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/I1
3.455 1.374 tINS FF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/F
4.055 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/I1
5.429 1.374 tINS FF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/F
6.029 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/I1
7.402 1.374 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s13/F
8.002 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/I0
9.292 1.290 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/F
9.892 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
10.454 0.454 tCL FF 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
11.054 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/CLK
10.554 -0.500 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3
Path Statistics:
Clock Skew: 0.146
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%
Arrival Data Path Delay: cell: 5.411, 60.231%; route: 3.000, 33.392%; tC2Q: 0.573, 6.377%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%

Path 2

Path Summary:
Slack 0.662
Data Arrival Time 9.892
Data Required Time 10.554
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3
Launch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
0.454 0.454 tCL RR 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
0.908 0.454 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/CLK
1.481 0.573 tC2Q RF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/Q
2.081 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/I1
3.455 1.374 tINS FF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/F
4.055 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/I1
5.429 1.374 tINS FF 4 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s17/F
6.029 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s14/I1
7.402 1.374 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s14/F
8.002 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/I0
9.292 1.290 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/F
9.892 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
10.454 0.454 tCL FF 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
11.054 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK
10.554 -0.500 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3
Path Statistics:
Clock Skew: 0.146
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%
Arrival Data Path Delay: cell: 5.411, 60.231%; route: 3.000, 33.392%; tC2Q: 0.573, 6.377%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%

Path 3

Path Summary:
Slack 1.008
Data Arrival Time 9.546
Data Required Time 10.554
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3
Launch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
0.454 0.454 tCL RR 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
0.908 0.454 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/CLK
1.481 0.573 tC2Q RF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/Q
2.081 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/I1
3.455 1.374 tINS FF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/F
4.055 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s25/I1
5.429 1.374 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s25/F
6.029 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s15/I2
7.056 1.028 tINS FF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s15/F
7.656 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/I0
8.946 1.290 tINS FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/F
9.546 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
10.454 0.454 tCL FF 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
11.054 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/CLK
10.554 -0.500 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3
Path Statistics:
Clock Skew: 0.146
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%
Arrival Data Path Delay: cell: 5.065, 58.636%; route: 3.000, 34.731%; tC2Q: 0.573, 6.633%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%

Path 4

Path Summary:
Slack 3.827
Data Arrival Time 7.174
Data Required Time 11.000
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3
Launch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
0.454 0.454 tCL RR 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
0.908 0.454 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/CLK
1.481 0.573 tC2Q RF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/Q
2.081 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/I1
3.455 1.374 tINS FF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/F
4.055 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s6/I3
4.837 0.782 tINS FF 5 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s6/F
5.437 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s4/I0
6.720 1.283 tINS FR 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s4/F
7.174 0.454 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
10.454 0.454 tCL FF 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
11.054 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/CLK
11.000 -0.054 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3
Path Statistics:
Clock Skew: 0.146
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%
Arrival Data Path Delay: cell: 3.439, 54.885%; route: 2.254, 35.971%; tC2Q: 0.573, 9.144%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%

Path 5

Path Summary:
Slack 3.827
Data Arrival Time 7.174
Data Required Time 11.000
From Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0
To Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3
Launch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[F]
Latch Clk Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
0.454 0.454 tCL RR 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
0.908 0.454 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/CLK
1.481 0.573 tC2Q RF 2 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/reg_clksel_0_s0/Q
2.081 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/I1
3.455 1.374 tINS FF 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s4/F
4.055 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s6/I3
4.837 0.782 tINS FF 5 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n764_s6/F
5.437 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s4/I0
6.720 1.283 tINS FR 3 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s4/F
7.174 0.454 tNET RR 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT.default_gen_clk
10.454 0.454 tCL FF 260 Gowin_EMPU_inst/sysclk/clkdiv_inst/CLKOUT
11.054 0.600 tNET FF 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/CLK
11.000 -0.054 tSu 1 Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3
Path Statistics:
Clock Skew: 0.146
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%
Arrival Data Path Delay: cell: 3.439, 54.885%; route: 2.254, 35.971%; tC2Q: 0.573, 9.144%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.454, 100.000%