Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.03\IDE\ipcore\UARTMASTER\data\uart_master_top.v
C:\Gowin\Gowin_V1.9.8.03\IDE\ipcore\UARTMASTER\data\uart_master_encrypt.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.03
Part Number GW1N-LV4LQ144C6/I5
Device GW1N-4
Created Time Fri Jan 21 11:22:50 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module UART_MASTER_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.228s, Peak memory usage = 44.355MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 44.355MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 44.355MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 44.355MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 44.355MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 44.355MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 44.355MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 44.355MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 44.355MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 44.355MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 44.355MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 44.355MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.768s, Peak memory usage = 55.246MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 55.246MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 55.246MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 55.246MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 38
I/O Buf 38
    IBUF 23
    OBUF 15
Register 208
    DFFS 2
    DFFR 3
    DFFP 11
    DFFPE 11
    DFFC 117
    DFFCE 64
LUT 257
    LUT2 58
    LUT3 76
    LUT4 123
ALU 8
    ALU 8
INV 10
    INV 10
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 275(267 LUTs, 8 ALUs) / 4608 6%
Register 208 / 3756 6%
  --Register as Latch 0 / 3756 0%
  --Register as FF 208 / 3756 6%
BSRAM 2 / 10 20%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_CLK Base 20.000 50.0 0.000 10.000 I_CLK_ibuf/I
rxclk_Z Base 20.000 50.0 0.000 10.000 i4/u_baudset/rxclk_s1/Q

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_CLK 50.0(MHz) 112.8(MHz) 7 TOP
2 rxclk_Z 50.0(MHz) 166.4(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 11.138
Data Arrival Time 9.807
Data Required Time 20.945
From i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rbin_0_s0
To i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0
Launch Clk I_CLK[R]
Latch Clk I_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_CLK
0.000 0.000 tCL RR 1 I_CLK_ibuf/I
0.982 0.982 tINS RR 162 I_CLK_ibuf/O
1.345 0.363 tNET RR 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rbin_0_s0/CLK
1.803 0.458 tC2Q RF 3 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rbin_0_s0/Q
2.283 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rbinnext_1_s5/I1
3.382 1.099 tINS FF 7 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rbinnext_1_s5/F
3.862 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rbinnext_1_s3/I1
4.961 1.099 tINS FF 2 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rbinnext_1_s3/F
5.441 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rgraynext_1_s1/I0
6.473 1.032 tINS FF 2 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rgraynext_1_s1/F
6.953 0.480 tNET FF 2 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/n51_s0/I0
7.911 0.958 tINS FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/n51_s0/COUT
7.911 0.000 tNET FF 2 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/n52_s0/CIN
7.968 0.057 tINS FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/n52_s0/COUT
7.968 0.000 tNET FF 2 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/n53_s0/CIN
8.025 0.057 tINS FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/n53_s0/COUT
8.505 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rempty_val_s1/I2
9.327 0.822 tINS FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rempty_val_s1/F
9.807 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_CLK
20.000 0.000 tCL RR 1 I_CLK_ibuf/I
20.982 0.982 tINS RR 162 I_CLK_ibuf/O
21.345 0.363 tNET RR 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0/CLK
20.945 -0.400 tSu 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 5.124, 60.551%; route: 2.880, 34.033%; tC2Q: 0.458, 5.416%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 11.725
Data Arrival Time 9.220
Data Required Time 20.945
From i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0
To i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0
Launch Clk I_CLK[R]
Latch Clk I_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_CLK
0.000 0.000 tCL RR 1 I_CLK_ibuf/I
0.982 0.982 tINS RR 162 I_CLK_ibuf/O
1.345 0.363 tNET RR 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0/CLK
1.803 0.458 tC2Q RF 6 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0/Q
2.283 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rgraynext_0_s1/I0
3.315 1.032 tINS FF 2 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rgraynext_0_s1/F
3.795 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rgraynext_3_s1/I3
4.421 0.626 tINS FF 3 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rgraynext_3_s1/F
4.901 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rgraynext_3_s0/I1
6.000 1.099 tINS FF 2 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rgraynext_3_s0/F
6.480 0.480 tNET FF 2 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/n53_s0/I0
7.438 0.958 tINS FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/n53_s0/COUT
7.918 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rempty_val_s1/I2
8.740 0.822 tINS FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rempty_val_s1/F
9.220 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_CLK
20.000 0.000 tCL RR 1 I_CLK_ibuf/I
20.982 0.982 tINS RR 162 I_CLK_ibuf/O
21.345 0.363 tNET RR 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0/CLK
20.945 -0.400 tSu 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_rptr_empty/rempty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.537, 57.610%; route: 2.880, 36.570%; tC2Q: 0.458, 5.820%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 12.690
Data Arrival Time 8.255
Data Required Time 20.945
From i4/u_uart_sram/ThrWRn_re_s0
To i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0
Launch Clk I_CLK[R]
Latch Clk I_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_CLK
0.000 0.000 tCL RR 1 I_CLK_ibuf/I
0.982 0.982 tINS RR 162 I_CLK_ibuf/O
1.345 0.363 tNET RR 1 i4/u_uart_sram/ThrWRn_re_s0/CLK
1.803 0.458 tC2Q RF 7 i4/u_uart_sram/ThrWRn_re_s0/Q
2.283 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wbinnext_1_s4/I1
3.382 1.099 tINS FF 7 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wbinnext_1_s4/F
3.862 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wbinnext_3_s3/I1
4.961 1.099 tINS FF 3 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wbinnext_3_s3/F
5.441 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s1/I2
6.263 0.822 tINS FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s1/F
6.743 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s0/I0
7.775 1.032 tINS FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s0/F
8.255 0.480 tNET FF 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_CLK
20.000 0.000 tCL RR 1 I_CLK_ibuf/I
20.982 0.982 tINS RR 162 I_CLK_ibuf/O
21.345 0.363 tNET RR 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0/CLK
20.945 -0.400 tSu 1 i4/U_Txmitt/Tx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.052, 58.636%; route: 2.400, 34.731%; tC2Q: 0.458, 6.633%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 12.819
Data Arrival Time 8.126
Data Required Time 20.945
From i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0
To i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0
Launch Clk I_CLK[R]
Latch Clk I_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_CLK
0.000 0.000 tCL RR 1 I_CLK_ibuf/I
0.982 0.982 tINS RR 162 I_CLK_ibuf/O
1.345 0.363 tNET RR 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0/CLK
1.803 0.458 tC2Q RF 4 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0/Q
2.283 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wgraynext_2_s1/I1
3.382 1.099 tINS FF 7 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wgraynext_2_s1/F
3.862 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s4/I1
4.961 1.099 tINS FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s4/F
5.441 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s2/I1
6.540 1.099 tINS FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s2/F
7.020 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s0/I3
7.646 0.626 tINS FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_val_s0/F
8.126 0.480 tNET FF 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_CLK
20.000 0.000 tCL RR 1 I_CLK_ibuf/I
20.982 0.982 tINS RR 162 I_CLK_ibuf/O
21.345 0.363 tNET RR 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0/CLK
20.945 -0.400 tSu 1 i4/U_Rxcver/Rx_FIFO/u_uart_fifo/u_wptr_full/wfull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.923, 57.850%; route: 2.400, 35.391%; tC2Q: 0.458, 6.759%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 12.900
Data Arrival Time 8.045
Data Required Time 20.945
From i4/u_baudset/cnt1_5_s0
To i4/u_baudset/cnt1_3_s0
Launch Clk I_CLK[R]
Latch Clk I_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_CLK
0.000 0.000 tCL RR 1 I_CLK_ibuf/I
0.982 0.982 tINS RR 162 I_CLK_ibuf/O
1.345 0.363 tNET RR 1 i4/u_baudset/cnt1_5_s0/CLK
1.803 0.458 tC2Q RF 3 i4/u_baudset/cnt1_5_s0/Q
2.283 0.480 tNET FF 1 i4/u_baudset/n36_s2/I1
3.382 1.099 tINS FF 3 i4/u_baudset/n36_s2/F
3.862 0.480 tNET FF 1 i4/u_baudset/n34_s2/I2
4.684 0.822 tINS FF 2 i4/u_baudset/n34_s2/F
5.164 0.480 tNET FF 1 i4/u_baudset/rxclk_s3/I1
6.263 1.099 tINS FF 3 i4/u_baudset/rxclk_s3/F
6.743 0.480 tNET FF 1 i4/u_baudset/n39_s1/I2
7.565 0.822 tINS FF 1 i4/u_baudset/n39_s1/F
8.045 0.480 tNET FF 1 i4/u_baudset/cnt1_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_CLK
20.000 0.000 tCL RR 1 I_CLK_ibuf/I
20.982 0.982 tINS RR 162 I_CLK_ibuf/O
21.345 0.363 tNET RR 1 i4/u_baudset/cnt1_3_s0/CLK
20.945 -0.400 tSu 1 i4/u_baudset/cnt1_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.842, 57.341%; route: 2.400, 35.819%; tC2Q: 0.458, 6.840%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%