Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\USBSoftPHY\data\usb_softphy_top.v
C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\USBSoftPHY\data\usb_softphy.vp
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW1NSR-LV4MG64PC7/I6
Device GW1NSR-4
Created Time Mon Jul 11 09:33:00 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module USB_SoftPHY_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.297s, Peak memory usage = 34.461MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 34.461MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 34.461MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 34.461MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 34.461MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 34.461MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.461MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 34.461MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 34.461MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 34.461MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 34.461MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 34.461MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 44.605MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 44.605MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 44.605MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 44.605MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 32
I/O Buf 32
    IBUF 16
    OBUF 14
    IOBUF 2
Register 47
    DFFPE 2
    DFFC 25
    DFFCE 20
LUT 159
    LUT2 16
    LUT3 36
    LUT4 107

Resource Utilization Summary

Resource Usage Utilization
Logic 159(159 LUTs, 0 ALUs) / 4608 3%
Register 47 / 3621 1%
  --Register as Latch 0 / 3621 0%
  --Register as FF 47 / 3621 1%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 20.000 50.0 0.000 10.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 50.0(MHz) 148.3(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 13.257
Data Arrival Time 7.443
Data Required Time 20.700
From u_usb_phy/u_usb_phy_rt/rx_dn_q_s4
To u_usb_phy/u_usb_phy_rt/ones_count_q_0_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 47 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/CLK
1.336 0.340 tC2Q RF 7 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/Q
1.692 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/in_j_w_s1/I1
2.506 0.814 tINS FF 6 u_usb_phy/u_usb_phy_rt/in_j_w_s1/F
2.862 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n527_s6/I1
3.676 0.814 tINS FF 3 u_usb_phy/u_usb_phy_rt/n527_s6/F
4.032 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n362_s4/I0
4.797 0.765 tINS FF 1 u_usb_phy/u_usb_phy_rt/n362_s4/F
5.152 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n362_s3/I0
5.917 0.765 tINS FF 3 u_usb_phy/u_usb_phy_rt/n362_s3/F
6.273 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n363_s2/I1
7.087 0.814 tINS FF 1 u_usb_phy/u_usb_phy_rt/n363_s2/F
7.443 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/ones_count_q_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 47 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/ones_count_q_0_s1/CLK
20.700 -0.296 tSu 1 u_usb_phy/u_usb_phy_rt/ones_count_q_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.973, 61.625%; route: 2.134, 33.106%; tC2Q: 0.340, 5.269%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 2

Path Summary:
Slack 13.307
Data Arrival Time 7.393
Data Required Time 20.700
From u_usb_phy/u_usb_phy_rt/rx_dn_q_s4
To u_usb_phy/u_usb_phy_rt/ones_count_q_1_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 47 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/CLK
1.336 0.340 tC2Q RF 7 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/Q
1.692 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/in_j_w_s1/I1
2.506 0.814 tINS FF 6 u_usb_phy/u_usb_phy_rt/in_j_w_s1/F
2.862 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n527_s6/I1
3.676 0.814 tINS FF 3 u_usb_phy/u_usb_phy_rt/n527_s6/F
4.032 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n362_s4/I0
4.797 0.765 tINS FF 1 u_usb_phy/u_usb_phy_rt/n362_s4/F
5.152 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n362_s3/I0
5.917 0.765 tINS FF 3 u_usb_phy/u_usb_phy_rt/n362_s3/F
6.273 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n362_s2/I0
7.037 0.765 tINS FF 1 u_usb_phy/u_usb_phy_rt/n362_s2/F
7.393 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/ones_count_q_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 47 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/ones_count_q_1_s1/CLK
20.700 -0.296 tSu 1 u_usb_phy/u_usb_phy_rt/ones_count_q_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.923, 61.328%; route: 2.134, 33.363%; tC2Q: 0.340, 5.309%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack 13.307
Data Arrival Time 7.393
Data Required Time 20.700
From u_usb_phy/u_usb_phy_rt/rx_dn_q_s4
To u_usb_phy/u_usb_phy_rt/ones_count_q_2_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 47 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/CLK
1.336 0.340 tC2Q RF 7 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/Q
1.692 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/in_j_w_s1/I1
2.506 0.814 tINS FF 6 u_usb_phy/u_usb_phy_rt/in_j_w_s1/F
2.862 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n527_s6/I1
3.676 0.814 tINS FF 3 u_usb_phy/u_usb_phy_rt/n527_s6/F
4.032 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n362_s4/I0
4.797 0.765 tINS FF 1 u_usb_phy/u_usb_phy_rt/n362_s4/F
5.152 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n362_s3/I0
5.917 0.765 tINS FF 3 u_usb_phy/u_usb_phy_rt/n362_s3/F
6.273 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n361_s2/I0
7.037 0.765 tINS FF 1 u_usb_phy/u_usb_phy_rt/n361_s2/F
7.393 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/ones_count_q_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 47 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/ones_count_q_2_s1/CLK
20.700 -0.296 tSu 1 u_usb_phy/u_usb_phy_rt/ones_count_q_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.923, 61.328%; route: 2.134, 33.363%; tC2Q: 0.340, 5.309%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack 13.413
Data Arrival Time 7.287
Data Required Time 20.700
From u_usb_phy/u_usb_phy_rt/rx_dn_q_s4
To u_usb_phy/u_usb_phy_rt/state_q_0_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 47 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/CLK
1.336 0.340 tC2Q RF 7 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/Q
1.692 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/in_j_w_s1/I1
2.506 0.814 tINS FF 6 u_usb_phy/u_usb_phy_rt/in_j_w_s1/F
2.862 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n527_s6/I1
3.676 0.814 tINS FF 3 u_usb_phy/u_usb_phy_rt/n527_s6/F
4.032 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/next_state_r_0_s68/I0
4.797 0.765 tINS FF 1 u_usb_phy/u_usb_phy_rt/next_state_r_0_s68/F
5.152 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/next_state_r_0_s64/I1
5.967 0.814 tINS FF 1 u_usb_phy/u_usb_phy_rt/next_state_r_0_s64/F
6.322 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/next_state_r_0_s61/I2
6.931 0.609 tINS FF 1 u_usb_phy/u_usb_phy_rt/next_state_r_0_s61/F
7.287 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/state_q_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 47 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/state_q_0_s1/CLK
20.700 -0.296 tSu 1 u_usb_phy/u_usb_phy_rt/state_q_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.817, 60.676%; route: 2.134, 33.925%; tC2Q: 0.340, 5.399%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 5

Path Summary:
Slack 13.463
Data Arrival Time 7.238
Data Required Time 20.700
From u_usb_phy/u_usb_phy_rt/rx_dn_q_s4
To u_usb_phy/u_usb_phy_rt/tx_ready_q_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 47 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/CLK
1.336 0.340 tC2Q RF 7 u_usb_phy/u_usb_phy_rt/rx_dn_q_s4/Q
1.692 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/in_j_w_s1/I1
2.506 0.814 tINS FF 6 u_usb_phy/u_usb_phy_rt/in_j_w_s1/F
2.862 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n327_s2/I2
3.471 0.609 tINS FF 6 u_usb_phy/u_usb_phy_rt/n327_s2/F
3.827 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n327_s3/I0
4.591 0.765 tINS FF 18 u_usb_phy/u_usb_phy_rt/n327_s3/F
4.947 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n609_s2/I1
5.761 0.814 tINS FF 1 u_usb_phy/u_usb_phy_rt/n609_s2/F
6.117 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/n609_s1/I0
6.882 0.765 tINS FF 1 u_usb_phy/u_usb_phy_rt/n609_s1/F
7.238 0.356 tNET FF 1 u_usb_phy/u_usb_phy_rt/tx_ready_q_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.728 0.728 tINS RR 47 clk_i_ibuf/O
20.997 0.269 tNET RR 1 u_usb_phy/u_usb_phy_rt/tx_ready_q_s0/CLK
20.700 -0.296 tSu 1 u_usb_phy/u_usb_phy_rt/tx_ready_q_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.767, 60.363%; route: 2.134, 34.195%; tC2Q: 0.340, 5.442%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%