Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\TOP.v
C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\fifo_sc_top\fifo_sc_top.v
C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\gowin_pllvr\gowin_pllvr.v
C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\usb_descriptor.v
C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\usb_device_controller\usb_device_controller.v
C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\usb_softphy\usb_softphy.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW1NSR-LV4MG64PC7/I6
Device GW1NSR-4
Created Time Mon Jul 11 09:33:53 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.635s, Peak memory usage = 138.254MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 138.254MB
    Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 138.254MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 138.254MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 138.254MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 138.254MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 138.254MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 138.254MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 138.254MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 138.254MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 138.254MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 147.594MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.119s, Peak memory usage = 147.594MB
Generate output files:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 147.594MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 147.594MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 5
I/O Buf 5
    IBUF 2
    OBUF 1
    IOBUF 2
Register 512
    DFF 15
    DFFE 74
    DFFS 6
    DFFSE 3
    DFFR 22
    DFFRE 153
    DFFP 3
    DFFPE 8
    DFFC 106
    DFFCE 122
LUT 1264
    LUT2 141
    LUT3 363
    LUT4 760
ALU 118
    ALU 118
INV 3
    INV 3
BSRAM 2
    SDPB 2
CLOCK 1
    PLLVR 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1385(1267 LUTs, 118 ALUs) / 4608 30%
Register 512 / 3621 14%
  --Register as Latch 0 / 3621 0%
  --Register as FF 512 / 3621 14%
BSRAM 2 / 10 20%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
CLK_IN Base 83.333 12.0 0.000 41.667 CLK_IN_ibuf/I
u_pll/pllvr_inst/CLKOUT.default_gen_clk Generated 16.667 60.0 0.000 8.333 CLK_IN_ibuf/I CLK_IN u_pll/pllvr_inst/CLKOUT
u_pll/pllvr_inst/CLKOUTP.default_gen_clk Generated 16.667 60.0 0.000 8.333 CLK_IN_ibuf/I CLK_IN u_pll/pllvr_inst/CLKOUTP
u_pll/pllvr_inst/CLKOUTD.default_gen_clk Generated 33.333 30.0 0.000 16.667 CLK_IN_ibuf/I CLK_IN u_pll/pllvr_inst/CLKOUTD
u_pll/pllvr_inst/CLKOUTD3.default_gen_clk Generated 50.000 20.0 0.000 25.000 CLK_IN_ibuf/I CLK_IN u_pll/pllvr_inst/CLKOUTD3

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_pll/pllvr_inst/CLKOUT.default_gen_clk 60.0(MHz) 76.3(MHz) 14 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.558
Data Arrival Time 14.384
Data Required Time 17.942
From u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0
To u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_3_s0
Launch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
1.302 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
1.571 0.269 tNET RR 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/CLK
1.911 0.340 tC2Q RF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/Q
2.267 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/I1
3.081 0.814 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/F
3.437 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/I3
3.901 0.464 tINS FF 18 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/F
4.256 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/I2
4.865 0.609 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/F
5.221 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/I0
5.986 0.765 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/F
6.342 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/I1
7.156 0.814 tINS FF 14 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/F
7.512 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s16/I0
8.276 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s16/F
8.632 0.356 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n785_s0/I1
9.406 0.774 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n785_s0/COUT
9.406 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n786_s0/CIN
9.449 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n786_s0/COUT
9.449 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/CIN
9.491 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/COUT
9.491 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/CIN
9.533 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/COUT
9.533 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/CIN
9.575 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/COUT
9.575 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/CIN
9.618 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/COUT
9.618 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/CIN
9.660 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/COUT
9.660 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/CIN
9.702 0.042 tINS FF 4 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/COUT
10.058 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/I2
10.667 0.609 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/F
11.022 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/I0
11.787 0.765 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/F
12.143 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n973_s12/I0
12.908 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n973_s12/F
13.263 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n973_s11/I0
14.028 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n973_s11/F
14.384 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
16.667 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
17.969 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
18.238 0.269 tNET RR 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_3_s0/CLK
17.942 -0.296 tSu 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 16.667
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 8.204, 64.036%; route: 4.268, 33.313%; tC2Q: 0.340, 2.651%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%

Path 2

Path Summary:
Slack 3.558
Data Arrival Time 14.384
Data Required Time 17.942
From u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0
To u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_4_s0
Launch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
1.302 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
1.571 0.269 tNET RR 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/CLK
1.911 0.340 tC2Q RF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/Q
2.267 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/I1
3.081 0.814 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/F
3.437 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/I3
3.901 0.464 tINS FF 18 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/F
4.256 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/I2
4.865 0.609 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/F
5.221 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/I0
5.986 0.765 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/F
6.342 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/I1
7.156 0.814 tINS FF 14 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/F
7.512 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s16/I0
8.276 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s16/F
8.632 0.356 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n785_s0/I1
9.406 0.774 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n785_s0/COUT
9.406 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n786_s0/CIN
9.449 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n786_s0/COUT
9.449 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/CIN
9.491 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/COUT
9.491 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/CIN
9.533 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/COUT
9.533 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/CIN
9.575 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/COUT
9.575 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/CIN
9.618 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/COUT
9.618 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/CIN
9.660 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/COUT
9.660 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/CIN
9.702 0.042 tINS FF 4 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/COUT
10.058 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/I2
10.667 0.609 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/F
11.022 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/I0
11.787 0.765 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/F
12.143 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s12/I0
12.908 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s12/F
13.263 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s11/I0
14.028 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s11/F
14.384 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
16.667 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
17.969 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
18.238 0.269 tNET RR 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_4_s0/CLK
17.942 -0.296 tSu 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 16.667
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 8.204, 64.036%; route: 4.268, 33.313%; tC2Q: 0.340, 2.651%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%

Path 3

Path Summary:
Slack 3.714
Data Arrival Time 14.228
Data Required Time 17.942
From u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0
To u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_2_s0
Launch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
1.302 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
1.571 0.269 tNET RR 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/CLK
1.911 0.340 tC2Q RF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/Q
2.267 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/I1
3.081 0.814 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/F
3.437 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/I3
3.901 0.464 tINS FF 18 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/F
4.256 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/I2
4.865 0.609 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/F
5.221 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/I0
5.986 0.765 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/F
6.342 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/I1
7.156 0.814 tINS FF 14 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/F
7.512 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s16/I0
8.276 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s16/F
8.632 0.356 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n785_s0/I1
9.406 0.774 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n785_s0/COUT
9.406 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n786_s0/CIN
9.449 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n786_s0/COUT
9.449 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/CIN
9.491 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/COUT
9.491 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/CIN
9.533 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/COUT
9.533 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/CIN
9.575 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/COUT
9.575 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/CIN
9.618 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/COUT
9.618 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/CIN
9.660 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/COUT
9.660 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/CIN
9.702 0.042 tINS FF 4 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/COUT
10.058 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/I2
10.667 0.609 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/F
11.022 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/I0
11.787 0.765 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/F
12.143 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n976_s13/I2
12.752 0.609 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n976_s13/F
13.108 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n976_s11/I0
13.872 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n976_s11/F
14.228 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
16.667 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
17.969 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
18.238 0.269 tNET RR 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_2_s0/CLK
17.942 -0.296 tSu 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 16.667
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 8.049, 63.594%; route: 4.268, 33.723%; tC2Q: 0.340, 2.683%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%

Path 4

Path Summary:
Slack 3.869
Data Arrival Time 14.072
Data Required Time 17.942
From u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0
To u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2
Launch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
1.302 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
1.571 0.269 tNET RR 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/CLK
1.911 0.340 tC2Q RF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/Q
2.267 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/I1
3.081 0.814 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/F
3.437 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/I3
3.901 0.464 tINS FF 18 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/F
4.256 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/I2
4.865 0.609 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/F
5.221 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/I0
5.986 0.765 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/F
6.342 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/I1
7.156 0.814 tINS FF 14 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/F
7.512 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s16/I0
8.276 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s16/F
8.632 0.356 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n785_s0/I1
9.406 0.774 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n785_s0/COUT
9.406 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n786_s0/CIN
9.449 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n786_s0/COUT
9.449 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/CIN
9.491 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/COUT
9.491 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/CIN
9.533 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/COUT
9.533 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/CIN
9.575 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/COUT
9.575 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/CIN
9.618 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/COUT
9.618 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/CIN
9.660 0.042 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/COUT
9.660 0.000 tNET FF 2 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/CIN
9.702 0.042 tINS FF 4 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/COUT
10.058 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/I2
10.667 0.609 tINS FF 3 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/F
11.022 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s35/I0
11.787 0.765 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s35/F
12.143 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s36/I2
12.752 0.609 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s36/F
13.108 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s32/I2
13.717 0.609 tINS FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s32/F
14.072 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
16.667 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
17.969 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
18.238 0.269 tNET RR 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2/CLK
17.942 -0.296 tSu 1 u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 16.667
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 7.893, 63.140%; route: 4.268, 34.143%; tC2Q: 0.340, 2.717%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%

Path 5

Path Summary:
Slack 4.209
Data Arrival Time 13.733
Data Required Time 17.942
From u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12
To tx_fifo/fifo_sc_inst/Empty_s0
Launch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_pll/pllvr_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
1.302 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
1.571 0.269 tNET RR 1 u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK
1.911 0.340 tC2Q RF 7 u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q
2.267 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1
3.081 0.814 tINS FF 4 u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F
3.437 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3
3.901 0.464 tINS FF 6 u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F
4.256 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3
4.720 0.464 tINS FF 19 u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F
5.076 0.356 tNET FF 1 u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0
5.841 0.765 tINS FF 7 u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F
6.196 0.356 tNET FF 1 tx_fifo_rd_s0/I0
6.961 0.765 tINS FF 2 tx_fifo_rd_s0/F
7.317 0.356 tNET FF 1 tx_fifo/fifo_sc_inst/n78_s0/I1
8.131 0.814 tINS FF 1 tx_fifo/fifo_sc_inst/n78_s0/F
8.487 0.356 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_0_s/I1
9.261 0.774 tINS FF 1 tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT
9.261 0.000 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN
9.303 0.042 tINS FF 1 tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT
9.303 0.000 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN
9.346 0.042 tINS FF 1 tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT
9.346 0.000 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN
9.388 0.042 tINS FF 1 tx_fifo/fifo_sc_inst/rbin_next_3_s/COUT
9.388 0.000 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_4_s/CIN
9.430 0.042 tINS FF 1 tx_fifo/fifo_sc_inst/rbin_next_4_s/COUT
9.430 0.000 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_5_s/CIN
9.472 0.042 tINS FF 1 tx_fifo/fifo_sc_inst/rbin_next_5_s/COUT
9.472 0.000 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_6_s/CIN
9.515 0.042 tINS FF 1 tx_fifo/fifo_sc_inst/rbin_next_6_s/COUT
9.515 0.000 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_7_s/CIN
9.557 0.042 tINS FF 1 tx_fifo/fifo_sc_inst/rbin_next_7_s/COUT
9.557 0.000 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_8_s/CIN
9.599 0.042 tINS FF 1 tx_fifo/fifo_sc_inst/rbin_next_8_s/COUT
9.599 0.000 tNET FF 2 tx_fifo/fifo_sc_inst/rbin_next_9_s/CIN
10.016 0.417 tINS FF 4 tx_fifo/fifo_sc_inst/rbin_next_9_s/SUM
10.372 0.356 tNET FF 1 tx_fifo/fifo_sc_inst/n13_s3/I0
11.137 0.765 tINS FF 1 tx_fifo/fifo_sc_inst/n13_s3/F
11.492 0.356 tNET FF 1 tx_fifo/fifo_sc_inst/n13_s1/I0
12.257 0.765 tINS FF 2 tx_fifo/fifo_sc_inst/n13_s1/F
12.613 0.356 tNET FF 1 tx_fifo/fifo_sc_inst/rempty_val_s0/I0
13.377 0.765 tINS FF 1 tx_fifo/fifo_sc_inst/rempty_val_s0/F
13.733 0.356 tNET FF 1 tx_fifo/fifo_sc_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
16.667 0.000 u_pll/pllvr_inst/CLKOUT.default_gen_clk
17.969 1.302 tCL RR 516 u_pll/pllvr_inst/CLKOUT
18.238 0.269 tNET RR 1 tx_fifo/fifo_sc_inst/Empty_s0/CLK
17.942 -0.296 tSu 1 tx_fifo/fifo_sc_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 16.667
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 7.909, 65.036%; route: 3.912, 32.171%; tC2Q: 0.340, 2.793%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%