Synthesis Messages

Report Title GowinSynthesis Report
Design File F:\Winson\USB\Trunk\usb_device_controller\Demo\GW1NSR4\usb2jtag\src\fifo_sc_top\temp\FIFO_SC\fifo_sc_define.v
F:\Winson\USB\Trunk\usb_device_controller\Demo\GW1NSR4\usb2jtag\src\fifo_sc_top\temp\FIFO_SC\fifo_sc_parameter.v
C:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\FIFO_SC\data\edc_sc.v
C:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\FIFO_SC\data\fifo_sc.v
C:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\FIFO_SC\data\fifo_sc_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.6.02Beta
Created Time Thu Dec 31 14:54:55 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: fifo_sc_top
Part Number: GW1N-LV1QN48C6/I5

Resource

Resource Usage Summary

I/OPORT Usage: 32
I/OBUF Usage: 32
    IBUF 12
    OBUF 20
REG Usage: 32
    DFFP 1
    DFFC 31
LUT Usage: 18
    LUT2 5
    LUT4 13
ALU Usage: 30
    ALU 30
BSRAM Usage: 1
    SDPB 1

Resource Utilization Summary

Target Device: GW1N-1-QFN48
CFU Logics 48(18 LUTs, 30 ALUs) / 1152 4%
Registers 32 / 945 3%
BSRAMs 1 / 4 25%
DSP Macros 0 / (0*2) -


Timing

Clock Summary:

Clock Type Frequency Period Rise Fall Source Master Object
DEFAULT_CLK Base 100.0 MHz 10.000 0.000 5.000 Clk_ibuf/I

Timing Report:

Top View: fifo_sc_top
Requested Frequency: 100.0 MHz
Paths Requested: 5
Constraint File(ignored):
All time values displayed in nanoseconds(ns).

Performance Summary:

Worst Slack in Design: 0.035
Start Clock Slack Requested Frequency Estimated Frequency Requested Period Estimated Period Clock Type
DEFAULT_CLK 0.035 100.0 MHz 100.3 MHz 10.000 9.965 Base

Detail Timing Paths Information

Path information for path number 1 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(critical): 0.035
Data Arrival Time: 10.875
Data Required Time: 10.910
Number of Logic Level: 8
Starting Point: fifo_sc_inst/Empty_s0
Ending Point: fifo_sc_inst/Empty_s0
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
Clk_ibuf IBUF I In - 0.000 -
Clk_ibuf IBUF O Out 0.982 0.982 -
Clk_d Net - - 0.363 - 34
\fifo_sc_inst/Empty_s0 DFFP CLK In - 1.345 -
\fifo_sc_inst/Empty_s0 DFFP Q Out 0.458 1.803 -
Empty_d Net - - 0.480 - 3
\fifo_sc_inst/n78_s0 LUT2 I0 In - 2.283 -
\fifo_sc_inst/n78_s0 LUT2 F Out 1.032 3.315 -
n78_3 Net - - 0.480 - 1
\fifo_sc_inst/rbin_next_0_s ALU I1 In - 3.795 -
\fifo_sc_inst/rbin_next_0_s ALU COUT Out 1.045 4.840 -
fifo_sc_inst_rbin_next_0_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_1_s ALU CIN In - 4.840 -
\fifo_sc_inst/rbin_next_1_s ALU COUT Out 0.057 4.897 -
fifo_sc_inst_rbin_next_1_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_2_s ALU CIN In - 4.897 -
\fifo_sc_inst/rbin_next_2_s ALU COUT Out 0.057 4.954 -
fifo_sc_inst_rbin_next_2_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_3_s ALU CIN In - 4.954 -
\fifo_sc_inst/rbin_next_3_s ALU COUT Out 0.057 5.011 -
fifo_sc_inst_rbin_next_3_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_4_s ALU CIN In - 5.011 -
\fifo_sc_inst/rbin_next_4_s ALU COUT Out 0.057 5.068 -
fifo_sc_inst_rbin_next_4_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_5_s ALU CIN In - 5.068 -
\fifo_sc_inst/rbin_next_5_s ALU COUT Out 0.057 5.125 -
fifo_sc_inst_rbin_next_5_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_6_s ALU CIN In - 5.125 -
\fifo_sc_inst/rbin_next_6_s ALU COUT Out 0.057 5.182 -
fifo_sc_inst_rbin_next_6_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_7_s ALU CIN In - 5.182 -
\fifo_sc_inst/rbin_next_7_s ALU COUT Out 0.057 5.239 -
fifo_sc_inst_rbin_next_7_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_8_s ALU CIN In - 5.239 -
\fifo_sc_inst/rbin_next_8_s ALU COUT Out 0.057 5.296 -
fifo_sc_inst_rbin_next_8_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_9_s ALU CIN In - 5.296 -
\fifo_sc_inst/rbin_next_9_s ALU SUM Out 0.563 5.859 -
rbin_next[9] Net - - 0.480 - 4
\fifo_sc_inst/n13_s3 LUT4 I0 In - 6.339 -
\fifo_sc_inst/n13_s3 LUT4 F Out 1.032 7.371 -
n13_6 Net - - 0.480 - 1
\fifo_sc_inst/n13_s1 LUT4 I0 In - 7.851 -
\fifo_sc_inst/n13_s1 LUT4 F Out 1.032 8.883 -
n13_4 Net - - 0.480 - 2
\fifo_sc_inst/rempty_val_s0 LUT2 I0 In - 9.363 -
\fifo_sc_inst/rempty_val_s0 LUT2 F Out 1.032 10.395 -
rempty_val Net - - 0.480 - 1
\fifo_sc_inst/Empty_s0 DFFP D In - 10.875 -

Total Path Delay: 10.875
Logic Delay: 7.632(70.2%)
Route Delay: 3.243(29.8%)


Path information for path number 2 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 0.245
Data Arrival Time: 10.665
Data Required Time: 10.910
Number of Logic Level: 8
Starting Point: fifo_sc_inst/Full_s0
Ending Point: fifo_sc_inst/Full_s0
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
Clk_ibuf IBUF I In - 0.000 -
Clk_ibuf IBUF O Out 0.982 0.982 -
Clk_d Net - - 0.363 - 34
\fifo_sc_inst/Full_s0 DFFC CLK In - 1.345 -
\fifo_sc_inst/Full_s0 DFFC Q Out 0.458 1.803 -
Full_d Net - - 0.480 - 2
\fifo_sc_inst/n7_s1 LUT2 I0 In - 2.283 -
\fifo_sc_inst/n7_s1 LUT2 F Out 1.032 3.315 -
n7_5 Net - - 0.480 - 2
\fifo_sc_inst/wbin_next_0_s ALU I1 In - 3.795 -
\fifo_sc_inst/wbin_next_0_s ALU COUT Out 1.045 4.840 -
fifo_sc_inst_wbin_next_0_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wbin_next_1_s ALU CIN In - 4.840 -
\fifo_sc_inst/wbin_next_1_s ALU COUT Out 0.057 4.897 -
fifo_sc_inst_wbin_next_1_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wbin_next_2_s ALU CIN In - 4.897 -
\fifo_sc_inst/wbin_next_2_s ALU COUT Out 0.057 4.954 -
fifo_sc_inst_wbin_next_2_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wbin_next_3_s ALU CIN In - 4.954 -
\fifo_sc_inst/wbin_next_3_s ALU COUT Out 0.057 5.011 -
fifo_sc_inst_wbin_next_3_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wbin_next_4_s ALU CIN In - 5.011 -
\fifo_sc_inst/wbin_next_4_s ALU COUT Out 0.057 5.068 -
fifo_sc_inst_wbin_next_4_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wbin_next_5_s ALU CIN In - 5.068 -
\fifo_sc_inst/wbin_next_5_s ALU COUT Out 0.057 5.125 -
fifo_sc_inst_wbin_next_5_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wbin_next_6_s ALU CIN In - 5.125 -
\fifo_sc_inst/wbin_next_6_s ALU COUT Out 0.057 5.182 -
fifo_sc_inst_wbin_next_6_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wbin_next_7_s ALU CIN In - 5.182 -
\fifo_sc_inst/wbin_next_7_s ALU COUT Out 0.057 5.239 -
fifo_sc_inst_wbin_next_7_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wbin_next_8_s ALU CIN In - 5.239 -
\fifo_sc_inst/wbin_next_8_s ALU COUT Out 0.057 5.296 -
fifo_sc_inst_wbin_next_8_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wbin_next_9_s ALU CIN In - 5.296 -
\fifo_sc_inst/wbin_next_9_s ALU SUM Out 0.563 5.859 -
wbin_next[9] Net - - 0.480 - 3
\fifo_sc_inst/wfull_val_s3 LUT4 I0 In - 6.339 -
\fifo_sc_inst/wfull_val_s3 LUT4 F Out 1.032 7.371 -
wfull_val_6 Net - - 0.480 - 1
\fifo_sc_inst/wfull_val_s1 LUT4 I2 In - 7.851 -
\fifo_sc_inst/wfull_val_s1 LUT4 F Out 0.822 8.673 -
wfull_val_4 Net - - 0.480 - 1
\fifo_sc_inst/wfull_val_s0 LUT2 I0 In - 9.153 -
\fifo_sc_inst/wfull_val_s0 LUT2 F Out 1.032 10.185 -
wfull_val Net - - 0.480 - 1
\fifo_sc_inst/Full_s0 DFFC D In - 10.665 -

Total Path Delay: 10.665
Logic Delay: 7.422(69.6%)
Route Delay: 3.243(30.4%)


Path information for path number 3 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 0.371
Data Arrival Time: 10.752
Data Required Time: 11.123
Number of Logic Level: 8
Starting Point: fifo_sc_inst/Empty_s0
Ending Point: fifo_sc_inst/mem_mem_0_0_s
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
Clk_ibuf IBUF I In - 0.000 -
Clk_ibuf IBUF O Out 0.982 0.982 -
Clk_d Net - - 0.363 - 34
\fifo_sc_inst/Empty_s0 DFFP CLK In - 1.345 -
\fifo_sc_inst/Empty_s0 DFFP Q Out 0.458 1.803 -
Empty_d Net - - 0.480 - 3
\fifo_sc_inst/n78_s0 LUT2 I0 In - 2.283 -
\fifo_sc_inst/n78_s0 LUT2 F Out 1.032 3.315 -
n78_3 Net - - 0.480 - 1
\fifo_sc_inst/rbin_next_0_s ALU I1 In - 3.795 -
\fifo_sc_inst/rbin_next_0_s ALU COUT Out 1.045 4.840 -
fifo_sc_inst_rbin_next_0_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_1_s ALU CIN In - 4.840 -
\fifo_sc_inst/rbin_next_1_s ALU COUT Out 0.057 4.897 -
fifo_sc_inst_rbin_next_1_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_2_s ALU CIN In - 4.897 -
\fifo_sc_inst/rbin_next_2_s ALU COUT Out 0.057 4.954 -
fifo_sc_inst_rbin_next_2_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_3_s ALU CIN In - 4.954 -
\fifo_sc_inst/rbin_next_3_s ALU COUT Out 0.057 5.011 -
fifo_sc_inst_rbin_next_3_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_4_s ALU CIN In - 5.011 -
\fifo_sc_inst/rbin_next_4_s ALU COUT Out 0.057 5.068 -
fifo_sc_inst_rbin_next_4_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_5_s ALU CIN In - 5.068 -
\fifo_sc_inst/rbin_next_5_s ALU COUT Out 0.057 5.125 -
fifo_sc_inst_rbin_next_5_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_6_s ALU CIN In - 5.125 -
\fifo_sc_inst/rbin_next_6_s ALU COUT Out 0.057 5.182 -
fifo_sc_inst_rbin_next_6_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_7_s ALU CIN In - 5.182 -
\fifo_sc_inst/rbin_next_7_s ALU COUT Out 0.057 5.239 -
fifo_sc_inst_rbin_next_7_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_8_s ALU CIN In - 5.239 -
\fifo_sc_inst/rbin_next_8_s ALU COUT Out 0.057 5.296 -
fifo_sc_inst_rbin_next_8_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_9_s ALU CIN In - 5.296 -
\fifo_sc_inst/rbin_next_9_s ALU SUM Out 0.563 5.859 -
rbin_next[9] Net - - 0.480 - 4
\fifo_sc_inst/n13_s3 LUT4 I0 In - 6.339 -
\fifo_sc_inst/n13_s3 LUT4 F Out 1.032 7.371 -
n13_6 Net - - 0.480 - 1
\fifo_sc_inst/n13_s1 LUT4 I0 In - 7.851 -
\fifo_sc_inst/n13_s1 LUT4 F Out 1.032 8.883 -
n13_4 Net - - 0.480 - 2
\fifo_sc_inst/n13_s0 LUT4 I0 In - 9.363 -
\fifo_sc_inst/n13_s0 LUT4 F Out 1.026 10.389 -
n13_3 Net - - 0.363 - 1
\fifo_sc_inst/mem_mem_0_0_s SDPB CEB In - 10.752 -

Total Path Delay: 10.752
Logic Delay: 7.626(70.9%)
Route Delay: 3.126(29.1%)


Path information for path number 4 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 1.529
Data Arrival Time: 9.381
Data Required Time: 10.910
Number of Logic Level: 7
Starting Point: fifo_sc_inst/Empty_s0
Ending Point: fifo_sc_inst/Wnum_9_s0
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
Clk_ibuf IBUF I In - 0.000 -
Clk_ibuf IBUF O Out 0.982 0.982 -
Clk_d Net - - 0.363 - 34
\fifo_sc_inst/Empty_s0 DFFP CLK In - 1.345 -
\fifo_sc_inst/Empty_s0 DFFP Q Out 0.458 1.803 -
Empty_d Net - - 0.480 - 3
\fifo_sc_inst/n78_s0 LUT2 I0 In - 2.283 -
\fifo_sc_inst/n78_s0 LUT2 F Out 1.032 3.315 -
n78_3 Net - - 0.480 - 1
\fifo_sc_inst/rbin_next_0_s ALU I1 In - 3.795 -
\fifo_sc_inst/rbin_next_0_s ALU COUT Out 1.045 4.840 -
fifo_sc_inst_rbin_next_0_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_1_s ALU CIN In - 4.840 -
\fifo_sc_inst/rbin_next_1_s ALU COUT Out 0.057 4.897 -
fifo_sc_inst_rbin_next_1_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_2_s ALU CIN In - 4.897 -
\fifo_sc_inst/rbin_next_2_s ALU COUT Out 0.057 4.954 -
fifo_sc_inst_rbin_next_2_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_3_s ALU CIN In - 4.954 -
\fifo_sc_inst/rbin_next_3_s ALU COUT Out 0.057 5.011 -
fifo_sc_inst_rbin_next_3_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_4_s ALU CIN In - 5.011 -
\fifo_sc_inst/rbin_next_4_s ALU COUT Out 0.057 5.068 -
fifo_sc_inst_rbin_next_4_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_5_s ALU CIN In - 5.068 -
\fifo_sc_inst/rbin_next_5_s ALU COUT Out 0.057 5.125 -
fifo_sc_inst_rbin_next_5_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_6_s ALU CIN In - 5.125 -
\fifo_sc_inst/rbin_next_6_s ALU COUT Out 0.057 5.182 -
fifo_sc_inst_rbin_next_6_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_7_s ALU CIN In - 5.182 -
\fifo_sc_inst/rbin_next_7_s ALU COUT Out 0.057 5.239 -
fifo_sc_inst_rbin_next_7_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_8_s ALU CIN In - 5.239 -
\fifo_sc_inst/rbin_next_8_s ALU COUT Out 0.057 5.296 -
fifo_sc_inst_rbin_next_8_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_9_s ALU CIN In - 5.296 -
\fifo_sc_inst/rbin_next_9_s ALU SUM Out 0.563 5.859 -
rbin_next[9] Net - - 0.480 - 4
\fifo_sc_inst/n112_s0 LUT2 I1 In - 6.339 -
\fifo_sc_inst/n112_s0 LUT2 F Out 1.099 7.438 -
n112_3 Net - - 0.480 - 1
\fifo_sc_inst/wcnt_sub_9_s ALU I0 In - 7.918 -
\fifo_sc_inst/wcnt_sub_9_s ALU SUM Out 0.983 8.901 -
wcnt_sub[9] Net - - 0.480 - 1
\fifo_sc_inst/Wnum_9_s0 DFFC D In - 9.381 -

Total Path Delay: 9.381
Logic Delay: 6.618(70.5%)
Route Delay: 2.763(29.5%)


Path information for path number 5 : 
Clock Skew: 0.000
Setup Relationship: 10.000
Slack(non-critical): 2.597
Data Arrival Time: 8.313
Data Required Time: 10.910
Number of Logic Level: 7
Starting Point: fifo_sc_inst/Empty_s0
Ending Point: fifo_sc_inst/Wnum_8_s0
The Start Point Is Clocked By: DEFAULT_CLK[rising]
The End Point Is Clocked By: DEFAULT_CLK[rising]


Instance/Net Name Type Pin Name Pin Dir Delay Arrival Time Fanout
Clk_ibuf IBUF I In - 0.000 -
Clk_ibuf IBUF O Out 0.982 0.982 -
Clk_d Net - - 0.363 - 34
\fifo_sc_inst/Empty_s0 DFFP CLK In - 1.345 -
\fifo_sc_inst/Empty_s0 DFFP Q Out 0.458 1.803 -
Empty_d Net - - 0.480 - 3
\fifo_sc_inst/n78_s0 LUT2 I0 In - 2.283 -
\fifo_sc_inst/n78_s0 LUT2 F Out 1.032 3.315 -
n78_3 Net - - 0.480 - 1
\fifo_sc_inst/rbin_next_0_s ALU I1 In - 3.795 -
\fifo_sc_inst/rbin_next_0_s ALU COUT Out 1.045 4.840 -
fifo_sc_inst_rbin_next_0_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/rbin_next_1_s ALU CIN In - 4.840 -
\fifo_sc_inst/rbin_next_1_s ALU SUM Out 0.563 5.403 -
rbin_next[1] Net - - 0.480 - 5
\fifo_sc_inst/wcnt_sub_1_s ALU I1 In - 5.883 -
\fifo_sc_inst/wcnt_sub_1_s ALU COUT Out 1.045 6.928 -
fifo_sc_inst_wcnt_sub_1_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wcnt_sub_2_s ALU CIN In - 6.928 -
\fifo_sc_inst/wcnt_sub_2_s ALU COUT Out 0.057 6.985 -
fifo_sc_inst_wcnt_sub_2_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wcnt_sub_3_s ALU CIN In - 6.985 -
\fifo_sc_inst/wcnt_sub_3_s ALU COUT Out 0.057 7.042 -
fifo_sc_inst_wcnt_sub_3_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wcnt_sub_4_s ALU CIN In - 7.042 -
\fifo_sc_inst/wcnt_sub_4_s ALU COUT Out 0.057 7.099 -
fifo_sc_inst_wcnt_sub_4_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wcnt_sub_5_s ALU CIN In - 7.099 -
\fifo_sc_inst/wcnt_sub_5_s ALU COUT Out 0.057 7.156 -
fifo_sc_inst_wcnt_sub_5_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wcnt_sub_6_s ALU CIN In - 7.156 -
\fifo_sc_inst/wcnt_sub_6_s ALU COUT Out 0.057 7.213 -
fifo_sc_inst_wcnt_sub_6_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wcnt_sub_7_s ALU CIN In - 7.213 -
\fifo_sc_inst/wcnt_sub_7_s ALU COUT Out 0.057 7.270 -
fifo_sc_inst_wcnt_sub_7_0_COUT Net - - 0.000 - 1
\fifo_sc_inst/wcnt_sub_8_s ALU CIN In - 7.270 -
\fifo_sc_inst/wcnt_sub_8_s ALU SUM Out 0.563 7.833 -
wcnt_sub[8] Net - - 0.480 - 1
\fifo_sc_inst/Wnum_8_s0 DFFC D In - 8.313 -

Total Path Delay: 8.313
Logic Delay: 6.030(72.5%)
Route Delay: 2.283(27.5%)


Summary

Total Warnings: 3
Total Informations: 35

Synthesis completed successfully!
Process took 0h:0m:2s realtime, 0h:0m:1s cputime
Memory peak: 37.3MB