PnR Messages

Report Title PnR Report
Design File C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\impl\gwsynthesis\gowin_usb_refdesign.vg
Physical Constraints File C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\usb_ref.cst
Timing Constraints File C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\usb_ref.sdc
Version V1.9.8.07
Part Number GW1NSR-LV4MG64PC7/I6
Device GW1NSR-4
Created Time Mon Jul 11 09:34:00 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.191s, Elapsed time = 0h 0m 0.191s Placement Phase 1: CPU time = 0h 0m 0.113s, Elapsed time = 0h 0m 0.112s Placement Phase 2: CPU time = 0h 0m 0.233s, Elapsed time = 0h 0m 0.233s Placement Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Total Placement: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.11s, Elapsed time = 0h 0m 0.109s Routing Phase 2: CPU time = 0h 0m 0.608s, Elapsed time = 0h 0m 0.608s Total Routing: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.718s Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Time and Memory Usage CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 199MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1402/4608 30%
    --LUT,ALU,ROM16 1402(1268 LUT, 134 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 514/3621 14%
    --Logic Register as Latch 0/3456 0%
    --Logic Register as FF 512/3456 14%
    --I/O Register as Latch 0/165 0%
    --I/O Register as FF 2/165 1%
CLS 847/2304 36%
I/O Port 5 -
I/O Buf 5 -
    --Input Buf 2 -
    --Output Buf 1 -
    --Inout Buf 2 -
IOLOGIC 0 0%
BSRAM 2 SDPB
20%
DSP 00%
PLL 1/2 50%
DCS 0/4 0%
DQCE 0/12 0%
OSC 0/1 0%
User Flash 0/1 0%
CLKDIV 0/6 0%
DLLDLY 0/6 0%
DHCEN 0/12 0%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 0/10(0%)
bank 1 2/28(7%)
bank 2 3/18(16%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 1/8(12%)
SECONDARY 2/8(25%)
GCLK_PIN 1/6(16%)
PLL 1/2(50%)
CLKDIV 0/6(0%)
DLLDLY 0/6(0%)

Global Clock Signals:

Signal Global Clock Location
PHY_CLKOUT PRIMARY LEFT RIGHT
RESET_IN_6 SECONDARY -
usb_busreset SECONDARY -
CLK_IN_d HCLK TOP[0]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor BankVccio
CLK_IN C5/1 Y in IOT20[A] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
RESET_N A5/1 Y in IOT17[B] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
LED G1/2 Y out IOR2[A] LVCMOS33 8 NONE NA NA OFF FAST NA OFF NA 3.3
USB_DP G6/2 Y io IOR13[A] LVCMOS33 8 NONE NA NONE OFF FAST NA OFF NA 3.3
USB_DM H6/2 Y io IOR13[B] LVCMOS33 8 NONE NA NONE OFF FAST NA OFF NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor Bank Vccio
E2/0 - in IOT2[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
E3/0 - out IOT2[B] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA -
D2/0 - in IOT3[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
D3/0 - in IOT3[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
F1/0 - in IOT4[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
F2/0 - in IOT4[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
D1/0 - in IOT5[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
E1/0 - in IOT6[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
C1/0 - in IOT8[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
C2/0 - in IOT8[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA -
A1/1 - in IOT11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
B1/1 - in IOT11[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
A2/1 - in IOT12[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
B2/1 - in IOT12[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
B3/1 - in IOT13[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
A3/1 - in IOT13[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
B4/1 - in IOT15[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
A4/1 - in IOT15[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
B5/1 - in IOT17[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
A5/1 RESET_N in IOT17[B] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
C5/1 CLK_IN in IOT20[A] LVCMOS33 NA UP NA NONE NA NA NA NA NA 1.2
C4/1 - in IOT20[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
B6/1 - in IOT21[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
A6/1 - in IOT21[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
B7/1 - in IOT22[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
A7/1 - in IOT22[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
A8/1 - in IOT24[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
B8/1 - in IOT24[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
C7/1 - in IOT26[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
C8/1 - in IOT26[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
E6/1 - in IOT29[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
D6/1 - in IOT29[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
D7/1 - in IOT31[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
D8/1 - in IOT31[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
E7/1 - in IOT33[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
E8/1 - in IOT33[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
F7/1 - in IOT35[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
F8/1 - in IOT35[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 1.2
G1/2 LED out IOR2[A] LVCMOS33 8 NONE NA NA OFF FAST NA OFF NA 3.3
H1/2 - in IOR2[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
G2/2 - in IOR4[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
H2/2 - in IOR4[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
G3/2 - in IOR6[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
H3/2 - in IOR6[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
G4/2 - in IOR8[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
H4/2 - in IOR8[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
F5/2 - in IOR9[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
F4/2 - in IOR9[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
G5/2 - in IOR11[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
H5/2 - in IOR11[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
G6/2 USB_DP io IOR13[A] LVCMOS33 8 NONE NA NONE OFF FAST NA OFF NA 3.3
H6/2 USB_DM io IOR13[B] LVCMOS33 8 NONE NA NONE OFF FAST NA OFF NA 3.3
G7/2 - in IOR15[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
H7/2 - in IOR15[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
G8/2 - in IOR17[A] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3
H8/2 - in IOR17[B] LVCMOS18 NA UP NA NONE NA NA NA NA NA 3.3