Timing Messages
Report Title | Timing Analysis Report |
Design File | C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\impl\gwsynthesis\gowin_usb_refdesign.vg |
Physical Constraints File | C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\usb_ref.cst |
Timing Constraint File | C:\Users\Administrator\Desktop\Gowin_USB1.1_SoftPHY_RefDesign\Gowin_USB1.1_SoftPHY_RefDesign\project\src\usb_ref.sdc |
Version | V1.9.8.07 |
Part Number | GW1NSR-LV4MG64PC7/I6 |
Device | GW1NSR-4 |
Created Time | Mon Jul 11 09:34:00 2022 |
Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C C7/I6 |
Hold Delay Model | Fast 1.26V 0C C7/I6 |
Numbers of Paths Analyzed | 2587 |
Numbers of Endpoints Analyzed | 1382 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
CLK_IN | Base | 83.333 | 12.000 | 0.000 | 41.667 | CLK_IN_ibuf/I | ||
u_pll/pllvr_inst/CLKOUT.default_gen_clk | Generated | 16.667 | 60.000 | 0.000 | 8.333 | CLK_IN_ibuf/I | CLK_IN | u_pll/pllvr_inst/CLKOUT |
u_pll/pllvr_inst/CLKOUTP.default_gen_clk | Generated | 16.667 | 60.000 | 0.000 | 8.333 | CLK_IN_ibuf/I | CLK_IN | u_pll/pllvr_inst/CLKOUTP |
u_pll/pllvr_inst/CLKOUTD.default_gen_clk | Generated | 33.333 | 30.000 | 0.000 | 16.667 | CLK_IN_ibuf/I | CLK_IN | u_pll/pllvr_inst/CLKOUTD |
u_pll/pllvr_inst/CLKOUTD3.default_gen_clk | Generated | 50.000 | 20.000 | 0.000 | 25.000 | CLK_IN_ibuf/I | CLK_IN | u_pll/pllvr_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | 60.000(MHz) | 65.812(MHz) | 12 | TOP |
No timing paths to get frequency of CLK_IN!
No timing paths to get frequency of u_pll/pllvr_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u_pll/pllvr_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u_pll/pllvr_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
CLK_IN | Setup | 0.000 | 0 |
CLK_IN | Hold | 0.000 | 0 |
u_pll/pllvr_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
u_pll/pllvr_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
u_pll/pllvr_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_pll/pllvr_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u_pll/pllvr_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
u_pll/pllvr_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
u_pll/pllvr_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u_pll/pllvr_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.472 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/mem_mem_0_0_s/CEB | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 15.056 |
2 | 1.778 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Empty_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 14.593 |
3 | 2.260 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Full_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 14.110 |
4 | 2.524 | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_3_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.846 |
5 | 2.680 | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_4_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.690 |
6 | 2.829 | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_2_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.542 |
7 | 2.904 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0/Q | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_0_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.466 |
8 | 3.036 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Wnum_9_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.334 |
9 | 3.124 | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_5_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.246 |
10 | 3.163 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Wnum_8_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.208 |
11 | 3.205 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Wnum_7_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.165 |
12 | 3.247 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Wnum_6_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.123 |
13 | 3.289 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Wnum_5_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.081 |
14 | 3.294 | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.076 |
15 | 3.332 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Wnum_4_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 13.039 |
16 | 3.637 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Wnum_3_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.733 |
17 | 3.775 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Wnum_2_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.595 |
18 | 3.864 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0/Q | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/PHY_DATAOUT_0_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.507 |
19 | 3.901 | u_usb_device_controller_top/u_usb_device_controller/s_state_1_s1/Q | rx_fifo/fifo_sc_inst/Full_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.469 |
20 | 4.081 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/Wnum_1_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.290 |
21 | 4.161 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_0_s0/Q | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_1_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.209 |
22 | 4.245 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/rbin_7_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.125 |
23 | 4.269 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_0_s0/Q | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_15_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.101 |
24 | 4.293 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0/Q | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_8_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.077 |
25 | 4.309 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q | tx_fifo/fifo_sc_inst/mem_mem_0_0_s/ADB[9] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 16.667 | 0.000 | 12.326 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.524 | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_q_s4/Q | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_q_s4/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
2 | 0.524 | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4/Q | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
3 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
4 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_4_s1/Q | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_4_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
5 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_9_s1/Q | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_9_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
6 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_11_s1/Q | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_11_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
7 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_13_s1/Q | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_13_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
8 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_3_s0/Q | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_3_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
9 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s0/Q | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
10 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer2_0_s1/Q | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer2_0_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
11 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer1_0_s1/Q | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer1_0_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
12 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_15_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_15_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
13 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_13_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_13_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
14 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_12_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_12_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
15 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_11_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_11_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
16 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_10_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_10_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
17 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/osync_9_s1/Q | u_usb_device_controller_top/u_usb_device_controller/osync_9_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
18 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_7_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_7_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
19 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_6_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_6_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
20 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/osync_5_s1/Q | u_usb_device_controller_top/u_usb_device_controller/osync_5_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
21 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_5_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_5_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
22 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_4_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_4_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
23 | 0.524 | u_usb_device_controller_top/u_usb_device_controller/isync_3_s1/Q | u_usb_device_controller_top/u_usb_device_controller/isync_3_s1/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
24 | 0.524 | led_cnt_3_s0/Q | led_cnt_3_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
25 | 0.524 | led_cnt_10_s0/Q | led_cnt_10_s0/D | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.524 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | led_cnt_15_s0 |
2 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | led_cnt_13_s0 |
3 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | led_cnt_9_s0 |
4 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | led_cnt_1_s0 |
5 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | s_req_code_1_s0 |
6 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | s_dte_rate_1_s0 |
7 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | tx_fifo/fifo_sc_inst/wbin_4_s0 |
8 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | u_usb_device_controller_top/u_usb_device_controller/isync_14_s1 |
9 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4 |
10 | 7.349 | 8.276 | 0.926 | Low Pulse Width | u_pll/pllvr_inst/CLKOUT.default_gen_clk | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/out_dn_q_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.472 |
Data Arrival Time | 16.383 |
Data Required Time | 17.854 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/mem_mem_0_0_s |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
11.824 | 0.042 | tINS | FF | 1 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/COUT |
11.824 | 0.000 | tNET | FF | 2 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/CIN |
12.241 | 0.417 | tINS | FF | 5 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/SUM |
13.224 | 0.983 | tNET | FF | 1 | R12C8[3][A] | tx_fifo/fifo_sc_inst/n13_s5/I2 |
13.989 | 0.765 | tINS | FF | 1 | R12C8[3][A] | tx_fifo/fifo_sc_inst/n13_s5/F |
14.238 | 0.249 | tNET | FF | 1 | R12C8[1][B] | tx_fifo/fifo_sc_inst/n13_s1/I2 |
15.003 | 0.765 | tINS | FF | 2 | R12C8[1][B] | tx_fifo/fifo_sc_inst/n13_s1/F |
15.011 | 0.008 | tNET | FF | 1 | R12C8[2][B] | tx_fifo/fifo_sc_inst/n13_s0/I0 |
15.797 | 0.786 | tINS | FR | 2 | R12C8[2][B] | tx_fifo/fifo_sc_inst/n13_s0/F |
16.383 | 0.586 | tNET | RR | 1 | BSRAM_R10[2] | tx_fifo/fifo_sc_inst/mem_mem_0_0_s/CEB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | BSRAM_R10[2] | tx_fifo/fifo_sc_inst/mem_mem_0_0_s/CLKB |
17.854 | -0.139 | tSu | 1 | BSRAM_R10[2] | tx_fifo/fifo_sc_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 6.797, 45.145%; route: 7.919, 52.599%; tC2Q: 0.340, 2.256% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path2
Path Summary:
Slack | 1.778 |
Data Arrival Time | 15.919 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Empty_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
11.824 | 0.042 | tINS | FF | 1 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/COUT |
11.824 | 0.000 | tNET | FF | 2 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/CIN |
12.241 | 0.417 | tINS | FF | 5 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/SUM |
13.224 | 0.983 | tNET | FF | 1 | R12C8[3][A] | tx_fifo/fifo_sc_inst/n13_s5/I2 |
13.989 | 0.765 | tINS | FF | 1 | R12C8[3][A] | tx_fifo/fifo_sc_inst/n13_s5/F |
14.238 | 0.249 | tNET | FF | 1 | R12C8[1][B] | tx_fifo/fifo_sc_inst/n13_s1/I2 |
14.998 | 0.760 | tINS | FR | 2 | R12C8[1][B] | tx_fifo/fifo_sc_inst/n13_s1/F |
15.310 | 0.312 | tNET | RR | 1 | R12C7[0][A] | tx_fifo/fifo_sc_inst/rempty_val_s0/I0 |
15.919 | 0.609 | tINS | RF | 1 | R12C7[0][A] | tx_fifo/fifo_sc_inst/rempty_val_s0/F |
15.919 | 0.000 | tNET | FF | 1 | R12C7[0][A] | tx_fifo/fifo_sc_inst/Empty_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R12C7[0][A] | tx_fifo/fifo_sc_inst/Empty_s0/CLK |
17.697 | -0.296 | tSu | 1 | R12C7[0][A] | tx_fifo/fifo_sc_inst/Empty_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 6.616, 45.335%; route: 7.637, 52.337%; tC2Q: 0.340, 2.327% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path3
Path Summary:
Slack | 2.260 |
Data Arrival Time | 15.436 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Full_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
11.824 | 0.042 | tINS | FF | 1 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/COUT |
11.824 | 0.000 | tNET | FF | 2 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/CIN |
11.866 | 0.042 | tINS | FF | 1 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/COUT |
11.866 | 0.000 | tNET | FF | 2 | R13C6[2][B] | tx_fifo/fifo_sc_inst/rbin_next_5_s/CIN |
11.908 | 0.042 | tINS | FF | 1 | R13C6[2][B] | tx_fifo/fifo_sc_inst/rbin_next_5_s/COUT |
11.908 | 0.000 | tNET | FF | 2 | R13C7[0][A] | tx_fifo/fifo_sc_inst/rbin_next_6_s/CIN |
11.951 | 0.042 | tINS | FF | 1 | R13C7[0][A] | tx_fifo/fifo_sc_inst/rbin_next_6_s/COUT |
11.951 | 0.000 | tNET | FF | 2 | R13C7[0][B] | tx_fifo/fifo_sc_inst/rbin_next_7_s/CIN |
12.368 | 0.417 | tINS | FF | 5 | R13C7[0][B] | tx_fifo/fifo_sc_inst/rbin_next_7_s/SUM |
12.988 | 0.620 | tNET | FF | 1 | R13C8[3][B] | tx_fifo/fifo_sc_inst/wfull_val_s4/I2 |
13.597 | 0.609 | tINS | FF | 1 | R13C8[3][B] | tx_fifo/fifo_sc_inst/wfull_val_s4/F |
13.601 | 0.004 | tNET | FF | 1 | R13C8[0][B] | tx_fifo/fifo_sc_inst/wfull_val_s1/I3 |
14.361 | 0.760 | tINS | FR | 1 | R13C8[0][B] | tx_fifo/fifo_sc_inst/wfull_val_s1/F |
14.671 | 0.310 | tNET | RR | 1 | R13C7[2][A] | tx_fifo/fifo_sc_inst/wfull_val_s0/I0 |
15.436 | 0.765 | tINS | RF | 1 | R13C7[2][A] | tx_fifo/fifo_sc_inst/wfull_val_s0/F |
15.436 | 0.000 | tNET | FF | 1 | R13C7[2][A] | tx_fifo/fifo_sc_inst/Full_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C7[2][A] | tx_fifo/fifo_sc_inst/Full_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C7[2][A] | tx_fifo/fifo_sc_inst/Full_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 6.742, 47.785%; route: 7.028, 49.808%; tC2Q: 0.340, 2.407% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path4
Path Summary:
Slack | 2.524 |
Data Arrival Time | 15.172 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_3_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 2 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q |
1.917 | 0.251 | tNET | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/I2 |
2.732 | 0.814 | tINS | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/F |
2.736 | 0.004 | tNET | FF | 1 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/I3 |
3.500 | 0.765 | tINS | FF | 18 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/F |
3.895 | 0.394 | tNET | FF | 1 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/I2 |
4.504 | 0.609 | tINS | FF | 3 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/F |
4.875 | 0.371 | tNET | FF | 1 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/I0 |
5.689 | 0.814 | tINS | FF | 3 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/F |
5.701 | 0.012 | tNET | FF | 1 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/I1 |
6.311 | 0.609 | tINS | FF | 14 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/F |
6.935 | 0.625 | tNET | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/I0 |
7.700 | 0.765 | tINS | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/F |
8.789 | 1.089 | tNET | FF | 2 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/I1 |
9.564 | 0.774 | tINS | FF | 1 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/COUT |
9.564 | 0.000 | tNET | FF | 2 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/CIN |
9.606 | 0.042 | tINS | FF | 1 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/COUT |
9.606 | 0.000 | tNET | FF | 2 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/CIN |
9.648 | 0.042 | tINS | FF | 1 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/COUT |
9.648 | 0.000 | tNET | FF | 2 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/CIN |
9.690 | 0.042 | tINS | FF | 1 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/COUT |
9.690 | 0.000 | tNET | FF | 2 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/CIN |
9.733 | 0.042 | tINS | FF | 1 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/COUT |
9.733 | 0.000 | tNET | FF | 2 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/CIN |
9.775 | 0.042 | tINS | FF | 4 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/COUT |
10.792 | 1.017 | tNET | FF | 1 | R9C28[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/I2 |
11.606 | 0.814 | tINS | FF | 3 | R9C28[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/F |
11.977 | 0.371 | tNET | FF | 1 | R9C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/I0 |
12.742 | 0.765 | tINS | FF | 3 | R9C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/F |
13.589 | 0.847 | tNET | FF | 1 | R13C26[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n973_s12/I0 |
14.404 | 0.814 | tINS | FF | 1 | R13C26[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n973_s12/F |
14.408 | 0.004 | tNET | FF | 1 | R13C26[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n973_s11/I0 |
15.172 | 0.765 | tINS | FF | 1 | R13C26[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n973_s11/F |
15.172 | 0.000 | tNET | FF | 1 | R13C26[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C26[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_3_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C26[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 8.520, 61.534%; route: 4.986, 36.013%; tC2Q: 0.340, 2.453% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path5
Path Summary:
Slack | 2.680 |
Data Arrival Time | 15.017 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_4_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 2 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q |
1.917 | 0.251 | tNET | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/I2 |
2.732 | 0.814 | tINS | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/F |
2.736 | 0.004 | tNET | FF | 1 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/I3 |
3.500 | 0.765 | tINS | FF | 18 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/F |
3.895 | 0.394 | tNET | FF | 1 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/I2 |
4.504 | 0.609 | tINS | FF | 3 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/F |
4.875 | 0.371 | tNET | FF | 1 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/I0 |
5.689 | 0.814 | tINS | FF | 3 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/F |
5.701 | 0.012 | tNET | FF | 1 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/I1 |
6.311 | 0.609 | tINS | FF | 14 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/F |
6.935 | 0.625 | tNET | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/I0 |
7.700 | 0.765 | tINS | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/F |
8.789 | 1.089 | tNET | FF | 2 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/I1 |
9.564 | 0.774 | tINS | FF | 1 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/COUT |
9.564 | 0.000 | tNET | FF | 2 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/CIN |
9.606 | 0.042 | tINS | FF | 1 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/COUT |
9.606 | 0.000 | tNET | FF | 2 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/CIN |
9.648 | 0.042 | tINS | FF | 1 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/COUT |
9.648 | 0.000 | tNET | FF | 2 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/CIN |
9.690 | 0.042 | tINS | FF | 1 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/COUT |
9.690 | 0.000 | tNET | FF | 2 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/CIN |
9.733 | 0.042 | tINS | FF | 1 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/COUT |
9.733 | 0.000 | tNET | FF | 2 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/CIN |
9.775 | 0.042 | tINS | FF | 4 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/COUT |
10.792 | 1.017 | tNET | FF | 1 | R9C28[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/I2 |
11.606 | 0.814 | tINS | FF | 3 | R9C28[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/F |
11.977 | 0.371 | tNET | FF | 1 | R9C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/I0 |
12.742 | 0.765 | tINS | FF | 3 | R9C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/F |
13.589 | 0.847 | tNET | FF | 1 | R13C26[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s12/I0 |
14.404 | 0.814 | tINS | FF | 1 | R13C26[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s12/F |
14.408 | 0.004 | tNET | FF | 1 | R13C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s11/I0 |
15.017 | 0.609 | tINS | FF | 1 | R13C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s11/F |
15.017 | 0.000 | tNET | FF | 1 | R13C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_4_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 8.364, 61.097%; route: 4.986, 36.422%; tC2Q: 0.340, 2.481% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path6
Path Summary:
Slack | 2.829 |
Data Arrival Time | 14.868 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_2_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 2 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q |
1.917 | 0.251 | tNET | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/I2 |
2.732 | 0.814 | tINS | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/F |
2.736 | 0.004 | tNET | FF | 1 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/I3 |
3.500 | 0.765 | tINS | FF | 18 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/F |
3.895 | 0.394 | tNET | FF | 1 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/I2 |
4.504 | 0.609 | tINS | FF | 3 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/F |
4.875 | 0.371 | tNET | FF | 1 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/I0 |
5.689 | 0.814 | tINS | FF | 3 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/F |
5.701 | 0.012 | tNET | FF | 1 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/I1 |
6.311 | 0.609 | tINS | FF | 14 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/F |
6.935 | 0.625 | tNET | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/I0 |
7.700 | 0.765 | tINS | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/F |
8.789 | 1.089 | tNET | FF | 2 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/I1 |
9.564 | 0.774 | tINS | FF | 1 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/COUT |
9.564 | 0.000 | tNET | FF | 2 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/CIN |
9.606 | 0.042 | tINS | FF | 1 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/COUT |
9.606 | 0.000 | tNET | FF | 2 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/CIN |
9.648 | 0.042 | tINS | FF | 1 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/COUT |
9.648 | 0.000 | tNET | FF | 2 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/CIN |
9.690 | 0.042 | tINS | FF | 1 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/COUT |
9.690 | 0.000 | tNET | FF | 2 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/CIN |
9.733 | 0.042 | tINS | FF | 1 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/COUT |
9.733 | 0.000 | tNET | FF | 2 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/CIN |
9.775 | 0.042 | tINS | FF | 4 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/COUT |
10.792 | 1.017 | tNET | FF | 1 | R9C28[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/I2 |
11.606 | 0.814 | tINS | FF | 3 | R9C28[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/F |
11.977 | 0.371 | tNET | FF | 1 | R9C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/I0 |
12.742 | 0.765 | tINS | FF | 3 | R9C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n970_s14/F |
13.586 | 0.844 | tNET | FF | 1 | R13C25[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n976_s13/I2 |
14.400 | 0.814 | tINS | FF | 1 | R13C25[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n976_s13/F |
14.404 | 0.004 | tNET | FF | 1 | R13C25[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n976_s11/I0 |
14.868 | 0.464 | tINS | FF | 1 | R13C25[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n976_s11/F |
14.868 | 0.000 | tNET | FF | 1 | R13C25[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C25[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_2_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C25[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 8.219, 60.695%; route: 4.983, 36.797%; tC2Q: 0.340, 2.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path7
Path Summary:
Slack | 2.904 |
Data Arrival Time | 14.793 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_0_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R6C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 34 | R6C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0/Q |
4.080 | 2.414 | tNET | FF | 1 | R11C9[0][A] | usb_txdat_7_s1/I2 |
4.845 | 0.765 | tINS | FF | 22 | R11C9[0][A] | usb_txdat_7_s1/F |
5.484 | 0.639 | tNET | FF | 1 | R9C8[0][B] | usb_txdat_0_s0/I2 |
6.248 | 0.765 | tINS | FF | 2 | R9C8[0][B] | usb_txdat_0_s0/F |
7.578 | 1.329 | tNET | FF | 1 | R9C22[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s20/I1 |
8.392 | 0.814 | tINS | FF | 1 | R9C22[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s20/F |
8.755 | 0.363 | tNET | FF | 1 | R11C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s16/I1 |
9.218 | 0.463 | tINS | FR | 1 | R11C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s16/F |
9.529 | 0.310 | tNET | RR | 1 | R11C21[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s10/I3 |
10.138 | 0.609 | tINS | RF | 2 | R11C21[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s10/F |
10.738 | 0.600 | tNET | FF | 1 | R11C18[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s7/I0 |
11.347 | 0.609 | tINS | FF | 4 | R11C18[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s7/F |
12.196 | 0.849 | tNET | FF | 1 | R13C17[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n653_s12/I0 |
13.010 | 0.814 | tINS | FF | 2 | R13C17[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n653_s12/F |
14.793 | 1.782 | tNET | FF | 1 | R13C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_0_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 4.839, 35.938%; route: 8.287, 61.540%; tC2Q: 0.340, 2.522% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path8
Path Summary:
Slack | 3.036 |
Data Arrival Time | 14.661 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Wnum_9_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
11.824 | 0.042 | tINS | FF | 1 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/COUT |
11.824 | 0.000 | tNET | FF | 2 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/CIN |
11.866 | 0.042 | tINS | FF | 1 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/COUT |
11.866 | 0.000 | tNET | FF | 2 | R13C6[2][B] | tx_fifo/fifo_sc_inst/rbin_next_5_s/CIN |
11.908 | 0.042 | tINS | FF | 1 | R13C6[2][B] | tx_fifo/fifo_sc_inst/rbin_next_5_s/COUT |
11.908 | 0.000 | tNET | FF | 2 | R13C7[0][A] | tx_fifo/fifo_sc_inst/rbin_next_6_s/CIN |
11.951 | 0.042 | tINS | FF | 1 | R13C7[0][A] | tx_fifo/fifo_sc_inst/rbin_next_6_s/COUT |
11.951 | 0.000 | tNET | FF | 2 | R13C7[0][B] | tx_fifo/fifo_sc_inst/rbin_next_7_s/CIN |
11.993 | 0.042 | tINS | FF | 1 | R13C7[0][B] | tx_fifo/fifo_sc_inst/rbin_next_7_s/COUT |
11.993 | 0.000 | tNET | FF | 2 | R13C7[1][A] | tx_fifo/fifo_sc_inst/rbin_next_8_s/CIN |
12.035 | 0.042 | tINS | FF | 1 | R13C7[1][A] | tx_fifo/fifo_sc_inst/rbin_next_8_s/COUT |
12.035 | 0.000 | tNET | FF | 2 | R13C7[1][B] | tx_fifo/fifo_sc_inst/rbin_next_9_s/CIN |
12.452 | 0.417 | tINS | FF | 4 | R13C7[1][B] | tx_fifo/fifo_sc_inst/rbin_next_9_s/SUM |
12.828 | 0.375 | tNET | FF | 1 | R13C9[3][B] | tx_fifo/fifo_sc_inst/n112_s0/I1 |
13.614 | 0.786 | tINS | FR | 1 | R13C9[3][B] | tx_fifo/fifo_sc_inst/n112_s0/F |
13.924 | 0.310 | tNET | RR | 2 | R13C10[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_9_s/I0 |
14.661 | 0.737 | tINS | RR | 1 | R13C10[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_9_s/SUM |
14.661 | 0.000 | tNET | RR | 1 | R13C10[1][B] | tx_fifo/fifo_sc_inst/Wnum_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C10[1][B] | tx_fifo/fifo_sc_inst/Wnum_9_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C10[1][B] | tx_fifo/fifo_sc_inst/Wnum_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 6.216, 46.613%; route: 6.779, 50.840%; tC2Q: 0.340, 2.547% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path9
Path Summary:
Slack | 3.124 |
Data Arrival Time | 14.573 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_5_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 2 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q |
1.917 | 0.251 | tNET | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/I2 |
2.732 | 0.814 | tINS | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/F |
2.736 | 0.004 | tNET | FF | 1 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/I3 |
3.500 | 0.765 | tINS | FF | 18 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/F |
3.895 | 0.394 | tNET | FF | 1 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/I2 |
4.504 | 0.609 | tINS | FF | 3 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/F |
4.875 | 0.371 | tNET | FF | 1 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/I0 |
5.689 | 0.814 | tINS | FF | 3 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/F |
5.701 | 0.012 | tNET | FF | 1 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/I1 |
6.311 | 0.609 | tINS | FF | 14 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/F |
6.935 | 0.625 | tNET | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/I0 |
7.700 | 0.765 | tINS | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/F |
8.789 | 1.089 | tNET | FF | 2 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/I1 |
9.564 | 0.774 | tINS | FF | 1 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/COUT |
9.564 | 0.000 | tNET | FF | 2 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/CIN |
9.606 | 0.042 | tINS | FF | 1 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/COUT |
9.606 | 0.000 | tNET | FF | 2 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/CIN |
9.648 | 0.042 | tINS | FF | 1 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/COUT |
9.648 | 0.000 | tNET | FF | 2 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/CIN |
9.690 | 0.042 | tINS | FF | 1 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/COUT |
9.690 | 0.000 | tNET | FF | 2 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/CIN |
9.733 | 0.042 | tINS | FF | 1 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/COUT |
9.733 | 0.000 | tNET | FF | 2 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/CIN |
9.775 | 0.042 | tINS | FF | 4 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/COUT |
10.800 | 1.026 | tNET | FF | 1 | R9C28[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s16/I3 |
11.410 | 0.609 | tINS | FF | 3 | R9C28[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s16/F |
12.736 | 1.326 | tNET | FF | 1 | R11C25[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n967_s13/I0 |
13.200 | 0.464 | tINS | FF | 1 | R11C25[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n967_s13/F |
13.808 | 0.608 | tNET | FF | 1 | R12C25[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n967_s11/I1 |
14.573 | 0.765 | tINS | FF | 1 | R12C25[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n967_s11/F |
14.573 | 0.000 | tNET | FF | 1 | R12C25[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R12C25[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_5_s0/CLK |
17.697 | -0.296 | tSu | 1 | R12C25[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_answerptr_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 7.200, 54.352%; route: 5.707, 43.084%; tC2Q: 0.340, 2.564% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path10
Path Summary:
Slack | 3.163 |
Data Arrival Time | 14.534 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Wnum_8_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
12.199 | 0.417 | tINS | FF | 5 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/SUM |
13.540 | 1.341 | tNET | FF | 2 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/I1 |
13.948 | 0.408 | tINS | FR | 1 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/COUT |
13.948 | 0.000 | tNET | RR | 2 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/CIN |
13.990 | 0.042 | tINS | RF | 1 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/COUT |
13.990 | 0.000 | tNET | FF | 2 | R13C9[2][B] | tx_fifo/fifo_sc_inst/wcnt_sub_5_s/CIN |
14.032 | 0.042 | tINS | FF | 1 | R13C9[2][B] | tx_fifo/fifo_sc_inst/wcnt_sub_5_s/COUT |
14.032 | 0.000 | tNET | FF | 2 | R13C10[0][A] | tx_fifo/fifo_sc_inst/wcnt_sub_6_s/CIN |
14.074 | 0.042 | tINS | FF | 1 | R13C10[0][A] | tx_fifo/fifo_sc_inst/wcnt_sub_6_s/COUT |
14.074 | 0.000 | tNET | FF | 2 | R13C10[0][B] | tx_fifo/fifo_sc_inst/wcnt_sub_7_s/CIN |
14.117 | 0.042 | tINS | FF | 1 | R13C10[0][B] | tx_fifo/fifo_sc_inst/wcnt_sub_7_s/COUT |
14.117 | 0.000 | tNET | FF | 2 | R13C10[1][A] | tx_fifo/fifo_sc_inst/wcnt_sub_8_s/CIN |
14.534 | 0.417 | tINS | FF | 1 | R13C10[1][A] | tx_fifo/fifo_sc_inst/wcnt_sub_8_s/SUM |
14.534 | 0.000 | tNET | FF | 1 | R13C10[1][A] | tx_fifo/fifo_sc_inst/Wnum_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C10[1][A] | tx_fifo/fifo_sc_inst/Wnum_8_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C10[1][A] | tx_fifo/fifo_sc_inst/Wnum_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.433, 41.136%; route: 7.435, 56.293%; tC2Q: 0.340, 2.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path11
Path Summary:
Slack | 3.205 |
Data Arrival Time | 14.492 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Wnum_7_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
12.199 | 0.417 | tINS | FF | 5 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/SUM |
13.540 | 1.341 | tNET | FF | 2 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/I1 |
13.948 | 0.408 | tINS | FR | 1 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/COUT |
13.948 | 0.000 | tNET | RR | 2 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/CIN |
13.990 | 0.042 | tINS | RF | 1 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/COUT |
13.990 | 0.000 | tNET | FF | 2 | R13C9[2][B] | tx_fifo/fifo_sc_inst/wcnt_sub_5_s/CIN |
14.032 | 0.042 | tINS | FF | 1 | R13C9[2][B] | tx_fifo/fifo_sc_inst/wcnt_sub_5_s/COUT |
14.032 | 0.000 | tNET | FF | 2 | R13C10[0][A] | tx_fifo/fifo_sc_inst/wcnt_sub_6_s/CIN |
14.074 | 0.042 | tINS | FF | 1 | R13C10[0][A] | tx_fifo/fifo_sc_inst/wcnt_sub_6_s/COUT |
14.074 | 0.000 | tNET | FF | 2 | R13C10[0][B] | tx_fifo/fifo_sc_inst/wcnt_sub_7_s/CIN |
14.492 | 0.417 | tINS | FF | 1 | R13C10[0][B] | tx_fifo/fifo_sc_inst/wcnt_sub_7_s/SUM |
14.492 | 0.000 | tNET | FF | 1 | R13C10[0][B] | tx_fifo/fifo_sc_inst/Wnum_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C10[0][B] | tx_fifo/fifo_sc_inst/Wnum_7_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C10[0][B] | tx_fifo/fifo_sc_inst/Wnum_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.391, 40.947%; route: 7.435, 56.474%; tC2Q: 0.340, 2.580% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path12
Path Summary:
Slack | 3.247 |
Data Arrival Time | 14.449 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Wnum_6_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
12.199 | 0.417 | tINS | FF | 5 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/SUM |
13.540 | 1.341 | tNET | FF | 2 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/I1 |
13.948 | 0.408 | tINS | FR | 1 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/COUT |
13.948 | 0.000 | tNET | RR | 2 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/CIN |
13.990 | 0.042 | tINS | RF | 1 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/COUT |
13.990 | 0.000 | tNET | FF | 2 | R13C9[2][B] | tx_fifo/fifo_sc_inst/wcnt_sub_5_s/CIN |
14.032 | 0.042 | tINS | FF | 1 | R13C9[2][B] | tx_fifo/fifo_sc_inst/wcnt_sub_5_s/COUT |
14.032 | 0.000 | tNET | FF | 2 | R13C10[0][A] | tx_fifo/fifo_sc_inst/wcnt_sub_6_s/CIN |
14.449 | 0.417 | tINS | FF | 1 | R13C10[0][A] | tx_fifo/fifo_sc_inst/wcnt_sub_6_s/SUM |
14.449 | 0.000 | tNET | FF | 1 | R13C10[0][A] | tx_fifo/fifo_sc_inst/Wnum_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C10[0][A] | tx_fifo/fifo_sc_inst/Wnum_6_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C10[0][A] | tx_fifo/fifo_sc_inst/Wnum_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.349, 40.757%; route: 7.435, 56.655%; tC2Q: 0.340, 2.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path13
Path Summary:
Slack | 3.289 |
Data Arrival Time | 14.407 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Wnum_5_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
12.199 | 0.417 | tINS | FF | 5 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/SUM |
13.540 | 1.341 | tNET | FF | 2 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/I1 |
13.948 | 0.408 | tINS | FR | 1 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/COUT |
13.948 | 0.000 | tNET | RR | 2 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/CIN |
13.990 | 0.042 | tINS | RF | 1 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/COUT |
13.990 | 0.000 | tNET | FF | 2 | R13C9[2][B] | tx_fifo/fifo_sc_inst/wcnt_sub_5_s/CIN |
14.407 | 0.417 | tINS | FF | 1 | R13C9[2][B] | tx_fifo/fifo_sc_inst/wcnt_sub_5_s/SUM |
14.407 | 0.000 | tNET | FF | 1 | R13C9[2][B] | tx_fifo/fifo_sc_inst/Wnum_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C9[2][B] | tx_fifo/fifo_sc_inst/Wnum_5_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C9[2][B] | tx_fifo/fifo_sc_inst/Wnum_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.306, 40.565%; route: 7.435, 56.838%; tC2Q: 0.340, 2.596% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path14
Path Summary:
Slack | 3.294 |
Data Arrival Time | 14.403 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 2 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q |
1.917 | 0.251 | tNET | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/I2 |
2.732 | 0.814 | tINS | FF | 1 | R7C24[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s6/F |
2.736 | 0.004 | tNET | FF | 1 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/I3 |
3.500 | 0.765 | tINS | FF | 18 | R7C24[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1055_s4/F |
3.895 | 0.394 | tNET | FF | 1 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/I2 |
4.504 | 0.609 | tINS | FF | 3 | R7C26[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n280_s13/F |
4.875 | 0.371 | tNET | FF | 1 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/I0 |
5.689 | 0.814 | tINS | FF | 3 | R7C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s12/F |
5.701 | 0.012 | tNET | FF | 1 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/I1 |
6.311 | 0.609 | tINS | FF | 14 | R7C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_0_s10/F |
6.935 | 0.625 | tNET | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/I0 |
7.700 | 0.765 | tINS | FF | 1 | R8C29[3][B] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_2_s14/F |
8.789 | 1.089 | tNET | FF | 2 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/I1 |
9.564 | 0.774 | tINS | FF | 1 | R12C27[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n787_s0/COUT |
9.564 | 0.000 | tNET | FF | 2 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/CIN |
9.606 | 0.042 | tINS | FF | 1 | R12C27[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n788_s0/COUT |
9.606 | 0.000 | tNET | FF | 2 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/CIN |
9.648 | 0.042 | tINS | FF | 1 | R12C27[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n789_s0/COUT |
9.648 | 0.000 | tNET | FF | 2 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/CIN |
9.690 | 0.042 | tINS | FF | 1 | R12C28[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n790_s0/COUT |
9.690 | 0.000 | tNET | FF | 2 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/CIN |
9.733 | 0.042 | tINS | FF | 1 | R12C28[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n791_s0/COUT |
9.733 | 0.000 | tNET | FF | 2 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/CIN |
9.775 | 0.042 | tINS | FF | 4 | R12C28[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n792_s0/COUT |
10.792 | 1.017 | tNET | FF | 1 | R9C28[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/I2 |
11.606 | 0.814 | tINS | FF | 3 | R9C28[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n982_s15/F |
11.615 | 0.008 | tNET | FF | 1 | R9C28[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s35/I0 |
12.379 | 0.765 | tINS | FF | 1 | R9C28[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s35/F |
12.975 | 0.596 | tNET | FF | 1 | R9C25[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s36/I2 |
13.790 | 0.814 | tINS | FF | 1 | R9C25[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s36/F |
13.794 | 0.004 | tNET | FF | 1 | R9C25[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s32/I2 |
14.403 | 0.609 | tINS | FF | 1 | R9C25[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n988_s32/F |
14.403 | 0.000 | tNET | FF | 1 | R9C25[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R9C25[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2/CLK |
17.697 | -0.296 | tSu | 1 | R9C25[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 8.364, 63.965%; route: 4.372, 33.437%; tC2Q: 0.340, 2.597% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path15
Path Summary:
Slack | 3.332 |
Data Arrival Time | 14.365 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Wnum_4_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
12.199 | 0.417 | tINS | FF | 5 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/SUM |
13.540 | 1.341 | tNET | FF | 2 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/I1 |
13.948 | 0.408 | tINS | FR | 1 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/COUT |
13.948 | 0.000 | tNET | RR | 2 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/CIN |
14.365 | 0.417 | tINS | RF | 1 | R13C9[2][A] | tx_fifo/fifo_sc_inst/wcnt_sub_4_s/SUM |
14.365 | 0.000 | tNET | FF | 1 | R13C9[2][A] | tx_fifo/fifo_sc_inst/Wnum_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C9[2][A] | tx_fifo/fifo_sc_inst/Wnum_4_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C9[2][A] | tx_fifo/fifo_sc_inst/Wnum_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.264, 40.373%; route: 7.435, 57.022%; tC2Q: 0.340, 2.605% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path16
Path Summary:
Slack | 3.637 |
Data Arrival Time | 14.060 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Wnum_3_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
12.199 | 0.417 | tINS | FF | 5 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/SUM |
13.540 | 1.341 | tNET | FF | 2 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/I1 |
14.060 | 0.519 | tINS | FR | 1 | R13C9[1][B] | tx_fifo/fifo_sc_inst/wcnt_sub_3_s/SUM |
14.060 | 0.000 | tNET | RR | 1 | R13C9[1][B] | tx_fifo/fifo_sc_inst/Wnum_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C9[1][B] | tx_fifo/fifo_sc_inst/Wnum_3_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C9[1][B] | tx_fifo/fifo_sc_inst/Wnum_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 10 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 4.959, 38.943%; route: 7.435, 58.390%; tC2Q: 0.340, 2.667% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path17
Path Summary:
Slack | 3.775 |
Data Arrival Time | 13.921 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Wnum_2_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
12.114 | 0.417 | tINS | RF | 5 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/SUM |
13.097 | 0.982 | tNET | FF | 2 | R13C9[0][B] | tx_fifo/fifo_sc_inst/wcnt_sub_1_s/I1 |
13.504 | 0.408 | tINS | FR | 1 | R13C9[0][B] | tx_fifo/fifo_sc_inst/wcnt_sub_1_s/COUT |
13.504 | 0.000 | tNET | RR | 2 | R13C9[1][A] | tx_fifo/fifo_sc_inst/wcnt_sub_2_s/CIN |
13.921 | 0.417 | tINS | RF | 1 | R13C9[1][A] | tx_fifo/fifo_sc_inst/wcnt_sub_2_s/SUM |
13.921 | 0.000 | tNET | FF | 1 | R13C9[1][A] | tx_fifo/fifo_sc_inst/Wnum_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C9[1][A] | tx_fifo/fifo_sc_inst/Wnum_2_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C9[1][A] | tx_fifo/fifo_sc_inst/Wnum_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.180, 41.124%; route: 7.076, 56.179%; tC2Q: 0.340, 2.697% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path18
Path Summary:
Slack | 3.864 |
Data Arrival Time | 13.833 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/PHY_DATAOUT_0_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R6C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 34 | R6C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0/Q |
4.080 | 2.414 | tNET | FF | 1 | R11C9[0][A] | usb_txdat_7_s1/I2 |
4.845 | 0.765 | tINS | FF | 22 | R11C9[0][A] | usb_txdat_7_s1/F |
5.484 | 0.639 | tNET | FF | 1 | R9C8[0][B] | usb_txdat_0_s0/I2 |
6.248 | 0.765 | tINS | FF | 2 | R9C8[0][B] | usb_txdat_0_s0/F |
7.578 | 1.329 | tNET | FF | 1 | R9C22[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s20/I1 |
8.392 | 0.814 | tINS | FF | 1 | R9C22[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s20/F |
8.755 | 0.363 | tNET | FF | 1 | R11C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s16/I1 |
9.218 | 0.463 | tINS | FR | 1 | R11C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s16/F |
9.529 | 0.310 | tNET | RR | 1 | R11C21[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s10/I3 |
10.138 | 0.609 | tINS | RF | 2 | R11C21[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s10/F |
10.738 | 0.600 | tNET | FF | 1 | R11C18[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s7/I0 |
11.347 | 0.609 | tINS | FF | 4 | R11C18[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s7/F |
12.196 | 0.849 | tNET | FF | 1 | R13C17[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n653_s12/I0 |
13.010 | 0.814 | tINS | FF | 2 | R13C17[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n653_s12/F |
13.019 | 0.008 | tNET | FF | 1 | R13C17[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n784_s0/I0 |
13.833 | 0.814 | tINS | FF | 1 | R13C17[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n784_s0/F |
13.833 | 0.000 | tNET | FF | 1 | R13C17[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/PHY_DATAOUT_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C17[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/PHY_DATAOUT_0_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C17[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/PHY_DATAOUT_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.654, 45.207%; route: 6.513, 52.078%; tC2Q: 0.340, 2.716% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path19
Path Summary:
Slack | 3.901 |
Data Arrival Time | 13.796 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/s_state_1_s1 |
To | rx_fifo/fifo_sc_inst/Full_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R9C11[2][A] | u_usb_device_controller_top/u_usb_device_controller/s_state_1_s1/CLK |
1.666 | 0.340 | tC2Q | RF | 23 | R9C11[2][A] | u_usb_device_controller_top/u_usb_device_controller/s_state_1_s1/Q |
2.664 | 0.998 | tNET | FF | 1 | R8C13[2][A] | u_usb_device_controller_top/u_usb_device_controller/rxact_o_d_s1/I1 |
3.429 | 0.765 | tINS | FF | 47 | R8C13[2][A] | u_usb_device_controller_top/u_usb_device_controller/rxact_o_d_s1/F |
4.058 | 0.629 | tNET | FF | 1 | R7C12[3][A] | u_usb_device_controller_top/u_usb_device_controller/rxval_o_d_s0/I0 |
4.667 | 0.609 | tINS | FF | 9 | R7C12[3][A] | u_usb_device_controller_top/u_usb_device_controller/rxval_o_d_s0/F |
6.123 | 1.456 | tNET | FF | 1 | R12C9[3][B] | rx_fifo_wren_s0/I0 |
6.937 | 0.814 | tINS | FF | 1 | R12C9[3][B] | rx_fifo_wren_s0/F |
8.252 | 1.314 | tNET | FF | 1 | R15C6[1][B] | rx_fifo/fifo_sc_inst/n7_s1/I1 |
8.861 | 0.609 | tINS | FF | 2 | R15C6[1][B] | rx_fifo/fifo_sc_inst/n7_s1/F |
9.473 | 0.612 | tNET | FF | 2 | R15C4[0][A] | rx_fifo/fifo_sc_inst/wbin_next_0_s/I1 |
9.881 | 0.408 | tINS | FR | 1 | R15C4[0][A] | rx_fifo/fifo_sc_inst/wbin_next_0_s/COUT |
9.881 | 0.000 | tNET | RR | 2 | R15C4[0][B] | rx_fifo/fifo_sc_inst/wbin_next_1_s/CIN |
9.923 | 0.042 | tINS | RF | 1 | R15C4[0][B] | rx_fifo/fifo_sc_inst/wbin_next_1_s/COUT |
9.923 | 0.000 | tNET | FF | 2 | R15C4[1][A] | rx_fifo/fifo_sc_inst/wbin_next_2_s/CIN |
9.965 | 0.042 | tINS | FF | 1 | R15C4[1][A] | rx_fifo/fifo_sc_inst/wbin_next_2_s/COUT |
9.965 | 0.000 | tNET | FF | 2 | R15C4[1][B] | rx_fifo/fifo_sc_inst/wbin_next_3_s/CIN |
10.007 | 0.042 | tINS | FF | 1 | R15C4[1][B] | rx_fifo/fifo_sc_inst/wbin_next_3_s/COUT |
10.007 | 0.000 | tNET | FF | 2 | R15C4[2][A] | rx_fifo/fifo_sc_inst/wbin_next_4_s/CIN |
10.049 | 0.042 | tINS | FF | 1 | R15C4[2][A] | rx_fifo/fifo_sc_inst/wbin_next_4_s/COUT |
10.049 | 0.000 | tNET | FF | 2 | R15C4[2][B] | rx_fifo/fifo_sc_inst/wbin_next_5_s/CIN |
10.092 | 0.042 | tINS | FF | 1 | R15C4[2][B] | rx_fifo/fifo_sc_inst/wbin_next_5_s/COUT |
10.092 | 0.000 | tNET | FF | 2 | R15C5[0][A] | rx_fifo/fifo_sc_inst/wbin_next_6_s/CIN |
10.509 | 0.417 | tINS | FF | 2 | R15C5[0][A] | rx_fifo/fifo_sc_inst/wbin_next_6_s/SUM |
11.354 | 0.845 | tNET | FF | 1 | R15C6[0][B] | rx_fifo/fifo_sc_inst/wfull_val_s6/I3 |
11.963 | 0.609 | tINS | FF | 1 | R15C6[0][B] | rx_fifo/fifo_sc_inst/wfull_val_s6/F |
11.967 | 0.004 | tNET | FF | 1 | R15C6[2][A] | rx_fifo/fifo_sc_inst/wfull_val_s2/I3 |
12.782 | 0.814 | tINS | FF | 1 | R15C6[2][A] | rx_fifo/fifo_sc_inst/wfull_val_s2/F |
13.031 | 0.249 | tNET | FF | 1 | R15C6[0][A] | rx_fifo/fifo_sc_inst/wfull_val_s0/I1 |
13.796 | 0.765 | tINS | FF | 1 | R15C6[0][A] | rx_fifo/fifo_sc_inst/wfull_val_s0/F |
13.796 | 0.000 | tNET | FF | 1 | R15C6[0][A] | rx_fifo/fifo_sc_inst/Full_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R15C6[0][A] | rx_fifo/fifo_sc_inst/Full_s0/CLK |
17.697 | -0.296 | tSu | 1 | R15C6[0][A] | rx_fifo/fifo_sc_inst/Full_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 6.021, 48.290%; route: 6.108, 48.986%; tC2Q: 0.340, 2.724% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path20
Path Summary:
Slack | 4.081 |
Data Arrival Time | 13.616 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/Wnum_1_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
12.114 | 0.417 | tINS | RF | 5 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/SUM |
13.097 | 0.982 | tNET | FF | 2 | R13C9[0][B] | tx_fifo/fifo_sc_inst/wcnt_sub_1_s/I1 |
13.616 | 0.519 | tINS | FR | 1 | R13C9[0][B] | tx_fifo/fifo_sc_inst/wcnt_sub_1_s/SUM |
13.616 | 0.000 | tNET | RR | 1 | R13C9[0][B] | tx_fifo/fifo_sc_inst/Wnum_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R13C9[0][B] | tx_fifo/fifo_sc_inst/Wnum_1_s0/CLK |
17.697 | -0.296 | tSu | 1 | R13C9[0][B] | tx_fifo/fifo_sc_inst/Wnum_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 10 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 4.874, 39.662%; route: 7.076, 57.575%; tC2Q: 0.340, 2.763% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path21
Path Summary:
Slack | 4.161 |
Data Arrival Time | 13.535 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_0_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_1_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R6C16[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_0_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 29 | R6C16[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_0_s0/Q |
3.724 | 2.058 | tNET | FF | 1 | R9C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbt_stall_s3/I0 |
4.333 | 0.609 | tINS | FF | 24 | R9C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbt_stall_s3/F |
5.692 | 1.359 | tNET | FF | 1 | R12C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n781_s7/I1 |
6.507 | 0.814 | tINS | FF | 7 | R12C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n781_s7/F |
7.371 | 0.865 | tNET | FF | 1 | R13C18[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n641_s16/I0 |
8.186 | 0.814 | tINS | FF | 1 | R13C18[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n641_s16/F |
8.190 | 0.004 | tNET | FF | 1 | R13C18[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n641_s15/I0 |
9.004 | 0.814 | tINS | FF | 2 | R13C18[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n641_s15/F |
9.852 | 0.848 | tNET | FF | 1 | R9C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n773_s3/I0 |
10.617 | 0.765 | tINS | FF | 5 | R9C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n773_s3/F |
11.711 | 1.094 | tNET | FF | 1 | R14C20[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n774_s2/I0 |
12.174 | 0.464 | tINS | FF | 1 | R14C20[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n774_s2/F |
12.771 | 0.596 | tNET | FF | 1 | R11C20[2][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n774_s1/I0 |
13.535 | 0.765 | tINS | FF | 1 | R11C20[2][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n774_s1/F |
13.535 | 0.000 | tNET | FF | 1 | R11C20[2][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R11C20[2][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_1_s1/CLK |
17.697 | -0.296 | tSu | 1 | R11C20[2][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.045, 41.326%; route: 6.824, 55.892%; tC2Q: 0.340, 2.782% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path22
Path Summary:
Slack | 4.245 |
Data Arrival Time | 13.451 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/rbin_7_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
11.824 | 0.042 | tINS | FF | 1 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/COUT |
11.824 | 0.000 | tNET | FF | 2 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/CIN |
11.866 | 0.042 | tINS | FF | 1 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/COUT |
11.866 | 0.000 | tNET | FF | 2 | R13C6[2][B] | tx_fifo/fifo_sc_inst/rbin_next_5_s/CIN |
11.908 | 0.042 | tINS | FF | 1 | R13C6[2][B] | tx_fifo/fifo_sc_inst/rbin_next_5_s/COUT |
11.908 | 0.000 | tNET | FF | 2 | R13C7[0][A] | tx_fifo/fifo_sc_inst/rbin_next_6_s/CIN |
11.951 | 0.042 | tINS | FF | 1 | R13C7[0][A] | tx_fifo/fifo_sc_inst/rbin_next_6_s/COUT |
11.951 | 0.000 | tNET | FF | 2 | R13C7[0][B] | tx_fifo/fifo_sc_inst/rbin_next_7_s/CIN |
12.368 | 0.417 | tINS | FF | 5 | R13C7[0][B] | tx_fifo/fifo_sc_inst/rbin_next_7_s/SUM |
13.451 | 1.084 | tNET | FF | 1 | R12C7[1][B] | tx_fifo/fifo_sc_inst/rbin_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R12C7[1][B] | tx_fifo/fifo_sc_inst/rbin_7_s0/CLK |
17.697 | -0.296 | tSu | 1 | R12C7[1][B] | tx_fifo/fifo_sc_inst/rbin_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 10 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 4.608, 38.006%; route: 7.177, 59.193%; tC2Q: 0.340, 2.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path23
Path Summary:
Slack | 4.269 |
Data Arrival Time | 13.427 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_0_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_15_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R6C16[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_0_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 29 | R6C16[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_0_s0/Q |
3.724 | 2.058 | tNET | FF | 1 | R9C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbt_stall_s3/I0 |
4.333 | 0.609 | tINS | FF | 24 | R9C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usbt_stall_s3/F |
5.692 | 1.359 | tNET | FF | 1 | R12C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n781_s7/I1 |
6.507 | 0.814 | tINS | FF | 7 | R12C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n781_s7/F |
7.371 | 0.865 | tNET | FF | 1 | R13C18[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n641_s16/I0 |
8.186 | 0.814 | tINS | FF | 1 | R13C18[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n641_s16/F |
8.190 | 0.004 | tNET | FF | 1 | R13C18[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n641_s15/I0 |
9.004 | 0.814 | tINS | FF | 2 | R13C18[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n641_s15/F |
9.852 | 0.848 | tNET | FF | 1 | R9C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n773_s3/I0 |
10.617 | 0.765 | tINS | FF | 5 | R9C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n773_s3/F |
11.592 | 0.975 | tNET | FF | 1 | R12C20[2][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n760_s2/I0 |
12.352 | 0.760 | tINS | FR | 1 | R12C20[2][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n760_s2/F |
12.663 | 0.310 | tNET | RR | 1 | R11C20[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n760_s1/I0 |
13.427 | 0.765 | tINS | RF | 1 | R11C20[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n760_s1/F |
13.427 | 0.000 | tNET | FF | 1 | R11C20[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R11C20[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_15_s1/CLK |
17.697 | -0.296 | tSu | 1 | R11C20[2][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.342, 44.144%; route: 6.420, 53.050%; tC2Q: 0.340, 2.807% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path24
Path Summary:
Slack | 4.293 |
Data Arrival Time | 13.403 |
Data Required Time | 17.697 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_8_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R6C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0/CLK |
1.666 | 0.340 | tC2Q | RF | 34 | R6C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_2_s0/Q |
4.080 | 2.414 | tNET | FF | 1 | R11C9[0][A] | usb_txdat_7_s1/I2 |
4.845 | 0.765 | tINS | FF | 22 | R11C9[0][A] | usb_txdat_7_s1/F |
5.484 | 0.639 | tNET | FF | 1 | R9C8[0][B] | usb_txdat_0_s0/I2 |
6.248 | 0.765 | tINS | FF | 2 | R9C8[0][B] | usb_txdat_0_s0/F |
7.578 | 1.329 | tNET | FF | 1 | R9C22[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s20/I1 |
8.392 | 0.814 | tINS | FF | 1 | R9C22[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s20/F |
8.755 | 0.363 | tNET | FF | 1 | R11C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s16/I1 |
9.218 | 0.463 | tINS | FR | 1 | R11C22[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s16/F |
9.529 | 0.310 | tNET | RR | 1 | R11C21[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s10/I3 |
10.138 | 0.609 | tINS | RF | 2 | R11C21[1][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n327_s10/F |
10.750 | 0.612 | tNET | FF | 1 | R11C19[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n766_s2/I0 |
11.359 | 0.609 | tINS | FF | 2 | R11C19[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n766_s2/F |
11.367 | 0.008 | tNET | FF | 1 | R11C19[2][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n775_s3/I3 |
11.976 | 0.609 | tINS | FF | 4 | R11C19[2][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n775_s3/F |
12.589 | 0.613 | tNET | FF | 1 | R12C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n767_s1/I1 |
13.403 | 0.814 | tINS | FF | 1 | R12C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n767_s1/F |
13.403 | 0.000 | tNET | FF | 1 | R12C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | R12C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_8_s1/CLK |
17.697 | -0.296 | tSu | 1 | R12C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/crc16_buf_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 5.449, 45.116%; route: 6.289, 52.072%; tC2Q: 0.340, 2.812% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path25
Path Summary:
Slack | 4.309 |
Data Arrival Time | 13.652 |
Data Required Time | 17.961 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12 |
To | tx_fifo/fifo_sc_inst/mem_mem_0_0_s |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.326 | 0.181 | tNET | RR | 1 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/CLK |
1.666 | 0.340 | tC2Q | RF | 7 | R11C15[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_state_3_s12/Q |
2.280 | 0.614 | tNET | FF | 1 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/I1 |
3.045 | 0.765 | tINS | FF | 4 | R12C14[3][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n917_s3/F |
3.652 | 0.607 | tNET | FF | 1 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/I3 |
4.116 | 0.464 | tINS | FF | 6 | R13C16[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s5/F |
5.083 | 0.967 | tNET | FF | 1 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/I3 |
5.848 | 0.765 | tINS | FF | 19 | R12C17[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n621_s40/F |
7.080 | 1.232 | tNET | FF | 1 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/I0 |
7.689 | 0.609 | tINS | FF | 7 | R8C21[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s2/F |
9.399 | 1.710 | tNET | FF | 1 | R12C9[1][A] | tx_fifo_rd_s0/I0 |
9.863 | 0.464 | tINS | FF | 2 | R12C9[1][A] | tx_fifo_rd_s0/F |
10.230 | 0.367 | tNET | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/I1 |
10.694 | 0.464 | tINS | FF | 1 | R12C7[2][A] | tx_fifo/fifo_sc_inst/n78_s0/F |
11.290 | 0.596 | tNET | FF | 2 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/I1 |
11.697 | 0.408 | tINS | FR | 1 | R13C6[0][A] | tx_fifo/fifo_sc_inst/rbin_next_0_s/COUT |
11.697 | 0.000 | tNET | RR | 2 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/CIN |
11.739 | 0.042 | tINS | RF | 1 | R13C6[0][B] | tx_fifo/fifo_sc_inst/rbin_next_1_s/COUT |
11.739 | 0.000 | tNET | FF | 2 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/CIN |
11.782 | 0.042 | tINS | FF | 1 | R13C6[1][A] | tx_fifo/fifo_sc_inst/rbin_next_2_s/COUT |
11.782 | 0.000 | tNET | FF | 2 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/CIN |
11.824 | 0.042 | tINS | FF | 1 | R13C6[1][B] | tx_fifo/fifo_sc_inst/rbin_next_3_s/COUT |
11.824 | 0.000 | tNET | FF | 2 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/CIN |
11.866 | 0.042 | tINS | FF | 1 | R13C6[2][A] | tx_fifo/fifo_sc_inst/rbin_next_4_s/COUT |
11.866 | 0.000 | tNET | FF | 2 | R13C6[2][B] | tx_fifo/fifo_sc_inst/rbin_next_5_s/CIN |
11.908 | 0.042 | tINS | FF | 1 | R13C6[2][B] | tx_fifo/fifo_sc_inst/rbin_next_5_s/COUT |
11.908 | 0.000 | tNET | FF | 2 | R13C7[0][A] | tx_fifo/fifo_sc_inst/rbin_next_6_s/CIN |
12.326 | 0.417 | tINS | FF | 5 | R13C7[0][A] | tx_fifo/fifo_sc_inst/rbin_next_6_s/SUM |
13.652 | 1.326 | tNET | FF | 1 | BSRAM_R10[2] | tx_fifo/fifo_sc_inst/mem_mem_0_0_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
17.812 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
17.993 | 0.181 | tNET | RR | 1 | BSRAM_R10[2] | tx_fifo/fifo_sc_inst/mem_mem_0_0_s/CLKB |
17.961 | -0.032 | tSu | 1 | BSRAM_R10[2] | tx_fifo/fifo_sc_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 10 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 4.566, 37.045%; route: 7.420, 60.199%; tC2Q: 0.340, 2.755% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_q_s4 |
To | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_q_s4 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R15C21[1][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_q_s4/CLK |
1.529 | 0.247 | tC2Q | RR | 3 | R15C21[1][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_q_s4/Q |
1.531 | 0.002 | tNET | RR | 1 | R15C21[1][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/n51_s2/I0 |
1.807 | 0.276 | tINS | RF | 1 | R15C21[1][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/n51_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R15C21[1][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_q_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R15C21[1][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_q_s4/CLK |
1.282 | 0.000 | tHld | 1 | R15C21[1][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_q_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path2
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4 |
To | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R13C37[0][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R13C37[0][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4/Q |
1.531 | 0.002 | tNET | RR | 1 | R13C37[0][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/n29_s2/I0 |
1.807 | 0.276 | tINS | RF | 1 | R13C37[0][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/n29_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R13C37[0][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R13C37[0][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4/CLK |
1.282 | 0.000 | tHld | 1 | R13C37[0][A] | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path3
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q |
1.531 | 0.002 | tNET | RR | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n274_s9/I2 |
1.807 | 0.276 | tINS | RF | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n274_s9/F |
1.807 | 0.000 | tNET | FF | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/CLK |
1.282 | 0.000 | tHld | 1 | R7C24[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path4
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_4_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_4_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R6C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_4_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 4 | R6C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_4_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R6C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/n958_s16/I1 |
1.807 | 0.276 | tINS | RF | 1 | R6C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/n958_s16/F |
1.807 | 0.000 | tNET | FF | 1 | R6C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R6C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_4_s1/CLK |
1.282 | 0.000 | tHld | 1 | R6C20[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path5
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_9_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_9_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R6C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_9_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R6C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_9_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R6C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/n948_s12/I2 |
1.807 | 0.276 | tINS | RF | 1 | R6C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/n948_s12/F |
1.807 | 0.000 | tNET | FF | 1 | R6C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R6C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_9_s1/CLK |
1.282 | 0.000 | tHld | 1 | R6C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path6
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_11_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_11_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R8C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_11_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R8C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_11_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R8C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/n942_s12/I2 |
1.807 | 0.276 | tINS | RF | 1 | R8C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/n942_s12/F |
1.807 | 0.000 | tNET | FF | 1 | R8C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R8C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_11_s1/CLK |
1.282 | 0.000 | tHld | 1 | R8C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path7
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_13_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_13_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R7C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_13_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 3 | R7C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_13_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R7C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/n936_s12/I2 |
1.807 | 0.276 | tINS | RF | 1 | R7C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/n936_s12/F |
1.807 | 0.000 | tNET | FF | 1 | R7C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_13_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R7C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_13_s1/CLK |
1.282 | 0.000 | tHld | 1 | R7C21[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/wait_count_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path8
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_3_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_3_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R14C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_3_s0/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R14C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_3_s0/Q |
1.531 | 0.002 | tNET | RR | 1 | R14C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n647_s12/I1 |
1.807 | 0.276 | tINS | RF | 1 | R14C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n647_s12/F |
1.807 | 0.000 | tNET | FF | 1 | R14C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R14C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_3_s0/CLK |
1.282 | 0.000 | tHld | 1 | R14C19[1][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path9
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s0/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R12C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s0/Q |
1.531 | 0.002 | tNET | RR | 1 | R12C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n639_s12/I1 |
1.807 | 0.276 | tINS | RF | 1 | R12C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n639_s12/F |
1.807 | 0.000 | tNET | FF | 1 | R12C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s0/CLK |
1.282 | 0.000 | tHld | 1 | R12C19[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/s_dataout_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path10
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer2_0_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer2_0_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R6C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer2_0_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 3 | R6C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer2_0_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R6C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/n243_s3/I1 |
1.807 | 0.276 | tINS | RF | 1 | R6C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/n243_s3/F |
1.807 | 0.000 | tNET | FF | 1 | R6C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer2_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R6C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer2_0_s1/CLK |
1.282 | 0.000 | tHld | 1 | R6C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer2_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path11
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer1_0_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer1_0_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R7C29[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer1_0_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 3 | R7C29[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer1_0_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R7C29[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/n213_s3/I0 |
1.807 | 0.276 | tINS | RF | 1 | R7C29[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/n213_s3/F |
1.807 | 0.000 | tNET | FF | 1 | R7C29[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer1_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R7C29[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer1_0_s1/CLK |
1.282 | 0.000 | tHld | 1 | R7C29[0][A] | u_usb_device_controller_top/u_usb_device_controller/u_usb_init/s_timer1_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path12
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_15_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_15_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C31[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_15_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R12C31[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_15_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R12C31[1][A] | u_usb_device_controller_top/u_usb_device_controller/n1107_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R12C31[1][A] | u_usb_device_controller_top/u_usb_device_controller/n1107_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R12C31[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C31[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_15_s1/CLK |
1.282 | 0.000 | tHld | 1 | R12C31[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path13
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_13_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_13_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_13_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R12C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_13_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R12C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/n983_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R12C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/n983_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R12C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_13_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_13_s1/CLK |
1.282 | 0.000 | tHld | 1 | R12C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path14
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_12_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_12_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C31[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_12_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R12C31[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_12_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R12C31[0][A] | u_usb_device_controller_top/u_usb_device_controller/n922_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R12C31[0][A] | u_usb_device_controller_top/u_usb_device_controller/n922_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R12C31[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C31[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_12_s1/CLK |
1.282 | 0.000 | tHld | 1 | R12C31[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path15
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_11_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_11_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C30[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_11_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R11C30[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_11_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R11C30[1][A] | u_usb_device_controller_top/u_usb_device_controller/n863_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R11C30[1][A] | u_usb_device_controller_top/u_usb_device_controller/n863_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R11C30[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_11_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C30[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_11_s1/CLK |
1.282 | 0.000 | tHld | 1 | R11C30[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path16
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_10_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_10_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_10_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R11C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_10_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R11C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/n802_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R11C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/n802_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R11C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_10_s1/CLK |
1.282 | 0.000 | tHld | 1 | R11C30[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path17
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/osync_9_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/osync_9_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R6C14[1][A] | u_usb_device_controller_top/u_usb_device_controller/osync_9_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 3 | R6C14[1][A] | u_usb_device_controller_top/u_usb_device_controller/osync_9_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R6C14[1][A] | u_usb_device_controller_top/u_usb_device_controller/n744_s1/I1 |
1.807 | 0.276 | tINS | RF | 1 | R6C14[1][A] | u_usb_device_controller_top/u_usb_device_controller/n744_s1/F |
1.807 | 0.000 | tNET | FF | 1 | R6C14[1][A] | u_usb_device_controller_top/u_usb_device_controller/osync_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R6C14[1][A] | u_usb_device_controller_top/u_usb_device_controller/osync_9_s1/CLK |
1.282 | 0.000 | tHld | 1 | R6C14[1][A] | u_usb_device_controller_top/u_usb_device_controller/osync_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path18
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_7_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_7_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_7_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R11C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_7_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R11C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/n627_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R11C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/n627_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R11C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_7_s1/CLK |
1.282 | 0.000 | tHld | 1 | R11C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path19
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_6_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_6_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C33[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_6_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R11C33[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_6_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R11C33[0][A] | u_usb_device_controller_top/u_usb_device_controller/n566_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R11C33[0][A] | u_usb_device_controller_top/u_usb_device_controller/n566_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R11C33[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C33[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_6_s1/CLK |
1.282 | 0.000 | tHld | 1 | R11C33[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path20
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/osync_5_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/osync_5_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R5C13[0][A] | u_usb_device_controller_top/u_usb_device_controller/osync_5_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 3 | R5C13[0][A] | u_usb_device_controller_top/u_usb_device_controller/osync_5_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R5C13[0][A] | u_usb_device_controller_top/u_usb_device_controller/n508_s1/I1 |
1.807 | 0.276 | tINS | RF | 1 | R5C13[0][A] | u_usb_device_controller_top/u_usb_device_controller/n508_s1/F |
1.807 | 0.000 | tNET | FF | 1 | R5C13[0][A] | u_usb_device_controller_top/u_usb_device_controller/osync_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R5C13[0][A] | u_usb_device_controller_top/u_usb_device_controller/osync_5_s1/CLK |
1.282 | 0.000 | tHld | 1 | R5C13[0][A] | u_usb_device_controller_top/u_usb_device_controller/osync_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path21
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_5_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_5_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_5_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R12C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_5_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R12C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/n507_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R12C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/n507_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R12C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_5_s1/CLK |
1.282 | 0.000 | tHld | 1 | R12C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/isync_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path22
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_4_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_4_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_4_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R11C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_4_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R11C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/n448_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R11C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/n448_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R11C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_4_s1/CLK |
1.282 | 0.000 | tHld | 1 | R11C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path23
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | u_usb_device_controller_top/u_usb_device_controller/isync_3_s1 |
To | u_usb_device_controller_top/u_usb_device_controller/isync_3_s1 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C33[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_3_s1/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R11C33[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_3_s1/Q |
1.531 | 0.002 | tNET | RR | 1 | R11C33[1][A] | u_usb_device_controller_top/u_usb_device_controller/n391_s2/I1 |
1.807 | 0.276 | tINS | RF | 1 | R11C33[1][A] | u_usb_device_controller_top/u_usb_device_controller/n391_s2/F |
1.807 | 0.000 | tNET | FF | 1 | R11C33[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C33[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_3_s1/CLK |
1.282 | 0.000 | tHld | 1 | R11C33[1][A] | u_usb_device_controller_top/u_usb_device_controller/isync_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path24
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | led_cnt_3_s0 |
To | led_cnt_3_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C4[0][A] | led_cnt_3_s0/CLK |
1.529 | 0.247 | tC2Q | RR | 2 | R11C4[0][A] | led_cnt_3_s0/Q |
1.531 | 0.002 | tNET | RR | 1 | R11C4[0][A] | n70_s1/I1 |
1.807 | 0.276 | tINS | RF | 1 | R11C4[0][A] | n70_s1/F |
1.807 | 0.000 | tNET | FF | 1 | R11C4[0][A] | led_cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R11C4[0][A] | led_cnt_3_s0/CLK |
1.282 | 0.000 | tHld | 1 | R11C4[0][A] | led_cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path25
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.807 |
Data Required Time | 1.282 |
From | led_cnt_10_s0 |
To | led_cnt_10_s0 |
Launch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_pll/pllvr_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C4[1][A] | led_cnt_10_s0/CLK |
1.529 | 0.247 | tC2Q | RR | 4 | R12C4[1][A] | led_cnt_10_s0/Q |
1.531 | 0.002 | tNET | RR | 1 | R12C4[1][A] | n63_s1/I1 |
1.807 | 0.276 | tINS | RF | 1 | R12C4[1][A] | n63_s1/F |
1.807 | 0.000 | tNET | FF | 1 | R12C4[1][A] | led_cnt_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||||
1.146 | 1.146 | tCL | RR | 518 | PLL_L | u_pll/pllvr_inst/CLKOUT |
1.282 | 0.137 | tNET | RR | 1 | R12C4[1][A] | led_cnt_10_s0/CLK |
1.282 | 0.000 | tHld | 1 | R12C4[1][A] | led_cnt_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | led_cnt_15_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | led_cnt_15_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | led_cnt_15_s0/CLK |
MPW2
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | led_cnt_13_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | led_cnt_13_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | led_cnt_13_s0/CLK |
MPW3
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | led_cnt_9_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | led_cnt_9_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | led_cnt_9_s0/CLK |
MPW4
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | led_cnt_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | led_cnt_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | led_cnt_1_s0/CLK |
MPW5
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | s_req_code_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | s_req_code_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | s_req_code_1_s0/CLK |
MPW6
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | s_dte_rate_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | s_dte_rate_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | s_dte_rate_1_s0/CLK |
MPW7
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | tx_fifo/fifo_sc_inst/wbin_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | tx_fifo/fifo_sc_inst/wbin_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | tx_fifo/fifo_sc_inst/wbin_4_s0/CLK |
MPW8
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | u_usb_device_controller_top/u_usb_device_controller/isync_14_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | u_usb_device_controller_top/u_usb_device_controller/isync_14_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | u_usb_device_controller_top/u_usb_device_controller/isync_14_s1/CLK |
MPW9
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/rxd_ms_s4/CLK |
MPW10
MPW Summary:
Slack: | 7.349 |
Actual Width: | 8.276 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | u_pll/pllvr_inst/CLKOUT.default_gen_clk |
Objects: | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/out_dn_q_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
9.479 | 1.146 | tCL | FF | u_pll/pllvr_inst/CLKOUT |
9.673 | 0.195 | tNET | FF | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/out_dn_q_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | u_pll/pllvr_inst/CLKOUT.default_gen_clk | ||
17.812 | 1.146 | tCL | RR | u_pll/pllvr_inst/CLKOUT |
17.949 | 0.137 | tNET | RR | u_USB_SoftPHY_Top/u_usb_phy/u_usb_phy_rt/out_dn_q_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
518 | PHY_CLKOUT | 1.472 | 0.195 |
88 | usb_busreset | 9.216 | 2.431 |
64 | n275_9 | 10.502 | 2.467 |
54 | setup_active | 4.611 | 1.384 |
47 | usb_rxact | 3.901 | 1.235 |
46 | n2102_3 | 9.216 | 5.682 |
38 | n2417_5 | 6.434 | 1.975 |
36 | state_q[1] | 8.644 | 2.078 |
36 | state_q[2] | 8.335 | 1.258 |
35 | state_q[0] | 8.395 | 1.493 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R5C32 | 88.89% |
R5C31 | 86.11% |
R13C9 | 83.33% |
R14C18 | 83.33% |
R15C19 | 83.33% |
R7C12 | 81.94% |
R8C8 | 81.94% |
R12C6 | 80.56% |
R13C32 | 80.56% |
R14C26 | 79.17% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|