Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\USB_DEVICE_CONTROLLER\data\usb_device_controller_top.v
C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\USB_DEVICE_CONTROLLER\data\usb_device_controller.vp
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NSR-LV4MG64PC7/I6
Device GW1NSR-4
Created Time Fri Mar 05 10:20:51 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module USB_Device_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 57.832MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 57.832MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 57.832MB
    Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 57.832MB
    Optimizing Phase 2: CPU time = 0h 0m 0.124s, Elapsed time = 0h 0m 0.123s, Peak memory usage = 57.832MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 57.832MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 57.832MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 57.832MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 57.832MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 57.832MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 57.832MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 57.832MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 7s, Peak memory usage = 74.449MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 74.449MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 74.449MB
Total Time and Memory Usage CPU time = 0h 0m 7s, Elapsed time = 0h 0m 8s, Peak memory usage = 74.449MB

Resource

Resource Usage Summary

I/O Port 242
I/O Buf 196
    IBUF 148
    OBUF 48
Register 307
    DFF 15
    DFFE 77
    DFFS 6
    DFFSE 3
    DFFR 23
    DFFRE 154
    DFFC 10
    DFFCE 19
LUT 885
    LUT2 102
    LUT3 240
    LUT4 543
ALU 71
    ALU 71
INV 2
    INV 2

Resource Utilization Summary

Logic 958(887 LUTs, 71 ALUs) / 4608 21%
Register 307 / 3624 8%
  --Register as Latch 0 / 3624 0%
  --Register as FF 307 / 3624 8%
BSRAM 0 / 10 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 10.000 100.0 0.000 5.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 100.0(MHz) 76.3(MHz) 14 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -3.109
Data Arrival Time 13.809
Data Required Time 10.700
From u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0
To u_usb_device_controller/usb_control_inst/s_answerptr_3_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 307 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/CLK
1.336 0.340 tC2Q RF 3 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/Q
1.692 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/I1
2.506 0.814 tINS FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/F
2.862 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s4/I3
3.326 0.464 tINS FF 21 u_usb_device_controller/usb_control_inst/n1055_s4/F
3.681 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n280_s13/I2
4.291 0.609 tINS FF 3 u_usb_device_controller/usb_control_inst/n280_s13/F
4.646 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s12/I0
5.411 0.765 tINS FF 3 u_usb_device_controller/usbc_dsclen_0_s12/F
5.767 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s10/I1
6.581 0.814 tINS FF 17 u_usb_device_controller/usbc_dsclen_0_s10/F
6.937 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s16/I0
7.701 0.765 tINS FF 1 u_usb_device_controller/usbc_dsclen_0_s16/F
8.057 0.356 tNET FF 2 u_usb_device_controller/usb_control_inst/n785_s0/I1
8.831 0.774 tINS FF 1 u_usb_device_controller/usb_control_inst/n785_s0/COUT
8.831 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n786_s0/CIN
8.874 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n786_s0/COUT
8.874 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n787_s0/CIN
8.916 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n787_s0/COUT
8.916 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n788_s0/CIN
8.958 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n788_s0/COUT
8.958 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n789_s0/CIN
9.000 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n789_s0/COUT
9.000 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n790_s0/CIN
9.043 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n790_s0/COUT
9.043 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n791_s0/CIN
9.085 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n791_s0/COUT
9.085 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n792_s0/CIN
9.127 0.042 tINS FF 4 u_usb_device_controller/usb_control_inst/n792_s0/COUT
9.483 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n982_s15/I2
10.092 0.609 tINS FF 3 u_usb_device_controller/usb_control_inst/n982_s15/F
10.448 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n970_s14/I0
11.212 0.765 tINS FF 3 u_usb_device_controller/usb_control_inst/n970_s14/F
11.568 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n973_s12/I0
12.333 0.765 tINS FF 1 u_usb_device_controller/usb_control_inst/n973_s12/F
12.688 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n973_s11/I0
13.453 0.765 tINS FF 1 u_usb_device_controller/usb_control_inst/n973_s11/F
13.809 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/s_answerptr_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.728 0.728 tINS RR 307 clk_i_ibuf/O
10.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_answerptr_3_s0/CLK
10.700 -0.296 tSu 1 u_usb_device_controller/usb_control_inst/s_answerptr_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 8.204, 64.036%; route: 4.268, 33.313%; tC2Q: 0.340, 2.651%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 2

Path Summary:
Slack -3.109
Data Arrival Time 13.809
Data Required Time 10.700
From u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0
To u_usb_device_controller/usb_control_inst/s_answerptr_4_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 307 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/CLK
1.336 0.340 tC2Q RF 3 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/Q
1.692 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/I1
2.506 0.814 tINS FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/F
2.862 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s4/I3
3.326 0.464 tINS FF 21 u_usb_device_controller/usb_control_inst/n1055_s4/F
3.681 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n280_s13/I2
4.291 0.609 tINS FF 3 u_usb_device_controller/usb_control_inst/n280_s13/F
4.646 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s12/I0
5.411 0.765 tINS FF 3 u_usb_device_controller/usbc_dsclen_0_s12/F
5.767 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s10/I1
6.581 0.814 tINS FF 17 u_usb_device_controller/usbc_dsclen_0_s10/F
6.937 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s16/I0
7.701 0.765 tINS FF 1 u_usb_device_controller/usbc_dsclen_0_s16/F
8.057 0.356 tNET FF 2 u_usb_device_controller/usb_control_inst/n785_s0/I1
8.831 0.774 tINS FF 1 u_usb_device_controller/usb_control_inst/n785_s0/COUT
8.831 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n786_s0/CIN
8.874 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n786_s0/COUT
8.874 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n787_s0/CIN
8.916 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n787_s0/COUT
8.916 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n788_s0/CIN
8.958 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n788_s0/COUT
8.958 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n789_s0/CIN
9.000 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n789_s0/COUT
9.000 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n790_s0/CIN
9.043 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n790_s0/COUT
9.043 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n791_s0/CIN
9.085 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n791_s0/COUT
9.085 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n792_s0/CIN
9.127 0.042 tINS FF 4 u_usb_device_controller/usb_control_inst/n792_s0/COUT
9.483 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n982_s15/I2
10.092 0.609 tINS FF 3 u_usb_device_controller/usb_control_inst/n982_s15/F
10.448 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n970_s14/I0
11.212 0.765 tINS FF 3 u_usb_device_controller/usb_control_inst/n970_s14/F
11.568 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n970_s12/I0
12.333 0.765 tINS FF 1 u_usb_device_controller/usb_control_inst/n970_s12/F
12.688 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n970_s11/I0
13.453 0.765 tINS FF 1 u_usb_device_controller/usb_control_inst/n970_s11/F
13.809 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/s_answerptr_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.728 0.728 tINS RR 307 clk_i_ibuf/O
10.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_answerptr_4_s0/CLK
10.700 -0.296 tSu 1 u_usb_device_controller/usb_control_inst/s_answerptr_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 8.204, 64.036%; route: 4.268, 33.313%; tC2Q: 0.340, 2.651%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 3

Path Summary:
Slack -2.953
Data Arrival Time 13.653
Data Required Time 10.700
From u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0
To u_usb_device_controller/usb_control_inst/s_answerptr_2_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 307 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/CLK
1.336 0.340 tC2Q RF 3 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/Q
1.692 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/I1
2.506 0.814 tINS FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/F
2.862 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s4/I3
3.326 0.464 tINS FF 21 u_usb_device_controller/usb_control_inst/n1055_s4/F
3.681 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n280_s13/I2
4.291 0.609 tINS FF 3 u_usb_device_controller/usb_control_inst/n280_s13/F
4.646 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s12/I0
5.411 0.765 tINS FF 3 u_usb_device_controller/usbc_dsclen_0_s12/F
5.767 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s10/I1
6.581 0.814 tINS FF 17 u_usb_device_controller/usbc_dsclen_0_s10/F
6.937 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s16/I0
7.701 0.765 tINS FF 1 u_usb_device_controller/usbc_dsclen_0_s16/F
8.057 0.356 tNET FF 2 u_usb_device_controller/usb_control_inst/n785_s0/I1
8.831 0.774 tINS FF 1 u_usb_device_controller/usb_control_inst/n785_s0/COUT
8.831 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n786_s0/CIN
8.874 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n786_s0/COUT
8.874 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n787_s0/CIN
8.916 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n787_s0/COUT
8.916 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n788_s0/CIN
8.958 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n788_s0/COUT
8.958 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n789_s0/CIN
9.000 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n789_s0/COUT
9.000 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n790_s0/CIN
9.043 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n790_s0/COUT
9.043 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n791_s0/CIN
9.085 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n791_s0/COUT
9.085 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n792_s0/CIN
9.127 0.042 tINS FF 4 u_usb_device_controller/usb_control_inst/n792_s0/COUT
9.483 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n982_s15/I2
10.092 0.609 tINS FF 3 u_usb_device_controller/usb_control_inst/n982_s15/F
10.448 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n970_s14/I0
11.212 0.765 tINS FF 3 u_usb_device_controller/usb_control_inst/n970_s14/F
11.568 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n976_s13/I2
12.177 0.609 tINS FF 1 u_usb_device_controller/usb_control_inst/n976_s13/F
12.533 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n976_s11/I0
13.297 0.765 tINS FF 1 u_usb_device_controller/usb_control_inst/n976_s11/F
13.653 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/s_answerptr_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.728 0.728 tINS RR 307 clk_i_ibuf/O
10.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_answerptr_2_s0/CLK
10.700 -0.296 tSu 1 u_usb_device_controller/usb_control_inst/s_answerptr_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 8.049, 63.594%; route: 4.268, 33.723%; tC2Q: 0.340, 2.683%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack -2.797
Data Arrival Time 13.497
Data Required Time 10.700
From u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0
To u_usb_device_controller/usb_control_inst/s_state_9_s2
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 307 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/CLK
1.336 0.340 tC2Q RF 3 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/Q
1.692 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/I1
2.506 0.814 tINS FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/F
2.862 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s4/I3
3.326 0.464 tINS FF 21 u_usb_device_controller/usb_control_inst/n1055_s4/F
3.681 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n280_s13/I2
4.291 0.609 tINS FF 3 u_usb_device_controller/usb_control_inst/n280_s13/F
4.646 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s12/I0
5.411 0.765 tINS FF 3 u_usb_device_controller/usbc_dsclen_0_s12/F
5.767 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s10/I1
6.581 0.814 tINS FF 17 u_usb_device_controller/usbc_dsclen_0_s10/F
6.937 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s16/I0
7.701 0.765 tINS FF 1 u_usb_device_controller/usbc_dsclen_0_s16/F
8.057 0.356 tNET FF 2 u_usb_device_controller/usb_control_inst/n785_s0/I1
8.831 0.774 tINS FF 1 u_usb_device_controller/usb_control_inst/n785_s0/COUT
8.831 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n786_s0/CIN
8.874 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n786_s0/COUT
8.874 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n787_s0/CIN
8.916 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n787_s0/COUT
8.916 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n788_s0/CIN
8.958 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n788_s0/COUT
8.958 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n789_s0/CIN
9.000 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n789_s0/COUT
9.000 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n790_s0/CIN
9.043 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n790_s0/COUT
9.043 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n791_s0/CIN
9.085 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n791_s0/COUT
9.085 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n792_s0/CIN
9.127 0.042 tINS FF 4 u_usb_device_controller/usb_control_inst/n792_s0/COUT
9.483 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n982_s15/I2
10.092 0.609 tINS FF 3 u_usb_device_controller/usb_control_inst/n982_s15/F
10.448 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n988_s35/I0
11.212 0.765 tINS FF 1 u_usb_device_controller/usb_control_inst/n988_s35/F
11.568 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n988_s36/I2
12.177 0.609 tINS FF 1 u_usb_device_controller/usb_control_inst/n988_s36/F
12.533 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n988_s32/I2
13.142 0.609 tINS FF 1 u_usb_device_controller/usb_control_inst/n988_s32/F
13.497 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/s_state_9_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.728 0.728 tINS RR 307 clk_i_ibuf/O
10.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_state_9_s2/CLK
10.700 -0.296 tSu 1 u_usb_device_controller/usb_control_inst/s_state_9_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 7.893, 63.140%; route: 4.268, 34.143%; tC2Q: 0.340, 2.717%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 5

Path Summary:
Slack -1.893
Data Arrival Time 12.593
Data Required Time 10.700
From u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0
To u_usb_device_controller/usb_control_inst/s_answerptr_5_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.728 0.728 tINS RR 307 clk_i_ibuf/O
0.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/CLK
1.336 0.340 tC2Q RF 3 u_usb_device_controller/usb_control_inst/s_ctlparam_6_s0/Q
1.692 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/I1
2.506 0.814 tINS FF 1 u_usb_device_controller/usb_control_inst/n1055_s6/F
2.862 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n1055_s4/I3
3.326 0.464 tINS FF 21 u_usb_device_controller/usb_control_inst/n1055_s4/F
3.681 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n280_s13/I2
4.291 0.609 tINS FF 3 u_usb_device_controller/usb_control_inst/n280_s13/F
4.646 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s12/I0
5.411 0.765 tINS FF 3 u_usb_device_controller/usbc_dsclen_0_s12/F
5.767 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s10/I1
6.581 0.814 tINS FF 17 u_usb_device_controller/usbc_dsclen_0_s10/F
6.937 0.356 tNET FF 1 u_usb_device_controller/usbc_dsclen_0_s16/I0
7.701 0.765 tINS FF 1 u_usb_device_controller/usbc_dsclen_0_s16/F
8.057 0.356 tNET FF 2 u_usb_device_controller/usb_control_inst/n785_s0/I1
8.831 0.774 tINS FF 1 u_usb_device_controller/usb_control_inst/n785_s0/COUT
8.831 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n786_s0/CIN
8.874 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n786_s0/COUT
8.874 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n787_s0/CIN
8.916 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n787_s0/COUT
8.916 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n788_s0/CIN
8.958 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n788_s0/COUT
8.958 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n789_s0/CIN
9.000 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n789_s0/COUT
9.000 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n790_s0/CIN
9.043 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n790_s0/COUT
9.043 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n791_s0/CIN
9.085 0.042 tINS FF 1 u_usb_device_controller/usb_control_inst/n791_s0/COUT
9.085 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n792_s0/CIN
9.127 0.042 tINS FF 4 u_usb_device_controller/usb_control_inst/n792_s0/COUT
9.483 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n982_s16/I3
9.947 0.464 tINS FF 3 u_usb_device_controller/usb_control_inst/n982_s16/F
10.302 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n967_s13/I0
11.067 0.765 tINS FF 1 u_usb_device_controller/usb_control_inst/n967_s13/F
11.423 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/n967_s11/I1
12.237 0.814 tINS FF 1 u_usb_device_controller/usb_control_inst/n967_s11/F
12.593 0.356 tNET FF 1 u_usb_device_controller/usb_control_inst/s_answerptr_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.728 0.728 tINS RR 307 clk_i_ibuf/O
10.997 0.269 tNET RR 1 u_usb_device_controller/usb_control_inst/s_answerptr_5_s0/CLK
10.700 -0.296 tSu 1 u_usb_device_controller/usb_control_inst/s_answerptr_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 7.344, 63.332%; route: 3.912, 33.739%; tC2Q: 0.340, 2.929%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%