Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\DIVIDER\data\div_wrap.v C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\DIVIDER\data\qdiv.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
| Part Number | GW1N-LV2LQ144XC7/I6 |
| Device | GW1N-2 |
| Created Time | Mon May 10 08:46:21 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Fixed_Point_Divider_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 33.723MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 33.723MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 33.723MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 33.723MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 33.723MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 33.723MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.723MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 33.723MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 33.723MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 33.723MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 33.723MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 33.723MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.437s, Peak memory usage = 48.707MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 48.707MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 48.707MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 48.707MB |
Resource
Resource Usage Summary
| I/O Port | 99 |
| I/O Buf | 99 |
| IBUF | 66 |
| OBUF | 33 |
| Register | 132 |
| DFF | 1 |
| DFFE | 62 |
| DFFS | 1 |
| DFFSE | 2 |
| DFFRE | 66 |
| LUT | 128 |
| LUT2 | 5 |
| LUT3 | 20 |
| LUT4 | 103 |
| ALU | 69 |
| ALU | 69 |
| INV | 1 |
| INV | 1 |
Resource Utilization Summary
| Logic | 198(129 LUTs, 69 ALUs) / 2304 | 9% |
| Register | 132 / 2646 | 5% |
| --Register as Latch | 0 / 2646 | 0% |
| --Register as FF | 132 / 2358 | 6% |
| BSRAM | 0 / 4 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.0(MHz) | 137.1(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.707 |
| Data Arrival Time | 8.425 |
| Data Required Time | 11.132 |
| From | u_fra_div/divider_copy_0_s0 |
| To | u_fra_div/dividend_copy_0_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 1.170 | 0.316 | tNET | RR | 1 | u_fra_div/divider_copy_0_s0/CLK |
| 1.569 | 0.399 | tC2Q | RF | 2 | u_fra_div/divider_copy_0_s0/Q |
| 1.986 | 0.418 | tNET | FF | 2 | u_fra_div/n48_s124/I1 |
| 2.896 | 0.909 | tINS | FF | 1 | u_fra_div/n48_s124/COUT |
| 2.896 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s125/CIN |
| 2.945 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s125/COUT |
| 2.945 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s126/CIN |
| 2.995 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s126/COUT |
| 2.995 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s127/CIN |
| 3.044 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s127/COUT |
| 3.044 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s128/CIN |
| 3.094 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s128/COUT |
| 3.094 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s129/CIN |
| 3.143 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s129/COUT |
| 3.143 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s130/CIN |
| 3.193 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s130/COUT |
| 3.193 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s131/CIN |
| 3.243 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s131/COUT |
| 3.243 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s132/CIN |
| 3.292 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s132/COUT |
| 3.292 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s133/CIN |
| 3.342 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s133/COUT |
| 3.342 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s134/CIN |
| 3.391 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s134/COUT |
| 3.391 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s135/CIN |
| 3.441 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s135/COUT |
| 3.441 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s136/CIN |
| 3.491 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s136/COUT |
| 3.491 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s137/CIN |
| 3.540 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s137/COUT |
| 3.540 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s138/CIN |
| 3.590 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s138/COUT |
| 3.590 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s139/CIN |
| 3.639 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s139/COUT |
| 3.639 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s140/CIN |
| 3.689 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s140/COUT |
| 3.689 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s141/CIN |
| 3.739 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s141/COUT |
| 3.739 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s142/CIN |
| 3.788 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s142/COUT |
| 3.788 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s143/CIN |
| 3.838 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s143/COUT |
| 3.838 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s144/CIN |
| 3.887 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s144/COUT |
| 3.887 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s145/CIN |
| 3.937 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s145/COUT |
| 3.937 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s146/CIN |
| 3.987 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s146/COUT |
| 3.987 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s147/CIN |
| 4.036 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s147/COUT |
| 4.036 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s148/CIN |
| 4.086 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s148/COUT |
| 4.086 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s149/CIN |
| 4.135 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s149/COUT |
| 4.135 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s150/CIN |
| 4.185 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s150/COUT |
| 4.185 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s151/CIN |
| 4.234 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s151/COUT |
| 4.234 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s152/CIN |
| 4.284 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s152/COUT |
| 4.284 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s153/CIN |
| 4.334 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s153/COUT |
| 4.334 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s154/CIN |
| 4.383 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s154/COUT |
| 4.383 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s155/CIN |
| 4.433 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s155/COUT |
| 4.850 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s9/I3 |
| 5.395 | 0.545 | tINS | FF | 2 | u_fra_div/n935_s9/F |
| 5.813 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s2/I1 |
| 6.769 | 0.956 | tINS | FF | 26 | u_fra_div/n935_s2/F |
| 7.186 | 0.418 | tNET | FF | 1 | u_fra_div/dividend_copy_30_s3/I1 |
| 8.109 | 0.923 | tINS | FR | 31 | u_fra_div/dividend_copy_30_s3/F |
| 8.425 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_0_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 11.170 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_0_s1/CLK |
| 11.132 | -0.038 | tSu | 1 | u_fra_div/dividend_copy_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |
| Arrival Data Path Delay: | cell: 4.870, 67.128%; route: 1.986, 27.376%; tC2Q: 0.399, 5.496% |
| Required Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |
Path 2
Path Summary:| Slack | 2.707 |
| Data Arrival Time | 8.425 |
| Data Required Time | 11.132 |
| From | u_fra_div/divider_copy_0_s0 |
| To | u_fra_div/dividend_copy_1_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 1.170 | 0.316 | tNET | RR | 1 | u_fra_div/divider_copy_0_s0/CLK |
| 1.569 | 0.399 | tC2Q | RF | 2 | u_fra_div/divider_copy_0_s0/Q |
| 1.986 | 0.418 | tNET | FF | 2 | u_fra_div/n48_s124/I1 |
| 2.896 | 0.909 | tINS | FF | 1 | u_fra_div/n48_s124/COUT |
| 2.896 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s125/CIN |
| 2.945 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s125/COUT |
| 2.945 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s126/CIN |
| 2.995 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s126/COUT |
| 2.995 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s127/CIN |
| 3.044 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s127/COUT |
| 3.044 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s128/CIN |
| 3.094 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s128/COUT |
| 3.094 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s129/CIN |
| 3.143 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s129/COUT |
| 3.143 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s130/CIN |
| 3.193 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s130/COUT |
| 3.193 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s131/CIN |
| 3.243 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s131/COUT |
| 3.243 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s132/CIN |
| 3.292 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s132/COUT |
| 3.292 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s133/CIN |
| 3.342 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s133/COUT |
| 3.342 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s134/CIN |
| 3.391 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s134/COUT |
| 3.391 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s135/CIN |
| 3.441 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s135/COUT |
| 3.441 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s136/CIN |
| 3.491 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s136/COUT |
| 3.491 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s137/CIN |
| 3.540 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s137/COUT |
| 3.540 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s138/CIN |
| 3.590 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s138/COUT |
| 3.590 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s139/CIN |
| 3.639 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s139/COUT |
| 3.639 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s140/CIN |
| 3.689 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s140/COUT |
| 3.689 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s141/CIN |
| 3.739 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s141/COUT |
| 3.739 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s142/CIN |
| 3.788 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s142/COUT |
| 3.788 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s143/CIN |
| 3.838 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s143/COUT |
| 3.838 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s144/CIN |
| 3.887 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s144/COUT |
| 3.887 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s145/CIN |
| 3.937 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s145/COUT |
| 3.937 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s146/CIN |
| 3.987 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s146/COUT |
| 3.987 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s147/CIN |
| 4.036 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s147/COUT |
| 4.036 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s148/CIN |
| 4.086 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s148/COUT |
| 4.086 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s149/CIN |
| 4.135 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s149/COUT |
| 4.135 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s150/CIN |
| 4.185 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s150/COUT |
| 4.185 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s151/CIN |
| 4.234 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s151/COUT |
| 4.234 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s152/CIN |
| 4.284 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s152/COUT |
| 4.284 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s153/CIN |
| 4.334 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s153/COUT |
| 4.334 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s154/CIN |
| 4.383 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s154/COUT |
| 4.383 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s155/CIN |
| 4.433 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s155/COUT |
| 4.850 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s9/I3 |
| 5.395 | 0.545 | tINS | FF | 2 | u_fra_div/n935_s9/F |
| 5.813 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s2/I1 |
| 6.769 | 0.956 | tINS | FF | 26 | u_fra_div/n935_s2/F |
| 7.186 | 0.418 | tNET | FF | 1 | u_fra_div/dividend_copy_30_s3/I1 |
| 8.109 | 0.923 | tINS | FR | 31 | u_fra_div/dividend_copy_30_s3/F |
| 8.425 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_1_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 11.170 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_1_s1/CLK |
| 11.132 | -0.038 | tSu | 1 | u_fra_div/dividend_copy_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |
| Arrival Data Path Delay: | cell: 4.870, 67.128%; route: 1.986, 27.376%; tC2Q: 0.399, 5.496% |
| Required Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |
Path 3
Path Summary:| Slack | 2.707 |
| Data Arrival Time | 8.425 |
| Data Required Time | 11.132 |
| From | u_fra_div/divider_copy_0_s0 |
| To | u_fra_div/dividend_copy_2_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 1.170 | 0.316 | tNET | RR | 1 | u_fra_div/divider_copy_0_s0/CLK |
| 1.569 | 0.399 | tC2Q | RF | 2 | u_fra_div/divider_copy_0_s0/Q |
| 1.986 | 0.418 | tNET | FF | 2 | u_fra_div/n48_s124/I1 |
| 2.896 | 0.909 | tINS | FF | 1 | u_fra_div/n48_s124/COUT |
| 2.896 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s125/CIN |
| 2.945 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s125/COUT |
| 2.945 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s126/CIN |
| 2.995 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s126/COUT |
| 2.995 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s127/CIN |
| 3.044 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s127/COUT |
| 3.044 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s128/CIN |
| 3.094 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s128/COUT |
| 3.094 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s129/CIN |
| 3.143 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s129/COUT |
| 3.143 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s130/CIN |
| 3.193 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s130/COUT |
| 3.193 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s131/CIN |
| 3.243 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s131/COUT |
| 3.243 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s132/CIN |
| 3.292 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s132/COUT |
| 3.292 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s133/CIN |
| 3.342 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s133/COUT |
| 3.342 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s134/CIN |
| 3.391 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s134/COUT |
| 3.391 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s135/CIN |
| 3.441 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s135/COUT |
| 3.441 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s136/CIN |
| 3.491 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s136/COUT |
| 3.491 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s137/CIN |
| 3.540 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s137/COUT |
| 3.540 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s138/CIN |
| 3.590 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s138/COUT |
| 3.590 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s139/CIN |
| 3.639 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s139/COUT |
| 3.639 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s140/CIN |
| 3.689 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s140/COUT |
| 3.689 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s141/CIN |
| 3.739 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s141/COUT |
| 3.739 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s142/CIN |
| 3.788 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s142/COUT |
| 3.788 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s143/CIN |
| 3.838 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s143/COUT |
| 3.838 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s144/CIN |
| 3.887 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s144/COUT |
| 3.887 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s145/CIN |
| 3.937 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s145/COUT |
| 3.937 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s146/CIN |
| 3.987 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s146/COUT |
| 3.987 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s147/CIN |
| 4.036 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s147/COUT |
| 4.036 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s148/CIN |
| 4.086 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s148/COUT |
| 4.086 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s149/CIN |
| 4.135 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s149/COUT |
| 4.135 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s150/CIN |
| 4.185 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s150/COUT |
| 4.185 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s151/CIN |
| 4.234 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s151/COUT |
| 4.234 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s152/CIN |
| 4.284 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s152/COUT |
| 4.284 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s153/CIN |
| 4.334 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s153/COUT |
| 4.334 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s154/CIN |
| 4.383 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s154/COUT |
| 4.383 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s155/CIN |
| 4.433 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s155/COUT |
| 4.850 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s9/I3 |
| 5.395 | 0.545 | tINS | FF | 2 | u_fra_div/n935_s9/F |
| 5.813 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s2/I1 |
| 6.769 | 0.956 | tINS | FF | 26 | u_fra_div/n935_s2/F |
| 7.186 | 0.418 | tNET | FF | 1 | u_fra_div/dividend_copy_30_s3/I1 |
| 8.109 | 0.923 | tINS | FR | 31 | u_fra_div/dividend_copy_30_s3/F |
| 8.425 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_2_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 11.170 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_2_s1/CLK |
| 11.132 | -0.038 | tSu | 1 | u_fra_div/dividend_copy_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |
| Arrival Data Path Delay: | cell: 4.870, 67.128%; route: 1.986, 27.376%; tC2Q: 0.399, 5.496% |
| Required Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |
Path 4
Path Summary:| Slack | 2.707 |
| Data Arrival Time | 8.425 |
| Data Required Time | 11.132 |
| From | u_fra_div/divider_copy_0_s0 |
| To | u_fra_div/dividend_copy_3_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 1.170 | 0.316 | tNET | RR | 1 | u_fra_div/divider_copy_0_s0/CLK |
| 1.569 | 0.399 | tC2Q | RF | 2 | u_fra_div/divider_copy_0_s0/Q |
| 1.986 | 0.418 | tNET | FF | 2 | u_fra_div/n48_s124/I1 |
| 2.896 | 0.909 | tINS | FF | 1 | u_fra_div/n48_s124/COUT |
| 2.896 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s125/CIN |
| 2.945 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s125/COUT |
| 2.945 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s126/CIN |
| 2.995 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s126/COUT |
| 2.995 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s127/CIN |
| 3.044 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s127/COUT |
| 3.044 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s128/CIN |
| 3.094 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s128/COUT |
| 3.094 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s129/CIN |
| 3.143 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s129/COUT |
| 3.143 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s130/CIN |
| 3.193 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s130/COUT |
| 3.193 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s131/CIN |
| 3.243 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s131/COUT |
| 3.243 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s132/CIN |
| 3.292 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s132/COUT |
| 3.292 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s133/CIN |
| 3.342 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s133/COUT |
| 3.342 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s134/CIN |
| 3.391 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s134/COUT |
| 3.391 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s135/CIN |
| 3.441 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s135/COUT |
| 3.441 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s136/CIN |
| 3.491 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s136/COUT |
| 3.491 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s137/CIN |
| 3.540 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s137/COUT |
| 3.540 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s138/CIN |
| 3.590 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s138/COUT |
| 3.590 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s139/CIN |
| 3.639 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s139/COUT |
| 3.639 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s140/CIN |
| 3.689 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s140/COUT |
| 3.689 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s141/CIN |
| 3.739 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s141/COUT |
| 3.739 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s142/CIN |
| 3.788 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s142/COUT |
| 3.788 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s143/CIN |
| 3.838 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s143/COUT |
| 3.838 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s144/CIN |
| 3.887 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s144/COUT |
| 3.887 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s145/CIN |
| 3.937 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s145/COUT |
| 3.937 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s146/CIN |
| 3.987 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s146/COUT |
| 3.987 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s147/CIN |
| 4.036 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s147/COUT |
| 4.036 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s148/CIN |
| 4.086 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s148/COUT |
| 4.086 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s149/CIN |
| 4.135 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s149/COUT |
| 4.135 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s150/CIN |
| 4.185 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s150/COUT |
| 4.185 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s151/CIN |
| 4.234 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s151/COUT |
| 4.234 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s152/CIN |
| 4.284 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s152/COUT |
| 4.284 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s153/CIN |
| 4.334 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s153/COUT |
| 4.334 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s154/CIN |
| 4.383 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s154/COUT |
| 4.383 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s155/CIN |
| 4.433 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s155/COUT |
| 4.850 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s9/I3 |
| 5.395 | 0.545 | tINS | FF | 2 | u_fra_div/n935_s9/F |
| 5.813 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s2/I1 |
| 6.769 | 0.956 | tINS | FF | 26 | u_fra_div/n935_s2/F |
| 7.186 | 0.418 | tNET | FF | 1 | u_fra_div/dividend_copy_30_s3/I1 |
| 8.109 | 0.923 | tINS | FR | 31 | u_fra_div/dividend_copy_30_s3/F |
| 8.425 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_3_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 11.170 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_3_s1/CLK |
| 11.132 | -0.038 | tSu | 1 | u_fra_div/dividend_copy_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |
| Arrival Data Path Delay: | cell: 4.870, 67.128%; route: 1.986, 27.376%; tC2Q: 0.399, 5.496% |
| Required Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |
Path 5
Path Summary:| Slack | 2.707 |
| Data Arrival Time | 8.425 |
| Data Required Time | 11.132 |
| From | u_fra_div/divider_copy_0_s0 |
| To | u_fra_div/dividend_copy_4_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 1.170 | 0.316 | tNET | RR | 1 | u_fra_div/divider_copy_0_s0/CLK |
| 1.569 | 0.399 | tC2Q | RF | 2 | u_fra_div/divider_copy_0_s0/Q |
| 1.986 | 0.418 | tNET | FF | 2 | u_fra_div/n48_s124/I1 |
| 2.896 | 0.909 | tINS | FF | 1 | u_fra_div/n48_s124/COUT |
| 2.896 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s125/CIN |
| 2.945 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s125/COUT |
| 2.945 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s126/CIN |
| 2.995 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s126/COUT |
| 2.995 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s127/CIN |
| 3.044 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s127/COUT |
| 3.044 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s128/CIN |
| 3.094 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s128/COUT |
| 3.094 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s129/CIN |
| 3.143 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s129/COUT |
| 3.143 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s130/CIN |
| 3.193 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s130/COUT |
| 3.193 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s131/CIN |
| 3.243 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s131/COUT |
| 3.243 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s132/CIN |
| 3.292 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s132/COUT |
| 3.292 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s133/CIN |
| 3.342 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s133/COUT |
| 3.342 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s134/CIN |
| 3.391 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s134/COUT |
| 3.391 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s135/CIN |
| 3.441 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s135/COUT |
| 3.441 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s136/CIN |
| 3.491 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s136/COUT |
| 3.491 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s137/CIN |
| 3.540 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s137/COUT |
| 3.540 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s138/CIN |
| 3.590 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s138/COUT |
| 3.590 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s139/CIN |
| 3.639 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s139/COUT |
| 3.639 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s140/CIN |
| 3.689 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s140/COUT |
| 3.689 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s141/CIN |
| 3.739 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s141/COUT |
| 3.739 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s142/CIN |
| 3.788 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s142/COUT |
| 3.788 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s143/CIN |
| 3.838 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s143/COUT |
| 3.838 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s144/CIN |
| 3.887 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s144/COUT |
| 3.887 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s145/CIN |
| 3.937 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s145/COUT |
| 3.937 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s146/CIN |
| 3.987 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s146/COUT |
| 3.987 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s147/CIN |
| 4.036 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s147/COUT |
| 4.036 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s148/CIN |
| 4.086 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s148/COUT |
| 4.086 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s149/CIN |
| 4.135 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s149/COUT |
| 4.135 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s150/CIN |
| 4.185 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s150/COUT |
| 4.185 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s151/CIN |
| 4.234 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s151/COUT |
| 4.234 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s152/CIN |
| 4.284 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s152/COUT |
| 4.284 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s153/CIN |
| 4.334 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s153/COUT |
| 4.334 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s154/CIN |
| 4.383 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s154/COUT |
| 4.383 | 0.000 | tNET | FF | 2 | u_fra_div/n48_s155/CIN |
| 4.433 | 0.050 | tINS | FF | 1 | u_fra_div/n48_s155/COUT |
| 4.850 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s9/I3 |
| 5.395 | 0.545 | tINS | FF | 2 | u_fra_div/n935_s9/F |
| 5.813 | 0.418 | tNET | FF | 1 | u_fra_div/n935_s2/I1 |
| 6.769 | 0.956 | tINS | FF | 26 | u_fra_div/n935_s2/F |
| 7.186 | 0.418 | tNET | FF | 1 | u_fra_div/dividend_copy_30_s3/I1 |
| 8.109 | 0.923 | tINS | FR | 31 | u_fra_div/dividend_copy_30_s3/F |
| 8.425 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_4_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.854 | 0.854 | tINS | RR | 132 | clk_ibuf/O |
| 11.170 | 0.316 | tNET | RR | 1 | u_fra_div/dividend_copy_4_s1/CLK |
| 11.132 | -0.038 | tSu | 1 | u_fra_div/dividend_copy_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |
| Arrival Data Path Delay: | cell: 4.870, 67.128%; route: 1.986, 27.376%; tC2Q: 0.399, 5.496% |
| Required Clock Path Delay: | cell: 0.854, 73.009%; route: 0.316, 26.991% |