#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020 #install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: GZAE-AE-CAOJIE # Wed Aug 26 11:16:02 2020 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro OS: Windows 6.1 Hostname: GZAE-AE-CAOJIE Implementation : rev_1 Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro OS: Windows 6.1 Hostname: GZAE-AE-CAOJIE Implementation : rev_1 Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\dvi_tx_top.v" (library work) @I:"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":"D:\proj\g2ar18_goai_boardtest\project\src\dvi_tx_top\temp\DviTx\top_define.v" (library work) @I:"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\static_macro_define.v" (library work) @I:"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":"D:\proj\g2ar18_goai_boardtest\project\src\dvi_tx_top\temp\DviTx\dvi_tx_defines.v" (library work) @I::"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\rgb2dvi.vp" (library work) @W:CG1347 : rgb2dvi.vp(168) | Duplicate defparam GSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(169) | Duplicate defparam LSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(168) | Duplicate defparam GSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(196) | Duplicate defparam GSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(169) | Duplicate defparam LSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(197) | Duplicate defparam LSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(168) | Duplicate defparam GSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(196) | Duplicate defparam GSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(224) | Duplicate defparam GSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(169) | Duplicate defparam LSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(197) | Duplicate defparam LSREN found ! Previously declared here. @W:CG1347 : rgb2dvi.vp(225) | Duplicate defparam LSREN found ! Previously declared here. Verilog syntax check successful! Selecting top level module DVI_TX_Top Running optimization stage 1 on \~TMDS8b10b.DVI_TX_Top ....... Running optimization stage 1 on OSER10 ....... Running optimization stage 1 on TLVDS_OBUF ....... Running optimization stage 1 on \~rgb2dvi.DVI_TX_Top ....... @N:CG364 : dvi_tx_top.v(26) | Synthesizing module DVI_TX_Top in library work. Running optimization stage 1 on DVI_TX_Top ....... Running optimization stage 2 on DVI_TX_Top ....... Running optimization stage 2 on \~rgb2dvi.DVI_TX_Top ....... Running optimization stage 2 on TLVDS_OBUF ....... Running optimization stage 2 on OSER10 ....... Running optimization stage 2 on \~TMDS8b10b.DVI_TX_Top ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 99MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Aug 26 11:16:03 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro OS: Windows 6.1 Hostname: GZAE-AE-CAOJIE Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:NF107 : dvi_tx_top.v(26) | Selected library: work cell: DVI_TX_Top view verilog as top level @N:NF107 : dvi_tx_top.v(26) | Selected library: work cell: DVI_TX_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Aug 26 11:16:04 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: dvi_tx_top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 22MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Aug 26 11:16:04 2020 ###########################################################]