Project Settings
Project Name DviTx Device Name rev_1: GOWIN-GW2AR : GW2AR_18C
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 1 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 8 12 0 - 00m:02s - 2020/8/26
11:16:04
(premap)Complete 5 2 0 0m:01s 0m:02s 225MB 2020/8/26
11:16:08
(fpga_mapper)Complete 9 2 0 0m:06s 0m:06s 253MB 2020/8/26
11:16:15
Multi-srs Generator Complete2020/8/26
11:16:05

Area Summary
I/O ports (io_port) 38 Non I/O Register bits (non_io_reg) 81 (0%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 0 (46) Block Multipliers (dsp_used) 0 (24)
LUTs (total_luts) 278 (1%)

Timing Summary
Clock NameReq FreqEst FreqSlack
DVI_TX_Top|I_rgb_clk94.8 MHz80.6 MHz-1.861
DVI_TX_Top|I_serial_clk150.0 MHzNANA

Optimizations Summary
Combined Clock Conversion 2 / 0