Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\Gowin\Gowin_V1.9.7.01Beta\IDE\ipcore\VFB_PSRAM\data\vfb_psram_top.v
E:\Gowin\Gowin_V1.9.7.01Beta\IDE\ipcore\VFB_PSRAM\data\vfb_psram_wrapper.vp
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.7.01Beta
Created Time Mon Nov 02 17:43:48 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: VFB_PSRAM_Top
Part Number: GW2AR-LV18QN88PC8/I7
Device: GW2AR-18C

Resource

Resource Usage Summary

I/O Port 206
I/O Buf 206
    IBUF 92
    OBUF 114
Register 420
    DFFS 8
    DFFR 2
    DFFP 12
    DFFPE 2
    DFFC 317
    DFFCE 71
    DFFNP 8
LUT 488
    LUT2 149
    LUT3 186
    LUT4 153
ALU 82
    ALU 82
INV 4
    INV 4
BSRAM 4
    SDPB 1
    SDPX9B 3

Resource Utilization Summary

Logic 574(492 LUTs, 82 ALUs) / 20736 3%
Register 420 / 15828 3%
BSRAM 4 / 46 9%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_vin0_clk Base 10.000 100.0 0.000 5.000 I_vin0_clk_ibuf/I
I_dma_clk Base 10.000 100.0 0.000 5.000 I_dma_clk_ibuf/I
I_vout0_clk Base 10.000 100.0 0.000 5.000 I_vout0_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_vin0_clk 100.0(MHz) 191.4(MHz) 8 TOP
2 I_dma_clk 100.0(MHz) 171.9(MHz) 9 TOP
3 I_vout0_clk 100.0(MHz) 269.0(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.996
Data Arrival Time 6.393
Data Required Time 10.390
From vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s1
To vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s
Launch Clk I_vout0_clk[R]
Latch Clk I_vout0_clk[F]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 I_vout0_clk_ibuf/I
5.687 0.687 tINS FF 96 I_vout0_clk_ibuf/O
5.924 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s1/CLK
6.156 0.232 tC2Q FF 52 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s1/Q
6.393 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESETB

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 I_vout0_clk_ibuf/I
0.682 0.682 tINS RR 96 I_vout0_clk_ibuf/O
0.862 0.18 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/CLKB

Path Statistic:
Clock Skew: -0.062
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.688, 74.365%; route: 0.237, 25.635%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 3.996
Data Arrival Time 6.393
Data Required Time 10.390
From vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s1
To vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s
Launch Clk I_vout0_clk[R]
Latch Clk I_vout0_clk[F]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 I_vout0_clk_ibuf/I
5.687 0.687 tINS FF 96 I_vout0_clk_ibuf/O
5.924 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s1/CLK
6.156 0.232 tC2Q FF 52 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s1/Q
6.393 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESETB

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 I_vout0_clk_ibuf/I
0.682 0.682 tINS RR 96 I_vout0_clk_ibuf/O
0.862 0.18 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB

Path Statistic:
Clock Skew: -0.124
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 1.375, 74.365%; route: 0.474, 25.635%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861%
Required Clock Path Delay: cell: 1.365, 79.130%; route: 0.360, 20.870%

Path 3

Path Summary:
Slack 3.996
Data Arrival Time 6.393
Data Required Time 10.390
From vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1
To vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[F]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 I_dma_clk_ibuf/I
5.687 0.687 tINS FF 215 I_dma_clk_ibuf/O
5.924 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1/CLK
6.156 0.232 tC2Q FF 61 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1/Q
6.393 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/RESETB

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 I_dma_clk_ibuf/I
0.682 0.682 tINS RR 215 I_dma_clk_ibuf/O
0.862 0.18 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKB

Path Statistic:
Clock Skew: -0.186
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 2.063, 74.365%; route: 0.711, 25.635%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.711, 75.398%; tC2Q: 0.232, 24.602%
Required Clock Path Delay: cell: 2.048, 79.130%; route: 0.540, 20.870%

Path 4

Path Summary:
Slack 3.996
Data Arrival Time 6.393
Data Required Time 10.390
From vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1
To vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[F]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5 0 tCL FF 1 I_dma_clk_ibuf/I
5.687 0.687 tINS FF 215 I_dma_clk_ibuf/O
5.924 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1/CLK
6.156 0.232 tC2Q FF 61 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1/Q
6.393 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/RESETB

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 I_dma_clk_ibuf/I
0.682 0.682 tINS RR 215 I_dma_clk_ibuf/O
0.862 0.18 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKB

Path Statistic:
Clock Skew: -0.248
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 2.750, 74.365%; route: 0.948, 25.635%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.948, 80.339%; tC2Q: 0.232, 19.661%
Required Clock Path Delay: cell: 2.730, 79.130%; route: 0.720, 20.870%

Path 5

Path Summary:
Slack 4.182
Data Arrival Time 6.611
Data Required Time 10.793
From vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s1
To vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 I_dma_clk_ibuf/I
0.682 0.682 tINS RR 215 I_dma_clk_ibuf/O
0.862 0.18 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s1/CLK
1.094 0.232 tC2Q RF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s1/Q
1.331 0.237 tNET FF 1 vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s2/I1
1.886 0.555 tINS FF 68 vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s2/F
2.123 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n60_s2/I2
2.576 0.453 tINS FF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n60_s2/F
2.813 0.237 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_0_s/I1
3.383 0.57 tINS FR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_0_s/COUT
3.383 0 tNET RR 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_1_s/CIN
3.418 0.035 tINS RF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_1_s/COUT
3.418 0 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s/CIN
3.453 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s/COUT
3.453 0 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_3_s/CIN
3.489 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_3_s/COUT
3.489 0 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_4_s/CIN
3.524 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_4_s/COUT
3.524 0 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_5_s/CIN
3.559 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_5_s/COUT
3.559 0 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_6_s/CIN
3.594 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_6_s/COUT
3.594 0 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_7_s/CIN
3.629 0.035 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_7_s/COUT
3.629 0 tNET FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_8_s/CIN
4.099 0.47 tINS FF 3 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_8_s/SUM
4.336 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_7_s0/I1
4.891 0.555 tINS FF 2 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_7_s0/F
5.128 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s3/I1
5.683 0.555 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s3/F
5.920 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/I2
6.373 0.453 tINS FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/F
6.610 0.237 tNET FF 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/D

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
0 0 tCL RR 1 I_dma_clk_ibuf/I
0.682 0.682 tINS RR 215 I_dma_clk_ibuf/O
0.862 0.18 tNET RR 1 vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/CLK

Path Statistic:
Clock Skew: -0.248
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 3.432, 75.266%; route: 1.128, 24.734%
Arrival Data Path Delay: cell: 3.857, 57.604%; route: 2.607, 38.931%; tC2Q: 0.232, 3.465%
Required Clock Path Delay: cell: 3.412, 79.130%; route: 0.900, 20.870%

Synthesis completed successfully!
Process took 0h:0m:4s realtime, 0h:0m:3s cputime
Memory peak: 44.4MB