#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020
#install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GZAE-AE-CAOJIE

# Wed Aug 26 11:16:02 2020

#Implementation: rev_1


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\dvi_tx_top.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":"D:\proj\g2ar18_goai_boardtest\project\src\dvi_tx_top\temp\DviTx\top_define.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\static_macro_define.v" (library work)
@I:"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":"D:\proj\g2ar18_goai_boardtest\project\src\dvi_tx_top\temp\DviTx\dvi_tx_defines.v" (library work)
@I::"D:\Gowin\Gowin_V1.9.6.02Beta\IDE\ipcore\DVI_TX\data\rgb2dvi.vp" (library work)
@W:CG1347 : rgb2dvi.vp(168) | Duplicate defparam GSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(169) | Duplicate defparam LSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(168) | Duplicate defparam GSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(196) | Duplicate defparam GSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(169) | Duplicate defparam LSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(197) | Duplicate defparam LSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(168) | Duplicate defparam GSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(196) | Duplicate defparam GSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(224) | Duplicate defparam GSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(169) | Duplicate defparam LSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(197) | Duplicate defparam LSREN found ! Previously declared here.
@W:CG1347 : rgb2dvi.vp(225) | Duplicate defparam LSREN found ! Previously declared here.
Verilog syntax check successful!
Selecting top level module DVI_TX_Top
Running optimization stage 1 on \~TMDS8b10b.DVI_TX_Top  .......
Running optimization stage 1 on OSER10 .......
Running optimization stage 1 on TLVDS_OBUF .......
Running optimization stage 1 on \~rgb2dvi.DVI_TX_Top  .......
@N:CG364 : dvi_tx_top.v(26) | Synthesizing module DVI_TX_Top in library work.
Running optimization stage 1 on DVI_TX_Top .......
Running optimization stage 2 on DVI_TX_Top .......
Running optimization stage 2 on \~rgb2dvi.DVI_TX_Top  .......
Running optimization stage 2 on TLVDS_OBUF .......
Running optimization stage 2 on OSER10 .......
Running optimization stage 2 on \~TMDS8b10b.DVI_TX_Top  .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 99MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Aug 26 11:16:03 2020

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
@N:NF107 : dvi_tx_top.v(26) | Selected library: work cell: DVI_TX_Top view verilog as top level
@N:NF107 : dvi_tx_top.v(26) | Selected library: work cell: DVI_TX_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Aug 26 11:16:04 2020

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  dvi_tx_top_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 22MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Aug 26 11:16:04 2020

###########################################################]


###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
@N:NF107 : dvi_tx_top.v(26) | Selected library: work cell: DVI_TX_Top view verilog as top level
@N:NF107 : dvi_tx_top.v(26) | Selected library: work cell: DVI_TX_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Aug 26 11:16:05 2020

###########################################################]


Premap Report



# Wed Aug 26 11:16:05 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@A:MF827 :  | No constraint file specified. 
Linked File:  dvi_tx_top_scck.rpt
See clock summary report "D:\proj\g2ar18_goai_boardtest\project\src\dvi_tx_top\temp\DviTx\rev_1\dvi_tx_top_scck.rpt"
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)

@W:BN117 : dvi_tx_top.v(45) | Instance rgb2dvi_inst of partition view:work.\\\~rgb2dvi\.DVI_TX_Top\ (verilog) has no references to its outputs; instance not removed. 
@W:BN117 : dvi_tx_top.v(45) | Instance rgb2dvi_inst of partition view:work.\\\~rgb2dvi\.DVI_TX_Top\ (verilog) has no references to its outputs; instance not removed. 

Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 222MB)



Clock Summary
******************

          Start                       Requested     Requested     Clock        Clock                     Clock
Level     Clock                       Frequency     Period        Type         Group                     Load 
--------------------------------------------------------------------------------------------------------------
0 -       DVI_TX_Top|I_rgb_clk        76.3 MHz      13.104        inferred     Autoconstr_clkgroup_0     82   
                                                                                                              
0 -       DVI_TX_Top|I_serial_clk     150.0 MHz     6.667         inferred     Autoconstr_clkgroup_1     4    
==============================================================================================================



Clock Load Summary
***********************

                            Clock     Source                 Clock Pin                        Non-clock Pin     Non-clock Pin
Clock                       Load      Pin                    Seq Example                      Seq Example       Comb Example 
-----------------------------------------------------------------------------------------------------------------------------
DVI_TX_Top|I_rgb_clk        82        I_rgb_clk(port)        rgb2dvi_inst.u_OSER10_r.PCLK     -                 -            
                                                                                                                             
DVI_TX_Top|I_serial_clk     4         I_serial_clk(port)     rgb2dvi_inst.u_OSER10_r.FCLK     -                 -            
=============================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 86 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId_0_0       I_rgb_clk           port                   82         ENCRYPTED      
ClockId_0_1       I_serial_clk        port                   4          ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\proj\g2ar18_goai_boardtest\project\src\dvi_tx_top\temp\DviTx\rev_1\dvi_tx_top.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 225MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Wed Aug 26 11:16:08 2020

###########################################################]


Map & Optimize Report



# Wed Aug 26 11:16:08 2020


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: D:\Gowin\Gowin_V1.9.6.02Beta\SynplifyPro
OS: Windows 6.1

Hostname: GZAE-AE-CAOJIE

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 219MB peak: 219MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 223MB peak: 223MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 224MB peak: 224MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 248MB peak: 248MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 233MB peak: 248MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 248MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 239MB peak: 248MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 239MB peak: 248MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 240MB peak: 248MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 251MB peak: 253MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -3.86ns		 255 /        73
   2		0h:00m:03s		    -3.79ns		 252 /        73
   3		0h:00m:03s		    -3.05ns		 253 /        73
   4		0h:00m:03s		    -2.98ns		 252 /        73
   5		0h:00m:03s		    -2.98ns		 253 /        73
   6		0h:00m:03s		    -2.98ns		 252 /        73
   7		0h:00m:03s		    -2.98ns		 253 /        73
   8		0h:00m:03s		    -2.98ns		 252 /        73
Timing driven replication report
Added 8 Registers via timing driven replication
Added 0 LUTs via timing driven replication

   9		0h:00m:04s		    -2.98ns		 255 /        81
  10		0h:00m:04s		    -2.84ns		 261 /        81
  11		0h:00m:04s		    -2.78ns		 262 /        81
  12		0h:00m:04s		    -2.92ns		 263 /        81
  13		0h:00m:04s		    -2.78ns		 265 /        81


  14		0h:00m:04s		    -2.78ns		 264 /        81
  15		0h:00m:04s		    -3.05ns		 264 /        81
  16		0h:00m:04s		    -2.92ns		 264 /        81

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 252MB peak: 253MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 252MB peak: 253MB)


Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 181MB peak: 253MB)

Writing Analyst data base D:\proj\g2ar18_goai_boardtest\project\src\dvi_tx_top\temp\DviTx\rev_1\synwork\dvi_tx_top_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 252MB peak: 253MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 253MB peak: 253MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 253MB peak: 253MB)


Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 250MB peak: 253MB)

@W:MT420 :  | Found inferred clock DVI_TX_Top|I_rgb_clk with period 10.54ns. Please declare a user-defined clock on port I_rgb_clk. 
@W:MT420 :  | Found inferred clock DVI_TX_Top|I_serial_clk with period 6.67ns. Please declare a user-defined clock on port I_serial_clk. 


##### START OF TIMING REPORT #####[
# Timing report written on Wed Aug 26 11:16:15 2020
#


Top view:               DVI_TX_Top
Requested Frequency:    94.8 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.861

                            Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock              Frequency     Frequency     Period        Period        Slack      Type         Group                
---------------------------------------------------------------------------------------------------------------------------------
DVI_TX_Top|I_rgb_clk        94.8 MHz      80.6 MHz      10.545        12.405        -1.861     inferred     Autoconstr_clkgroup_0
DVI_TX_Top|I_serial_clk     150.0 MHz     NA            6.667         NA            NA         inferred     Autoconstr_clkgroup_1
=================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------
Starting              Ending                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------
DVI_TX_Top|I_rgb_clk  DVI_TX_Top|I_rgb_clk  |  10.545      -1.861  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: DVI_TX_Top|I_rgb_clk
====================================



Starting Points with Worst Slack
********************************

                                                Starting                                                    Arrival           
Instance                                        Reference                Type     Pin     Net               Time        Slack 
                                                Clock                                                                         
------------------------------------------------------------------------------------------------------------------------------
rgb2dvi_inst.TMDS8b10b_inst_r.din_d_fast[5]     DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d_fast[5]     0.243       -1.861
rgb2dvi_inst.TMDS8b10b_inst_g.din_d_fast[5]     DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d_fast[5]     0.243       -1.857
rgb2dvi_inst.TMDS8b10b_inst_r.din_d_fast[3]     DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d_fast[3]     0.243       -1.840
rgb2dvi_inst.TMDS8b10b_inst_g.din_d_fast[3]     DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d_fast[3]     0.243       -1.836
rgb2dvi_inst.TMDS8b10b_inst_r.din_d[4]          DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d[4]          0.243       -1.796
rgb2dvi_inst.TMDS8b10b_inst_g.din_d[4]          DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d[4]          0.243       -1.545
rgb2dvi_inst.TMDS8b10b_inst_b.din_d_fast[3]     DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d_fast[3]     0.243       -1.511
rgb2dvi_inst.TMDS8b10b_inst_b.din_d[6]          DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d[6]          0.243       -1.490
rgb2dvi_inst.TMDS8b10b_inst_b.din_d_fast[4]     DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d_fast[4]     0.243       -1.403
rgb2dvi_inst.TMDS8b10b_inst_b.din_d_fast[5]     DVI_TX_Top|I_rgb_clk     DFFC     Q       din_d_fast[5]     0.243       -1.333
==============================================================================================================================


Ending Points with Worst Slack
******************************

                                         Starting                                                      Required           
Instance                                 Reference                Type     Pin     Net                 Time         Slack 
                                         Clock                                                                            
--------------------------------------------------------------------------------------------------------------------------
rgb2dvi_inst.TMDS8b10b_inst_r.cnt[4]     DVI_TX_Top|I_rgb_clk     DFFC     D       z[4]                10.484       -1.861
rgb2dvi_inst.TMDS8b10b_inst_g.cnt[4]     DVI_TX_Top|I_rgb_clk     DFFC     D       z[4]                10.484       -1.857
rgb2dvi_inst.TMDS8b10b_inst_b.cnt[4]     DVI_TX_Top|I_rgb_clk     DFFC     D       z_0_s_4_0_SUM       10.484       -1.511
rgb2dvi_inst.TMDS8b10b_inst_r.cnt[3]     DVI_TX_Top|I_rgb_clk     DFFC     D       z[3]                10.484       -1.468
rgb2dvi_inst.TMDS8b10b_inst_g.cnt[3]     DVI_TX_Top|I_rgb_clk     DFFC     D       z[3]                10.484       -1.398
rgb2dvi_inst.TMDS8b10b_inst_r.cnt[2]     DVI_TX_Top|I_rgb_clk     DFFC     D       z[2]                10.484       -1.210
rgb2dvi_inst.TMDS8b10b_inst_g.cnt[2]     DVI_TX_Top|I_rgb_clk     DFFC     D       z[2]                10.484       -1.199
rgb2dvi_inst.TMDS8b10b_inst_r.cnt[1]     DVI_TX_Top|I_rgb_clk     DFFC     D       z[1]                10.484       -1.175
rgb2dvi_inst.TMDS8b10b_inst_b.cnt[3]     DVI_TX_Top|I_rgb_clk     DFFC     D       z_0_cry_3_0_SUM     10.484       -1.139
rgb2dvi_inst.TMDS8b10b_inst_g.cnt[1]     DVI_TX_Top|I_rgb_clk     DFFC     D       z[1]                10.484       -0.729
==========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.545
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.484

    - Propagation time:                      12.344
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.861

    Number of logic level(s):                11
    Starting point:                          rgb2dvi_inst.TMDS8b10b_inst_r.din_d_fast[5] / Q
    Ending point:                            rgb2dvi_inst.TMDS8b10b_inst_r.cnt[4] / D
    The start point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK
    The end   point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK

Instance / Net                                           Pin      Pin               Arrival      No. of    
Name                                            Type     Name     Dir     Delay     Time         Fan Out(s)
-----------------------------------------------------------------------------------------------------------
rgb2dvi_inst.TMDS8b10b_inst_r.din_d_fast[5]     DFFC     Q        Out     0.243     0.243 r      -         
din_d_fast[5]                                   Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_r.N_5_1.g0_i_o2     LUT2     I1       In      -         0.778 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.N_5_1.g0_i_o2     LUT2     F        Out     0.570     1.348 r      -         
SUM_0_i_0[0]                                    Net      -        -       0.535     -            5         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_c1            LUT4     I0       In      -         1.883 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_c1            LUT4     F        Out     0.549     2.432 r      -         
N_7_c1                                          Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_0_m_1[1]      LUT4     I1       In      -         2.967 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_0_m_1[1]      LUT4     F        Out     0.570     3.537 r      -         
N_7_0_m_1[1]                                    Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_6              LUT4     I0       In      -         3.938 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_6              LUT4     F        Out     0.549     4.487 r      -         
ANB1                                            Net      -        -       0.535     -            7         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_9_RNITRQE      LUT2     I0       In      -         5.022 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_9_RNITRQE      LUT2     F        Out     0.549     5.571 r      -         
CO1                                             Net      -        -       0.535     -            5         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_1              LUT4     I0       In      -         6.106 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_1              LUT4     F        Out     0.549     6.655 r      -         
cnt63                                           Net      -        -       0.535     -            7         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_0              LUT4     I1       In      -         7.190 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_0              LUT4     F        Out     0.570     7.760 r      -         
dout_12[9]                                      Net      -        -       0.535     -            8         
rgb2dvi_inst.TMDS8b10b_inst_r.un17_0_i[1]       LUT3     I2       In      -         8.295 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.un17_0_i[1]       LUT3     F        Out     0.462     8.757 r      -         
N_116                                           Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_5_c4       LUT4     I1       In      -         9.292 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_5_c4       LUT4     F        Out     0.570     9.862 r      -         
z_5_c4                                          Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_axb_4      LUT4     I2       In      -         10.263 r     -         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_axb_4      LUT4     F        Out     0.462     10.725 r     -         
z_axb_4                                         Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_s_4_0      ALU      I0       In      -         11.260 r     -         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_s_4_0      ALU      SUM      Out     0.549     11.809 r     -         
z[4]                                            Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.cnt[4]            DFFC     D        In      -         12.344 r     -         
===========================================================================================================
Total path delay (propagation time + setup) of 12.405 is 6.253(50.4%) logic and 6.152(49.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.545
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.484

    - Propagation time:                      12.340
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.857

    Number of logic level(s):                11
    Starting point:                          rgb2dvi_inst.TMDS8b10b_inst_g.din_d_fast[5] / Q
    Ending point:                            rgb2dvi_inst.TMDS8b10b_inst_g.cnt[4] / D
    The start point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK
    The end   point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK

Instance / Net                                                Pin      Pin               Arrival      No. of    
Name                                                 Type     Name     Dir     Delay     Time         Fan Out(s)
----------------------------------------------------------------------------------------------------------------
rgb2dvi_inst.TMDS8b10b_inst_g.din_d_fast[5]          DFFC     Q        Out     0.243     0.243 r      -         
din_d_fast[5]                                        Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_g.N_5_1.SUM_0_i_0[0]     LUT2     I1       In      -         0.778 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.N_5_1.SUM_0_i_0[0]     LUT2     F        Out     0.570     1.348 r      -         
SUM_0_i_0[0]                                         Net      -        -       0.535     -            4         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_1_c1               LUT4     I0       In      -         1.883 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_1_c1               LUT4     F        Out     0.549     2.432 r      -         
N_7_1_c1                                             Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_0_m_N_3L3          LUT4     I1       In      -         2.967 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_0_m_N_3L3          LUT4     F        Out     0.570     3.537 r      -         
N_7_0_m_N_3L3                                        Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_0_m[1]             LUT4     I1       In      -         3.938 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_0_m[1]             LUT4     F        Out     0.570     4.508 r      -         
ANB1                                                 Net      -        -       0.535     -            4         
rgb2dvi_inst.TMDS8b10b_inst_g.CO1                    LUT4     I0       In      -         5.043 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.CO1                    LUT4     F        Out     0.549     5.592 r      -         
CO1                                                  Net      -        -       0.535     -            6         
rgb2dvi_inst.TMDS8b10b_inst_g.dout_12_1[9]           LUT4     I0       In      -         6.127 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.dout_12_1[9]           LUT4     F        Out     0.549     6.676 r      -         
dout_12_1[9]                                         Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_g.un17_0_i_1[2]          LUT3     I0       In      -         7.211 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.un17_0_i_1[2]          LUT3     F        Out     0.549     7.760 r      -         
un17_0_i_1[2]                                        Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_g.un17_0_i[2]            LUT4     I3       In      -         8.295 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.un17_0_i[2]            LUT4     F        Out     0.371     8.666 f      -         
N_117                                                Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_5_c4            LUT4     I1       In      -         9.201 f      -         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_5_c4            LUT4     F        Out     0.570     9.771 r      -         
z_5_c4                                               Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_axb_4           LUT4     I0       In      -         10.172 r     -         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_axb_4           LUT4     F        Out     0.549     10.721 r     -         
z_axb_4                                              Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_s_4_0           ALU      I0       In      -         11.256 r     -         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_s_4_0           ALU      SUM      Out     0.549     11.805 r     -         
z[4]                                                 Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.cnt[4]                 DFFC     D        In      -         12.340 r     -         
================================================================================================================
Total path delay (propagation time + setup) of 12.401 is 6.249(50.4%) logic and 6.152(49.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.545
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.484

    - Propagation time:                      12.323
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.840

    Number of logic level(s):                11
    Starting point:                          rgb2dvi_inst.TMDS8b10b_inst_r.din_d_fast[3] / Q
    Ending point:                            rgb2dvi_inst.TMDS8b10b_inst_r.cnt[4] / D
    The start point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK
    The end   point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK

Instance / Net                                           Pin      Pin               Arrival      No. of    
Name                                            Type     Name     Dir     Delay     Time         Fan Out(s)
-----------------------------------------------------------------------------------------------------------
rgb2dvi_inst.TMDS8b10b_inst_r.din_d_fast[3]     DFFC     Q        Out     0.243     0.243 r      -         
din_d_fast[3]                                   Net      -        -       0.535     -            5         
rgb2dvi_inst.TMDS8b10b_inst_r.N_5_1.g0_i_o2     LUT2     I0       In      -         0.778 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.N_5_1.g0_i_o2     LUT2     F        Out     0.549     1.327 r      -         
SUM_0_i_0[0]                                    Net      -        -       0.535     -            5         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_c1            LUT4     I0       In      -         1.862 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_c1            LUT4     F        Out     0.549     2.411 r      -         
N_7_c1                                          Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_0_m_1[1]      LUT4     I1       In      -         2.946 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_0_m_1[1]      LUT4     F        Out     0.570     3.516 r      -         
N_7_0_m_1[1]                                    Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_6              LUT4     I0       In      -         3.917 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_6              LUT4     F        Out     0.549     4.466 r      -         
ANB1                                            Net      -        -       0.535     -            7         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_9_RNITRQE      LUT2     I0       In      -         5.001 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_9_RNITRQE      LUT2     F        Out     0.549     5.550 r      -         
CO1                                             Net      -        -       0.535     -            5         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_1              LUT4     I0       In      -         6.085 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_1              LUT4     F        Out     0.549     6.634 r      -         
cnt63                                           Net      -        -       0.535     -            7         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_0              LUT4     I1       In      -         7.169 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_0              LUT4     F        Out     0.570     7.739 r      -         
dout_12[9]                                      Net      -        -       0.535     -            8         
rgb2dvi_inst.TMDS8b10b_inst_r.un17_0_i[1]       LUT3     I2       In      -         8.274 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.un17_0_i[1]       LUT3     F        Out     0.462     8.736 r      -         
N_116                                           Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_5_c4       LUT4     I1       In      -         9.271 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_5_c4       LUT4     F        Out     0.570     9.841 r      -         
z_5_c4                                          Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_axb_4      LUT4     I2       In      -         10.242 r     -         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_axb_4      LUT4     F        Out     0.462     10.704 r     -         
z_axb_4                                         Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_s_4_0      ALU      I0       In      -         11.239 r     -         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_s_4_0      ALU      SUM      Out     0.549     11.788 r     -         
z[4]                                            Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.cnt[4]            DFFC     D        In      -         12.323 r     -         
===========================================================================================================
Total path delay (propagation time + setup) of 12.384 is 6.232(50.3%) logic and 6.152(49.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.545
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.484

    - Propagation time:                      12.323
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.840

    Number of logic level(s):                11
    Starting point:                          rgb2dvi_inst.TMDS8b10b_inst_r.din_d_fast[5] / Q
    Ending point:                            rgb2dvi_inst.TMDS8b10b_inst_r.cnt[4] / D
    The start point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK
    The end   point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK

Instance / Net                                           Pin      Pin               Arrival      No. of    
Name                                            Type     Name     Dir     Delay     Time         Fan Out(s)
-----------------------------------------------------------------------------------------------------------
rgb2dvi_inst.TMDS8b10b_inst_r.din_d_fast[5]     DFFC     Q        Out     0.243     0.243 r      -         
din_d_fast[5]                                   Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_r.N_5_1.g0_i_o2     LUT2     I1       In      -         0.778 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.N_5_1.g0_i_o2     LUT2     F        Out     0.570     1.348 r      -         
SUM_0_i_0[0]                                    Net      -        -       0.535     -            5         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_1_c1          LUT4     I0       In      -         1.883 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_1_c1          LUT4     F        Out     0.549     2.432 r      -         
N_7_1_c1                                        Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_0_m_1[1]      LUT4     I0       In      -         2.967 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.N_7_0_m_1[1]      LUT4     F        Out     0.549     3.516 r      -         
N_7_0_m_1[1]                                    Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_6              LUT4     I0       In      -         3.917 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_6              LUT4     F        Out     0.549     4.466 r      -         
ANB1                                            Net      -        -       0.535     -            7         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_9_RNITRQE      LUT2     I0       In      -         5.001 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_9_RNITRQE      LUT2     F        Out     0.549     5.550 r      -         
CO1                                             Net      -        -       0.535     -            5         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_1              LUT4     I0       In      -         6.085 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_1              LUT4     F        Out     0.549     6.634 r      -         
cnt63                                           Net      -        -       0.535     -            7         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_0              LUT4     I1       In      -         7.169 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.g0_0              LUT4     F        Out     0.570     7.739 r      -         
dout_12[9]                                      Net      -        -       0.535     -            8         
rgb2dvi_inst.TMDS8b10b_inst_r.un17_0_i[1]       LUT3     I2       In      -         8.274 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.un17_0_i[1]       LUT3     F        Out     0.462     8.736 r      -         
N_116                                           Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_5_c4       LUT4     I1       In      -         9.271 r      -         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_5_c4       LUT4     F        Out     0.570     9.841 r      -         
z_5_c4                                          Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_axb_4      LUT4     I2       In      -         10.242 r     -         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_axb_4      LUT4     F        Out     0.462     10.704 r     -         
z_axb_4                                         Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_s_4_0      ALU      I0       In      -         11.239 r     -         
rgb2dvi_inst.TMDS8b10b_inst_r.un20.z_s_4_0      ALU      SUM      Out     0.549     11.788 r     -         
z[4]                                            Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_r.cnt[4]            DFFC     D        In      -         12.323 r     -         
===========================================================================================================
Total path delay (propagation time + setup) of 12.384 is 6.232(50.3%) logic and 6.152(49.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.545
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.484

    - Propagation time:                      12.319
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.836

    Number of logic level(s):                11
    Starting point:                          rgb2dvi_inst.TMDS8b10b_inst_g.din_d_fast[3] / Q
    Ending point:                            rgb2dvi_inst.TMDS8b10b_inst_g.cnt[4] / D
    The start point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK
    The end   point is clocked by            DVI_TX_Top|I_rgb_clk [rising] (rise=0.000 fall=5.272 period=10.545) on pin CLK

Instance / Net                                                Pin      Pin               Arrival      No. of    
Name                                                 Type     Name     Dir     Delay     Time         Fan Out(s)
----------------------------------------------------------------------------------------------------------------
rgb2dvi_inst.TMDS8b10b_inst_g.din_d_fast[3]          DFFC     Q        Out     0.243     0.243 r      -         
din_d_fast[3]                                        Net      -        -       0.535     -            5         
rgb2dvi_inst.TMDS8b10b_inst_g.N_5_1.SUM_0_i_0[0]     LUT2     I0       In      -         0.778 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.N_5_1.SUM_0_i_0[0]     LUT2     F        Out     0.549     1.327 r      -         
SUM_0_i_0[0]                                         Net      -        -       0.535     -            4         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_1_c1               LUT4     I0       In      -         1.862 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_1_c1               LUT4     F        Out     0.549     2.411 r      -         
N_7_1_c1                                             Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_0_m_N_3L3          LUT4     I1       In      -         2.946 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_0_m_N_3L3          LUT4     F        Out     0.570     3.516 r      -         
N_7_0_m_N_3L3                                        Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_0_m[1]             LUT4     I1       In      -         3.917 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.N_7_0_m[1]             LUT4     F        Out     0.570     4.487 r      -         
ANB1                                                 Net      -        -       0.535     -            4         
rgb2dvi_inst.TMDS8b10b_inst_g.CO1                    LUT4     I0       In      -         5.022 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.CO1                    LUT4     F        Out     0.549     5.571 r      -         
CO1                                                  Net      -        -       0.535     -            6         
rgb2dvi_inst.TMDS8b10b_inst_g.dout_12_1[9]           LUT4     I0       In      -         6.106 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.dout_12_1[9]           LUT4     F        Out     0.549     6.655 r      -         
dout_12_1[9]                                         Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_g.un17_0_i_1[2]          LUT3     I0       In      -         7.190 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.un17_0_i_1[2]          LUT3     F        Out     0.549     7.739 r      -         
un17_0_i_1[2]                                        Net      -        -       0.535     -            2         
rgb2dvi_inst.TMDS8b10b_inst_g.un17_0_i[2]            LUT4     I3       In      -         8.274 r      -         
rgb2dvi_inst.TMDS8b10b_inst_g.un17_0_i[2]            LUT4     F        Out     0.371     8.645 f      -         
N_117                                                Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_5_c4            LUT4     I1       In      -         9.180 f      -         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_5_c4            LUT4     F        Out     0.570     9.750 r      -         
z_5_c4                                               Net      -        -       0.401     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_axb_4           LUT4     I0       In      -         10.151 r     -         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_axb_4           LUT4     F        Out     0.549     10.700 r     -         
z_axb_4                                              Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_s_4_0           ALU      I0       In      -         11.235 r     -         
rgb2dvi_inst.TMDS8b10b_inst_g.un20.z_s_4_0           ALU      SUM      Out     0.549     11.784 r     -         
z[4]                                                 Net      -        -       0.535     -            1         
rgb2dvi_inst.TMDS8b10b_inst_g.cnt[4]                 DFFC     D        In      -         12.319 r     -         
================================================================================================================
Total path delay (propagation time + setup) of 12.380 is 6.228(50.3%) logic and 6.152(49.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 251MB peak: 253MB)


Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 251MB peak: 253MB)

---------------------------------------
Resource Usage Report for DVI_TX_Top 

Mapping to part: gw2ar_18cqfn88p-8
Cell usage:
ALU             15 uses
DFFC            78 uses
DFFP            3 uses
GSR             1 use
INV             1 use
MUX2_LUT5       13 uses
MUX2_LUT6       3 uses
OSER10          4 uses
LUT2            23 uses
LUT3            76 uses
LUT4            179 uses

I/O ports: 38
I/O primitives: 4
TLVDS_OBUF     4 uses

I/O Register bits:                  0
Register bits not including I/Os:   81 of 15552 (0%)
Total load per clock:
   DVI_TX_Top|I_rgb_clk: 85
   DVI_TX_Top|I_serial_clk: 4

@S |Mapping Summary:
Total  LUTs: 278 

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 78MB peak: 253MB)

Process took 0h:00m:06s realtime, 0h:00m:06s cputime
# Wed Aug 26 11:16:15 2020

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