`

    #Build: Synplify Pro (R) O-2018.09G-Beta3, Build 136R, Nov 19 2018
    #install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
    #OS: Linux
    #Hostname: jinan9110.sdgowin.com

    # Tue Dec 18 16:24:31 2018

    #Implementation: rev_1

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta3
    Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
    OS: CentOS release 6.8 (Final)
    Hostname: jinan9110.sdgowin.com

    Implementation : rev_1
    Synopsys HDL Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta3
    Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
    OS: CentOS release 6.8 (Final)
    Hostname: jinan9110.sdgowin.com

    Implementation : rev_1
    Synopsys Verilog Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

    @N: :  | Running in 64-bit mode
    @N:CG1349 :  | Running Verilog Compiler in System Verilog mode

    @N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode

    @I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/generic/gw2a.v" (library work)
    @I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__)
    @I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps)
    @I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps)
    @I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps)
    @I::"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/src/xcorr/xcorr.v" (library work)
    @I::"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/src/top.v" (library work)
    @I::"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/src/eliminate_shake.v" (library work)
    Verilog syntax check successful!
    Options changed - recompiling
    Selecting top level module top
    @N:CG364 : gw2a.v(1597) | Synthesizing module GSR in library work.
    Running optimization stage 1 on GSR .......
    Running optimization stage 1 on INV .......
    Running optimization stage 1 on LUT4 .......
    Running optimization stage 1 on LUT3 .......
    Running optimization stage 1 on LUT2 .......
    Running optimization stage 1 on MUX2_LUT5 .......
    Running optimization stage 1 on MUX2_LUT6 .......
    Running optimization stage 1 on DFF .......
    Running optimization stage 1 on DFFS .......
    Running optimization stage 1 on DFFE .......
    Running optimization stage 1 on DFFR .......
    Running optimization stage 1 on DFFRE .......
    Running optimization stage 1 on SDPX9 .......
    Running optimization stage 1 on ALU .......
    Running optimization stage 1 on MULT18X18 .......
    Running optimization stage 1 on GND .......
    Running optimization stage 1 on VCC .......
    Running optimization stage 1 on \(crosscorrelation)/(XCORR_Top)_17s_512s_3s .......
    @N:CG364 : xcorr.v(6895) | Synthesizing module XCORR_Top in library work.
    Running optimization stage 1 on XCORR_Top .......
    @N:CG364 : eliminate_shake.v(2) | Synthesizing module deUstb in library work.
    @N:CG179 : eliminate_shake.v(12) | Removing redundant assignment.
    Running optimization stage 1 on deUstb .......
    @N:CG364 : top.v(2) | Synthesizing module top in library work.
    Opening data file o_x.dat from directory ../../../data
    Opening data file o_y.dat from directory ../../../data
    @W:CG532 : top.v(37) | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
    @W:CG532 : top.v(45) | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
    Running optimization stage 1 on top .......
    Running optimization stage 2 on top .......
    Running optimization stage 2 on deUstb .......
    Running optimization stage 2 on XCORR_Top .......
    @N:CL159 : xcorr.v(6918) | Input rst is unused.
    Running optimization stage 2 on \(crosscorrelation)/(XCORR_Top)_17s_512s_3s .......
    Running optimization stage 2 on VCC .......
    Running optimization stage 2 on GND .......
    Running optimization stage 2 on MULT18X18 .......
    Running optimization stage 2 on ALU .......
    Running optimization stage 2 on SDPX9 .......
    Running optimization stage 2 on DFFRE .......
    Running optimization stage 2 on DFFR .......
    Running optimization stage 2 on DFFE .......
    Running optimization stage 2 on DFFS .......
    Running optimization stage 2 on DFF .......
    Running optimization stage 2 on MUX2_LUT6 .......
    Running optimization stage 2 on MUX2_LUT5 .......
    Running optimization stage 2 on LUT2 .......
    Running optimization stage 2 on LUT3 .......
    Running optimization stage 2 on LUT4 .......
    Running optimization stage 2 on INV .......
    Running optimization stage 2 on GSR .......

    For a summary of runtime and memory usage per design unit, please see file:
    ==========================================================
    Linked File:  layer0.rt.csv

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 79MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Dec 18 16:24:31 2018

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta3
    Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
    OS: CentOS release 6.8 (Final)
    Hostname: jinan9110.sdgowin.com

    Implementation : rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

    @N: :  | Running in 64-bit mode
    File C:\Gowin\1.8\SynplifyPro\bin64\syn_nfilter.exe changed - recompiling
    File F:\user-bak\Users\FDELL\Desktop\Gowin_XCORR_RefDesign\XCORR_512-3_case\project\impl\synthesize\rev_1\synwork\layer0.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 70MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Dec 18 16:24:32 2018

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Dec 18 16:24:32 2018

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta3
    Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
    OS: CentOS release 6.8 (Final)
    Hostname: jinan9110.sdgowin.com

    Database state : /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synthesize/rev_1/synwork/|rev_1
    Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

    @N: :  | Running in 64-bit mode
    File C:\Gowin\1.8\SynplifyPro\bin64\syn_nfilter.exe changed - recompiling
    File F:\user-bak\Users\FDELL\Desktop\Gowin_XCORR_RefDesign\XCORR_512-3_case\project\impl\synthesize\rev_1\synwork\XCORR_512-3_case_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 70MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Dec 18 16:24:33 2018

    ###########################################################]

`
`

    Premap Report

`
`

    # Tue Dec 18 16:24:33 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta3
    Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
    OS: CentOS release 6.8 (Final)
    Hostname: jinan9110.sdgowin.com
    max virtual memory: unlimited (bytes)
    max user processes: 1024
    max stack size: 10485760 (bytes)

    Implementation : rev_1
    Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1226R, Built Nov 21 2018 00:28:10

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    @A:MF827 :  | No constraint file specified.
    @N:MF284 :  | Setting synthesis effort to medium for the design
    Linked File:  XCORR_512-3_case_scck.rpt
    Printing clock  summary report in "/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synthesize/rev_1/XCORR_512-3_case_scck.rpt" file
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 103MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
    @N:MH105 :  | UMR3 is only supported for HAPS-80.
    @N:MH105 :  | UMR3 is only supported for HAPS-80.

    Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Rerun analysis in 0 latches

    Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    @N:MF974 :  | Total number of latches (multibit) processed = 0
    @N:MF975 :  | Total number of latches (bit blasted) processed = 0
    @N:MF976 :  | Total number of (multibit) opaque latches found = 0
    @N:MF977 :  | Total number of (bit blasted) opaque latches found = 0

    Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Detailed report for transparent and observable latches in design:
    Linked File:  XCORR_512-3_case_prem_latch_transparency_report.log

    Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    syn_allowed_resources : blockrams=140  set on top level netlist top

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

    Clock Summary
    ******************

              Start       Requested     Requested     Clock        Clock                     Clock
    Level     Clock       Frequency     Period        Type         Group                     Load
    ----------------------------------------------------------------------------------------------
    0 -       System      150.0 MHz     6.667         system       system_clkgroup           0

    0 -       top|clk     79.3 MHz      12.607        inferred     Autoconstr_clkgroup_0     352
    ==============================================================================================

    Clock Load Summary
    ***********************

                Clock     Source        Clock Pin            Non-clock Pin     Non-clock Pin
    Clock       Load      Pin           Seq Example          Seq Example       Comb Example
    ----------------------------------------------------------------------------------------
    System      0         -             -                    -                 -

    top|clk     352       clk(port)     series_x[16:0].C     -                 -
    ========================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    1 non-gated/non-generated clock tree(s) driving 352 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       clk                 Unconstrained_port     352        ad[8]
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synthesize/rev_1/XCORR_512-3_case.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)

    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 107MB peak: 193MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Tue Dec 18 16:24:35 2018

    ###########################################################]

`
`

    # Tue Dec 18 16:24:35 2018

    Copyright (C) 1994-2018 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: O-2018.09G-Beta3
    Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
    OS: CentOS release 6.8 (Final)
    Hostname: jinan9110.sdgowin.com
    max virtual memory: unlimited (bytes)
    max user processes: 1024
    max stack size: 10485760 (bytes)

    Implementation : rev_1
    Synopsys Generic Technology Mapper, Version mapgw, Build 1226R, Built Nov 21 2018 00:28:10

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

    @N:MF284 :  | Setting synthesis effort to medium for the design

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)

    Available hyper_sources - for debug and ip models
    	None Found

    @N:MT206 :  | Auto Constrain mode is enabled
    @N:FX493 :  | Applying initial value "00" on instance ut.isOk_r[1:0].
    @N:FX493 :  | Applying initial value "0000" on instance ut.cnt_r[3:0].
    @N:FX493 :  | Applying initial value "000000000" on instance ad[8:0].

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB)

    Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB)

    Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB)

    @A:BN291 : top.v(52) | Boundary register series_x[0] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[1] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[2] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[3] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[4] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[5] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[6] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[7] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[8] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[9] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[10] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[11] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[12] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[13] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[14] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[15] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[16] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[17] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[18] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[19] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[20] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[21] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[22] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[23] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[24] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[25] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[26] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[27] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[28] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[29] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[30] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[31] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[32] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A:BN291 : top.v(52) | Boundary register series_x[33] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_00 = 2621FE8818EDE513FBCFF641D3EFE1C99B3FEB2BE4AFF0A63845F8DCEE4FF2F2.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_01 = E61E0996E62A1E59EF91BA1355523AD2F3C816A324F00A47DCCDF119048A0009.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_02 = 379819C52FAFF5A6301C06A606B5E17EA854255F7319E3F4F6D823351CF3F928.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_03 = AF5FEC8C0F161D5573F80CB0EC442D9FA037E528EFD7F030A7B1F43329EC1B6A.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_04 = EDFBDB013E9C161EF9E9F51FF6CDF216C97DBFE6F385CB2FA597F8426B5A1247.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_05 = 22082A3FF943FC70A38BEC0E18941652EC2DD59EB1F9DB29647C07A738D2140B.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_06 = FED3EA676EA220D7E99FE66D0E44068B333E0BCE58740DC1137FD223B9DC2342.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_07 = 0643CBD846B1EF6333F1E8ABE95E0B07C5683A97C38834DF100C0CEDFA1C0FEC.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_08 = 2CD7EB195325F429D85DEB3F0DE22694FB77F717C215E674532DEC4344124BD9.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_09 = 12E42EE45BA7F9077A241519F16C00067DFE044F488C18E1E8662B62C419ECAE.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_0A = 2D64134E78C1F933095402E2499E0A2918120EBCEA71FA43E8BDEBCCDE1818C9.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_0B = DD400BBBF42DDF2DB3D0179F100C1C7BEA29FC2287621972B2EFE9BBBCA40A4A.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_0C = BE38062EB8160CF06D3DFEA4A611F8EEE7C7E379CAF5F6DF27200B0B3699FBD9.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_0D = C3D202205BBE11A3BC89F9AF000C23C8AC5414C000CDF375353C157622540DDA.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_0E = CEA5FA816F0FCDFF8A56328EB82218871F29F63AD7C3FC07A7AFCE4637DA1A75.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_0F = 0390285B0AAE03FD00C61B22D34E00472F05C571CA77F586E32610F4E5061004.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_10 = 1E9A0747D20FF4C9F18DFFED0EDFD4F3103BD271B37FFC34CD67F745CB37E7C0.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_11 = 0E13F69DBA901E7FF5B01F31F6D1EE15C29225B4FDD3C8ED6197F49C2B43CB67.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_12 = 78A607E64F2BD94212D3F4E38C23C82A5AD5E8FE8E361633DE022B377C44232D.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_13 = 0938170131FC121B2E11E5C2FEDBE6F8C375D70CDF7BF9AA481E109322CE0F16.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_14 = 1EC0013C35EA1464A16E1C11BB3BED221E7BFBC77D5BF75768782D9A3AC5D412.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_15 = ABABECD2FE6411D7F86C0AA8A6E808F417B5E27CE9F218BB3E67E534C59018B9.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_16 = 7BCFD343976A2EDCDCD1F8F1D354198A1F781148E449DD7CE94A0CB7B9BC2310.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_17 = 1A1DED5E117611443CFBF1E7B46A1180D5EC09683D07EA10428FEF6B12FA202D.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_18 = 02AC275592D206970DB1E3F0F4B9FA22680A2BFC543A1C96A05DDE175EBC31B0.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_19 = 8EAC124ECDF82C48307409A3CD242D84BF6A08F402C20D9604D42EBC2E15E4A5.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_1A = 4FADDC22F10E12CB177E02E32C8E1F3040A82A34440C2A6FCD082067F19DE215.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_1B = FD7FB999D028110085680C771C8BE7E5560210873C09FB02253010E8E8DA01F6.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_1C = EDA009CA0F61FC43964025C7C685F1BF4F81F29B76C22D5EF289DB90416410AA.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_1D = DF4F9872958231E872F800863CC3FC12D48C0104D93DDB458D29B2B0CB5201EC.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_1E = 248FF31FDE95E6FAD6521B0D11D1EF8821F1CA65F29DF6F85BFDBABEE891F6E6.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_1F = 64FFD63DE8ABE74445C5EA9C3CF81565B2221947C7221E6A3E67DFCEF04E1F1C.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_20 = 3159F5014E04036EB975DA98E4F3E65306341304D8EFDCB1A467BFF4FC36352B.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_21 = EF31FDBA250DF951A6621BF252F41767F9A9E28B647218B225F62045E1ABC942.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_22 = E21A0A36B961E9D130ABE706F7E9EC2E5AC1F431CE47FA103D17F4ED17D5B362.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_23 = 95781C8B3E13E541ECDDEDCED4D5FD3141C7F5CDF431E4A060BE14F5E1D9F801.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_24 = 0CA00581F159CA2AFE27FA2E3BA7F9A7DDB3DB9A4231E082F957DD724656094A.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_25 = 08A1F0ADE0781338F52616C7ECDE25BC7B021CC4EAB1E5F9E825F0E907462B33.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_26 = 0523BD0D2849E838116DE29F4CAFFB852C59E9FC145A02D00857B971E611F523.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_27 = C5F7DEEF2F4BEF06D14E317668CBEF674D04336053E3FAE06300090DFBABE62C.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_28 = D2DE39F19BE815FCF0CC18E0E0EDE7F8EF5FF4B53DA3E7ADBAB7F111941E089D.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_29 = 58E61802306BE9D26AF3FBEE4223D1D5DE61FD8FFD41DEAEDB0FD15A622DE18E.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_2A = F8E3D3CC4FDA1C263B9E09A4EB822595994C36A10B53EE9DF2BA0E788D0BEE03.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_2B = 45C3F79E310DFA137DD9DDEE2035ED75BD384C4239C205D4D47627A3030606DC.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_2C = 847E2D353B3022CEFAE1D67777AFDAF441361612022BC9064F3DE5882C15E106.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_2D = 010E103F3062392B9239E22A38E9EF00BFDA2BC10F17EA12A4DBF3390DB004AE.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_2E = BFE62FBFC8F5EB662218016EE503E656E781DF2CF2242A9DC5323F19941FFFDF.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_2F = 468024E40201D5912859FF8740BDE6070D5FCA50D579FEBA304C177324D7EBAC.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_30 = 93EE11A648BFDD999DF5DE1AE0641AAE4A4A0D12D25FF7B560BBF25FF181EC7E.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_31 = 1B87F199096BD3F455160F17ED0DED42ED88010AD49C0FDAFF35E615E4D20C0D.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_32 = FFE213EE1884093DD7664DEBD92E3289279201A21A7DCACE448217088091F785.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_33 = 16403D5A231E20A0E4261293EF0C02C49FF3DCB5255BFF72FC47FD44BBD43252.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_34 = F2880400F51BDFA9D20627501C41F75D0182065CA3F01B4EC267E2DB3936133F.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_35 = 3D4207F488400FD80A62001C14A7FA16D78BC02225F03C76F2D0360310102470.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_36 = 35C822684C8A11636225D6C65B61E0CBC98FE2F84C91E701CDFC0D81FCE7F7C0.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_37 = 9C5C163D15A5FE363C7611DBFC09D20F0D55D9374C65B00003E9EA45B94C1EA9.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_38 = 37AA02144D91F96DDE142D2DD303FC2F1487D43C8E821EFE25EC5B7868CBFAAC.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_39 = 24CFF570F2A9DABD56D1E4600B3010D49323FDC8E379F06407464B7200201827.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_3A = 8FE7EC351721DDA70243F47751861741647C1C9B6AD00F05CFC6095D25E40445.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_3B = EFC5FE4B26E816518985FC84F8E5FAFB36681BDA1B70376935CE0DB297DFF6CD.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_3C = 62D5D2B801480F9CBC61FA58887BE5187A9DD68A998601C8C6EDEF1C17E8452E.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_3D = C299D3BD34AC0C8AFEEDF0BB3FC00B2542F1CD1A06F9F9B038C3CDB8F1F40C1C.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_3E = E61BFDFDEF31F3B8762614B6018C0790D939DBA1DABFFB62CE5209A730A808A5.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_0.INIT_RAM_3F = 81C3E6F523DA01BDD7E629EAF21FFDE75511C34FC52403CF11A61D9CC9E5F400.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_00 = 0000000000000000000000030000000300000000000000030000000000000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_01 = 0000000300000003000000030000000000000003000000000000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_02 = 0000000000000000000000000000000000000003000000000000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_03 = 0000000300000000000000000000000300000003000000030000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_04 = 0000000300000000000000030000000300000003000000030000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_05 = 0000000000000003000000030000000000000003000000030000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_06 = 0000000300000003000000030000000000000000000000000000000000000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_07 = 0000000000000000000000000000000300000003000000030000000000000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_08 = 0000000000000000000000030000000000000003000000000000000000000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_09 = 0000000000000000000000000000000300000000000000000000000300000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_0A = 0000000000000000000000000000000000000000000000030000000300000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_0B = 0000000300000003000000030000000000000003000000030000000300000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_0C = 0000000300000003000000030000000300000003000000030000000000000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_0D = 0000000300000000000000000000000000000003000000000000000000000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_0E = 0000000300000000000000030000000300000000000000030000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_0F = 0000000000000000000000000000000300000000000000030000000300000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_10 = 0000000000000003000000030000000000000000000000030000000300000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_11 = 0000000000000003000000030000000300000003000000030000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_12 = 0000000000000000000000000000000000000000000000030000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_13 = 0000000000000000000000000000000300000003000000030000000000000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_14 = 0000000000000000000000030000000300000000000000000000000000000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_15 = 0000000300000003000000030000000300000000000000030000000000000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_16 = 0000000300000003000000030000000300000000000000030000000300000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_17 = 0000000000000000000000000000000300000003000000000000000000000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_18 = 0000000000000003000000000000000300000000000000000000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_19 = 0000000300000003000000000000000300000003000000000000000000000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_1A = 0000000000000003000000000000000000000000000000000000000300000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_1B = 0000000300000003000000000000000000000000000000000000000000000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_1C = 0000000300000000000000030000000300000000000000000000000300000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_1D = 0000000300000000000000000000000000000003000000030000000300000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_1E = 0000000000000003000000030000000000000000000000030000000000000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_1F = 0000000000000003000000000000000000000003000000030000000000000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_20 = 0000000000000003000000030000000300000000000000030000000300000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_21 = 0000000300000000000000030000000000000003000000000000000000000003.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_22 = 0000000300000003000000000000000300000000000000030000000000000000.
    @N:FX276 : top.v(59) | Initial value series_y_2_0_1.INIT_RAM_23 = 0000000300000000000000030000000300000000000000030000000000000003.

    Only the first 100 messages of id 'FX276' are reported. To see all messages use 'report_messages -log /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synthesize/rev_1/synlog/XCORR_512-3_case_fpga_mapper.srr -id FX276' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {FX276} -count unlimited' in the Tcl shell.
    @N:FX211 :  | Packed ROM series_y_2_0[33:0] (9 input, 34 output) to Block SelectRAM

    Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 194MB peak: 195MB)

    Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 194MB peak: 195MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:02s		    -2.64ns		 436 /        15
       2		0h:00m:02s		    -2.64ns		 436 /        15

       3		0h:00m:02s		    -2.64ns		 436 /        15

       4		0h:00m:02s		    -2.64ns		 436 /        15

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 194MB peak: 195MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
    @W:BN114 : top.v(59) | Removing instance series_y_2_0_0 (in view: work.top(verilog)) of black box view:VIRTEX.RAMB16(PRIM) because it does not drive other instances.
    @W:BN114 : top.v(59) | Removing instance series_y_2_0_1 (in view: work.top(verilog)) of black box view:VIRTEX.RAMB16(PRIM) because it does not drive other instances.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 194MB peak: 195MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 122MB peak: 196MB)

    Writing Analyst data base /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synthesize/rev_1/synwork/XCORR_512-3_case_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 197MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 195MB peak: 197MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 193MB peak: 197MB)

    Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 194MB peak: 197MB)

    @W:MT420 :  | Found inferred clock top|clk with period 6.41ns. Please declare a user-defined clock on port clk.

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Tue Dec 18 16:24:42 2018
    #

    Top view:               top
    Requested Frequency:    156.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: -1.131

                       Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
    ------------------------------------------------------------------------------------------------------------------------
    top|clk            156.0 MHz     132.6 MHz     6.409         7.540         -1.131     inferred     Autoconstr_clkgroup_0
    System             150.0 MHz     345.7 MHz     6.667         2.893         3.774      system       system_clkgroup
    ========================================================================================================================

    Clock Relationships
    *******************

    Clocks             |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ----------------------------------------------------------------------------------------------------------
    Starting  Ending   |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    ----------------------------------------------------------------------------------------------------------
    System    top|clk  |  6.409       3.774   |  No paths    -      |  No paths    -      |  No paths    -
    top|clk   System   |  6.409       5.448   |  No paths    -      |  No paths    -      |  No paths    -
    top|clk   top|clk  |  6.409       -1.131  |  No paths    -      |  No paths    -      |  No paths    -
    ==========================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: top|clk
    ====================================

    Starting Points with Worst Slack
    ********************************

                                              Starting                                               Arrival
    Instance                                  Reference     Type     Pin     Net                     Time        Slack
                                              Clock
    -------------------------------------------------------------------------------------------------------------------
    uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\]     top|clk       DFF      Q       memr_1_waddr_tmp[1]     0.243       -1.131
    uut.u_xcorr.\\memr_1_adreg_Z\[5\]         top|clk       DFFR     Q       memr_1_adreg[5]         0.243       -1.110
    uut.u_xcorr.\\memr_1_waddr_tmp_0\[2\]     top|clk       DFF      Q       memr_1_waddr_tmp[2]     0.243       -1.023
    uut.u_xcorr.\\memr_1_waddr_tmp_0\[5\]     top|clk       DFF      Q       memr_1_waddr_tmp[5]     0.243       -0.932
    uut.u_xcorr.\\memr_1_adreg_Z\[4\]         top|clk       DFFR     Q       memr_1_adreg[4]         0.243       -0.900
    uut.u_xcorr.\\memr_1_adreg_Z\[3\]         top|clk       DFFR     Q       memr_1_adreg[3]         0.243       -0.879
    uut.u_xcorr.\\delay_Z\[7\]                top|clk       DFF      Q       delay[7]                0.243       -0.845
    uut.u_xcorr.\\delay_Z\[6\]                top|clk       DFF      Q       delay[6]                0.243       -0.824
    uut.u_xcorr.\\memr_1_adreg_Z\[8\]         top|clk       DFFR     Q       memr_1_adreg[8]         0.243       -0.813
    uut.u_xcorr.\\delay_Z\[8\]                top|clk       DFF      Q       delay[8]                0.243       -0.798
    ===================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                     Starting                                        Required
    Instance                         Reference     Type     Pin     Net              Time         Slack
                                     Clock
    ----------------------------------------------------------------------------------------------------
    uut.u_xcorr.\\result_Z\[33\]     top|clk       DFFR     D       N_19_0           6.348        -1.131
    uut.u_xcorr.\\result_Z\[32\]     top|clk       DFFR     D       N_21_0           6.348        -1.096
    uut.u_xcorr.\\result_Z\[31\]     top|clk       DFFR     D       N_23_0           6.348        -1.061
    uut.u_xcorr.\\result_Z\[30\]     top|clk       DFFR     D       N_25_0           6.348        -1.026
    uut.u_xcorr.\\result_Z\[29\]     top|clk       DFFR     D       N_27_0           6.348        -0.991
    uut.u_xcorr.\\result_Z\[28\]     top|clk       DFFR     D       N_29_0           6.348        -0.956
    uut.u_xcorr.\\result_Z\[27\]     top|clk       DFFR     D       N_31_0           6.348        -0.921
    uut.u_xcorr.\\result_Z\[26\]     top|clk       DFFR     D       N_33_0           6.348        -0.886
    uut.u_xcorr.\\result_Z\[25\]     top|clk       DFFR     D       N_35_0           6.348        -0.851
    uut.u_xcorr.\\delay_1_Z\[1\]     top|clk       DFF      D       delay_1_0[1]     6.348        -0.845
    ====================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      6.409
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.348

        - Propagation time:                      7.479
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.131

        Number of logic level(s):                39
        Starting point:                          uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\] / Q
        Ending point:                            uut.u_xcorr.\\result_Z\[33\] / D
        The start point is clocked by            top|clk [rising] on pin CLK
        The end   point is clocked by            top|clk [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                      Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\]     DFF           Q        Out     0.243     0.243       -
    memr_1_waddr_tmp[1]                       Net           -        -       0.535     -           4
    uut.u_xcorr.memr_1_G_1_1_3_cZ             LUT4          I1       In      -         0.778       -
    uut.u_xcorr.memr_1_G_1_1_3_cZ             LUT4          F        Out     0.570     1.348       -
    memr_1_G_1_1_3                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_2_cZ             MUX2_LUT5     I0       In      -         1.348       -
    uut.u_xcorr.memr_1_G_1_1_2_cZ             MUX2_LUT5     O        Out     0.105     1.453       -
    memr_1_G_1_1_2                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     I1       In      -         1.453       -
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     O        Out     0.105     1.558       -
    memr_1_G_1_1_0                            Net           -        -       0.535     -           3
    uut.u_xcorr.memr_1_G_1                    LUT4          I1       In      -         2.093       -
    uut.u_xcorr.memr_1_G_1                    LUT4          F        Out     0.570     2.663       -
    memr_1_G_1                                Net           -        -       0.718     -           33
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          I2       In      -         3.381       -
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          F        Out     0.462     3.843       -
    un2_result_s_1_sf_lofx_cZ                 Net           -        -       0.535     -           1
    uut.u_xcorr.un2_result_cry_1_0            ALU           I0       In      -         4.378       -
    uut.u_xcorr.un2_result_cry_1_0            ALU           COUT     Out     0.549     4.927       -
    un2_result_cry_1_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_2_0            ALU           CIN      In      -         4.927       -
    uut.u_xcorr.un2_result_cry_2_0            ALU           COUT     Out     0.035     4.962       -
    un2_result_cry_2_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_3_0            ALU           CIN      In      -         4.962       -
    uut.u_xcorr.un2_result_cry_3_0            ALU           COUT     Out     0.035     4.997       -
    un2_result_cry_3_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_4_0            ALU           CIN      In      -         4.997       -
    uut.u_xcorr.un2_result_cry_4_0            ALU           COUT     Out     0.035     5.032       -
    un2_result_cry_4_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_5_0            ALU           CIN      In      -         5.032       -
    uut.u_xcorr.un2_result_cry_5_0            ALU           COUT     Out     0.035     5.067       -
    un2_result_cry_5_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_6_0            ALU           CIN      In      -         5.067       -
    uut.u_xcorr.un2_result_cry_6_0            ALU           COUT     Out     0.035     5.102       -
    un2_result_cry_6_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_7_0            ALU           CIN      In      -         5.102       -
    uut.u_xcorr.un2_result_cry_7_0            ALU           COUT     Out     0.035     5.137       -
    un2_result_cry_7_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_8_0            ALU           CIN      In      -         5.137       -
    uut.u_xcorr.un2_result_cry_8_0            ALU           COUT     Out     0.035     5.172       -
    un2_result_cry_8_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_9_0            ALU           CIN      In      -         5.172       -
    uut.u_xcorr.un2_result_cry_9_0            ALU           COUT     Out     0.035     5.207       -
    un2_result_cry_9_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_10_0           ALU           CIN      In      -         5.207       -
    uut.u_xcorr.un2_result_cry_10_0           ALU           COUT     Out     0.035     5.242       -
    un2_result_cry_10_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_11_0           ALU           CIN      In      -         5.242       -
    uut.u_xcorr.un2_result_cry_11_0           ALU           COUT     Out     0.035     5.277       -
    un2_result_cry_11_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_12_0           ALU           CIN      In      -         5.277       -
    uut.u_xcorr.un2_result_cry_12_0           ALU           COUT     Out     0.035     5.312       -
    un2_result_cry_12_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_13_0           ALU           CIN      In      -         5.312       -
    uut.u_xcorr.un2_result_cry_13_0           ALU           COUT     Out     0.035     5.347       -
    un2_result_cry_13_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_14_0           ALU           CIN      In      -         5.347       -
    uut.u_xcorr.un2_result_cry_14_0           ALU           COUT     Out     0.035     5.382       -
    un2_result_cry_14_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_15_0           ALU           CIN      In      -         5.382       -
    uut.u_xcorr.un2_result_cry_15_0           ALU           COUT     Out     0.035     5.417       -
    un2_result_cry_15_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_16_0           ALU           CIN      In      -         5.417       -
    uut.u_xcorr.un2_result_cry_16_0           ALU           COUT     Out     0.035     5.452       -
    un2_result_cry_16_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_17_0           ALU           CIN      In      -         5.452       -
    uut.u_xcorr.un2_result_cry_17_0           ALU           COUT     Out     0.035     5.487       -
    un2_result_cry_17_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_18_0           ALU           CIN      In      -         5.487       -
    uut.u_xcorr.un2_result_cry_18_0           ALU           COUT     Out     0.035     5.522       -
    un2_result_cry_18_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_19_0           ALU           CIN      In      -         5.522       -
    uut.u_xcorr.un2_result_cry_19_0           ALU           COUT     Out     0.035     5.557       -
    un2_result_cry_19_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_20_0           ALU           CIN      In      -         5.557       -
    uut.u_xcorr.un2_result_cry_20_0           ALU           COUT     Out     0.035     5.592       -
    un2_result_cry_20_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_21_0           ALU           CIN      In      -         5.592       -
    uut.u_xcorr.un2_result_cry_21_0           ALU           COUT     Out     0.035     5.627       -
    un2_result_cry_21_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_22_0           ALU           CIN      In      -         5.627       -
    uut.u_xcorr.un2_result_cry_22_0           ALU           COUT     Out     0.035     5.662       -
    un2_result_cry_22_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_23_0           ALU           CIN      In      -         5.662       -
    uut.u_xcorr.un2_result_cry_23_0           ALU           COUT     Out     0.035     5.697       -
    un2_result_cry_23_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_24_0           ALU           CIN      In      -         5.697       -
    uut.u_xcorr.un2_result_cry_24_0           ALU           COUT     Out     0.035     5.732       -
    un2_result_cry_24_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_25_0           ALU           CIN      In      -         5.732       -
    uut.u_xcorr.un2_result_cry_25_0           ALU           COUT     Out     0.035     5.767       -
    un2_result_cry_25_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_26_0           ALU           CIN      In      -         5.767       -
    uut.u_xcorr.un2_result_cry_26_0           ALU           COUT     Out     0.035     5.802       -
    un2_result_cry_26_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_27_0           ALU           CIN      In      -         5.802       -
    uut.u_xcorr.un2_result_cry_27_0           ALU           COUT     Out     0.035     5.837       -
    un2_result_cry_27_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_28_0           ALU           CIN      In      -         5.837       -
    uut.u_xcorr.un2_result_cry_28_0           ALU           COUT     Out     0.035     5.872       -
    un2_result_cry_28_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_29_0           ALU           CIN      In      -         5.872       -
    uut.u_xcorr.un2_result_cry_29_0           ALU           COUT     Out     0.035     5.907       -
    un2_result_cry_29_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_30_0           ALU           CIN      In      -         5.907       -
    uut.u_xcorr.un2_result_cry_30_0           ALU           COUT     Out     0.035     5.942       -
    un2_result_cry_30_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_31_0           ALU           CIN      In      -         5.942       -
    uut.u_xcorr.un2_result_cry_31_0           ALU           COUT     Out     0.035     5.977       -
    un2_result_cry_31_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_32_0           ALU           CIN      In      -         5.977       -
    uut.u_xcorr.un2_result_cry_32_0           ALU           COUT     Out     0.035     6.012       -
    un2_result_cry_32_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_s_33_0             ALU           CIN      In      -         6.012       -
    uut.u_xcorr.un2_result_s_33_0             ALU           SUM      Out     0.470     6.482       -
    un2_result_s_33_0_SUM                     Net           -        -       0.535     -           1
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          I2       In      -         7.017       -
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          F        Out     0.462     7.479       -
    N_19_0                                    Net           -        -       0.000     -           1
    uut.u_xcorr.\\result_Z\[33\]              DFFR          D        In      -         7.479       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 7.540 is 4.682(62.1%) logic and 2.858(37.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      6.409
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.348

        - Propagation time:                      7.479
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.131

        Number of logic level(s):                39
        Starting point:                          uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\] / Q
        Ending point:                            uut.u_xcorr.\\result_Z\[33\] / D
        The start point is clocked by            top|clk [rising] on pin CLK
        The end   point is clocked by            top|clk [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                      Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\]     DFF           Q        Out     0.243     0.243       -
    memr_1_waddr_tmp[1]                       Net           -        -       0.535     -           4
    uut.u_xcorr.memr_1_G_1_1_6_cZ             LUT4          I1       In      -         0.778       -
    uut.u_xcorr.memr_1_G_1_1_6_cZ             LUT4          F        Out     0.570     1.348       -
    memr_1_G_1_1_6                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_1_cZ             MUX2_LUT5     I1       In      -         1.348       -
    uut.u_xcorr.memr_1_G_1_1_1_cZ             MUX2_LUT5     O        Out     0.105     1.453       -
    memr_1_G_1_1_1                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     I0       In      -         1.453       -
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     O        Out     0.105     1.558       -
    memr_1_G_1_1_0                            Net           -        -       0.535     -           3
    uut.u_xcorr.memr_1_G_1                    LUT4          I1       In      -         2.093       -
    uut.u_xcorr.memr_1_G_1                    LUT4          F        Out     0.570     2.663       -
    memr_1_G_1                                Net           -        -       0.718     -           33
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          I2       In      -         3.381       -
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          F        Out     0.462     3.843       -
    un2_result_s_1_sf_lofx_cZ                 Net           -        -       0.535     -           1
    uut.u_xcorr.un2_result_cry_1_0            ALU           I0       In      -         4.378       -
    uut.u_xcorr.un2_result_cry_1_0            ALU           COUT     Out     0.549     4.927       -
    un2_result_cry_1_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_2_0            ALU           CIN      In      -         4.927       -
    uut.u_xcorr.un2_result_cry_2_0            ALU           COUT     Out     0.035     4.962       -
    un2_result_cry_2_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_3_0            ALU           CIN      In      -         4.962       -
    uut.u_xcorr.un2_result_cry_3_0            ALU           COUT     Out     0.035     4.997       -
    un2_result_cry_3_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_4_0            ALU           CIN      In      -         4.997       -
    uut.u_xcorr.un2_result_cry_4_0            ALU           COUT     Out     0.035     5.032       -
    un2_result_cry_4_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_5_0            ALU           CIN      In      -         5.032       -
    uut.u_xcorr.un2_result_cry_5_0            ALU           COUT     Out     0.035     5.067       -
    un2_result_cry_5_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_6_0            ALU           CIN      In      -         5.067       -
    uut.u_xcorr.un2_result_cry_6_0            ALU           COUT     Out     0.035     5.102       -
    un2_result_cry_6_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_7_0            ALU           CIN      In      -         5.102       -
    uut.u_xcorr.un2_result_cry_7_0            ALU           COUT     Out     0.035     5.137       -
    un2_result_cry_7_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_8_0            ALU           CIN      In      -         5.137       -
    uut.u_xcorr.un2_result_cry_8_0            ALU           COUT     Out     0.035     5.172       -
    un2_result_cry_8_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_9_0            ALU           CIN      In      -         5.172       -
    uut.u_xcorr.un2_result_cry_9_0            ALU           COUT     Out     0.035     5.207       -
    un2_result_cry_9_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_10_0           ALU           CIN      In      -         5.207       -
    uut.u_xcorr.un2_result_cry_10_0           ALU           COUT     Out     0.035     5.242       -
    un2_result_cry_10_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_11_0           ALU           CIN      In      -         5.242       -
    uut.u_xcorr.un2_result_cry_11_0           ALU           COUT     Out     0.035     5.277       -
    un2_result_cry_11_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_12_0           ALU           CIN      In      -         5.277       -
    uut.u_xcorr.un2_result_cry_12_0           ALU           COUT     Out     0.035     5.312       -
    un2_result_cry_12_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_13_0           ALU           CIN      In      -         5.312       -
    uut.u_xcorr.un2_result_cry_13_0           ALU           COUT     Out     0.035     5.347       -
    un2_result_cry_13_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_14_0           ALU           CIN      In      -         5.347       -
    uut.u_xcorr.un2_result_cry_14_0           ALU           COUT     Out     0.035     5.382       -
    un2_result_cry_14_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_15_0           ALU           CIN      In      -         5.382       -
    uut.u_xcorr.un2_result_cry_15_0           ALU           COUT     Out     0.035     5.417       -
    un2_result_cry_15_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_16_0           ALU           CIN      In      -         5.417       -
    uut.u_xcorr.un2_result_cry_16_0           ALU           COUT     Out     0.035     5.452       -
    un2_result_cry_16_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_17_0           ALU           CIN      In      -         5.452       -
    uut.u_xcorr.un2_result_cry_17_0           ALU           COUT     Out     0.035     5.487       -
    un2_result_cry_17_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_18_0           ALU           CIN      In      -         5.487       -
    uut.u_xcorr.un2_result_cry_18_0           ALU           COUT     Out     0.035     5.522       -
    un2_result_cry_18_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_19_0           ALU           CIN      In      -         5.522       -
    uut.u_xcorr.un2_result_cry_19_0           ALU           COUT     Out     0.035     5.557       -
    un2_result_cry_19_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_20_0           ALU           CIN      In      -         5.557       -
    uut.u_xcorr.un2_result_cry_20_0           ALU           COUT     Out     0.035     5.592       -
    un2_result_cry_20_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_21_0           ALU           CIN      In      -         5.592       -
    uut.u_xcorr.un2_result_cry_21_0           ALU           COUT     Out     0.035     5.627       -
    un2_result_cry_21_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_22_0           ALU           CIN      In      -         5.627       -
    uut.u_xcorr.un2_result_cry_22_0           ALU           COUT     Out     0.035     5.662       -
    un2_result_cry_22_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_23_0           ALU           CIN      In      -         5.662       -
    uut.u_xcorr.un2_result_cry_23_0           ALU           COUT     Out     0.035     5.697       -
    un2_result_cry_23_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_24_0           ALU           CIN      In      -         5.697       -
    uut.u_xcorr.un2_result_cry_24_0           ALU           COUT     Out     0.035     5.732       -
    un2_result_cry_24_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_25_0           ALU           CIN      In      -         5.732       -
    uut.u_xcorr.un2_result_cry_25_0           ALU           COUT     Out     0.035     5.767       -
    un2_result_cry_25_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_26_0           ALU           CIN      In      -         5.767       -
    uut.u_xcorr.un2_result_cry_26_0           ALU           COUT     Out     0.035     5.802       -
    un2_result_cry_26_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_27_0           ALU           CIN      In      -         5.802       -
    uut.u_xcorr.un2_result_cry_27_0           ALU           COUT     Out     0.035     5.837       -
    un2_result_cry_27_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_28_0           ALU           CIN      In      -         5.837       -
    uut.u_xcorr.un2_result_cry_28_0           ALU           COUT     Out     0.035     5.872       -
    un2_result_cry_28_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_29_0           ALU           CIN      In      -         5.872       -
    uut.u_xcorr.un2_result_cry_29_0           ALU           COUT     Out     0.035     5.907       -
    un2_result_cry_29_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_30_0           ALU           CIN      In      -         5.907       -
    uut.u_xcorr.un2_result_cry_30_0           ALU           COUT     Out     0.035     5.942       -
    un2_result_cry_30_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_31_0           ALU           CIN      In      -         5.942       -
    uut.u_xcorr.un2_result_cry_31_0           ALU           COUT     Out     0.035     5.977       -
    un2_result_cry_31_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_32_0           ALU           CIN      In      -         5.977       -
    uut.u_xcorr.un2_result_cry_32_0           ALU           COUT     Out     0.035     6.012       -
    un2_result_cry_32_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_s_33_0             ALU           CIN      In      -         6.012       -
    uut.u_xcorr.un2_result_s_33_0             ALU           SUM      Out     0.470     6.482       -
    un2_result_s_33_0_SUM                     Net           -        -       0.535     -           1
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          I2       In      -         7.017       -
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          F        Out     0.462     7.479       -
    N_19_0                                    Net           -        -       0.000     -           1
    uut.u_xcorr.\\result_Z\[33\]              DFFR          D        In      -         7.479       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 7.540 is 4.682(62.1%) logic and 2.858(37.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      6.409
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.348

        - Propagation time:                      7.479
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.131

        Number of logic level(s):                39
        Starting point:                          uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\] / Q
        Ending point:                            uut.u_xcorr.\\result_Z\[33\] / D
        The start point is clocked by            top|clk [rising] on pin CLK
        The end   point is clocked by            top|clk [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                      Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\]     DFF           Q        Out     0.243     0.243       -
    memr_1_waddr_tmp[1]                       Net           -        -       0.535     -           4
    uut.u_xcorr.memr_1_G_1_1_5_cZ             LUT4          I1       In      -         0.778       -
    uut.u_xcorr.memr_1_G_1_1_5_cZ             LUT4          F        Out     0.570     1.348       -
    memr_1_G_1_1_5                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_1_cZ             MUX2_LUT5     I0       In      -         1.348       -
    uut.u_xcorr.memr_1_G_1_1_1_cZ             MUX2_LUT5     O        Out     0.105     1.453       -
    memr_1_G_1_1_1                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     I0       In      -         1.453       -
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     O        Out     0.105     1.558       -
    memr_1_G_1_1_0                            Net           -        -       0.535     -           3
    uut.u_xcorr.memr_1_G_1                    LUT4          I1       In      -         2.093       -
    uut.u_xcorr.memr_1_G_1                    LUT4          F        Out     0.570     2.663       -
    memr_1_G_1                                Net           -        -       0.718     -           33
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          I2       In      -         3.381       -
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          F        Out     0.462     3.843       -
    un2_result_s_1_sf_lofx_cZ                 Net           -        -       0.535     -           1
    uut.u_xcorr.un2_result_cry_1_0            ALU           I0       In      -         4.378       -
    uut.u_xcorr.un2_result_cry_1_0            ALU           COUT     Out     0.549     4.927       -
    un2_result_cry_1_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_2_0            ALU           CIN      In      -         4.927       -
    uut.u_xcorr.un2_result_cry_2_0            ALU           COUT     Out     0.035     4.962       -
    un2_result_cry_2_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_3_0            ALU           CIN      In      -         4.962       -
    uut.u_xcorr.un2_result_cry_3_0            ALU           COUT     Out     0.035     4.997       -
    un2_result_cry_3_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_4_0            ALU           CIN      In      -         4.997       -
    uut.u_xcorr.un2_result_cry_4_0            ALU           COUT     Out     0.035     5.032       -
    un2_result_cry_4_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_5_0            ALU           CIN      In      -         5.032       -
    uut.u_xcorr.un2_result_cry_5_0            ALU           COUT     Out     0.035     5.067       -
    un2_result_cry_5_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_6_0            ALU           CIN      In      -         5.067       -
    uut.u_xcorr.un2_result_cry_6_0            ALU           COUT     Out     0.035     5.102       -
    un2_result_cry_6_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_7_0            ALU           CIN      In      -         5.102       -
    uut.u_xcorr.un2_result_cry_7_0            ALU           COUT     Out     0.035     5.137       -
    un2_result_cry_7_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_8_0            ALU           CIN      In      -         5.137       -
    uut.u_xcorr.un2_result_cry_8_0            ALU           COUT     Out     0.035     5.172       -
    un2_result_cry_8_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_9_0            ALU           CIN      In      -         5.172       -
    uut.u_xcorr.un2_result_cry_9_0            ALU           COUT     Out     0.035     5.207       -
    un2_result_cry_9_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_10_0           ALU           CIN      In      -         5.207       -
    uut.u_xcorr.un2_result_cry_10_0           ALU           COUT     Out     0.035     5.242       -
    un2_result_cry_10_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_11_0           ALU           CIN      In      -         5.242       -
    uut.u_xcorr.un2_result_cry_11_0           ALU           COUT     Out     0.035     5.277       -
    un2_result_cry_11_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_12_0           ALU           CIN      In      -         5.277       -
    uut.u_xcorr.un2_result_cry_12_0           ALU           COUT     Out     0.035     5.312       -
    un2_result_cry_12_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_13_0           ALU           CIN      In      -         5.312       -
    uut.u_xcorr.un2_result_cry_13_0           ALU           COUT     Out     0.035     5.347       -
    un2_result_cry_13_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_14_0           ALU           CIN      In      -         5.347       -
    uut.u_xcorr.un2_result_cry_14_0           ALU           COUT     Out     0.035     5.382       -
    un2_result_cry_14_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_15_0           ALU           CIN      In      -         5.382       -
    uut.u_xcorr.un2_result_cry_15_0           ALU           COUT     Out     0.035     5.417       -
    un2_result_cry_15_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_16_0           ALU           CIN      In      -         5.417       -
    uut.u_xcorr.un2_result_cry_16_0           ALU           COUT     Out     0.035     5.452       -
    un2_result_cry_16_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_17_0           ALU           CIN      In      -         5.452       -
    uut.u_xcorr.un2_result_cry_17_0           ALU           COUT     Out     0.035     5.487       -
    un2_result_cry_17_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_18_0           ALU           CIN      In      -         5.487       -
    uut.u_xcorr.un2_result_cry_18_0           ALU           COUT     Out     0.035     5.522       -
    un2_result_cry_18_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_19_0           ALU           CIN      In      -         5.522       -
    uut.u_xcorr.un2_result_cry_19_0           ALU           COUT     Out     0.035     5.557       -
    un2_result_cry_19_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_20_0           ALU           CIN      In      -         5.557       -
    uut.u_xcorr.un2_result_cry_20_0           ALU           COUT     Out     0.035     5.592       -
    un2_result_cry_20_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_21_0           ALU           CIN      In      -         5.592       -
    uut.u_xcorr.un2_result_cry_21_0           ALU           COUT     Out     0.035     5.627       -
    un2_result_cry_21_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_22_0           ALU           CIN      In      -         5.627       -
    uut.u_xcorr.un2_result_cry_22_0           ALU           COUT     Out     0.035     5.662       -
    un2_result_cry_22_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_23_0           ALU           CIN      In      -         5.662       -
    uut.u_xcorr.un2_result_cry_23_0           ALU           COUT     Out     0.035     5.697       -
    un2_result_cry_23_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_24_0           ALU           CIN      In      -         5.697       -
    uut.u_xcorr.un2_result_cry_24_0           ALU           COUT     Out     0.035     5.732       -
    un2_result_cry_24_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_25_0           ALU           CIN      In      -         5.732       -
    uut.u_xcorr.un2_result_cry_25_0           ALU           COUT     Out     0.035     5.767       -
    un2_result_cry_25_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_26_0           ALU           CIN      In      -         5.767       -
    uut.u_xcorr.un2_result_cry_26_0           ALU           COUT     Out     0.035     5.802       -
    un2_result_cry_26_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_27_0           ALU           CIN      In      -         5.802       -
    uut.u_xcorr.un2_result_cry_27_0           ALU           COUT     Out     0.035     5.837       -
    un2_result_cry_27_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_28_0           ALU           CIN      In      -         5.837       -
    uut.u_xcorr.un2_result_cry_28_0           ALU           COUT     Out     0.035     5.872       -
    un2_result_cry_28_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_29_0           ALU           CIN      In      -         5.872       -
    uut.u_xcorr.un2_result_cry_29_0           ALU           COUT     Out     0.035     5.907       -
    un2_result_cry_29_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_30_0           ALU           CIN      In      -         5.907       -
    uut.u_xcorr.un2_result_cry_30_0           ALU           COUT     Out     0.035     5.942       -
    un2_result_cry_30_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_31_0           ALU           CIN      In      -         5.942       -
    uut.u_xcorr.un2_result_cry_31_0           ALU           COUT     Out     0.035     5.977       -
    un2_result_cry_31_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_32_0           ALU           CIN      In      -         5.977       -
    uut.u_xcorr.un2_result_cry_32_0           ALU           COUT     Out     0.035     6.012       -
    un2_result_cry_32_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_s_33_0             ALU           CIN      In      -         6.012       -
    uut.u_xcorr.un2_result_s_33_0             ALU           SUM      Out     0.470     6.482       -
    un2_result_s_33_0_SUM                     Net           -        -       0.535     -           1
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          I2       In      -         7.017       -
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          F        Out     0.462     7.479       -
    N_19_0                                    Net           -        -       0.000     -           1
    uut.u_xcorr.\\result_Z\[33\]              DFFR          D        In      -         7.479       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 7.540 is 4.682(62.1%) logic and 2.858(37.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      6.409
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.348

        - Propagation time:                      7.479
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -1.131

        Number of logic level(s):                39
        Starting point:                          uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\] / Q
        Ending point:                            uut.u_xcorr.\\result_Z\[33\] / D
        The start point is clocked by            top|clk [rising] on pin CLK
        The end   point is clocked by            top|clk [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                      Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\]     DFF           Q        Out     0.243     0.243       -
    memr_1_waddr_tmp[1]                       Net           -        -       0.535     -           4
    uut.u_xcorr.memr_1_G_1_1_4_cZ             LUT4          I1       In      -         0.778       -
    uut.u_xcorr.memr_1_G_1_1_4_cZ             LUT4          F        Out     0.570     1.348       -
    memr_1_G_1_1_4                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_2_cZ             MUX2_LUT5     I1       In      -         1.348       -
    uut.u_xcorr.memr_1_G_1_1_2_cZ             MUX2_LUT5     O        Out     0.105     1.453       -
    memr_1_G_1_1_2                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     I1       In      -         1.453       -
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     O        Out     0.105     1.558       -
    memr_1_G_1_1_0                            Net           -        -       0.535     -           3
    uut.u_xcorr.memr_1_G_1                    LUT4          I1       In      -         2.093       -
    uut.u_xcorr.memr_1_G_1                    LUT4          F        Out     0.570     2.663       -
    memr_1_G_1                                Net           -        -       0.718     -           33
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          I2       In      -         3.381       -
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          F        Out     0.462     3.843       -
    un2_result_s_1_sf_lofx_cZ                 Net           -        -       0.535     -           1
    uut.u_xcorr.un2_result_cry_1_0            ALU           I0       In      -         4.378       -
    uut.u_xcorr.un2_result_cry_1_0            ALU           COUT     Out     0.549     4.927       -
    un2_result_cry_1_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_2_0            ALU           CIN      In      -         4.927       -
    uut.u_xcorr.un2_result_cry_2_0            ALU           COUT     Out     0.035     4.962       -
    un2_result_cry_2_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_3_0            ALU           CIN      In      -         4.962       -
    uut.u_xcorr.un2_result_cry_3_0            ALU           COUT     Out     0.035     4.997       -
    un2_result_cry_3_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_4_0            ALU           CIN      In      -         4.997       -
    uut.u_xcorr.un2_result_cry_4_0            ALU           COUT     Out     0.035     5.032       -
    un2_result_cry_4_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_5_0            ALU           CIN      In      -         5.032       -
    uut.u_xcorr.un2_result_cry_5_0            ALU           COUT     Out     0.035     5.067       -
    un2_result_cry_5_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_6_0            ALU           CIN      In      -         5.067       -
    uut.u_xcorr.un2_result_cry_6_0            ALU           COUT     Out     0.035     5.102       -
    un2_result_cry_6_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_7_0            ALU           CIN      In      -         5.102       -
    uut.u_xcorr.un2_result_cry_7_0            ALU           COUT     Out     0.035     5.137       -
    un2_result_cry_7_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_8_0            ALU           CIN      In      -         5.137       -
    uut.u_xcorr.un2_result_cry_8_0            ALU           COUT     Out     0.035     5.172       -
    un2_result_cry_8_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_9_0            ALU           CIN      In      -         5.172       -
    uut.u_xcorr.un2_result_cry_9_0            ALU           COUT     Out     0.035     5.207       -
    un2_result_cry_9_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_10_0           ALU           CIN      In      -         5.207       -
    uut.u_xcorr.un2_result_cry_10_0           ALU           COUT     Out     0.035     5.242       -
    un2_result_cry_10_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_11_0           ALU           CIN      In      -         5.242       -
    uut.u_xcorr.un2_result_cry_11_0           ALU           COUT     Out     0.035     5.277       -
    un2_result_cry_11_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_12_0           ALU           CIN      In      -         5.277       -
    uut.u_xcorr.un2_result_cry_12_0           ALU           COUT     Out     0.035     5.312       -
    un2_result_cry_12_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_13_0           ALU           CIN      In      -         5.312       -
    uut.u_xcorr.un2_result_cry_13_0           ALU           COUT     Out     0.035     5.347       -
    un2_result_cry_13_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_14_0           ALU           CIN      In      -         5.347       -
    uut.u_xcorr.un2_result_cry_14_0           ALU           COUT     Out     0.035     5.382       -
    un2_result_cry_14_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_15_0           ALU           CIN      In      -         5.382       -
    uut.u_xcorr.un2_result_cry_15_0           ALU           COUT     Out     0.035     5.417       -
    un2_result_cry_15_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_16_0           ALU           CIN      In      -         5.417       -
    uut.u_xcorr.un2_result_cry_16_0           ALU           COUT     Out     0.035     5.452       -
    un2_result_cry_16_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_17_0           ALU           CIN      In      -         5.452       -
    uut.u_xcorr.un2_result_cry_17_0           ALU           COUT     Out     0.035     5.487       -
    un2_result_cry_17_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_18_0           ALU           CIN      In      -         5.487       -
    uut.u_xcorr.un2_result_cry_18_0           ALU           COUT     Out     0.035     5.522       -
    un2_result_cry_18_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_19_0           ALU           CIN      In      -         5.522       -
    uut.u_xcorr.un2_result_cry_19_0           ALU           COUT     Out     0.035     5.557       -
    un2_result_cry_19_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_20_0           ALU           CIN      In      -         5.557       -
    uut.u_xcorr.un2_result_cry_20_0           ALU           COUT     Out     0.035     5.592       -
    un2_result_cry_20_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_21_0           ALU           CIN      In      -         5.592       -
    uut.u_xcorr.un2_result_cry_21_0           ALU           COUT     Out     0.035     5.627       -
    un2_result_cry_21_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_22_0           ALU           CIN      In      -         5.627       -
    uut.u_xcorr.un2_result_cry_22_0           ALU           COUT     Out     0.035     5.662       -
    un2_result_cry_22_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_23_0           ALU           CIN      In      -         5.662       -
    uut.u_xcorr.un2_result_cry_23_0           ALU           COUT     Out     0.035     5.697       -
    un2_result_cry_23_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_24_0           ALU           CIN      In      -         5.697       -
    uut.u_xcorr.un2_result_cry_24_0           ALU           COUT     Out     0.035     5.732       -
    un2_result_cry_24_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_25_0           ALU           CIN      In      -         5.732       -
    uut.u_xcorr.un2_result_cry_25_0           ALU           COUT     Out     0.035     5.767       -
    un2_result_cry_25_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_26_0           ALU           CIN      In      -         5.767       -
    uut.u_xcorr.un2_result_cry_26_0           ALU           COUT     Out     0.035     5.802       -
    un2_result_cry_26_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_27_0           ALU           CIN      In      -         5.802       -
    uut.u_xcorr.un2_result_cry_27_0           ALU           COUT     Out     0.035     5.837       -
    un2_result_cry_27_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_28_0           ALU           CIN      In      -         5.837       -
    uut.u_xcorr.un2_result_cry_28_0           ALU           COUT     Out     0.035     5.872       -
    un2_result_cry_28_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_29_0           ALU           CIN      In      -         5.872       -
    uut.u_xcorr.un2_result_cry_29_0           ALU           COUT     Out     0.035     5.907       -
    un2_result_cry_29_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_30_0           ALU           CIN      In      -         5.907       -
    uut.u_xcorr.un2_result_cry_30_0           ALU           COUT     Out     0.035     5.942       -
    un2_result_cry_30_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_31_0           ALU           CIN      In      -         5.942       -
    uut.u_xcorr.un2_result_cry_31_0           ALU           COUT     Out     0.035     5.977       -
    un2_result_cry_31_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_32_0           ALU           CIN      In      -         5.977       -
    uut.u_xcorr.un2_result_cry_32_0           ALU           COUT     Out     0.035     6.012       -
    un2_result_cry_32_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_s_33_0             ALU           CIN      In      -         6.012       -
    uut.u_xcorr.un2_result_s_33_0             ALU           SUM      Out     0.470     6.482       -
    un2_result_s_33_0_SUM                     Net           -        -       0.535     -           1
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          I2       In      -         7.017       -
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          F        Out     0.462     7.479       -
    N_19_0                                    Net           -        -       0.000     -           1
    uut.u_xcorr.\\result_Z\[33\]              DFFR          D        In      -         7.479       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 7.540 is 4.682(62.1%) logic and 2.858(37.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      6.409
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.348

        - Propagation time:                      7.458
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -1.110

        Number of logic level(s):                39
        Starting point:                          uut.u_xcorr.\\memr_1_adreg_Z\[5\] / Q
        Ending point:                            uut.u_xcorr.\\result_Z\[33\] / D
        The start point is clocked by            top|clk [rising] on pin CLK
        The end   point is clocked by            top|clk [rising] on pin CLK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                      Type          Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    uut.u_xcorr.\\memr_1_adreg_Z\[5\]         DFFR          Q        Out     0.243     0.243       -
    memr_1_adreg[5]                           Net           -        -       0.535     -           6
    uut.u_xcorr.memr_1_G_1_1_3_cZ             LUT4          I0       In      -         0.778       -
    uut.u_xcorr.memr_1_G_1_1_3_cZ             LUT4          F        Out     0.549     1.327       -
    memr_1_G_1_1_3                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_2_cZ             MUX2_LUT5     I0       In      -         1.327       -
    uut.u_xcorr.memr_1_G_1_1_2_cZ             MUX2_LUT5     O        Out     0.105     1.432       -
    memr_1_G_1_1_2                            Net           -        -       0.000     -           1
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     I1       In      -         1.432       -
    uut.u_xcorr.memr_1_G_1_1_0_cZ             MUX2_LUT6     O        Out     0.105     1.537       -
    memr_1_G_1_1_0                            Net           -        -       0.535     -           3
    uut.u_xcorr.memr_1_G_1                    LUT4          I1       In      -         2.072       -
    uut.u_xcorr.memr_1_G_1                    LUT4          F        Out     0.570     2.642       -
    memr_1_G_1                                Net           -        -       0.718     -           33
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          I2       In      -         3.360       -
    uut.u_xcorr.un2_result_s_1_sf_lofx_cZ     LUT3          F        Out     0.462     3.822       -
    un2_result_s_1_sf_lofx_cZ                 Net           -        -       0.535     -           1
    uut.u_xcorr.un2_result_cry_1_0            ALU           I0       In      -         4.357       -
    uut.u_xcorr.un2_result_cry_1_0            ALU           COUT     Out     0.549     4.906       -
    un2_result_cry_1_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_2_0            ALU           CIN      In      -         4.906       -
    uut.u_xcorr.un2_result_cry_2_0            ALU           COUT     Out     0.035     4.941       -
    un2_result_cry_2_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_3_0            ALU           CIN      In      -         4.941       -
    uut.u_xcorr.un2_result_cry_3_0            ALU           COUT     Out     0.035     4.976       -
    un2_result_cry_3_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_4_0            ALU           CIN      In      -         4.976       -
    uut.u_xcorr.un2_result_cry_4_0            ALU           COUT     Out     0.035     5.011       -
    un2_result_cry_4_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_5_0            ALU           CIN      In      -         5.011       -
    uut.u_xcorr.un2_result_cry_5_0            ALU           COUT     Out     0.035     5.046       -
    un2_result_cry_5_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_6_0            ALU           CIN      In      -         5.046       -
    uut.u_xcorr.un2_result_cry_6_0            ALU           COUT     Out     0.035     5.081       -
    un2_result_cry_6_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_7_0            ALU           CIN      In      -         5.081       -
    uut.u_xcorr.un2_result_cry_7_0            ALU           COUT     Out     0.035     5.116       -
    un2_result_cry_7_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_8_0            ALU           CIN      In      -         5.116       -
    uut.u_xcorr.un2_result_cry_8_0            ALU           COUT     Out     0.035     5.151       -
    un2_result_cry_8_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_9_0            ALU           CIN      In      -         5.151       -
    uut.u_xcorr.un2_result_cry_9_0            ALU           COUT     Out     0.035     5.186       -
    un2_result_cry_9_0_COUT                   Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_10_0           ALU           CIN      In      -         5.186       -
    uut.u_xcorr.un2_result_cry_10_0           ALU           COUT     Out     0.035     5.221       -
    un2_result_cry_10_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_11_0           ALU           CIN      In      -         5.221       -
    uut.u_xcorr.un2_result_cry_11_0           ALU           COUT     Out     0.035     5.256       -
    un2_result_cry_11_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_12_0           ALU           CIN      In      -         5.256       -
    uut.u_xcorr.un2_result_cry_12_0           ALU           COUT     Out     0.035     5.291       -
    un2_result_cry_12_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_13_0           ALU           CIN      In      -         5.291       -
    uut.u_xcorr.un2_result_cry_13_0           ALU           COUT     Out     0.035     5.326       -
    un2_result_cry_13_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_14_0           ALU           CIN      In      -         5.326       -
    uut.u_xcorr.un2_result_cry_14_0           ALU           COUT     Out     0.035     5.361       -
    un2_result_cry_14_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_15_0           ALU           CIN      In      -         5.361       -
    uut.u_xcorr.un2_result_cry_15_0           ALU           COUT     Out     0.035     5.396       -
    un2_result_cry_15_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_16_0           ALU           CIN      In      -         5.396       -
    uut.u_xcorr.un2_result_cry_16_0           ALU           COUT     Out     0.035     5.431       -
    un2_result_cry_16_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_17_0           ALU           CIN      In      -         5.431       -
    uut.u_xcorr.un2_result_cry_17_0           ALU           COUT     Out     0.035     5.466       -
    un2_result_cry_17_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_18_0           ALU           CIN      In      -         5.466       -
    uut.u_xcorr.un2_result_cry_18_0           ALU           COUT     Out     0.035     5.501       -
    un2_result_cry_18_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_19_0           ALU           CIN      In      -         5.501       -
    uut.u_xcorr.un2_result_cry_19_0           ALU           COUT     Out     0.035     5.536       -
    un2_result_cry_19_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_20_0           ALU           CIN      In      -         5.536       -
    uut.u_xcorr.un2_result_cry_20_0           ALU           COUT     Out     0.035     5.571       -
    un2_result_cry_20_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_21_0           ALU           CIN      In      -         5.571       -
    uut.u_xcorr.un2_result_cry_21_0           ALU           COUT     Out     0.035     5.606       -
    un2_result_cry_21_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_22_0           ALU           CIN      In      -         5.606       -
    uut.u_xcorr.un2_result_cry_22_0           ALU           COUT     Out     0.035     5.641       -
    un2_result_cry_22_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_23_0           ALU           CIN      In      -         5.641       -
    uut.u_xcorr.un2_result_cry_23_0           ALU           COUT     Out     0.035     5.676       -
    un2_result_cry_23_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_24_0           ALU           CIN      In      -         5.676       -
    uut.u_xcorr.un2_result_cry_24_0           ALU           COUT     Out     0.035     5.711       -
    un2_result_cry_24_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_25_0           ALU           CIN      In      -         5.711       -
    uut.u_xcorr.un2_result_cry_25_0           ALU           COUT     Out     0.035     5.746       -
    un2_result_cry_25_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_26_0           ALU           CIN      In      -         5.746       -
    uut.u_xcorr.un2_result_cry_26_0           ALU           COUT     Out     0.035     5.781       -
    un2_result_cry_26_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_27_0           ALU           CIN      In      -         5.781       -
    uut.u_xcorr.un2_result_cry_27_0           ALU           COUT     Out     0.035     5.816       -
    un2_result_cry_27_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_28_0           ALU           CIN      In      -         5.816       -
    uut.u_xcorr.un2_result_cry_28_0           ALU           COUT     Out     0.035     5.851       -
    un2_result_cry_28_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_29_0           ALU           CIN      In      -         5.851       -
    uut.u_xcorr.un2_result_cry_29_0           ALU           COUT     Out     0.035     5.886       -
    un2_result_cry_29_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_30_0           ALU           CIN      In      -         5.886       -
    uut.u_xcorr.un2_result_cry_30_0           ALU           COUT     Out     0.035     5.921       -
    un2_result_cry_30_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_31_0           ALU           CIN      In      -         5.921       -
    uut.u_xcorr.un2_result_cry_31_0           ALU           COUT     Out     0.035     5.956       -
    un2_result_cry_31_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_cry_32_0           ALU           CIN      In      -         5.956       -
    uut.u_xcorr.un2_result_cry_32_0           ALU           COUT     Out     0.035     5.991       -
    un2_result_cry_32_0_COUT                  Net           -        -       0.000     -           1
    uut.u_xcorr.un2_result_s_33_0             ALU           CIN      In      -         5.991       -
    uut.u_xcorr.un2_result_s_33_0             ALU           SUM      Out     0.470     6.461       -
    un2_result_s_33_0_SUM                     Net           -        -       0.535     -           1
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          I2       In      -         6.996       -
    uut.u_xcorr.\\result_0_0\[33\]            LUT3          F        Out     0.462     7.458       -
    N_19_0                                    Net           -        -       0.000     -           1
    uut.u_xcorr.\\result_Z\[33\]              DFFR          D        In      -         7.458       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 7.519 is 4.661(62.0%) logic and 2.858(38.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                  Starting                                                         Arrival
    Instance                                      Reference     Type     Pin     Net                               Time        Slack
                                                  Clock
    --------------------------------------------------------------------------------------------------------------------------------
    uut.u_xcorr.un1_delay_21_cry_3_0_RNO_0_cZ     System        INV      O       un1_delay_21_cry_3_0_RNO_0_cZ     0.000       3.774
    uut.u_xcorr.x_1_ret_33_0_RNI69O7              System        INV      O       x_1_ret_33_0_RNI69O7              0.000       5.630
    uut.u_xcorr.\\ad_RNO\[0\]                     System        INV      O       N_17_0                            0.000       5.813
    uut.u_xcorr.\\ad_RNO\[1\]                     System        INV      O       N_15_0                            0.000       5.813
    uut.u_xcorr.\\ad_RNO\[3\]                     System        INV      O       N_11_0                            0.000       5.813
    uut.u_xcorr.\\ad_RNO\[5\]                     System        INV      O       N_7_0                             0.000       5.813
    uut.u_xcorr.\\ad_RNO\[7\]                     System        INV      O       N_3_0                             0.000       5.813
    uut.u_xcorr.\\cnt_1_1_RNIDLTF\[0\]            System        INV      O       N_274_0                           0.000       5.813
    uut.u_xcorr.\\cnt_2_RNIUQOB\[0\]              System        INV      O       N_264_0                           0.000       5.813
    ut.cnt_r_RNO[2]                               System        INV      O       N_3_0                             0.000       5.813
    ================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                     Starting                                                Required
    Instance                         Reference     Type     Pin     Net                      Time         Slack
                                     Clock
    -----------------------------------------------------------------------------------------------------------
    uut.u_xcorr.x_1_ret_33_0         System        DFF      D       un1_x_112_0_cZ           6.348        3.774
    uut.u_xcorr.\\x_1_ret_0\[0\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.348        5.630
    uut.u_xcorr.\\x_1_ret_0\[1\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.348        5.630
    uut.u_xcorr.\\x_1_ret_0\[2\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.348        5.630
    uut.u_xcorr.\\x_1_ret_0\[3\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.348        5.630
    uut.u_xcorr.\\x_1_ret_0\[4\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.348        5.630
    uut.u_xcorr.\\x_1_ret_0\[5\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.348        5.630
    uut.u_xcorr.\\x_1_ret_0\[6\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.348        5.630
    uut.u_xcorr.\\x_1_ret_0\[7\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.348        5.630
    uut.u_xcorr.\\x_1_ret_0\[8\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.348        5.630
    ===========================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      6.409
        - Setup time:                            0.061
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         6.348

        - Propagation time:                      2.574
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 3.774

        Number of logic level(s):                9
        Starting point:                          uut.u_xcorr.un1_delay_21_cry_3_0_RNO_0_cZ / O
        Ending point:                            uut.u_xcorr.x_1_ret_33_0 / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            top|clk [rising] on pin CLK

    Instance / Net                                         Pin      Pin               Arrival     No. of
    Name                                          Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------
    uut.u_xcorr.un1_delay_21_cry_3_0_RNO_0_cZ     INV      O        Out     0.000     0.000       -
    un1_delay_21_cry_3_0_RNO_0_cZ                 Net      -        -       0.535     -           1
    uut.u_xcorr.un1_delay_21_cry_3_0              ALU      I3       In      -         0.535       -
    uut.u_xcorr.un1_delay_21_cry_3_0              ALU      COUT     Out     0.371     0.906       -
    un1_delay_21_cry_3_0_COUT                     Net      -        -       0.000     -           1
    uut.u_xcorr.un1_delay_21_cry_4_0              ALU      CIN      In      -         0.906       -
    uut.u_xcorr.un1_delay_21_cry_4_0              ALU      COUT     Out     0.035     0.941       -
    un1_delay_21_cry_4_0_COUT                     Net      -        -       0.000     -           1
    uut.u_xcorr.un1_delay_21_cry_5_0              ALU      CIN      In      -         0.941       -
    uut.u_xcorr.un1_delay_21_cry_5_0              ALU      COUT     Out     0.035     0.976       -
    un1_delay_21_cry_5_0_COUT                     Net      -        -       0.000     -           1
    uut.u_xcorr.un1_delay_21_cry_6_0              ALU      CIN      In      -         0.976       -
    uut.u_xcorr.un1_delay_21_cry_6_0              ALU      COUT     Out     0.035     1.011       -
    un1_delay_21_cry_6_0_COUT                     Net      -        -       0.000     -           1
    uut.u_xcorr.un1_delay_21_cry_7_0              ALU      CIN      In      -         1.011       -
    uut.u_xcorr.un1_delay_21_cry_7_0              ALU      COUT     Out     0.035     1.046       -
    un1_delay_21_cry_7_0_COUT                     Net      -        -       0.000     -           1
    uut.u_xcorr.un1_delay_21_cry_8_0              ALU      CIN      In      -         1.046       -
    uut.u_xcorr.un1_delay_21_cry_8_0              ALU      COUT     Out     0.035     1.081       -
    un1_delay_21_cry_8_0_COUT                     Net      -        -       0.000     -           1
    uut.u_xcorr.un1_delay_21_cry_9_0              ALU      CIN      In      -         1.081       -
    uut.u_xcorr.un1_delay_21_cry_9_0              ALU      COUT     Out     0.035     1.116       -
    un1_delay_21_cry_9_0_COUT                     Net      -        -       0.000     -           1
    uut.u_xcorr.un1_delay_21_cry_10_0             ALU      CIN      In      -         1.116       -
    uut.u_xcorr.un1_delay_21_cry_10_0             ALU      COUT     Out     0.035     1.151       -
    un1_delay_21_cry_10_0_COUT                    Net      -        -       0.961     -           1
    uut.u_xcorr.un1_x_112_0_cZ                    LUT4     I2       In      -         2.112       -
    uut.u_xcorr.un1_x_112_0_cZ                    LUT4     F        Out     0.462     2.574       -
    un1_x_112_0_cZ                                Net      -        -       0.000     -           1
    uut.u_xcorr.x_1_ret_33_0                      DFF      D        In      -         2.574       -
    ========================================================================================================
    Total path delay (propagation time + setup) of 2.635 is 1.139(43.2%) logic and 1.496(56.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 194MB peak: 197MB)

    Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 194MB peak: 197MB)

    ---------------------------------------
    Resource Usage Report for top

    Mapping to part: gw2a_55pbga484-8
    Cell usage:
    ALU             109 uses
    DFF             105 uses
    DFFE            34 uses
    DFFR            159 uses
    DFFRE           10 uses
    DFFS            2 uses
    GSR             1 use
    INV             10 uses
    MUX2_LUT5       4 uses
    MUX2_LUT6       2 uses
    ROM             2 uses
    SDPX9           4 uses
    LUT2            118 uses
    LUT3            187 uses
    LUT4            112 uses
    MULT18X18      1 use

    I/O ports: 82
    I/O primitives: 81
    IBUF           2 uses
    OBUF           79 uses

    I/O Register bits:                  0
    Register bits not including I/Os:   310 of 41040 (0%)

    RAM/ROM usage summary
    Block Rams : 6 of 140 (4%)

    Block Multipliers: 1 of 20 (5%)
    Total load per clock:
       top|clk: 320

    @S |Mapping Summary:
    Total  LUTs: 417 (0%)

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 41MB peak: 197MB)

    Process took 0h:00m:06s realtime, 0h:00m:06s cputime
    # Tue Dec 18 16:24:42 2018

    ###########################################################]

`