Selecting top level module top
@N: CG364 :"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/generic/gw2a.v":1597:7:1597:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on MUX2_LUT6 .......
Running optimization stage 1 on DFF .......
Running optimization stage 1 on DFFS .......
Running optimization stage 1 on DFFE .......
Running optimization stage 1 on DFFR .......
Running optimization stage 1 on DPX9 .......
Running optimization stage 1 on SDPX9 .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on MULT18X18 .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on \(crosscorrelation)/(XCORR_Top)_17s_1024s_1s .......
@N: CG364 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/xcorr/xcorr.v":6068:7:6068:15|Synthesizing module XCORR_Top in library work.
Running optimization stage 1 on XCORR_Top .......
@N: CG364 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/eliminate_shake.v":2:7:2:12|Synthesizing module deUstb in library work.
@N: CG179 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/eliminate_shake.v":12:23:12:27|Removing redundant assignment.
Running optimization stage 1 on deUstb .......
@N: CG364 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":2:7:2:9|Synthesizing module top in library work.
Opening data file o_x.dat from directory ../../../data
Opening data file o_y.dat from directory ../../../data
@W: CG532 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":37:0:37:6|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
@W: CG532 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":45:0:45:6|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
Running optimization stage 1 on top .......
Running optimization stage 2 on top .......
Running optimization stage 2 on deUstb .......
Running optimization stage 2 on XCORR_Top .......
@N: CL159 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/xcorr/xcorr.v":6091:6:6091:8|Input rst is unused.
Running optimization stage 2 on \(crosscorrelation)/(XCORR_Top)_17s_1024s_1s .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on MULT18X18 .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on SDPX9 .......
Running optimization stage 2 on DPX9 .......
Running optimization stage 2 on DFFR .......
Running optimization stage 2 on DFFE .......
Running optimization stage 2 on DFFS .......
Running optimization stage 2 on DFF .......
Running optimization stage 2 on MUX2_LUT6 .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
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@L: /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/synwork/layer0.rt.csv

