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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-048

Implementation : rev_1
Synopsys HDL compiler and linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

Modified Files: 8
FID:  path (prevtimestamp, timestamp)
0        C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v (N/A, 2019-02-13 03:01:50)
1        C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v (N/A, 2019-02-13 01:21:14)
2        C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v (N/A, 2019-02-13 01:21:14)
3        C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh (N/A, 2019-02-13 01:21:14)
4        C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v (N/A, 2019-02-13 01:21:14)
5        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\eliminate_shake.v (N/A, 2018-12-13 10:13:48)
6        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\top.v (N/A, 2018-12-18 11:29:39)
7        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\xcorr\xcorr.v (N/A, 2018-12-13 09:16:07)

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Modules that may have changed as a result of file changes: 4
MID:  lib.cell.view
0        work.XCORR_Top.verilog may have changed because the following files changed:
                        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\top.v (N/A, 2018-12-18 11:29:39) <-- (may instantiate this module)
                        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\xcorr\xcorr.v (N/A, 2018-12-13 09:16:07) <-- (module definition)
1        work.\(crosscorrelation)/(XCORR_Top)_17s_1024s_1s.verilog may have changed because the following files changed:
                        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\top.v (N/A, 2018-12-18 11:29:39) <-- (may instantiate this module)
                        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\xcorr\xcorr.v (N/A, 2018-12-13 09:16:07) <-- (module definition)
2        work.deUstb.verilog may have changed because the following files changed:
                        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\eliminate_shake.v (N/A, 2018-12-13 10:13:48) <-- (module definition)
                        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\top.v (N/A, 2018-12-18 11:29:39) <-- (may instantiate this module)
3        work.top.verilog may have changed because the following files changed:
                        F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\top.v (N/A, 2018-12-18 11:29:39) <-- (module definition)

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Unmodified files: 0
FID:  path (timestamp)

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Unchanged modules: 0
MID:  lib.cell.view
