@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1597:7:1597:9|Synthesizing module GSR in library work.
@N: CG364 :"F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_512-3_case\project\src\xcorr\xcorr.v":6895:7:6895:15|Synthesizing module XCORR_Top in library work.
@N: CG364 :"F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_512-3_case\project\src\eliminate_shake.v":2:7:2:12|Synthesizing module deUstb in library work.
@N: CG179 :"F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_512-3_case\project\src\eliminate_shake.v":12:23:12:27|Removing redundant assignment.
@N: CG364 :"F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_512-3_case\project\src\top.v":2:7:2:9|Synthesizing module top in library work.
@N: CL159 :"F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_512-3_case\project\src\xcorr\xcorr.v":6918:6:6918:8|Input rst is unused.
@N|Running in 64-bit mode

