library verilog;
use verilog.vl_types.all;
entity XCORR_Top is
    port(
        series_x        : in     vl_logic_vector(16 downto 0);
        series_y        : in     vl_logic_vector(16 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        start           : in     vl_logic;
        result          : out    vl_logic_vector(33 downto 0);
        complete        : out    vl_logic;
        delay           : out    vl_logic_vector(9 downto 0)
    );
end XCORR_Top;
