#Build: Synplify Pro (R) O-2018.09G-Beta3, Build 136R, Nov 19 2018
#install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
#OS: Linux 
#Hostname: jinan9110.sdgowin.com

# Thu Dec 13 13:40:52 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/generic/gw2a.v" (library work)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr_wrap.v" (library work)
@I:"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr_wrap.v":"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/define.v" (library work)
@I:"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr_wrap.v":"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/static_macro_define.v" (library work)
@I:"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr_wrap.v":"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/parameter.v" (library work)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr.v" (library work)
Verilog syntax check successful!
Selecting top level module XCORR_Top
Running optimization stage 1 on \(crosscorrelation)/(XCORR_Top)_17s_512s_3s .......
@N: CG364 :"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr_wrap.v":3:19:3:19|Synthesizing module XCORR_Top in library work.
Running optimization stage 1 on XCORR_Top .......
Running optimization stage 2 on XCORR_Top .......
Running optimization stage 2 on \(crosscorrelation)/(XCORR_Top)_17s_512s_3s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/rev_1/synwork/layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Dec 13 13:40:52 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

@N|Running in 64-bit mode
@N: NF107 :"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr_wrap.v":3:19:3:19|Selected library: work cell: XCORR_Top view verilog as top level
@N: NF107 :"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr_wrap.v":3:19:3:19|Selected library: work cell: XCORR_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Dec 13 13:40:52 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Dec 13 13:40:52 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com

Database state : /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/rev_1/synwork/|rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

@N|Running in 64-bit mode
@N: NF107 :"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr_wrap.v":3:19:3:19|Selected library: work cell: XCORR_Top view verilog as top level
@N: NF107 :"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr_wrap.v":3:19:3:19|Selected library: work cell: XCORR_Top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Dec 13 13:40:54 2018

###########################################################]
Premap Report

# Thu Dec 13 13:40:54 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1226R, Built Nov 21 2018 00:28:10


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/rev_1/xcorr_scck.rpt 
Printing clock  summary report in "/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/rev_1/xcorr_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.

Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)

@N: MF974 |Total number of latches (multibit) processed = 0 
@N: MF975 |Total number of latches (bit blasted) processed = 0 
@N: MF976 |Total number of (multibit) opaque latches found = 0 
@N: MF977 |Total number of (bit blasted) opaque latches found = 0 

Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)







Detailed report for transparent and observable latches in design:
@L: /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/rev_1/synwork/xcorr_prem_latch_transparency_report.log

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

syn_allowed_resources : blockrams=140,dsps=20  set on top level netlist XCORR_Top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)



Clock Summary
******************

          Start             Requested     Requested     Clock        Clock                     Clock
Level     Clock             Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------------
0 -       XCORR_Top|clk     219.8 MHz     4.549         inferred     Autoconstr_clkgroup_0     252  
====================================================================================================



Clock Load Summary
***********************

                  Clock     Source        Clock Pin                    Non-clock Pin     Non-clock Pin
Clock             Load      Pin           Seq Example                  Seq Example       Comb Example 
------------------------------------------------------------------------------------------------------
XCORR_Top|clk     252       clk(port)     u_xcorr.memr_1[33:0].CLK     -                 -            
======================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 155 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       clk                 Unconstrained_port     155        ENCRYPTED      
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/rev_1/xcorr.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 192MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 192MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 192MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 105MB peak: 192MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Dec 13 13:40:57 2018

###########################################################]
Map & Optimize Report

# Thu Dec 13 13:40:57 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1226R, Built Nov 21 2018 00:28:10


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

@N: MF284 |Setting synthesis effort to medium for the design


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled
@N: FX493 |Applying initial value "0" on instance u_xcorr.complete.
@N: FX493 |Applying initial value "0000000001" on instance u_xcorr.delay[9:0].
@N: FX493 |Applying initial value "0000000000000000000000000000000000" on instance u_xcorr.r_1[33:0].
@N: FX493 |Applying initial value "000000000" on instance u_xcorr.ad[8:0].
@N: FX493 |Applying initial value "0000000000000000000000000000000000" on instance u_xcorr.result[33:0].
@N: FX493 |Applying initial value "0000000000" on instance u_xcorr.delay_1[9:0].

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 192MB)

@N: FX493 |Applying initial value "00000000000000000" on instance x_1[16:0].
@N: FX493 |Applying initial value "0" on instance x_1_ret.
@N: FX493 |Applying initial value "0" on instance x_1_ret_0.
@N: FX493 |Applying initial value "0" on instance x_1_ret_1.
@N: FX493 |Applying initial value "0" on instance x_1_ret_2.
@N: FX493 |Applying initial value "0" on instance x_1_ret_3.
@N: FX493 |Applying initial value "0" on instance x_1_ret_4.
@N: FX493 |Applying initial value "0" on instance x_1_ret_5.
@N: FX493 |Applying initial value "0" on instance x_1_ret_6.
@N: FX493 |Applying initial value "0" on instance x_1_ret_7.
@N: FX493 |Applying initial value "0" on instance x_1_ret_8.
@N: FX493 |Applying initial value "0" on instance x_1_ret_9.
@N: FX493 |Applying initial value "0" on instance x_1_ret_10.
@N: FX493 |Applying initial value "0" on instance x_1_ret_11.
@N: FX493 |Applying initial value "0" on instance x_1_ret_12.
@N: FX493 |Applying initial value "0" on instance x_1_ret_13.
@N: FX493 |Applying initial value "0" on instance x_1_ret_14.
@N: FX493 |Applying initial value "0" on instance x_1_ret_15.
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[1].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[2].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[3].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[4].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[5].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[6].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[7].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[8].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[9].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[10].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[11].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[12].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[13].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[14].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[15].
@N: FX493 |Applying initial value "0" on instance x_1_ret_16[16].
@N: FX493 |Applying initial value "0" on instance x_1_ret_33.
@N: FX493 |Applying initial value "00000000000000000" on instance x_1_ret_16[16:0].
@N: FX493 |Applying initial value "0" on instance x_1_ret.
@N: FX493 |Applying initial value "0" on instance x_1_ret_0.
@N: FX493 |Applying initial value "1" on instance x_1_ret_1.
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[1].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[2].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[3].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[4].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[5].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[6].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[7].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[8].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[9].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[10].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[11].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[12].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[13].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[14].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[15].
@N: FX493 |Applying initial value "0" on instance x_1_ret_2[16].
@N: FX493 |Applying initial value "0" on instance x_1_ret_19.
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[1].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[2].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[3].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[4].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[5].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[6].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[7].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[8].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[9].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[10].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[11].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[12].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[13].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[14].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[15].
@N: FX493 |Applying initial value "0" on instance x_1_ret_20[16].
@N: FX493 |Applying initial value "00000000000000000" on instance y_1[16:0].
@N: FX493 |Applying initial value "0" on instance y_1_ret.
@N: FX493 |Applying initial value "0" on instance y_1_ret_0.
@N: FX493 |Applying initial value "0" on instance y_1_ret_1.
@N: FX493 |Applying initial value "0" on instance y_1_ret_2.
@N: FX493 |Applying initial value "0" on instance y_1_ret_3.
@N: FX493 |Applying initial value "0" on instance y_1_ret_4.
@N: FX493 |Applying initial value "0" on instance y_1_ret_5.
@N: FX493 |Applying initial value "0" on instance y_1_ret_6.
@N: FX493 |Applying initial value "0" on instance y_1_ret_7.
@N: FX493 |Applying initial value "0" on instance y_1_ret_8.
@N: FX493 |Applying initial value "0" on instance y_1_ret_9.
@N: FX493 |Applying initial value "0" on instance y_1_ret_10.
@N: FX493 |Applying initial value "0" on instance y_1_ret_11.
@N: FX493 |Applying initial value "0" on instance y_1_ret_12.
@N: FX493 |Applying initial value "0" on instance y_1_ret_13.
@N: FX493 |Applying initial value "0" on instance y_1_ret_14.
@N: FX493 |Applying initial value "0" on instance y_1_ret_15.
@N: FX493 |Applying initial value "0" on instance y_1_ret_16[1].
@N: FX493 |Applying initial value "0" on instance y_1_ret_16[2].
@N: FX493 |Applying initial value "0" on instance y_1_ret_16[3].
@N: FX493 |Applying initial value "0" on instance y_1_ret_16[4].

Only the first 100 messages of id 'FX493' are reported. To see all messages use 'report_messages -log /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/rev_1/synlog/xcorr_fpga_mapper.srr -id FX493' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {FX493} -count unlimited' in the Tcl shell.
@N: MF794 |RAM memy[33:0] required 53 registers during mapping 
@N: MF794 |RAM memr_1[33:0] required 53 registers during mapping 

Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 197MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 197MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 197MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 198MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 198MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 198MB)

@N: MF794 |RAM memy[33:0] required 52 registers during mapping 
@N: MF794 |RAM memr_1[33:0] required 52 registers during mapping 

Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 198MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 203MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -2.61ns		 443 /       291
   2		0h:00m:03s		    -2.61ns		 441 /       291
Timing driven replication report
Added 4 Registers via timing driven replication
Added 0 LUTs via timing driven replication

   3		0h:00m:03s		    -2.61ns		 441 /       295


   4		0h:00m:03s		    -2.61ns		 441 /       295

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 203MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB)


Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 130MB peak: 204MB)

Writing Analyst data base /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/src/xcorr/temp/XCORR/rev_1/synwork/xcorr_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 199MB peak: 204MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 200MB peak: 204MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 199MB peak: 204MB)


Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 200MB peak: 204MB)

@W: MT246 :"/share/gwsw/gui_proj/sw_test/Gowin/1.8/IDE/ipcore/XCORR/data/xcorr.v":119:15:119:24|Blackbox MULT18X18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock XCORR_Top|clk with period 6.41ns. Please declare a user-defined clock on port clk.


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Dec 13 13:41:05 2018
#


Top view:               XCORR_Top
Requested Frequency:    156.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -1.131

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
XCORR_Top|clk      156.0 MHz     132.6 MHz     6.409         7.540         -1.131     inferred     Autoconstr_clkgroup_0
System             150.0 MHz     345.7 MHz     6.667         2.893         3.774      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks                        |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------
Starting       Ending         |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------
System         XCORR_Top|clk  |  6.409       3.774   |  No paths    -      |  No paths    -      |  No paths    -    
XCORR_Top|clk  System         |  6.409       3.346   |  No paths    -      |  No paths    -      |  No paths    -    
XCORR_Top|clk  XCORR_Top|clk  |  6.409       -1.131  |  No paths    -      |  No paths    -      |  No paths    -    
=====================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: XCORR_Top|clk
====================================



Starting Points with Worst Slack
********************************

                                  Starting                                                   Arrival           
Instance                          Reference         Type     Pin     Net                     Time        Slack 
                                  Clock                                                                        
---------------------------------------------------------------------------------------------------------------
u_xcorr.memr_1_waddr_tmp_0[1]     XCORR_Top|clk     DFF      Q       memr_1_waddr_tmp[1]     0.243       -1.131
u_xcorr.memr_1_adreg[5]           XCORR_Top|clk     DFFR     Q       memr_1_adreg[5]         0.243       -1.110
u_xcorr.memr_1_waddr_tmp_0[2]     XCORR_Top|clk     DFF      Q       memr_1_waddr_tmp[2]     0.243       -1.023
u_xcorr.memr_1_waddr_tmp_0[5]     XCORR_Top|clk     DFF      Q       memr_1_waddr_tmp[5]     0.243       -0.932
u_xcorr.memr_1_adreg[4]           XCORR_Top|clk     DFFR     Q       memr_1_adreg[4]         0.243       -0.900
u_xcorr.memr_1_adreg[3]           XCORR_Top|clk     DFFR     Q       memr_1_adreg[3]         0.243       -0.879
u_xcorr.delay[7]                  XCORR_Top|clk     DFF      Q       delay[7]                0.243       -0.845
u_xcorr.delay[6]                  XCORR_Top|clk     DFF      Q       delay[6]                0.243       -0.824
u_xcorr.memr_1_adreg[8]           XCORR_Top|clk     DFFR     Q       memr_1_adreg[8]         0.243       -0.813
u_xcorr.delay[8]                  XCORR_Top|clk     DFF      Q       delay[8]                0.243       -0.798
===============================================================================================================


Ending Points with Worst Slack
******************************

                       Starting                                            Required           
Instance               Reference         Type     Pin     Net              Time         Slack 
                       Clock                                                                  
----------------------------------------------------------------------------------------------
u_xcorr.result[33]     XCORR_Top|clk     DFFR     D       N_19_0           6.348        -1.131
u_xcorr.result[32]     XCORR_Top|clk     DFFR     D       N_21_0           6.348        -1.096
u_xcorr.result[31]     XCORR_Top|clk     DFFR     D       N_23_0           6.348        -1.061
u_xcorr.result[30]     XCORR_Top|clk     DFFR     D       N_25_0           6.348        -1.026
u_xcorr.result[29]     XCORR_Top|clk     DFFR     D       N_27_0           6.348        -0.991
u_xcorr.result[28]     XCORR_Top|clk     DFFR     D       N_29_0           6.348        -0.956
u_xcorr.result[27]     XCORR_Top|clk     DFFR     D       N_31_0           6.348        -0.921
u_xcorr.result[26]     XCORR_Top|clk     DFFR     D       N_33_0           6.348        -0.886
u_xcorr.result[25]     XCORR_Top|clk     DFFR     D       N_35_0           6.348        -0.851
u_xcorr.delay_1[1]     XCORR_Top|clk     DFF      D       delay_1_0[1]     6.348        -0.845
==============================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      6.409
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.348

    - Propagation time:                      7.479
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.131

    Number of logic level(s):                39
    Starting point:                          u_xcorr.memr_1_waddr_tmp_0[1] / Q
    Ending point:                            u_xcorr.result[33] / D
    The start point is clocked by            XCORR_Top|clk [rising] on pin CLK
    The end   point is clocked by            XCORR_Top|clk [rising] on pin CLK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                               Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
u_xcorr.memr_1_waddr_tmp_0[1]      DFF           Q        Out     0.243     0.243       -         
memr_1_waddr_tmp[1]                Net           -        -       0.535     -           4         
u_xcorr.memr_1_G_1_1_3             LUT4          I1       In      -         0.778       -         
u_xcorr.memr_1_G_1_1_3             LUT4          F        Out     0.570     1.348       -         
memr_1_G_1_1_3                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_2             MUX2_LUT5     I0       In      -         1.348       -         
u_xcorr.memr_1_G_1_1_2             MUX2_LUT5     O        Out     0.105     1.453       -         
memr_1_G_1_1_2                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     I1       In      -         1.453       -         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     O        Out     0.105     1.558       -         
memr_1_G_1_1_0                     Net           -        -       0.535     -           3         
u_xcorr.memr_1_G_1                 LUT4          I1       In      -         2.093       -         
u_xcorr.memr_1_G_1                 LUT4          F        Out     0.570     2.663       -         
un2_result_s_0_sf_1                Net           -        -       0.718     -           33        
u_xcorr.un2_result_s_1_sf_lofx     LUT3          I2       In      -         3.381       -         
u_xcorr.un2_result_s_1_sf_lofx     LUT3          F        Out     0.462     3.843       -         
un2_result_s_1_sf_lofx             Net           -        -       0.535     -           1         
u_xcorr.un2_result_cry_1_0         ALU           I0       In      -         4.378       -         
u_xcorr.un2_result_cry_1_0         ALU           COUT     Out     0.549     4.927       -         
un2_result_cry_1                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_2_0         ALU           CIN      In      -         4.927       -         
u_xcorr.un2_result_cry_2_0         ALU           COUT     Out     0.035     4.962       -         
un2_result_cry_2                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_3_0         ALU           CIN      In      -         4.962       -         
u_xcorr.un2_result_cry_3_0         ALU           COUT     Out     0.035     4.997       -         
un2_result_cry_3                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_4_0         ALU           CIN      In      -         4.997       -         
u_xcorr.un2_result_cry_4_0         ALU           COUT     Out     0.035     5.032       -         
un2_result_cry_4                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_5_0         ALU           CIN      In      -         5.032       -         
u_xcorr.un2_result_cry_5_0         ALU           COUT     Out     0.035     5.067       -         
un2_result_cry_5                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_6_0         ALU           CIN      In      -         5.067       -         
u_xcorr.un2_result_cry_6_0         ALU           COUT     Out     0.035     5.102       -         
un2_result_cry_6                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_7_0         ALU           CIN      In      -         5.102       -         
u_xcorr.un2_result_cry_7_0         ALU           COUT     Out     0.035     5.137       -         
un2_result_cry_7                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_8_0         ALU           CIN      In      -         5.137       -         
u_xcorr.un2_result_cry_8_0         ALU           COUT     Out     0.035     5.172       -         
un2_result_cry_8                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_9_0         ALU           CIN      In      -         5.172       -         
u_xcorr.un2_result_cry_9_0         ALU           COUT     Out     0.035     5.207       -         
un2_result_cry_9                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_10_0        ALU           CIN      In      -         5.207       -         
u_xcorr.un2_result_cry_10_0        ALU           COUT     Out     0.035     5.242       -         
un2_result_cry_10                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_11_0        ALU           CIN      In      -         5.242       -         
u_xcorr.un2_result_cry_11_0        ALU           COUT     Out     0.035     5.277       -         
un2_result_cry_11                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_12_0        ALU           CIN      In      -         5.277       -         
u_xcorr.un2_result_cry_12_0        ALU           COUT     Out     0.035     5.312       -         
un2_result_cry_12                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_13_0        ALU           CIN      In      -         5.312       -         
u_xcorr.un2_result_cry_13_0        ALU           COUT     Out     0.035     5.347       -         
un2_result_cry_13                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_14_0        ALU           CIN      In      -         5.347       -         
u_xcorr.un2_result_cry_14_0        ALU           COUT     Out     0.035     5.382       -         
un2_result_cry_14                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_15_0        ALU           CIN      In      -         5.382       -         
u_xcorr.un2_result_cry_15_0        ALU           COUT     Out     0.035     5.417       -         
un2_result_cry_15                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_16_0        ALU           CIN      In      -         5.417       -         
u_xcorr.un2_result_cry_16_0        ALU           COUT     Out     0.035     5.452       -         
un2_result_cry_16                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_17_0        ALU           CIN      In      -         5.452       -         
u_xcorr.un2_result_cry_17_0        ALU           COUT     Out     0.035     5.487       -         
un2_result_cry_17                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_18_0        ALU           CIN      In      -         5.487       -         
u_xcorr.un2_result_cry_18_0        ALU           COUT     Out     0.035     5.522       -         
un2_result_cry_18                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_19_0        ALU           CIN      In      -         5.522       -         
u_xcorr.un2_result_cry_19_0        ALU           COUT     Out     0.035     5.557       -         
un2_result_cry_19                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_20_0        ALU           CIN      In      -         5.557       -         
u_xcorr.un2_result_cry_20_0        ALU           COUT     Out     0.035     5.592       -         
un2_result_cry_20                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_21_0        ALU           CIN      In      -         5.592       -         
u_xcorr.un2_result_cry_21_0        ALU           COUT     Out     0.035     5.627       -         
un2_result_cry_21                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_22_0        ALU           CIN      In      -         5.627       -         
u_xcorr.un2_result_cry_22_0        ALU           COUT     Out     0.035     5.662       -         
un2_result_cry_22                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_23_0        ALU           CIN      In      -         5.662       -         
u_xcorr.un2_result_cry_23_0        ALU           COUT     Out     0.035     5.697       -         
un2_result_cry_23                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_24_0        ALU           CIN      In      -         5.697       -         
u_xcorr.un2_result_cry_24_0        ALU           COUT     Out     0.035     5.732       -         
un2_result_cry_24                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_25_0        ALU           CIN      In      -         5.732       -         
u_xcorr.un2_result_cry_25_0        ALU           COUT     Out     0.035     5.767       -         
un2_result_cry_25                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_26_0        ALU           CIN      In      -         5.767       -         
u_xcorr.un2_result_cry_26_0        ALU           COUT     Out     0.035     5.802       -         
un2_result_cry_26                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_27_0        ALU           CIN      In      -         5.802       -         
u_xcorr.un2_result_cry_27_0        ALU           COUT     Out     0.035     5.837       -         
un2_result_cry_27                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_28_0        ALU           CIN      In      -         5.837       -         
u_xcorr.un2_result_cry_28_0        ALU           COUT     Out     0.035     5.872       -         
un2_result_cry_28                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_29_0        ALU           CIN      In      -         5.872       -         
u_xcorr.un2_result_cry_29_0        ALU           COUT     Out     0.035     5.907       -         
un2_result_cry_29                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_30_0        ALU           CIN      In      -         5.907       -         
u_xcorr.un2_result_cry_30_0        ALU           COUT     Out     0.035     5.942       -         
un2_result_cry_30                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_31_0        ALU           CIN      In      -         5.942       -         
u_xcorr.un2_result_cry_31_0        ALU           COUT     Out     0.035     5.977       -         
un2_result_cry_31                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_32_0        ALU           CIN      In      -         5.977       -         
u_xcorr.un2_result_cry_32_0        ALU           COUT     Out     0.035     6.012       -         
un2_result_cry_32                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_s_33_0          ALU           CIN      In      -         6.012       -         
u_xcorr.un2_result_s_33_0          ALU           SUM      Out     0.470     6.482       -         
un2_result_s_33_0_SUM              Net           -        -       0.535     -           1         
u_xcorr.result_0_0[33]             LUT3          I2       In      -         7.017       -         
u_xcorr.result_0_0[33]             LUT3          F        Out     0.462     7.479       -         
N_19_0                             Net           -        -       0.000     -           1         
u_xcorr.result[33]                 DFFR          D        In      -         7.479       -         
==================================================================================================
Total path delay (propagation time + setup) of 7.540 is 4.682(62.1%) logic and 2.858(37.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.409
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.348

    - Propagation time:                      7.479
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.131

    Number of logic level(s):                39
    Starting point:                          u_xcorr.memr_1_waddr_tmp_0[1] / Q
    Ending point:                            u_xcorr.result[33] / D
    The start point is clocked by            XCORR_Top|clk [rising] on pin CLK
    The end   point is clocked by            XCORR_Top|clk [rising] on pin CLK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                               Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
u_xcorr.memr_1_waddr_tmp_0[1]      DFF           Q        Out     0.243     0.243       -         
memr_1_waddr_tmp[1]                Net           -        -       0.535     -           4         
u_xcorr.memr_1_G_1_1_6             LUT4          I1       In      -         0.778       -         
u_xcorr.memr_1_G_1_1_6             LUT4          F        Out     0.570     1.348       -         
memr_1_G_1_1_6                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_1             MUX2_LUT5     I1       In      -         1.348       -         
u_xcorr.memr_1_G_1_1_1             MUX2_LUT5     O        Out     0.105     1.453       -         
memr_1_G_1_1_1                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     I0       In      -         1.453       -         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     O        Out     0.105     1.558       -         
memr_1_G_1_1_0                     Net           -        -       0.535     -           3         
u_xcorr.memr_1_G_1                 LUT4          I1       In      -         2.093       -         
u_xcorr.memr_1_G_1                 LUT4          F        Out     0.570     2.663       -         
un2_result_s_0_sf_1                Net           -        -       0.718     -           33        
u_xcorr.un2_result_s_1_sf_lofx     LUT3          I2       In      -         3.381       -         
u_xcorr.un2_result_s_1_sf_lofx     LUT3          F        Out     0.462     3.843       -         
un2_result_s_1_sf_lofx             Net           -        -       0.535     -           1         
u_xcorr.un2_result_cry_1_0         ALU           I0       In      -         4.378       -         
u_xcorr.un2_result_cry_1_0         ALU           COUT     Out     0.549     4.927       -         
un2_result_cry_1                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_2_0         ALU           CIN      In      -         4.927       -         
u_xcorr.un2_result_cry_2_0         ALU           COUT     Out     0.035     4.962       -         
un2_result_cry_2                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_3_0         ALU           CIN      In      -         4.962       -         
u_xcorr.un2_result_cry_3_0         ALU           COUT     Out     0.035     4.997       -         
un2_result_cry_3                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_4_0         ALU           CIN      In      -         4.997       -         
u_xcorr.un2_result_cry_4_0         ALU           COUT     Out     0.035     5.032       -         
un2_result_cry_4                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_5_0         ALU           CIN      In      -         5.032       -         
u_xcorr.un2_result_cry_5_0         ALU           COUT     Out     0.035     5.067       -         
un2_result_cry_5                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_6_0         ALU           CIN      In      -         5.067       -         
u_xcorr.un2_result_cry_6_0         ALU           COUT     Out     0.035     5.102       -         
un2_result_cry_6                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_7_0         ALU           CIN      In      -         5.102       -         
u_xcorr.un2_result_cry_7_0         ALU           COUT     Out     0.035     5.137       -         
un2_result_cry_7                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_8_0         ALU           CIN      In      -         5.137       -         
u_xcorr.un2_result_cry_8_0         ALU           COUT     Out     0.035     5.172       -         
un2_result_cry_8                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_9_0         ALU           CIN      In      -         5.172       -         
u_xcorr.un2_result_cry_9_0         ALU           COUT     Out     0.035     5.207       -         
un2_result_cry_9                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_10_0        ALU           CIN      In      -         5.207       -         
u_xcorr.un2_result_cry_10_0        ALU           COUT     Out     0.035     5.242       -         
un2_result_cry_10                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_11_0        ALU           CIN      In      -         5.242       -         
u_xcorr.un2_result_cry_11_0        ALU           COUT     Out     0.035     5.277       -         
un2_result_cry_11                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_12_0        ALU           CIN      In      -         5.277       -         
u_xcorr.un2_result_cry_12_0        ALU           COUT     Out     0.035     5.312       -         
un2_result_cry_12                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_13_0        ALU           CIN      In      -         5.312       -         
u_xcorr.un2_result_cry_13_0        ALU           COUT     Out     0.035     5.347       -         
un2_result_cry_13                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_14_0        ALU           CIN      In      -         5.347       -         
u_xcorr.un2_result_cry_14_0        ALU           COUT     Out     0.035     5.382       -         
un2_result_cry_14                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_15_0        ALU           CIN      In      -         5.382       -         
u_xcorr.un2_result_cry_15_0        ALU           COUT     Out     0.035     5.417       -         
un2_result_cry_15                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_16_0        ALU           CIN      In      -         5.417       -         
u_xcorr.un2_result_cry_16_0        ALU           COUT     Out     0.035     5.452       -         
un2_result_cry_16                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_17_0        ALU           CIN      In      -         5.452       -         
u_xcorr.un2_result_cry_17_0        ALU           COUT     Out     0.035     5.487       -         
un2_result_cry_17                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_18_0        ALU           CIN      In      -         5.487       -         
u_xcorr.un2_result_cry_18_0        ALU           COUT     Out     0.035     5.522       -         
un2_result_cry_18                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_19_0        ALU           CIN      In      -         5.522       -         
u_xcorr.un2_result_cry_19_0        ALU           COUT     Out     0.035     5.557       -         
un2_result_cry_19                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_20_0        ALU           CIN      In      -         5.557       -         
u_xcorr.un2_result_cry_20_0        ALU           COUT     Out     0.035     5.592       -         
un2_result_cry_20                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_21_0        ALU           CIN      In      -         5.592       -         
u_xcorr.un2_result_cry_21_0        ALU           COUT     Out     0.035     5.627       -         
un2_result_cry_21                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_22_0        ALU           CIN      In      -         5.627       -         
u_xcorr.un2_result_cry_22_0        ALU           COUT     Out     0.035     5.662       -         
un2_result_cry_22                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_23_0        ALU           CIN      In      -         5.662       -         
u_xcorr.un2_result_cry_23_0        ALU           COUT     Out     0.035     5.697       -         
un2_result_cry_23                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_24_0        ALU           CIN      In      -         5.697       -         
u_xcorr.un2_result_cry_24_0        ALU           COUT     Out     0.035     5.732       -         
un2_result_cry_24                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_25_0        ALU           CIN      In      -         5.732       -         
u_xcorr.un2_result_cry_25_0        ALU           COUT     Out     0.035     5.767       -         
un2_result_cry_25                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_26_0        ALU           CIN      In      -         5.767       -         
u_xcorr.un2_result_cry_26_0        ALU           COUT     Out     0.035     5.802       -         
un2_result_cry_26                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_27_0        ALU           CIN      In      -         5.802       -         
u_xcorr.un2_result_cry_27_0        ALU           COUT     Out     0.035     5.837       -         
un2_result_cry_27                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_28_0        ALU           CIN      In      -         5.837       -         
u_xcorr.un2_result_cry_28_0        ALU           COUT     Out     0.035     5.872       -         
un2_result_cry_28                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_29_0        ALU           CIN      In      -         5.872       -         
u_xcorr.un2_result_cry_29_0        ALU           COUT     Out     0.035     5.907       -         
un2_result_cry_29                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_30_0        ALU           CIN      In      -         5.907       -         
u_xcorr.un2_result_cry_30_0        ALU           COUT     Out     0.035     5.942       -         
un2_result_cry_30                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_31_0        ALU           CIN      In      -         5.942       -         
u_xcorr.un2_result_cry_31_0        ALU           COUT     Out     0.035     5.977       -         
un2_result_cry_31                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_32_0        ALU           CIN      In      -         5.977       -         
u_xcorr.un2_result_cry_32_0        ALU           COUT     Out     0.035     6.012       -         
un2_result_cry_32                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_s_33_0          ALU           CIN      In      -         6.012       -         
u_xcorr.un2_result_s_33_0          ALU           SUM      Out     0.470     6.482       -         
un2_result_s_33_0_SUM              Net           -        -       0.535     -           1         
u_xcorr.result_0_0[33]             LUT3          I2       In      -         7.017       -         
u_xcorr.result_0_0[33]             LUT3          F        Out     0.462     7.479       -         
N_19_0                             Net           -        -       0.000     -           1         
u_xcorr.result[33]                 DFFR          D        In      -         7.479       -         
==================================================================================================
Total path delay (propagation time + setup) of 7.540 is 4.682(62.1%) logic and 2.858(37.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.409
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.348

    - Propagation time:                      7.479
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.131

    Number of logic level(s):                39
    Starting point:                          u_xcorr.memr_1_waddr_tmp_0[1] / Q
    Ending point:                            u_xcorr.result[33] / D
    The start point is clocked by            XCORR_Top|clk [rising] on pin CLK
    The end   point is clocked by            XCORR_Top|clk [rising] on pin CLK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                               Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
u_xcorr.memr_1_waddr_tmp_0[1]      DFF           Q        Out     0.243     0.243       -         
memr_1_waddr_tmp[1]                Net           -        -       0.535     -           4         
u_xcorr.memr_1_G_1_1_5             LUT4          I1       In      -         0.778       -         
u_xcorr.memr_1_G_1_1_5             LUT4          F        Out     0.570     1.348       -         
memr_1_G_1_1_5                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_1             MUX2_LUT5     I0       In      -         1.348       -         
u_xcorr.memr_1_G_1_1_1             MUX2_LUT5     O        Out     0.105     1.453       -         
memr_1_G_1_1_1                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     I0       In      -         1.453       -         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     O        Out     0.105     1.558       -         
memr_1_G_1_1_0                     Net           -        -       0.535     -           3         
u_xcorr.memr_1_G_1                 LUT4          I1       In      -         2.093       -         
u_xcorr.memr_1_G_1                 LUT4          F        Out     0.570     2.663       -         
un2_result_s_0_sf_1                Net           -        -       0.718     -           33        
u_xcorr.un2_result_s_1_sf_lofx     LUT3          I2       In      -         3.381       -         
u_xcorr.un2_result_s_1_sf_lofx     LUT3          F        Out     0.462     3.843       -         
un2_result_s_1_sf_lofx             Net           -        -       0.535     -           1         
u_xcorr.un2_result_cry_1_0         ALU           I0       In      -         4.378       -         
u_xcorr.un2_result_cry_1_0         ALU           COUT     Out     0.549     4.927       -         
un2_result_cry_1                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_2_0         ALU           CIN      In      -         4.927       -         
u_xcorr.un2_result_cry_2_0         ALU           COUT     Out     0.035     4.962       -         
un2_result_cry_2                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_3_0         ALU           CIN      In      -         4.962       -         
u_xcorr.un2_result_cry_3_0         ALU           COUT     Out     0.035     4.997       -         
un2_result_cry_3                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_4_0         ALU           CIN      In      -         4.997       -         
u_xcorr.un2_result_cry_4_0         ALU           COUT     Out     0.035     5.032       -         
un2_result_cry_4                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_5_0         ALU           CIN      In      -         5.032       -         
u_xcorr.un2_result_cry_5_0         ALU           COUT     Out     0.035     5.067       -         
un2_result_cry_5                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_6_0         ALU           CIN      In      -         5.067       -         
u_xcorr.un2_result_cry_6_0         ALU           COUT     Out     0.035     5.102       -         
un2_result_cry_6                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_7_0         ALU           CIN      In      -         5.102       -         
u_xcorr.un2_result_cry_7_0         ALU           COUT     Out     0.035     5.137       -         
un2_result_cry_7                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_8_0         ALU           CIN      In      -         5.137       -         
u_xcorr.un2_result_cry_8_0         ALU           COUT     Out     0.035     5.172       -         
un2_result_cry_8                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_9_0         ALU           CIN      In      -         5.172       -         
u_xcorr.un2_result_cry_9_0         ALU           COUT     Out     0.035     5.207       -         
un2_result_cry_9                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_10_0        ALU           CIN      In      -         5.207       -         
u_xcorr.un2_result_cry_10_0        ALU           COUT     Out     0.035     5.242       -         
un2_result_cry_10                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_11_0        ALU           CIN      In      -         5.242       -         
u_xcorr.un2_result_cry_11_0        ALU           COUT     Out     0.035     5.277       -         
un2_result_cry_11                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_12_0        ALU           CIN      In      -         5.277       -         
u_xcorr.un2_result_cry_12_0        ALU           COUT     Out     0.035     5.312       -         
un2_result_cry_12                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_13_0        ALU           CIN      In      -         5.312       -         
u_xcorr.un2_result_cry_13_0        ALU           COUT     Out     0.035     5.347       -         
un2_result_cry_13                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_14_0        ALU           CIN      In      -         5.347       -         
u_xcorr.un2_result_cry_14_0        ALU           COUT     Out     0.035     5.382       -         
un2_result_cry_14                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_15_0        ALU           CIN      In      -         5.382       -         
u_xcorr.un2_result_cry_15_0        ALU           COUT     Out     0.035     5.417       -         
un2_result_cry_15                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_16_0        ALU           CIN      In      -         5.417       -         
u_xcorr.un2_result_cry_16_0        ALU           COUT     Out     0.035     5.452       -         
un2_result_cry_16                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_17_0        ALU           CIN      In      -         5.452       -         
u_xcorr.un2_result_cry_17_0        ALU           COUT     Out     0.035     5.487       -         
un2_result_cry_17                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_18_0        ALU           CIN      In      -         5.487       -         
u_xcorr.un2_result_cry_18_0        ALU           COUT     Out     0.035     5.522       -         
un2_result_cry_18                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_19_0        ALU           CIN      In      -         5.522       -         
u_xcorr.un2_result_cry_19_0        ALU           COUT     Out     0.035     5.557       -         
un2_result_cry_19                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_20_0        ALU           CIN      In      -         5.557       -         
u_xcorr.un2_result_cry_20_0        ALU           COUT     Out     0.035     5.592       -         
un2_result_cry_20                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_21_0        ALU           CIN      In      -         5.592       -         
u_xcorr.un2_result_cry_21_0        ALU           COUT     Out     0.035     5.627       -         
un2_result_cry_21                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_22_0        ALU           CIN      In      -         5.627       -         
u_xcorr.un2_result_cry_22_0        ALU           COUT     Out     0.035     5.662       -         
un2_result_cry_22                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_23_0        ALU           CIN      In      -         5.662       -         
u_xcorr.un2_result_cry_23_0        ALU           COUT     Out     0.035     5.697       -         
un2_result_cry_23                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_24_0        ALU           CIN      In      -         5.697       -         
u_xcorr.un2_result_cry_24_0        ALU           COUT     Out     0.035     5.732       -         
un2_result_cry_24                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_25_0        ALU           CIN      In      -         5.732       -         
u_xcorr.un2_result_cry_25_0        ALU           COUT     Out     0.035     5.767       -         
un2_result_cry_25                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_26_0        ALU           CIN      In      -         5.767       -         
u_xcorr.un2_result_cry_26_0        ALU           COUT     Out     0.035     5.802       -         
un2_result_cry_26                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_27_0        ALU           CIN      In      -         5.802       -         
u_xcorr.un2_result_cry_27_0        ALU           COUT     Out     0.035     5.837       -         
un2_result_cry_27                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_28_0        ALU           CIN      In      -         5.837       -         
u_xcorr.un2_result_cry_28_0        ALU           COUT     Out     0.035     5.872       -         
un2_result_cry_28                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_29_0        ALU           CIN      In      -         5.872       -         
u_xcorr.un2_result_cry_29_0        ALU           COUT     Out     0.035     5.907       -         
un2_result_cry_29                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_30_0        ALU           CIN      In      -         5.907       -         
u_xcorr.un2_result_cry_30_0        ALU           COUT     Out     0.035     5.942       -         
un2_result_cry_30                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_31_0        ALU           CIN      In      -         5.942       -         
u_xcorr.un2_result_cry_31_0        ALU           COUT     Out     0.035     5.977       -         
un2_result_cry_31                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_32_0        ALU           CIN      In      -         5.977       -         
u_xcorr.un2_result_cry_32_0        ALU           COUT     Out     0.035     6.012       -         
un2_result_cry_32                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_s_33_0          ALU           CIN      In      -         6.012       -         
u_xcorr.un2_result_s_33_0          ALU           SUM      Out     0.470     6.482       -         
un2_result_s_33_0_SUM              Net           -        -       0.535     -           1         
u_xcorr.result_0_0[33]             LUT3          I2       In      -         7.017       -         
u_xcorr.result_0_0[33]             LUT3          F        Out     0.462     7.479       -         
N_19_0                             Net           -        -       0.000     -           1         
u_xcorr.result[33]                 DFFR          D        In      -         7.479       -         
==================================================================================================
Total path delay (propagation time + setup) of 7.540 is 4.682(62.1%) logic and 2.858(37.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.409
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.348

    - Propagation time:                      7.479
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.131

    Number of logic level(s):                39
    Starting point:                          u_xcorr.memr_1_waddr_tmp_0[1] / Q
    Ending point:                            u_xcorr.result[33] / D
    The start point is clocked by            XCORR_Top|clk [rising] on pin CLK
    The end   point is clocked by            XCORR_Top|clk [rising] on pin CLK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                               Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
u_xcorr.memr_1_waddr_tmp_0[1]      DFF           Q        Out     0.243     0.243       -         
memr_1_waddr_tmp[1]                Net           -        -       0.535     -           4         
u_xcorr.memr_1_G_1_1_4             LUT4          I1       In      -         0.778       -         
u_xcorr.memr_1_G_1_1_4             LUT4          F        Out     0.570     1.348       -         
memr_1_G_1_1_4                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_2             MUX2_LUT5     I1       In      -         1.348       -         
u_xcorr.memr_1_G_1_1_2             MUX2_LUT5     O        Out     0.105     1.453       -         
memr_1_G_1_1_2                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     I1       In      -         1.453       -         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     O        Out     0.105     1.558       -         
memr_1_G_1_1_0                     Net           -        -       0.535     -           3         
u_xcorr.memr_1_G_1                 LUT4          I1       In      -         2.093       -         
u_xcorr.memr_1_G_1                 LUT4          F        Out     0.570     2.663       -         
un2_result_s_0_sf_1                Net           -        -       0.718     -           33        
u_xcorr.un2_result_s_1_sf_lofx     LUT3          I2       In      -         3.381       -         
u_xcorr.un2_result_s_1_sf_lofx     LUT3          F        Out     0.462     3.843       -         
un2_result_s_1_sf_lofx             Net           -        -       0.535     -           1         
u_xcorr.un2_result_cry_1_0         ALU           I0       In      -         4.378       -         
u_xcorr.un2_result_cry_1_0         ALU           COUT     Out     0.549     4.927       -         
un2_result_cry_1                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_2_0         ALU           CIN      In      -         4.927       -         
u_xcorr.un2_result_cry_2_0         ALU           COUT     Out     0.035     4.962       -         
un2_result_cry_2                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_3_0         ALU           CIN      In      -         4.962       -         
u_xcorr.un2_result_cry_3_0         ALU           COUT     Out     0.035     4.997       -         
un2_result_cry_3                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_4_0         ALU           CIN      In      -         4.997       -         
u_xcorr.un2_result_cry_4_0         ALU           COUT     Out     0.035     5.032       -         
un2_result_cry_4                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_5_0         ALU           CIN      In      -         5.032       -         
u_xcorr.un2_result_cry_5_0         ALU           COUT     Out     0.035     5.067       -         
un2_result_cry_5                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_6_0         ALU           CIN      In      -         5.067       -         
u_xcorr.un2_result_cry_6_0         ALU           COUT     Out     0.035     5.102       -         
un2_result_cry_6                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_7_0         ALU           CIN      In      -         5.102       -         
u_xcorr.un2_result_cry_7_0         ALU           COUT     Out     0.035     5.137       -         
un2_result_cry_7                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_8_0         ALU           CIN      In      -         5.137       -         
u_xcorr.un2_result_cry_8_0         ALU           COUT     Out     0.035     5.172       -         
un2_result_cry_8                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_9_0         ALU           CIN      In      -         5.172       -         
u_xcorr.un2_result_cry_9_0         ALU           COUT     Out     0.035     5.207       -         
un2_result_cry_9                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_10_0        ALU           CIN      In      -         5.207       -         
u_xcorr.un2_result_cry_10_0        ALU           COUT     Out     0.035     5.242       -         
un2_result_cry_10                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_11_0        ALU           CIN      In      -         5.242       -         
u_xcorr.un2_result_cry_11_0        ALU           COUT     Out     0.035     5.277       -         
un2_result_cry_11                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_12_0        ALU           CIN      In      -         5.277       -         
u_xcorr.un2_result_cry_12_0        ALU           COUT     Out     0.035     5.312       -         
un2_result_cry_12                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_13_0        ALU           CIN      In      -         5.312       -         
u_xcorr.un2_result_cry_13_0        ALU           COUT     Out     0.035     5.347       -         
un2_result_cry_13                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_14_0        ALU           CIN      In      -         5.347       -         
u_xcorr.un2_result_cry_14_0        ALU           COUT     Out     0.035     5.382       -         
un2_result_cry_14                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_15_0        ALU           CIN      In      -         5.382       -         
u_xcorr.un2_result_cry_15_0        ALU           COUT     Out     0.035     5.417       -         
un2_result_cry_15                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_16_0        ALU           CIN      In      -         5.417       -         
u_xcorr.un2_result_cry_16_0        ALU           COUT     Out     0.035     5.452       -         
un2_result_cry_16                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_17_0        ALU           CIN      In      -         5.452       -         
u_xcorr.un2_result_cry_17_0        ALU           COUT     Out     0.035     5.487       -         
un2_result_cry_17                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_18_0        ALU           CIN      In      -         5.487       -         
u_xcorr.un2_result_cry_18_0        ALU           COUT     Out     0.035     5.522       -         
un2_result_cry_18                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_19_0        ALU           CIN      In      -         5.522       -         
u_xcorr.un2_result_cry_19_0        ALU           COUT     Out     0.035     5.557       -         
un2_result_cry_19                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_20_0        ALU           CIN      In      -         5.557       -         
u_xcorr.un2_result_cry_20_0        ALU           COUT     Out     0.035     5.592       -         
un2_result_cry_20                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_21_0        ALU           CIN      In      -         5.592       -         
u_xcorr.un2_result_cry_21_0        ALU           COUT     Out     0.035     5.627       -         
un2_result_cry_21                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_22_0        ALU           CIN      In      -         5.627       -         
u_xcorr.un2_result_cry_22_0        ALU           COUT     Out     0.035     5.662       -         
un2_result_cry_22                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_23_0        ALU           CIN      In      -         5.662       -         
u_xcorr.un2_result_cry_23_0        ALU           COUT     Out     0.035     5.697       -         
un2_result_cry_23                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_24_0        ALU           CIN      In      -         5.697       -         
u_xcorr.un2_result_cry_24_0        ALU           COUT     Out     0.035     5.732       -         
un2_result_cry_24                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_25_0        ALU           CIN      In      -         5.732       -         
u_xcorr.un2_result_cry_25_0        ALU           COUT     Out     0.035     5.767       -         
un2_result_cry_25                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_26_0        ALU           CIN      In      -         5.767       -         
u_xcorr.un2_result_cry_26_0        ALU           COUT     Out     0.035     5.802       -         
un2_result_cry_26                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_27_0        ALU           CIN      In      -         5.802       -         
u_xcorr.un2_result_cry_27_0        ALU           COUT     Out     0.035     5.837       -         
un2_result_cry_27                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_28_0        ALU           CIN      In      -         5.837       -         
u_xcorr.un2_result_cry_28_0        ALU           COUT     Out     0.035     5.872       -         
un2_result_cry_28                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_29_0        ALU           CIN      In      -         5.872       -         
u_xcorr.un2_result_cry_29_0        ALU           COUT     Out     0.035     5.907       -         
un2_result_cry_29                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_30_0        ALU           CIN      In      -         5.907       -         
u_xcorr.un2_result_cry_30_0        ALU           COUT     Out     0.035     5.942       -         
un2_result_cry_30                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_31_0        ALU           CIN      In      -         5.942       -         
u_xcorr.un2_result_cry_31_0        ALU           COUT     Out     0.035     5.977       -         
un2_result_cry_31                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_32_0        ALU           CIN      In      -         5.977       -         
u_xcorr.un2_result_cry_32_0        ALU           COUT     Out     0.035     6.012       -         
un2_result_cry_32                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_s_33_0          ALU           CIN      In      -         6.012       -         
u_xcorr.un2_result_s_33_0          ALU           SUM      Out     0.470     6.482       -         
un2_result_s_33_0_SUM              Net           -        -       0.535     -           1         
u_xcorr.result_0_0[33]             LUT3          I2       In      -         7.017       -         
u_xcorr.result_0_0[33]             LUT3          F        Out     0.462     7.479       -         
N_19_0                             Net           -        -       0.000     -           1         
u_xcorr.result[33]                 DFFR          D        In      -         7.479       -         
==================================================================================================
Total path delay (propagation time + setup) of 7.540 is 4.682(62.1%) logic and 2.858(37.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.409
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.348

    - Propagation time:                      7.458
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.110

    Number of logic level(s):                39
    Starting point:                          u_xcorr.memr_1_adreg[5] / Q
    Ending point:                            u_xcorr.result[33] / D
    The start point is clocked by            XCORR_Top|clk [rising] on pin CLK
    The end   point is clocked by            XCORR_Top|clk [rising] on pin CLK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                               Type          Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
u_xcorr.memr_1_adreg[5]            DFFR          Q        Out     0.243     0.243       -         
memr_1_adreg[5]                    Net           -        -       0.535     -           6         
u_xcorr.memr_1_G_1_1_3             LUT4          I0       In      -         0.778       -         
u_xcorr.memr_1_G_1_1_3             LUT4          F        Out     0.549     1.327       -         
memr_1_G_1_1_3                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_2             MUX2_LUT5     I0       In      -         1.327       -         
u_xcorr.memr_1_G_1_1_2             MUX2_LUT5     O        Out     0.105     1.432       -         
memr_1_G_1_1_2                     Net           -        -       0.000     -           1         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     I1       In      -         1.432       -         
u_xcorr.memr_1_G_1_1_0             MUX2_LUT6     O        Out     0.105     1.537       -         
memr_1_G_1_1_0                     Net           -        -       0.535     -           3         
u_xcorr.memr_1_G_1                 LUT4          I1       In      -         2.072       -         
u_xcorr.memr_1_G_1                 LUT4          F        Out     0.570     2.642       -         
un2_result_s_0_sf_1                Net           -        -       0.718     -           33        
u_xcorr.un2_result_s_1_sf_lofx     LUT3          I2       In      -         3.360       -         
u_xcorr.un2_result_s_1_sf_lofx     LUT3          F        Out     0.462     3.822       -         
un2_result_s_1_sf_lofx             Net           -        -       0.535     -           1         
u_xcorr.un2_result_cry_1_0         ALU           I0       In      -         4.357       -         
u_xcorr.un2_result_cry_1_0         ALU           COUT     Out     0.549     4.906       -         
un2_result_cry_1                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_2_0         ALU           CIN      In      -         4.906       -         
u_xcorr.un2_result_cry_2_0         ALU           COUT     Out     0.035     4.941       -         
un2_result_cry_2                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_3_0         ALU           CIN      In      -         4.941       -         
u_xcorr.un2_result_cry_3_0         ALU           COUT     Out     0.035     4.976       -         
un2_result_cry_3                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_4_0         ALU           CIN      In      -         4.976       -         
u_xcorr.un2_result_cry_4_0         ALU           COUT     Out     0.035     5.011       -         
un2_result_cry_4                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_5_0         ALU           CIN      In      -         5.011       -         
u_xcorr.un2_result_cry_5_0         ALU           COUT     Out     0.035     5.046       -         
un2_result_cry_5                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_6_0         ALU           CIN      In      -         5.046       -         
u_xcorr.un2_result_cry_6_0         ALU           COUT     Out     0.035     5.081       -         
un2_result_cry_6                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_7_0         ALU           CIN      In      -         5.081       -         
u_xcorr.un2_result_cry_7_0         ALU           COUT     Out     0.035     5.116       -         
un2_result_cry_7                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_8_0         ALU           CIN      In      -         5.116       -         
u_xcorr.un2_result_cry_8_0         ALU           COUT     Out     0.035     5.151       -         
un2_result_cry_8                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_9_0         ALU           CIN      In      -         5.151       -         
u_xcorr.un2_result_cry_9_0         ALU           COUT     Out     0.035     5.186       -         
un2_result_cry_9                   Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_10_0        ALU           CIN      In      -         5.186       -         
u_xcorr.un2_result_cry_10_0        ALU           COUT     Out     0.035     5.221       -         
un2_result_cry_10                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_11_0        ALU           CIN      In      -         5.221       -         
u_xcorr.un2_result_cry_11_0        ALU           COUT     Out     0.035     5.256       -         
un2_result_cry_11                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_12_0        ALU           CIN      In      -         5.256       -         
u_xcorr.un2_result_cry_12_0        ALU           COUT     Out     0.035     5.291       -         
un2_result_cry_12                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_13_0        ALU           CIN      In      -         5.291       -         
u_xcorr.un2_result_cry_13_0        ALU           COUT     Out     0.035     5.326       -         
un2_result_cry_13                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_14_0        ALU           CIN      In      -         5.326       -         
u_xcorr.un2_result_cry_14_0        ALU           COUT     Out     0.035     5.361       -         
un2_result_cry_14                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_15_0        ALU           CIN      In      -         5.361       -         
u_xcorr.un2_result_cry_15_0        ALU           COUT     Out     0.035     5.396       -         
un2_result_cry_15                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_16_0        ALU           CIN      In      -         5.396       -         
u_xcorr.un2_result_cry_16_0        ALU           COUT     Out     0.035     5.431       -         
un2_result_cry_16                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_17_0        ALU           CIN      In      -         5.431       -         
u_xcorr.un2_result_cry_17_0        ALU           COUT     Out     0.035     5.466       -         
un2_result_cry_17                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_18_0        ALU           CIN      In      -         5.466       -         
u_xcorr.un2_result_cry_18_0        ALU           COUT     Out     0.035     5.501       -         
un2_result_cry_18                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_19_0        ALU           CIN      In      -         5.501       -         
u_xcorr.un2_result_cry_19_0        ALU           COUT     Out     0.035     5.536       -         
un2_result_cry_19                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_20_0        ALU           CIN      In      -         5.536       -         
u_xcorr.un2_result_cry_20_0        ALU           COUT     Out     0.035     5.571       -         
un2_result_cry_20                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_21_0        ALU           CIN      In      -         5.571       -         
u_xcorr.un2_result_cry_21_0        ALU           COUT     Out     0.035     5.606       -         
un2_result_cry_21                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_22_0        ALU           CIN      In      -         5.606       -         
u_xcorr.un2_result_cry_22_0        ALU           COUT     Out     0.035     5.641       -         
un2_result_cry_22                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_23_0        ALU           CIN      In      -         5.641       -         
u_xcorr.un2_result_cry_23_0        ALU           COUT     Out     0.035     5.676       -         
un2_result_cry_23                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_24_0        ALU           CIN      In      -         5.676       -         
u_xcorr.un2_result_cry_24_0        ALU           COUT     Out     0.035     5.711       -         
un2_result_cry_24                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_25_0        ALU           CIN      In      -         5.711       -         
u_xcorr.un2_result_cry_25_0        ALU           COUT     Out     0.035     5.746       -         
un2_result_cry_25                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_26_0        ALU           CIN      In      -         5.746       -         
u_xcorr.un2_result_cry_26_0        ALU           COUT     Out     0.035     5.781       -         
un2_result_cry_26                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_27_0        ALU           CIN      In      -         5.781       -         
u_xcorr.un2_result_cry_27_0        ALU           COUT     Out     0.035     5.816       -         
un2_result_cry_27                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_28_0        ALU           CIN      In      -         5.816       -         
u_xcorr.un2_result_cry_28_0        ALU           COUT     Out     0.035     5.851       -         
un2_result_cry_28                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_29_0        ALU           CIN      In      -         5.851       -         
u_xcorr.un2_result_cry_29_0        ALU           COUT     Out     0.035     5.886       -         
un2_result_cry_29                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_30_0        ALU           CIN      In      -         5.886       -         
u_xcorr.un2_result_cry_30_0        ALU           COUT     Out     0.035     5.921       -         
un2_result_cry_30                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_31_0        ALU           CIN      In      -         5.921       -         
u_xcorr.un2_result_cry_31_0        ALU           COUT     Out     0.035     5.956       -         
un2_result_cry_31                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_cry_32_0        ALU           CIN      In      -         5.956       -         
u_xcorr.un2_result_cry_32_0        ALU           COUT     Out     0.035     5.991       -         
un2_result_cry_32                  Net           -        -       0.000     -           1         
u_xcorr.un2_result_s_33_0          ALU           CIN      In      -         5.991       -         
u_xcorr.un2_result_s_33_0          ALU           SUM      Out     0.470     6.461       -         
un2_result_s_33_0_SUM              Net           -        -       0.535     -           1         
u_xcorr.result_0_0[33]             LUT3          I2       In      -         6.996       -         
u_xcorr.result_0_0[33]             LUT3          F        Out     0.462     7.458       -         
N_19_0                             Net           -        -       0.000     -           1         
u_xcorr.result[33]                 DFFR          D        In      -         7.458       -         
==================================================================================================
Total path delay (propagation time + setup) of 7.519 is 4.661(62.0%) logic and 2.858(38.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                                               Arrival          
Instance                                 Reference     Type          Pin         Net                            Time        Slack
                                         Clock                                                                                   
---------------------------------------------------------------------------------------------------------------------------------
u_xcorr.un1_delay_21_cry_3_0_RNO_0       System        INV           O           un1_delay_21_cry_3_0_RNO_0     0.000       3.774
u_xcorr.x_1_ret_33_0_RNI69O7             System        INV           O           un1_x_112_o_i                  0.000       5.630
u_xcorr.ad_RNO[0]                        System        INV           O           N_17_0                         0.000       5.813
u_xcorr.ad_RNO[1]                        System        INV           O           N_15_0                         0.000       5.813
u_xcorr.ad_RNO[3]                        System        INV           O           N_11_0                         0.000       5.813
u_xcorr.ad_RNO[5]                        System        INV           O           N_7_0                          0.000       5.813
u_xcorr.ad_RNO[7]                        System        INV           O           N_3_0                          0.000       5.813
u_xcorr.cnt_1_1_RNIDLTF[0]               System        INV           O           N_274_0                        0.000       5.813
u_xcorr.cnt_2_RNIUQOB[0]                 System        INV           O           N_264_0                        0.000       5.813
u_xcorr.r_1_2_preadd_mulonly_0[33:0]     System        MULT18X18     DOUT[0]     r_1_2[0]                       0.000       5.813
=================================================================================================================================


Ending Points with Worst Slack
******************************

                         Starting                                         Required          
Instance                 Reference     Type     Pin     Net               Time         Slack
                         Clock                                                              
--------------------------------------------------------------------------------------------
u_xcorr.x_1_ret_33_0     System        DFF      D       un1_x_112_0       6.348        3.774
u_xcorr.x_1_ret_0[0]     System        DFFE     CE      un1_x_112_o_i     6.348        5.630
u_xcorr.x_1_ret_0[1]     System        DFFE     CE      un1_x_112_o_i     6.348        5.630
u_xcorr.x_1_ret_0[2]     System        DFFE     CE      un1_x_112_o_i     6.348        5.630
u_xcorr.x_1_ret_0[3]     System        DFFE     CE      un1_x_112_o_i     6.348        5.630
u_xcorr.x_1_ret_0[4]     System        DFFE     CE      un1_x_112_o_i     6.348        5.630
u_xcorr.x_1_ret_0[5]     System        DFFE     CE      un1_x_112_o_i     6.348        5.630
u_xcorr.x_1_ret_0[6]     System        DFFE     CE      un1_x_112_o_i     6.348        5.630
u_xcorr.x_1_ret_0[7]     System        DFFE     CE      un1_x_112_o_i     6.348        5.630
u_xcorr.x_1_ret_0[8]     System        DFFE     CE      un1_x_112_o_i     6.348        5.630
============================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      6.409
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.348

    - Propagation time:                      2.574
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.774

    Number of logic level(s):                9
    Starting point:                          u_xcorr.un1_delay_21_cry_3_0_RNO_0 / O
    Ending point:                            u_xcorr.x_1_ret_33_0 / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            XCORR_Top|clk [rising] on pin CLK

Instance / Net                                  Pin      Pin               Arrival     No. of    
Name                                   Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
u_xcorr.un1_delay_21_cry_3_0_RNO_0     INV      O        Out     0.000     0.000       -         
un1_delay_21_cry_3_0_RNO_0             Net      -        -       0.535     -           1         
u_xcorr.un1_delay_21_cry_3_0           ALU      I3       In      -         0.535       -         
u_xcorr.un1_delay_21_cry_3_0           ALU      COUT     Out     0.371     0.906       -         
un1_delay_21_cry_3                     Net      -        -       0.000     -           1         
u_xcorr.un1_delay_21_cry_4_0           ALU      CIN      In      -         0.906       -         
u_xcorr.un1_delay_21_cry_4_0           ALU      COUT     Out     0.035     0.941       -         
un1_delay_21_cry_4                     Net      -        -       0.000     -           1         
u_xcorr.un1_delay_21_cry_5_0           ALU      CIN      In      -         0.941       -         
u_xcorr.un1_delay_21_cry_5_0           ALU      COUT     Out     0.035     0.976       -         
un1_delay_21_cry_5                     Net      -        -       0.000     -           1         
u_xcorr.un1_delay_21_cry_6_0           ALU      CIN      In      -         0.976       -         
u_xcorr.un1_delay_21_cry_6_0           ALU      COUT     Out     0.035     1.011       -         
un1_delay_21_cry_6                     Net      -        -       0.000     -           1         
u_xcorr.un1_delay_21_cry_7_0           ALU      CIN      In      -         1.011       -         
u_xcorr.un1_delay_21_cry_7_0           ALU      COUT     Out     0.035     1.046       -         
un1_delay_21_cry_7                     Net      -        -       0.000     -           1         
u_xcorr.un1_delay_21_cry_8_0           ALU      CIN      In      -         1.046       -         
u_xcorr.un1_delay_21_cry_8_0           ALU      COUT     Out     0.035     1.081       -         
un1_delay_21_cry_8                     Net      -        -       0.000     -           1         
u_xcorr.un1_delay_21_cry_9_0           ALU      CIN      In      -         1.081       -         
u_xcorr.un1_delay_21_cry_9_0           ALU      COUT     Out     0.035     1.116       -         
un1_delay_21_cry_9                     Net      -        -       0.000     -           1         
u_xcorr.un1_delay_21_cry_10_0          ALU      CIN      In      -         1.116       -         
u_xcorr.un1_delay_21_cry_10_0          ALU      COUT     Out     0.035     1.151       -         
un1_delay_21_cry_10                    Net      -        -       0.961     -           1         
u_xcorr.un1_x_112_0                    LUT4     I2       In      -         2.112       -         
u_xcorr.un1_x_112_0                    LUT4     F        Out     0.462     2.574       -         
un1_x_112_0                            Net      -        -       0.000     -           1         
u_xcorr.x_1_ret_33_0                   DFF      D        In      -         2.574       -         
=================================================================================================
Total path delay (propagation time + setup) of 2.635 is 1.139(43.2%) logic and 1.496(56.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 200MB peak: 204MB)


Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 200MB peak: 204MB)

---------------------------------------
Resource Usage Report for XCORR_Top 

Mapping to part: gw2a_55pbga484-8
Cell usage:
ALU             100 uses
DFF             103 uses
DFFE            34 uses
DFFR            148 uses
DFFRE           8 uses
DFFS            2 uses
GSR             1 use
INV             9 uses
MUX2_LUT5       4 uses
MUX2_LUT6       2 uses
SDPX9           4 uses
LUT2            115 uses
LUT3            185 uses
LUT4            111 uses
MULT18X18      1 use

I/O Register bits:                  0
Register bits not including I/Os:   295 of 41040 (0%)

RAM/ROM usage summary
Block Rams : 4 of 140 (2%)


Block Multipliers: 1 of 20 (5%)
Total load per clock:
   XCORR_Top|clk: 303

@S |Mapping Summary:
Total  LUTs: 411 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 44MB peak: 204MB)

Process took 0h:00m:08s realtime, 0h:00m:07s cputime
# Thu Dec 13 13:41:05 2018

###########################################################]
