Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | F:/user-bak/Users/FDELL/Desktop/IP/CrossCrorelation/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synplify/rev_1/XCORR_512-3_case.vm
Physical Constraints File | F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_512-3_case\project\src\XCORR_512-3_case.cst
Timing Constraints File | ---
GOWIN version | v1.9.0Beta
Part Number | GW2A-LV55PG484C8/I7
Created Time | Tue Feb 19 17:22:56 2019
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 0.95V 85C
Hold Delay Model | Fast 1.05V 0C
Numbers of Paths Analyzed | 1704
Numbers of Endpoints Analyzed | 4691
Numbers of Falling Endpoints | 1
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  |

## Max Frequency Summary:

NO. | Clock Name | Fmax | Entity
--- | --- | --- | ---
1 | DEFAULT_CLK | 117.492(MHz) | TOP

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
DEFAULT_CLK | Setup | 0.000 | 0
DEFAULT_CLK | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.489 | uut/u_xcorr/memr_1_waddr_tmp_0[5]/Q | uut/u_xcorr/result_Z[33]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 8.276
2 | 1.767 | uut/u_xcorr/memr_1_waddr_tmp_0[5]/Q | uut/u_xcorr/result_Z[32]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.998
3 | 1.802 | uut/u_xcorr/memr_1_waddr_tmp_0[5]/Q | uut/u_xcorr/result_Z[31]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 10.000 | 0.000 | 7.963
4 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
5 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
6 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
7 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
8 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
9 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
10 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_end_dly_Z/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
11 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
12 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
13 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_syn_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
14 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
15 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
16 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
17 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_dly_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
18 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
19 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
20 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/trigger_seq_start_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
21 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
22 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
23 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
24 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
25 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.213 | u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI1 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.462
2 | 0.213 | u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI0 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.462
3 | 0.307 | ut/isOk_r_Z[0]/Q | ut/isOk_r_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.318
4 | 0.310 | uut/u_xcorr/r_1_Z[11]/Q | uut/u_xcorr/memr_1_din_tmp_0[11]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.321
5 | 0.315 | uut/u_xcorr/r_1_Z[20]/Q | uut/u_xcorr/memr_1_din_tmp_0[20]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.326
6 | 0.341 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/ADA13 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.459
7 | 0.352 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/ADA11 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.470
8 | 0.353 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA13 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.471
9 | 0.354 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/ADA11 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.472
10 | 0.354 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA5 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.472
11 | 0.362 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA3 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.480
12 | 0.362 | ad_Z[8]/Q | series_y_2_0_1/AD13 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.480
13 | 0.363 | u_la0_top/u_ao_mem_ctrl/data_reg_Z[41]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/DI1 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.612
14 | 0.364 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA2 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.482
15 | 0.365 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA12 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.483
16 | 0.365 | uut/u_xcorr/cnt_1_1[4]/Q | uut/u_xcorr/memy_1_memy_1_0_0/ADA8 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.483
17 | 0.365 | uut/u_xcorr/cnt_1_1[4]/Q | uut/u_xcorr/memx_1_memx_1_0_0/ADA8 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.483
18 | 0.376 | ad_Z[7]/Q | series_y_2_0_1/AD12 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.494
19 | 0.425 | uut/u_xcorr/ad_Z[8]/Q | uut/u_xcorr/ad_Z[8]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436
20 | 0.425 | ut/cnt_r_Z[0]/Q | ut/cnt_r_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436
21 | 0.425 | uut/u_xcorr/ad_Z[1]/Q | uut/u_xcorr/ad_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436
22 | 0.425 | ut/cnt_r_Z[3]/Q | ut/cnt_r_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436
23 | 0.425 | uut/u_xcorr/ad_Z[6]/Q | uut/u_xcorr/ad_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436
24 | 0.427 | u_la0_top/capture_window_sel_Z[2]/Q | u_la0_top/capture_window_sel_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438
25 | 0.427 | uut/u_xcorr/ad_Z[3]/Q | uut/u_xcorr/ad_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
2 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
3 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
4 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_dly_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
5 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
6 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
7 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
8 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
9 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
10 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_end_dly_Z/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
11 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
12 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
13 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
14 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
15 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
16 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
17 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
18 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
19 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
20 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/trigger_seq_start_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
21 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
22 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
23 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
24 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880
25 | 1.853 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.880

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
2 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
3 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
4 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
5 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
6 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_end_dly_Z/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
7 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
8 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
9 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
10 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
11 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
12 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
13 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
14 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/trigger_seq_start_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
15 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
16 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
17 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
18 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
19 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
20 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
21 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
22 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
23 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
24 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946
25 | 6.748 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.946

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | ad_Z[0]
2 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | ad_Z[2]
3 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | ad_Z[6]
4 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/memy_memy_0_0
5 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/memr_1_din_tmp_0[19]
6 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/memr_1_din_tmp_0[15]
7 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/memy_adreg_Z[5]
8 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/x_1_ret_0[13]
9 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/x_1_ret_0[12]
10 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/cnt_1_1[5]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.489
Data Arrival Time | 10.159
Data Required Time | 11.648
From | uut/u_xcorr/memr_1_waddr_tmp_0[5]
To | uut/u_xcorr/result_Z[33]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.883 | 1.201 | tNET | RR | 1 | R17C55[0][B] | uut/u_xcorr/memr_1_waddr_tmp_0[5]/CLK
2.115 | 0.232 | tC2Q | RF | 4 | R17C55[0][B] | uut/u_xcorr/memr_1_waddr_tmp_0[5]/Q
2.297 | 0.182 | tNET | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_5_cZ/I3
2.852 | 0.555 | tINS | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_5_cZ/F
2.852 | 0.000 | tNET | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_1_cZ/I0
2.955 | 0.103 | tINS | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_1_cZ/O
2.955 | 0.000 | tNET | FF | 1 | R17C55[2][B] | uut/u_xcorr/memr_1_G_1_1_0_cZ/I0
3.058 | 0.103 | tINS | FF | 3 | R17C55[2][B] | uut/u_xcorr/memr_1_G_1_1_0_cZ/O
4.001 | 0.943 | tNET | FF | 1 | R17C42[1][A] | uut/u_xcorr/memr_1_G_1_cZ/I1
4.556 | 0.555 | tINS | FF | 33 | R17C42[1][A] | uut/u_xcorr/memr_1_G_1_cZ/F
5.557 | 1.001 | tNET | FF | 1 | R18C53[1][A] | uut/u_xcorr/un2_result_s_3_sf_lofx_cZ_cZ/I2
6.112 | 0.555 | tINS | FF | 1 | R18C53[1][A] | uut/u_xcorr/un2_result_s_3_sf_lofx_cZ_cZ/F
6.873 | 0.761 | tNET | FF | 2 | R17C43[2][B] | uut/u_xcorr/un2_result_cry_3_0/I0
7.443 | 0.570 | tINS | FR | 1 | R17C43[2][B] | uut/u_xcorr/un2_result_cry_3_0/COUT
7.443 | 0.000 | tNET | RR | 2 | R17C44[0][A] | uut/u_xcorr/un2_result_cry_4_0/CIN
7.478 | 0.035 | tINS | RF | 1 | R17C44[0][A] | uut/u_xcorr/un2_result_cry_4_0/COUT
7.478 | 0.000 | tNET | FF | 2 | R17C44[0][B] | uut/u_xcorr/un2_result_cry_5_0/CIN
7.513 | 0.035 | tINS | FF | 1 | R17C44[0][B] | uut/u_xcorr/un2_result_cry_5_0/COUT
7.513 | 0.000 | tNET | FF | 2 | R17C44[1][A] | uut/u_xcorr/un2_result_cry_6_0/CIN
7.548 | 0.035 | tINS | FF | 1 | R17C44[1][A] | uut/u_xcorr/un2_result_cry_6_0/COUT
7.548 | 0.000 | tNET | FF | 2 | R17C44[1][B] | uut/u_xcorr/un2_result_cry_7_0/CIN
7.583 | 0.035 | tINS | FF | 1 | R17C44[1][B] | uut/u_xcorr/un2_result_cry_7_0/COUT
7.583 | 0.000 | tNET | FF | 2 | R17C44[2][A] | uut/u_xcorr/un2_result_cry_8_0/CIN
7.619 | 0.035 | tINS | FF | 1 | R17C44[2][A] | uut/u_xcorr/un2_result_cry_8_0/COUT
7.619 | 0.000 | tNET | FF | 2 | R17C44[2][B] | uut/u_xcorr/un2_result_cry_9_0/CIN
7.654 | 0.035 | tINS | FF | 1 | R17C44[2][B] | uut/u_xcorr/un2_result_cry_9_0/COUT
7.654 | 0.000 | tNET | FF | 2 | R17C45[0][A] | uut/u_xcorr/un2_result_cry_10_0/CIN
7.689 | 0.035 | tINS | FF | 1 | R17C45[0][A] | uut/u_xcorr/un2_result_cry_10_0/COUT
7.689 | 0.000 | tNET | FF | 2 | R17C45[0][B] | uut/u_xcorr/un2_result_cry_11_0/CIN
7.724 | 0.035 | tINS | FF | 1 | R17C45[0][B] | uut/u_xcorr/un2_result_cry_11_0/COUT
7.724 | 0.000 | tNET | FF | 2 | R17C45[1][A] | uut/u_xcorr/un2_result_cry_12_0/CIN
7.759 | 0.035 | tINS | FF | 1 | R17C45[1][A] | uut/u_xcorr/un2_result_cry_12_0/COUT
7.759 | 0.000 | tNET | FF | 2 | R17C45[1][B] | uut/u_xcorr/un2_result_cry_13_0/CIN
7.795 | 0.035 | tINS | FF | 1 | R17C45[1][B] | uut/u_xcorr/un2_result_cry_13_0/COUT
7.795 | 0.000 | tNET | FF | 2 | R17C45[2][A] | uut/u_xcorr/un2_result_cry_14_0/CIN
7.830 | 0.035 | tINS | FF | 1 | R17C45[2][A] | uut/u_xcorr/un2_result_cry_14_0/COUT
7.830 | 0.000 | tNET | FF | 2 | R17C45[2][B] | uut/u_xcorr/un2_result_cry_15_0/CIN
7.865 | 0.035 | tINS | FF | 1 | R17C45[2][B] | uut/u_xcorr/un2_result_cry_15_0/COUT
7.865 | 0.000 | tNET | FF | 2 | R17C46[0][A] | uut/u_xcorr/un2_result_cry_16_0/CIN
7.900 | 0.035 | tINS | FF | 1 | R17C46[0][A] | uut/u_xcorr/un2_result_cry_16_0/COUT
7.900 | 0.000 | tNET | FF | 2 | R17C46[0][B] | uut/u_xcorr/un2_result_cry_17_0/CIN
7.935 | 0.035 | tINS | FF | 1 | R17C46[0][B] | uut/u_xcorr/un2_result_cry_17_0/COUT
7.935 | 0.000 | tNET | FF | 2 | R17C46[1][A] | uut/u_xcorr/un2_result_cry_18_0/CIN
7.971 | 0.035 | tINS | FF | 1 | R17C46[1][A] | uut/u_xcorr/un2_result_cry_18_0/COUT
7.971 | 0.000 | tNET | FF | 2 | R17C46[1][B] | uut/u_xcorr/un2_result_cry_19_0/CIN
8.006 | 0.035 | tINS | FF | 1 | R17C46[1][B] | uut/u_xcorr/un2_result_cry_19_0/COUT
8.006 | 0.000 | tNET | FF | 2 | R17C46[2][A] | uut/u_xcorr/un2_result_cry_20_0/CIN
8.041 | 0.035 | tINS | FF | 1 | R17C46[2][A] | uut/u_xcorr/un2_result_cry_20_0/COUT
8.041 | 0.000 | tNET | FF | 2 | R17C46[2][B] | uut/u_xcorr/un2_result_cry_21_0/CIN
8.076 | 0.035 | tINS | FF | 1 | R17C46[2][B] | uut/u_xcorr/un2_result_cry_21_0/COUT
8.076 | 0.000 | tNET | FF | 2 | R17C47[0][A] | uut/u_xcorr/un2_result_cry_22_0/CIN
8.111 | 0.035 | tINS | FF | 1 | R17C47[0][A] | uut/u_xcorr/un2_result_cry_22_0/COUT
8.111 | 0.000 | tNET | FF | 2 | R17C47[0][B] | uut/u_xcorr/un2_result_cry_23_0/CIN
8.147 | 0.035 | tINS | FF | 1 | R17C47[0][B] | uut/u_xcorr/un2_result_cry_23_0/COUT
8.147 | 0.000 | tNET | FF | 2 | R17C47[1][A] | uut/u_xcorr/un2_result_cry_24_0/CIN
8.182 | 0.035 | tINS | FF | 1 | R17C47[1][A] | uut/u_xcorr/un2_result_cry_24_0/COUT
8.182 | 0.000 | tNET | FF | 2 | R17C47[1][B] | uut/u_xcorr/un2_result_cry_25_0/CIN
8.217 | 0.035 | tINS | FF | 1 | R17C47[1][B] | uut/u_xcorr/un2_result_cry_25_0/COUT
8.217 | 0.000 | tNET | FF | 2 | R17C47[2][A] | uut/u_xcorr/un2_result_cry_26_0/CIN
8.252 | 0.035 | tINS | FF | 1 | R17C47[2][A] | uut/u_xcorr/un2_result_cry_26_0/COUT
8.252 | 0.000 | tNET | FF | 2 | R17C47[2][B] | uut/u_xcorr/un2_result_cry_27_0/CIN
8.287 | 0.035 | tINS | FF | 1 | R17C47[2][B] | uut/u_xcorr/un2_result_cry_27_0/COUT
8.287 | 0.000 | tNET | FF | 2 | R17C48[0][A] | uut/u_xcorr/un2_result_cry_28_0/CIN
8.323 | 0.035 | tINS | FF | 1 | R17C48[0][A] | uut/u_xcorr/un2_result_cry_28_0/COUT
8.323 | 0.000 | tNET | FF | 2 | R17C48[0][B] | uut/u_xcorr/un2_result_cry_29_0/CIN
8.358 | 0.035 | tINS | FF | 1 | R17C48[0][B] | uut/u_xcorr/un2_result_cry_29_0/COUT
8.358 | 0.000 | tNET | FF | 2 | R17C48[1][A] | uut/u_xcorr/un2_result_cry_30_0/CIN
8.393 | 0.035 | tINS | FF | 1 | R17C48[1][A] | uut/u_xcorr/un2_result_cry_30_0/COUT
8.393 | 0.000 | tNET | FF | 2 | R17C48[1][B] | uut/u_xcorr/un2_result_cry_31_0/CIN
8.428 | 0.035 | tINS | FF | 1 | R17C48[1][B] | uut/u_xcorr/un2_result_cry_31_0/COUT
8.428 | 0.000 | tNET | FF | 2 | R17C48[2][A] | uut/u_xcorr/un2_result_cry_32_0/CIN
8.463 | 0.035 | tINS | FF | 1 | R17C48[2][A] | uut/u_xcorr/un2_result_cry_32_0/COUT
8.463 | 0.000 | tNET | FF | 2 | R17C48[2][B] | uut/u_xcorr/un2_result_s_33_0/CIN
8.933 | 0.470 | tINS | FF | 1 | R17C48[2][B] | uut/u_xcorr/un2_result_s_33_0/SUM
9.589 | 0.656 | tNET | FF | 1 | R16C44[0][B] | uut/u_xcorr/result_0_0[33]/I2
10.159 | 0.570 | tINS | FR | 1 | R16C44[0][B] | uut/u_xcorr/result_0_0[33]/F
10.159 | 0.000 | tNET | RR | 1 | R16C44[0][B] | uut/u_xcorr/result_Z[33]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R16C44[0][B] | uut/u_xcorr/result_Z[33]/CLK
11.683 | -0.200 | tUnc |  |  |  | uut/u_xcorr/result_Z[33]
11.648 | -0.035 | tSu |  | 1 | R16C44[0][B] | uut/u_xcorr/result_Z[33]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 8
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay | cell: 4.502, 54.395%; route: 3.542, 42.802%; tC2Q: 0.232, 2.803%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path2

Path Summary:

Slack | 1.767
Data Arrival Time | 9.881
Data Required Time | 11.648
From | uut/u_xcorr/memr_1_waddr_tmp_0[5]
To | uut/u_xcorr/result_Z[32]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.883 | 1.201 | tNET | RR | 1 | R17C55[0][B] | uut/u_xcorr/memr_1_waddr_tmp_0[5]/CLK
2.115 | 0.232 | tC2Q | RF | 4 | R17C55[0][B] | uut/u_xcorr/memr_1_waddr_tmp_0[5]/Q
2.297 | 0.182 | tNET | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_5_cZ/I3
2.852 | 0.555 | tINS | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_5_cZ/F
2.852 | 0.000 | tNET | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_1_cZ/I0
2.955 | 0.103 | tINS | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_1_cZ/O
2.955 | 0.000 | tNET | FF | 1 | R17C55[2][B] | uut/u_xcorr/memr_1_G_1_1_0_cZ/I0
3.058 | 0.103 | tINS | FF | 3 | R17C55[2][B] | uut/u_xcorr/memr_1_G_1_1_0_cZ/O
4.001 | 0.943 | tNET | FF | 1 | R17C42[1][A] | uut/u_xcorr/memr_1_G_1_cZ/I1
4.556 | 0.555 | tINS | FF | 33 | R17C42[1][A] | uut/u_xcorr/memr_1_G_1_cZ/F
5.557 | 1.001 | tNET | FF | 1 | R18C53[1][A] | uut/u_xcorr/un2_result_s_3_sf_lofx_cZ_cZ/I2
6.112 | 0.555 | tINS | FF | 1 | R18C53[1][A] | uut/u_xcorr/un2_result_s_3_sf_lofx_cZ_cZ/F
6.873 | 0.761 | tNET | FF | 2 | R17C43[2][B] | uut/u_xcorr/un2_result_cry_3_0/I0
7.443 | 0.570 | tINS | FR | 1 | R17C43[2][B] | uut/u_xcorr/un2_result_cry_3_0/COUT
7.443 | 0.000 | tNET | RR | 2 | R17C44[0][A] | uut/u_xcorr/un2_result_cry_4_0/CIN
7.478 | 0.035 | tINS | RF | 1 | R17C44[0][A] | uut/u_xcorr/un2_result_cry_4_0/COUT
7.478 | 0.000 | tNET | FF | 2 | R17C44[0][B] | uut/u_xcorr/un2_result_cry_5_0/CIN
7.513 | 0.035 | tINS | FF | 1 | R17C44[0][B] | uut/u_xcorr/un2_result_cry_5_0/COUT
7.513 | 0.000 | tNET | FF | 2 | R17C44[1][A] | uut/u_xcorr/un2_result_cry_6_0/CIN
7.548 | 0.035 | tINS | FF | 1 | R17C44[1][A] | uut/u_xcorr/un2_result_cry_6_0/COUT
7.548 | 0.000 | tNET | FF | 2 | R17C44[1][B] | uut/u_xcorr/un2_result_cry_7_0/CIN
7.583 | 0.035 | tINS | FF | 1 | R17C44[1][B] | uut/u_xcorr/un2_result_cry_7_0/COUT
7.583 | 0.000 | tNET | FF | 2 | R17C44[2][A] | uut/u_xcorr/un2_result_cry_8_0/CIN
7.619 | 0.035 | tINS | FF | 1 | R17C44[2][A] | uut/u_xcorr/un2_result_cry_8_0/COUT
7.619 | 0.000 | tNET | FF | 2 | R17C44[2][B] | uut/u_xcorr/un2_result_cry_9_0/CIN
7.654 | 0.035 | tINS | FF | 1 | R17C44[2][B] | uut/u_xcorr/un2_result_cry_9_0/COUT
7.654 | 0.000 | tNET | FF | 2 | R17C45[0][A] | uut/u_xcorr/un2_result_cry_10_0/CIN
7.689 | 0.035 | tINS | FF | 1 | R17C45[0][A] | uut/u_xcorr/un2_result_cry_10_0/COUT
7.689 | 0.000 | tNET | FF | 2 | R17C45[0][B] | uut/u_xcorr/un2_result_cry_11_0/CIN
7.724 | 0.035 | tINS | FF | 1 | R17C45[0][B] | uut/u_xcorr/un2_result_cry_11_0/COUT
7.724 | 0.000 | tNET | FF | 2 | R17C45[1][A] | uut/u_xcorr/un2_result_cry_12_0/CIN
7.759 | 0.035 | tINS | FF | 1 | R17C45[1][A] | uut/u_xcorr/un2_result_cry_12_0/COUT
7.759 | 0.000 | tNET | FF | 2 | R17C45[1][B] | uut/u_xcorr/un2_result_cry_13_0/CIN
7.795 | 0.035 | tINS | FF | 1 | R17C45[1][B] | uut/u_xcorr/un2_result_cry_13_0/COUT
7.795 | 0.000 | tNET | FF | 2 | R17C45[2][A] | uut/u_xcorr/un2_result_cry_14_0/CIN
7.830 | 0.035 | tINS | FF | 1 | R17C45[2][A] | uut/u_xcorr/un2_result_cry_14_0/COUT
7.830 | 0.000 | tNET | FF | 2 | R17C45[2][B] | uut/u_xcorr/un2_result_cry_15_0/CIN
7.865 | 0.035 | tINS | FF | 1 | R17C45[2][B] | uut/u_xcorr/un2_result_cry_15_0/COUT
7.865 | 0.000 | tNET | FF | 2 | R17C46[0][A] | uut/u_xcorr/un2_result_cry_16_0/CIN
7.900 | 0.035 | tINS | FF | 1 | R17C46[0][A] | uut/u_xcorr/un2_result_cry_16_0/COUT
7.900 | 0.000 | tNET | FF | 2 | R17C46[0][B] | uut/u_xcorr/un2_result_cry_17_0/CIN
7.935 | 0.035 | tINS | FF | 1 | R17C46[0][B] | uut/u_xcorr/un2_result_cry_17_0/COUT
7.935 | 0.000 | tNET | FF | 2 | R17C46[1][A] | uut/u_xcorr/un2_result_cry_18_0/CIN
7.971 | 0.035 | tINS | FF | 1 | R17C46[1][A] | uut/u_xcorr/un2_result_cry_18_0/COUT
7.971 | 0.000 | tNET | FF | 2 | R17C46[1][B] | uut/u_xcorr/un2_result_cry_19_0/CIN
8.006 | 0.035 | tINS | FF | 1 | R17C46[1][B] | uut/u_xcorr/un2_result_cry_19_0/COUT
8.006 | 0.000 | tNET | FF | 2 | R17C46[2][A] | uut/u_xcorr/un2_result_cry_20_0/CIN
8.041 | 0.035 | tINS | FF | 1 | R17C46[2][A] | uut/u_xcorr/un2_result_cry_20_0/COUT
8.041 | 0.000 | tNET | FF | 2 | R17C46[2][B] | uut/u_xcorr/un2_result_cry_21_0/CIN
8.076 | 0.035 | tINS | FF | 1 | R17C46[2][B] | uut/u_xcorr/un2_result_cry_21_0/COUT
8.076 | 0.000 | tNET | FF | 2 | R17C47[0][A] | uut/u_xcorr/un2_result_cry_22_0/CIN
8.111 | 0.035 | tINS | FF | 1 | R17C47[0][A] | uut/u_xcorr/un2_result_cry_22_0/COUT
8.111 | 0.000 | tNET | FF | 2 | R17C47[0][B] | uut/u_xcorr/un2_result_cry_23_0/CIN
8.147 | 0.035 | tINS | FF | 1 | R17C47[0][B] | uut/u_xcorr/un2_result_cry_23_0/COUT
8.147 | 0.000 | tNET | FF | 2 | R17C47[1][A] | uut/u_xcorr/un2_result_cry_24_0/CIN
8.182 | 0.035 | tINS | FF | 1 | R17C47[1][A] | uut/u_xcorr/un2_result_cry_24_0/COUT
8.182 | 0.000 | tNET | FF | 2 | R17C47[1][B] | uut/u_xcorr/un2_result_cry_25_0/CIN
8.217 | 0.035 | tINS | FF | 1 | R17C47[1][B] | uut/u_xcorr/un2_result_cry_25_0/COUT
8.217 | 0.000 | tNET | FF | 2 | R17C47[2][A] | uut/u_xcorr/un2_result_cry_26_0/CIN
8.252 | 0.035 | tINS | FF | 1 | R17C47[2][A] | uut/u_xcorr/un2_result_cry_26_0/COUT
8.252 | 0.000 | tNET | FF | 2 | R17C47[2][B] | uut/u_xcorr/un2_result_cry_27_0/CIN
8.287 | 0.035 | tINS | FF | 1 | R17C47[2][B] | uut/u_xcorr/un2_result_cry_27_0/COUT
8.287 | 0.000 | tNET | FF | 2 | R17C48[0][A] | uut/u_xcorr/un2_result_cry_28_0/CIN
8.323 | 0.035 | tINS | FF | 1 | R17C48[0][A] | uut/u_xcorr/un2_result_cry_28_0/COUT
8.323 | 0.000 | tNET | FF | 2 | R17C48[0][B] | uut/u_xcorr/un2_result_cry_29_0/CIN
8.358 | 0.035 | tINS | FF | 1 | R17C48[0][B] | uut/u_xcorr/un2_result_cry_29_0/COUT
8.358 | 0.000 | tNET | FF | 2 | R17C48[1][A] | uut/u_xcorr/un2_result_cry_30_0/CIN
8.393 | 0.035 | tINS | FF | 1 | R17C48[1][A] | uut/u_xcorr/un2_result_cry_30_0/COUT
8.393 | 0.000 | tNET | FF | 2 | R17C48[1][B] | uut/u_xcorr/un2_result_cry_31_0/CIN
8.428 | 0.035 | tINS | FF | 1 | R17C48[1][B] | uut/u_xcorr/un2_result_cry_31_0/COUT
8.428 | 0.000 | tNET | FF | 2 | R17C48[2][A] | uut/u_xcorr/un2_result_cry_32_0/CIN
8.898 | 0.470 | tINS | FF | 1 | R17C48[2][A] | uut/u_xcorr/un2_result_cry_32_0/SUM
9.311 | 0.413 | tNET | FF | 1 | R16C47[0][B] | uut/u_xcorr/result_0_0[32]/I2
9.881 | 0.570 | tINS | FR | 1 | R16C47[0][B] | uut/u_xcorr/result_0_0[32]/F
9.881 | 0.000 | tNET | RR | 1 | R16C47[0][B] | uut/u_xcorr/result_Z[32]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R16C47[0][B] | uut/u_xcorr/result_Z[32]/CLK
11.683 | -0.200 | tUnc |  |  |  | uut/u_xcorr/result_Z[32]
11.648 | -0.035 | tSu |  | 1 | R16C47[0][B] | uut/u_xcorr/result_Z[32]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 8
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay | cell: 4.467, 55.845%; route: 3.300, 41.255%; tC2Q: 0.232, 2.901%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path3

Path Summary:

Slack | 1.802
Data Arrival Time | 9.846
Data Required Time | 11.648
From | uut/u_xcorr/memr_1_waddr_tmp_0[5]
To | uut/u_xcorr/result_Z[31]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.883 | 1.201 | tNET | RR | 1 | R17C55[0][B] | uut/u_xcorr/memr_1_waddr_tmp_0[5]/CLK
2.115 | 0.232 | tC2Q | RF | 4 | R17C55[0][B] | uut/u_xcorr/memr_1_waddr_tmp_0[5]/Q
2.297 | 0.182 | tNET | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_5_cZ/I3
2.852 | 0.555 | tINS | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_5_cZ/F
2.852 | 0.000 | tNET | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_1_cZ/I0
2.955 | 0.103 | tINS | FF | 1 | R17C55[3][A] | uut/u_xcorr/memr_1_G_1_1_1_cZ/O
2.955 | 0.000 | tNET | FF | 1 | R17C55[2][B] | uut/u_xcorr/memr_1_G_1_1_0_cZ/I0
3.058 | 0.103 | tINS | FF | 3 | R17C55[2][B] | uut/u_xcorr/memr_1_G_1_1_0_cZ/O
4.001 | 0.943 | tNET | FF | 1 | R17C42[1][A] | uut/u_xcorr/memr_1_G_1_cZ/I1
4.556 | 0.555 | tINS | FF | 33 | R17C42[1][A] | uut/u_xcorr/memr_1_G_1_cZ/F
5.557 | 1.001 | tNET | FF | 1 | R18C53[1][A] | uut/u_xcorr/un2_result_s_3_sf_lofx_cZ_cZ/I2
6.112 | 0.555 | tINS | FF | 1 | R18C53[1][A] | uut/u_xcorr/un2_result_s_3_sf_lofx_cZ_cZ/F
6.873 | 0.761 | tNET | FF | 2 | R17C43[2][B] | uut/u_xcorr/un2_result_cry_3_0/I0
7.443 | 0.570 | tINS | FR | 1 | R17C43[2][B] | uut/u_xcorr/un2_result_cry_3_0/COUT
7.443 | 0.000 | tNET | RR | 2 | R17C44[0][A] | uut/u_xcorr/un2_result_cry_4_0/CIN
7.478 | 0.035 | tINS | RF | 1 | R17C44[0][A] | uut/u_xcorr/un2_result_cry_4_0/COUT
7.478 | 0.000 | tNET | FF | 2 | R17C44[0][B] | uut/u_xcorr/un2_result_cry_5_0/CIN
7.513 | 0.035 | tINS | FF | 1 | R17C44[0][B] | uut/u_xcorr/un2_result_cry_5_0/COUT
7.513 | 0.000 | tNET | FF | 2 | R17C44[1][A] | uut/u_xcorr/un2_result_cry_6_0/CIN
7.548 | 0.035 | tINS | FF | 1 | R17C44[1][A] | uut/u_xcorr/un2_result_cry_6_0/COUT
7.548 | 0.000 | tNET | FF | 2 | R17C44[1][B] | uut/u_xcorr/un2_result_cry_7_0/CIN
7.583 | 0.035 | tINS | FF | 1 | R17C44[1][B] | uut/u_xcorr/un2_result_cry_7_0/COUT
7.583 | 0.000 | tNET | FF | 2 | R17C44[2][A] | uut/u_xcorr/un2_result_cry_8_0/CIN
7.619 | 0.035 | tINS | FF | 1 | R17C44[2][A] | uut/u_xcorr/un2_result_cry_8_0/COUT
7.619 | 0.000 | tNET | FF | 2 | R17C44[2][B] | uut/u_xcorr/un2_result_cry_9_0/CIN
7.654 | 0.035 | tINS | FF | 1 | R17C44[2][B] | uut/u_xcorr/un2_result_cry_9_0/COUT
7.654 | 0.000 | tNET | FF | 2 | R17C45[0][A] | uut/u_xcorr/un2_result_cry_10_0/CIN
7.689 | 0.035 | tINS | FF | 1 | R17C45[0][A] | uut/u_xcorr/un2_result_cry_10_0/COUT
7.689 | 0.000 | tNET | FF | 2 | R17C45[0][B] | uut/u_xcorr/un2_result_cry_11_0/CIN
7.724 | 0.035 | tINS | FF | 1 | R17C45[0][B] | uut/u_xcorr/un2_result_cry_11_0/COUT
7.724 | 0.000 | tNET | FF | 2 | R17C45[1][A] | uut/u_xcorr/un2_result_cry_12_0/CIN
7.759 | 0.035 | tINS | FF | 1 | R17C45[1][A] | uut/u_xcorr/un2_result_cry_12_0/COUT
7.759 | 0.000 | tNET | FF | 2 | R17C45[1][B] | uut/u_xcorr/un2_result_cry_13_0/CIN
7.795 | 0.035 | tINS | FF | 1 | R17C45[1][B] | uut/u_xcorr/un2_result_cry_13_0/COUT
7.795 | 0.000 | tNET | FF | 2 | R17C45[2][A] | uut/u_xcorr/un2_result_cry_14_0/CIN
7.830 | 0.035 | tINS | FF | 1 | R17C45[2][A] | uut/u_xcorr/un2_result_cry_14_0/COUT
7.830 | 0.000 | tNET | FF | 2 | R17C45[2][B] | uut/u_xcorr/un2_result_cry_15_0/CIN
7.865 | 0.035 | tINS | FF | 1 | R17C45[2][B] | uut/u_xcorr/un2_result_cry_15_0/COUT
7.865 | 0.000 | tNET | FF | 2 | R17C46[0][A] | uut/u_xcorr/un2_result_cry_16_0/CIN
7.900 | 0.035 | tINS | FF | 1 | R17C46[0][A] | uut/u_xcorr/un2_result_cry_16_0/COUT
7.900 | 0.000 | tNET | FF | 2 | R17C46[0][B] | uut/u_xcorr/un2_result_cry_17_0/CIN
7.935 | 0.035 | tINS | FF | 1 | R17C46[0][B] | uut/u_xcorr/un2_result_cry_17_0/COUT
7.935 | 0.000 | tNET | FF | 2 | R17C46[1][A] | uut/u_xcorr/un2_result_cry_18_0/CIN
7.971 | 0.035 | tINS | FF | 1 | R17C46[1][A] | uut/u_xcorr/un2_result_cry_18_0/COUT
7.971 | 0.000 | tNET | FF | 2 | R17C46[1][B] | uut/u_xcorr/un2_result_cry_19_0/CIN
8.006 | 0.035 | tINS | FF | 1 | R17C46[1][B] | uut/u_xcorr/un2_result_cry_19_0/COUT
8.006 | 0.000 | tNET | FF | 2 | R17C46[2][A] | uut/u_xcorr/un2_result_cry_20_0/CIN
8.041 | 0.035 | tINS | FF | 1 | R17C46[2][A] | uut/u_xcorr/un2_result_cry_20_0/COUT
8.041 | 0.000 | tNET | FF | 2 | R17C46[2][B] | uut/u_xcorr/un2_result_cry_21_0/CIN
8.076 | 0.035 | tINS | FF | 1 | R17C46[2][B] | uut/u_xcorr/un2_result_cry_21_0/COUT
8.076 | 0.000 | tNET | FF | 2 | R17C47[0][A] | uut/u_xcorr/un2_result_cry_22_0/CIN
8.111 | 0.035 | tINS | FF | 1 | R17C47[0][A] | uut/u_xcorr/un2_result_cry_22_0/COUT
8.111 | 0.000 | tNET | FF | 2 | R17C47[0][B] | uut/u_xcorr/un2_result_cry_23_0/CIN
8.147 | 0.035 | tINS | FF | 1 | R17C47[0][B] | uut/u_xcorr/un2_result_cry_23_0/COUT
8.147 | 0.000 | tNET | FF | 2 | R17C47[1][A] | uut/u_xcorr/un2_result_cry_24_0/CIN
8.182 | 0.035 | tINS | FF | 1 | R17C47[1][A] | uut/u_xcorr/un2_result_cry_24_0/COUT
8.182 | 0.000 | tNET | FF | 2 | R17C47[1][B] | uut/u_xcorr/un2_result_cry_25_0/CIN
8.217 | 0.035 | tINS | FF | 1 | R17C47[1][B] | uut/u_xcorr/un2_result_cry_25_0/COUT
8.217 | 0.000 | tNET | FF | 2 | R17C47[2][A] | uut/u_xcorr/un2_result_cry_26_0/CIN
8.252 | 0.035 | tINS | FF | 1 | R17C47[2][A] | uut/u_xcorr/un2_result_cry_26_0/COUT
8.252 | 0.000 | tNET | FF | 2 | R17C47[2][B] | uut/u_xcorr/un2_result_cry_27_0/CIN
8.287 | 0.035 | tINS | FF | 1 | R17C47[2][B] | uut/u_xcorr/un2_result_cry_27_0/COUT
8.287 | 0.000 | tNET | FF | 2 | R17C48[0][A] | uut/u_xcorr/un2_result_cry_28_0/CIN
8.323 | 0.035 | tINS | FF | 1 | R17C48[0][A] | uut/u_xcorr/un2_result_cry_28_0/COUT
8.323 | 0.000 | tNET | FF | 2 | R17C48[0][B] | uut/u_xcorr/un2_result_cry_29_0/CIN
8.358 | 0.035 | tINS | FF | 1 | R17C48[0][B] | uut/u_xcorr/un2_result_cry_29_0/COUT
8.358 | 0.000 | tNET | FF | 2 | R17C48[1][A] | uut/u_xcorr/un2_result_cry_30_0/CIN
8.393 | 0.035 | tINS | FF | 1 | R17C48[1][A] | uut/u_xcorr/un2_result_cry_30_0/COUT
8.393 | 0.000 | tNET | FF | 2 | R17C48[1][B] | uut/u_xcorr/un2_result_cry_31_0/CIN
8.863 | 0.470 | tINS | FF | 1 | R17C48[1][B] | uut/u_xcorr/un2_result_cry_31_0/SUM
9.276 | 0.413 | tNET | FF | 1 | R16C47[0][A] | uut/u_xcorr/result_0_0[31]/I2
9.846 | 0.570 | tINS | FR | 1 | R16C47[0][A] | uut/u_xcorr/result_0_0[31]/F
9.846 | 0.000 | tNET | RR | 1 | R16C47[0][A] | uut/u_xcorr/result_Z[31]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R16C47[0][A] | uut/u_xcorr/result_Z[31]/CLK
11.683 | -0.200 | tUnc |  |  |  | uut/u_xcorr/result_Z[31]
11.648 | -0.035 | tSu |  | 1 | R16C47[0][A] | uut/u_xcorr/result_Z[31]

Path Statistics:

Clock Skew | 0.000
Setup Relationship | 10.000
Logic Level | 8
Arrival Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay | cell: 4.431, 55.650%; route: 3.300, 41.437%; tC2Q: 0.232, 2.913%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path4

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648 | -0.035 | tSu |  | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path5

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648 | -0.035 | tSu |  | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path6

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[2]
11.648 | -0.035 | tSu |  | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path7

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R12C8[0][B] | u_la0_top/triger_level_cnt_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C8[0][B] | u_la0_top/triger_level_cnt_Z[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[3]
11.648 | -0.035 | tSu |  | 1 | R12C8[0][B] | u_la0_top/triger_level_cnt_Z[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path8

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R3C4[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C4[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[0]
11.648 | -0.035 | tSu |  | 1 | R3C4[0][B] | u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path9

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R3C3[2][A] | u_la0_top/triger_level_cnt_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C3[2][A] | u_la0_top/triger_level_cnt_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[1]
11.648 | -0.035 | tSu |  | 1 | R3C3[2][A] | u_la0_top/triger_level_cnt_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path10

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_end_dly_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R4C11[1][B] | u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C11[1][B] | u_la0_top/capture_end_dly_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_end_dly_Z
11.648 | -0.035 | tSu |  | 1 | R4C11[1][B] | u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path11

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R9C2[2][A] | u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/capture_window_sel[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel[3]
11.648 | -0.035 | tSu |  | 1 | R9C2[2][A] | u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path12

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R8C3[2][A] | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C3[2][A] | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_force_triger_syn_Z[0]
11.648 | -0.035 | tSu |  | 1 | R8C3[2][A] | u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path13

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R6C11[2][A] | u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R6C11[2][A] | u_la0_top/internal_reg_start_syn_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_syn_Z[0]
11.648 | -0.035 | tSu |  | 1 | R6C11[2][A] | u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path14

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R9C2[2][B] | u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R9C2[2][B] | u_la0_top/triger_level_cnt_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[2]
11.648 | -0.035 | tSu |  | 1 | R9C2[2][B] | u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path15

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_force_triger_syn_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R8C3[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C3[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_force_triger_syn_Z[1]
11.648 | -0.035 | tSu |  | 1 | R8C3[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path16

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R3C7[1][B] | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C7[1][B] | u_la0_top/internal_reg_start_dly_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_dly_Z[0]
11.648 | -0.035 | tSu |  | 1 | R3C7[1][B] | u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path17

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_dly_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R11C10[2][A] | u_la0_top/internal_reg_start_dly_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R11C10[2][A] | u_la0_top/internal_reg_start_dly_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_dly_Z[1]
11.648 | -0.035 | tSu |  | 1 | R11C10[2][A] | u_la0_top/internal_reg_start_dly_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path18

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648 | -0.035 | tSu |  | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path19

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
11.648 | -0.035 | tSu |  | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path20

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/trigger_seq_start_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R6C9[2][A] | u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R6C9[2][A] | u_la0_top/trigger_seq_start_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/trigger_seq_start_Z
11.648 | -0.035 | tSu |  | 1 | R6C9[2][A] | u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path21

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R3C3[2][B] | u_la0_top/capture_window_sel_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C3[2][B] | u_la0_top/capture_window_sel_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[0]
11.648 | -0.035 | tSu |  | 1 | R3C3[2][B] | u_la0_top/capture_window_sel_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path22

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R5C2[2][A] | u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R5C2[2][A] | u_la0_top/capture_window_sel_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[1]
11.648 | -0.035 | tSu |  | 1 | R5C2[2][A] | u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path23

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_syn_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R8C2[0][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C2[0][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_syn_Z[1]
11.648 | -0.035 | tSu |  | 1 | R8C2[0][B] | u_la0_top/internal_reg_start_syn_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path24

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
11.648 | -0.035 | tSu |  | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path25

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
11.648 | -0.035 | tSu |  | 1 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.213
Data Arrival Time | 2.040
Data Required Time | 1.826
From | u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R9C9[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]/CLK
1.779 | 0.202 | tC2Q | RR | 1 | R9C9[1][A] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[37]/Q
2.040 | 0.260 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
1.826 | 0.249 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path2

Path Summary:

Slack | 0.213
Data Arrival Time | 2.040
Data Required Time | 1.826
From | u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R9C9[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]/CLK
1.779 | 0.202 | tC2Q | RR | 1 | R9C9[0][B] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[36]/Q
2.040 | 0.260 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/DI0

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
1.826 | 0.249 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path3

Path Summary:

Slack | 0.307
Data Arrival Time | 1.895
Data Required Time | 1.588
From | ut/isOk_r_Z[0]
To | ut/isOk_r_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C60[2][A] | ut/isOk_r_Z[0]/CLK
1.778 | 0.201 | tC2Q | RF | 1 | R17C60[2][A] | ut/isOk_r_Z[0]/Q
1.895 | 0.117 | tNET | FF | 1 | R17C60[2][B] | ut/isOk_r_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C60[2][B] | ut/isOk_r_Z[1]/CLK
1.577 | 0.000 | tUnc |  |  |  | ut/isOk_r_Z[1]
1.588 | 0.011 | tHld |  | 1 | R17C60[2][B] | ut/isOk_r_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path4

Path Summary:

Slack | 0.310
Data Arrival Time | 1.899
Data Required Time | 1.588
From | uut/u_xcorr/r_1_Z[11]
To | uut/u_xcorr/memr_1_din_tmp_0[11]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R16C49[1][A] | uut/u_xcorr/r_1_Z[11]/CLK
1.778 | 0.201 | tC2Q | RF | 2 | R16C49[1][A] | uut/u_xcorr/r_1_Z[11]/Q
1.899 | 0.120 | tNET | FF | 1 | R16C49[0][A] | uut/u_xcorr/memr_1_din_tmp_0[11]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R16C49[0][A] | uut/u_xcorr/memr_1_din_tmp_0[11]/CLK
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/memr_1_din_tmp_0[11]
1.588 | 0.011 | tHld |  | 1 | R16C49[0][A] | uut/u_xcorr/memr_1_din_tmp_0[11]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path5

Path Summary:

Slack | 0.315
Data Arrival Time | 1.904
Data Required Time | 1.588
From | uut/u_xcorr/r_1_Z[20]
To | uut/u_xcorr/memr_1_din_tmp_0[20]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C50[2][B] | uut/u_xcorr/r_1_Z[20]/CLK
1.779 | 0.202 | tC2Q | RR | 2 | R18C50[2][B] | uut/u_xcorr/r_1_Z[20]/Q
1.904 | 0.124 | tNET | RR | 1 | R18C52[0][A] | uut/u_xcorr/memr_1_din_tmp_0[20]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C52[0][A] | uut/u_xcorr/memr_1_din_tmp_0[20]/CLK
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/memr_1_din_tmp_0[20]
1.588 | 0.011 | tHld |  | 1 | R18C52[0][A] | uut/u_xcorr/memr_1_din_tmp_0[20]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 38.121%; tC2Q: 0.202, 61.879%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path6

Path Summary:

Slack | 0.341
Data Arrival Time | 2.036
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q
2.036 | 0.257 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/ADA13

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.257, 55.970%; tC2Q: 0.202, 44.030%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path7

Path Summary:

Slack | 0.352
Data Arrival Time | 2.047
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.047 | 0.268 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/ADA11

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_18

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.268, 56.996%; tC2Q: 0.202, 43.004%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path8

Path Summary:

Slack | 0.353
Data Arrival Time | 2.048
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/Q
2.048 | 0.269 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA13

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.107%; tC2Q: 0.202, 42.893%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path9

Path Summary:

Slack | 0.354
Data Arrival Time | 2.049
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.049 | 0.270 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/ADA11

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.270, 57.208%; tC2Q: 0.202, 42.792%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path10

Path Summary:

Slack | 0.354
Data Arrival Time | 2.050
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R12C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.050 | 0.270 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA5

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.270, 57.213%; tC2Q: 0.202, 42.787%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path11

Path Summary:

Slack | 0.362
Data Arrival Time | 2.058
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/Q
2.058 | 0.278 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA3

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 57.951%; tC2Q: 0.202, 42.049%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path12

Path Summary:

Slack | 0.362
Data Arrival Time | 2.058
Data Required Time | 1.695
From | ad_Z[8]
To | series_y_2_0_1
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C18[2][A] | ad_Z[8]/CLK
1.779 | 0.202 | tC2Q | RR | 3 | R17C18[2][A] | ad_Z[8]/Q
2.058 | 0.278 | tNET | RR | 1 | BSRAM_R10[4] | series_y_2_0_1/AD13

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[4] | series_y_2_0_1/CLK
1.577 | 0.000 | tUnc |  |  |  | series_y_2_0_1
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[4] | series_y_2_0_1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.278, 57.951%; tC2Q: 0.202, 42.049%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path13

Path Summary:

Slack | 0.363
Data Arrival Time | 2.189
Data Required Time | 1.826
From | u_la0_top/u_ao_mem_ctrl/data_reg_Z[41]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R9C10[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[41]/CLK
1.779 | 0.202 | tC2Q | RR | 1 | R9C10[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[41]/Q
2.189 | 0.410 | tNET | RR | 1 | BSRAM_R10[5] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/DI1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[5] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_20/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_20
1.826 | 0.249 | tHld |  | 1 | BSRAM_R10[5] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_20

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path14

Path Summary:

Slack | 0.364
Data Arrival Time | 2.059
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R9C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R9C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/Q
2.059 | 0.280 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA2

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.280, 58.075%; tC2Q: 0.202, 41.925%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path15

Path Summary:

Slack | 0.365
Data Arrival Time | 2.060
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q
2.060 | 0.281 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/ADA12

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_13

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.281, 58.164%; tC2Q: 0.202, 41.836%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path16

Path Summary:

Slack | 0.365
Data Arrival Time | 2.060
Data Required Time | 1.695
From | uut/u_xcorr/cnt_1_1[4]
To | uut/u_xcorr/memy_1_memy_1_0_0
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C27[2][A] | uut/u_xcorr/cnt_1_1[4]/CLK
1.779 | 0.202 | tC2Q | RR | 12 | R18C27[2][A] | uut/u_xcorr/cnt_1_1[4]/Q
2.060 | 0.281 | tNET | RR | 1 | BSRAM_R10[7] | uut/u_xcorr/memy_1_memy_1_0_0/ADA8

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[7] | uut/u_xcorr/memy_1_memy_1_0_0/CLKA
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/memy_1_memy_1_0_0
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[7] | uut/u_xcorr/memy_1_memy_1_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.281, 58.164%; tC2Q: 0.202, 41.836%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path17

Path Summary:

Slack | 0.365
Data Arrival Time | 2.060
Data Required Time | 1.695
From | uut/u_xcorr/cnt_1_1[4]
To | uut/u_xcorr/memx_1_memx_1_0_0
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C27[2][A] | uut/u_xcorr/cnt_1_1[4]/CLK
1.779 | 0.202 | tC2Q | RR | 12 | R18C27[2][A] | uut/u_xcorr/cnt_1_1[4]/Q
2.060 | 0.281 | tNET | RR | 1 | BSRAM_R10[8] | uut/u_xcorr/memx_1_memx_1_0_0/ADA8

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[8] | uut/u_xcorr/memx_1_memx_1_0_0/CLKA
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/memx_1_memx_1_0_0
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[8] | uut/u_xcorr/memx_1_memx_1_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.281, 58.164%; tC2Q: 0.202, 41.836%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path18

Path Summary:

Slack | 0.376
Data Arrival Time | 2.072
Data Required Time | 1.695
From | ad_Z[7]
To | series_y_2_0_1
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C18[1][B] | ad_Z[7]/CLK
1.779 | 0.202 | tC2Q | RR | 3 | R17C18[1][B] | ad_Z[7]/Q
2.072 | 0.292 | tNET | RR | 1 | BSRAM_R10[4] | series_y_2_0_1/AD12

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[4] | series_y_2_0_1/CLK
1.577 | 0.000 | tUnc |  |  |  | series_y_2_0_1
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[4] | series_y_2_0_1

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.292, 59.138%; tC2Q: 0.202, 40.862%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path19

Path Summary:

Slack | 0.425
Data Arrival Time | 2.014
Data Required Time | 1.588
From | uut/u_xcorr/ad_Z[8]
To | uut/u_xcorr/ad_Z[8]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C19[0][A] | uut/u_xcorr/ad_Z[8]/CLK
1.779 | 0.202 | tC2Q | RR | 2 | R18C19[0][A] | uut/u_xcorr/ad_Z[8]/Q
1.782 | 0.002 | tNET | RR | 1 | R18C19[0][A] | uut/u_xcorr/ad_RNO[8]/I0
2.014 | 0.232 | tINS | RF | 1 | R18C19[0][A] | uut/u_xcorr/ad_RNO[8]/F
2.014 | 0.000 | tNET | FF | 1 | R18C19[0][A] | uut/u_xcorr/ad_Z[8]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C19[0][A] | uut/u_xcorr/ad_Z[8]/CLK
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/ad_Z[8]
1.588 | 0.011 | tHld |  | 1 | R18C19[0][A] | uut/u_xcorr/ad_Z[8]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path20

Path Summary:

Slack | 0.425
Data Arrival Time | 2.014
Data Required Time | 1.588
From | ut/cnt_r_Z[0]
To | ut/cnt_r_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C60[1][A] | ut/cnt_r_Z[0]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R17C60[1][A] | ut/cnt_r_Z[0]/Q
1.782 | 0.002 | tNET | RR | 1 | R17C60[1][A] | ut/cnt_r_RNO[0]/I0
2.014 | 0.232 | tINS | RF | 1 | R17C60[1][A] | ut/cnt_r_RNO[0]/F
2.014 | 0.000 | tNET | FF | 1 | R17C60[1][A] | ut/cnt_r_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C60[1][A] | ut/cnt_r_Z[0]/CLK
1.577 | 0.000 | tUnc |  |  |  | ut/cnt_r_Z[0]
1.588 | 0.011 | tHld |  | 1 | R17C60[1][A] | ut/cnt_r_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path21

Path Summary:

Slack | 0.425
Data Arrival Time | 2.014
Data Required Time | 1.588
From | uut/u_xcorr/ad_Z[1]
To | uut/u_xcorr/ad_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R16C18[0][A] | uut/u_xcorr/ad_Z[1]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R16C18[0][A] | uut/u_xcorr/ad_Z[1]/Q
1.782 | 0.002 | tNET | RR | 1 | R16C18[0][A] | uut/u_xcorr/ad_RNO[1]/I0
2.014 | 0.232 | tINS | RF | 1 | R16C18[0][A] | uut/u_xcorr/ad_RNO[1]/F
2.014 | 0.000 | tNET | FF | 1 | R16C18[0][A] | uut/u_xcorr/ad_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R16C18[0][A] | uut/u_xcorr/ad_Z[1]/CLK
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/ad_Z[1]
1.588 | 0.011 | tHld |  | 1 | R16C18[0][A] | uut/u_xcorr/ad_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path22

Path Summary:

Slack | 0.425
Data Arrival Time | 2.014
Data Required Time | 1.588
From | ut/cnt_r_Z[3]
To | ut/cnt_r_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C60[0][A] | ut/cnt_r_Z[3]/CLK
1.779 | 0.202 | tC2Q | RR | 2 | R17C60[0][A] | ut/cnt_r_Z[3]/Q
1.782 | 0.002 | tNET | RR | 1 | R17C60[0][A] | ut/cnt_r_RNO[3]/I1
2.014 | 0.232 | tINS | RF | 1 | R17C60[0][A] | ut/cnt_r_RNO[3]/F
2.014 | 0.000 | tNET | FF | 1 | R17C60[0][A] | ut/cnt_r_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C60[0][A] | ut/cnt_r_Z[3]/CLK
1.577 | 0.000 | tUnc |  |  |  | ut/cnt_r_Z[3]
1.588 | 0.011 | tHld |  | 1 | R17C60[0][A] | ut/cnt_r_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path23

Path Summary:

Slack | 0.425
Data Arrival Time | 2.014
Data Required Time | 1.588
From | uut/u_xcorr/ad_Z[6]
To | uut/u_xcorr/ad_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C19[0][A] | uut/u_xcorr/ad_Z[6]/CLK
1.779 | 0.202 | tC2Q | RR | 3 | R17C19[0][A] | uut/u_xcorr/ad_Z[6]/Q
1.782 | 0.002 | tNET | RR | 1 | R17C19[0][A] | uut/u_xcorr/ad_RNO[6]/I0
2.014 | 0.232 | tINS | RF | 1 | R17C19[0][A] | uut/u_xcorr/ad_RNO[6]/F
2.014 | 0.000 | tNET | FF | 1 | R17C19[0][A] | uut/u_xcorr/ad_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C19[0][A] | uut/u_xcorr/ad_Z[6]/CLK
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/ad_Z[6]
1.588 | 0.011 | tHld |  | 1 | R17C19[0][A] | uut/u_xcorr/ad_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path24

Path Summary:

Slack | 0.427
Data Arrival Time | 2.015
Data Required Time | 1.588
From | u_la0_top/capture_window_sel_Z[2]
To | u_la0_top/capture_window_sel_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/Q
1.783 | 0.004 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_3_cZ[2]/I0
2.015 | 0.232 | tINS | RF | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_3_cZ[2]/F
2.015 | 0.000 | tNET | FF | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/CLK
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[2]
1.588 | 0.011 | tHld |  | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path25

Path Summary:

Slack | 0.427
Data Arrival Time | 2.015
Data Required Time | 1.588
From | uut/u_xcorr/ad_Z[3]
To | uut/u_xcorr/ad_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C18[0][A] | uut/u_xcorr/ad_Z[3]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R18C18[0][A] | uut/u_xcorr/ad_Z[3]/Q
1.783 | 0.004 | tNET | RR | 1 | R18C18[0][A] | uut/u_xcorr/ad_RNO[3]/I0
2.015 | 0.232 | tINS | RF | 1 | R18C18[0][A] | uut/u_xcorr/ad_RNO[3]/F
2.015 | 0.000 | tNET | FF | 1 | R18C18[0][A] | uut/u_xcorr/ad_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C18[0][A] | uut/u_xcorr/ad_Z[3]/CLK
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/ad_Z[3]
1.588 | 0.011 | tHld |  | 1 | R18C18[0][A] | uut/u_xcorr/ad_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R9C2[2][B] | u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R9C2[2][B] | u_la0_top/triger_level_cnt_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[2]
11.648 | -0.035 | tSu |  | 1 | R9C2[2][B] | u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path2

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R3C4[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C4[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[0]
11.648 | -0.035 | tSu |  | 1 | R3C4[0][B] | u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path3

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[2]
11.648 | -0.035 | tSu |  | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path4

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_dly_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R11C10[2][A] | u_la0_top/internal_reg_start_dly_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R11C10[2][A] | u_la0_top/internal_reg_start_dly_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_dly_Z[1]
11.648 | -0.035 | tSu |  | 1 | R11C10[2][A] | u_la0_top/internal_reg_start_dly_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path5

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648 | -0.035 | tSu |  | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path6

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_force_triger_syn_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R8C3[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C3[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/internal_reg_force_triger_syn_Z[1]
11.648 | -0.035 | tSu |  | 1 | R8C3[1][B] | u_la0_top/internal_reg_force_triger_syn_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path7

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R9C2[2][A] | u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/capture_window_sel[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel[3]
11.648 | -0.035 | tSu |  | 1 | R9C2[2][A] | u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path8

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648 | -0.035 | tSu |  | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path9

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R5C2[2][A] | u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R5C2[2][A] | u_la0_top/capture_window_sel_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[1]
11.648 | -0.035 | tSu |  | 1 | R5C2[2][A] | u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path10

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_end_dly_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R4C11[1][B] | u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C11[1][B] | u_la0_top/capture_end_dly_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_end_dly_Z
11.648 | -0.035 | tSu |  | 1 | R4C11[1][B] | u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path11

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R8C7[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C7[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648 | -0.035 | tSu |  | 1 | R8C7[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path12

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R3C3[2][B] | u_la0_top/capture_window_sel_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C3[2][B] | u_la0_top/capture_window_sel_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[0]
11.648 | -0.035 | tSu |  | 1 | R3C3[2][B] | u_la0_top/capture_window_sel_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path13

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648 | -0.035 | tSu |  | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path14

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648 | -0.035 | tSu |  | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path15

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648 | -0.035 | tSu |  | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path16

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]
11.648 | -0.035 | tSu |  | 1 | R8C7[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[12]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path17

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648 | -0.035 | tSu |  | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path18

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R9C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R9C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648 | -0.035 | tSu |  | 1 | R9C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path19

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R4C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648 | -0.035 | tSu |  | 1 | R4C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path20

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/trigger_seq_start_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R6C9[2][A] | u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R6C9[2][A] | u_la0_top/trigger_seq_start_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/trigger_seq_start_Z
11.648 | -0.035 | tSu |  | 1 | R6C9[2][A] | u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path21

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
11.648 | -0.035 | tSu |  | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path22

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R3C7[1][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C7[1][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/genblk1.u_ao_match_0/match_sep
11.648 | -0.035 | tSu |  | 1 | R3C7[1][A] | u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path23

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648 | -0.035 | tSu |  | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path24

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R12C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648 | -0.035 | tSu |  | 1 | R12C3[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path25

Path Summary:

Slack | 1.853
Data Arrival Time | 9.796
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
9.796 | 2.648 | tNET | FF | 1 | R6C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R6C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648 | -0.035 | tSu |  | 1 | R6C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.648, 91.943%; tC2Q: 0.232, 8.057%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R9C2[2][B] | u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R9C2[2][B] | u_la0_top/triger_level_cnt_Z[2]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[2]
1.788 | 0.011 | tHld |  | 1 | R9C2[2][B] | u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path2

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R12C8[0][B] | u_la0_top/triger_level_cnt_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C8[0][B] | u_la0_top/triger_level_cnt_Z[3]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[3]
1.788 | 0.011 | tHld |  | 1 | R12C8[0][B] | u_la0_top/triger_level_cnt_Z[3]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path3

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R3C4[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C4[0][B] | u_la0_top/triger_level_cnt_Z[0]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[0]
1.788 | 0.011 | tHld |  | 1 | R3C4[0][B] | u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path4

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/triger_level_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R3C3[2][A] | u_la0_top/triger_level_cnt_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C3[2][A] | u_la0_top/triger_level_cnt_Z[1]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[1]
1.788 | 0.011 | tHld |  | 1 | R3C3[2][A] | u_la0_top/triger_level_cnt_Z[1]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path5

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_window_sel_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[2]
1.788 | 0.011 | tHld |  | 1 | R12C2[0][A] | u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path6

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/capture_end_dly_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R4C11[1][B] | u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R4C11[1][B] | u_la0_top/capture_end_dly_Z/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/capture_end_dly_Z
1.788 | 0.011 | tHld |  | 1 | R4C11[1][B] | u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path7

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R3C7[1][B] | u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C7[1][B] | u_la0_top/internal_reg_start_dly_Z[0]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_dly_Z[0]
1.788 | 0.011 | tHld |  | 1 | R3C7[1][B] | u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path8

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R8C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788 | 0.011 | tHld |  | 1 | R8C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path9

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R4C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R4C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788 | 0.011 | tHld |  | 1 | R4C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path10

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
1.788 | 0.011 | tHld |  | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path11

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788 | 0.011 | tHld |  | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path12

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R4C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R4C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788 | 0.011 | tHld |  | 1 | R4C11[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path13

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/internal_reg_start_syn_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R8C2[0][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C2[0][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/internal_reg_start_syn_Z[1]
1.788 | 0.011 | tHld |  | 1 | R8C2[0][B] | u_la0_top/internal_reg_start_syn_Z[1]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path14

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/trigger_seq_start_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R6C9[2][A] | u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R6C9[2][A] | u_la0_top/trigger_seq_start_Z/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/trigger_seq_start_Z
1.788 | 0.011 | tHld |  | 1 | R6C9[2][A] | u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path15

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
1.788 | 0.011 | tHld |  | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path16

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R4C11[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R4C11[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788 | 0.011 | tHld |  | 1 | R4C11[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path17

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
1.788 | 0.011 | tHld |  | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path18

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
1.788 | 0.011 | tHld |  | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path19

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788 | 0.011 | tHld |  | 1 | R9C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path20

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R3C7[1][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C7[1][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/genblk1.u_ao_match_0/match_sep
1.788 | 0.011 | tHld |  | 1 | R3C7[1][A] | u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path21

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R4C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R4C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788 | 0.011 | tHld |  | 1 | R4C11[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path22

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
1.788 | 0.011 | tHld |  | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path23

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788 | 0.011 | tHld |  | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path24

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R12C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788 | 0.011 | tHld |  | 1 | R12C3[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path25

Path Summary:

Slack | 6.748
Data Arrival Time | 8.536
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 474 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C2[2][B] | u_la0_top/rst_ao_Z/Q
8.536 | 1.744 | tNET | RR | 1 | R7C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 474 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R7C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788 | 0.011 | tHld |  | 1 | R7C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.744, 89.619%; tC2Q: 0.202, 10.381%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | ad_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | ad_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | ad_Z[0]/CLK

### MPW2

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | ad_Z[2]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | ad_Z[2]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | ad_Z[2]/CLK

### MPW3

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | ad_Z[6]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | ad_Z[6]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | ad_Z[6]/CLK

### MPW4

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/memy_memy_0_0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/memy_memy_0_0/CLKB

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/memy_memy_0_0/CLKB

### MPW5

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/memr_1_din_tmp_0[19]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/memr_1_din_tmp_0[19]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/memr_1_din_tmp_0[19]/CLK

### MPW6

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/memr_1_din_tmp_0[15]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/memr_1_din_tmp_0[15]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/memr_1_din_tmp_0[15]/CLK

### MPW7

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/memy_adreg_Z[5]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/memy_adreg_Z[5]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/memy_adreg_Z[5]/CLK

### MPW8

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/x_1_ret_0[13]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/x_1_ret_0[13]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/x_1_ret_0[13]/CLK

### MPW9

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/x_1_ret_0[12]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/x_1_ret_0[12]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/x_1_ret_0[12]/CLK

### MPW10

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/cnt_1_1[5]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/cnt_1_1[5]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/cnt_1_1[5]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
320 | clk_c | 1.489 | 1.228
196 | start | 2.763 | 2.325
35 | x_1_ret_33_0 | 6.510 | 2.055
34 | result_0_1[30] | 5.426 | 1.185
34 | x_1_ret_19_0 | 6.301 | 0.737
34 | x_1_ret_1_0 | 4.688 | 2.766
34 | memy_G_1 | 5.236 | 1.026
34 | N_48 | 3.719 | 1.859
33 | memr_1_G_1 | 1.489 | 1.076
27 | cnt9 | 2.763 | 1.399

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R17C28 | 0.681
R18C32 | 0.667
R17C23 | 0.583
R18C31 | 0.556
R18C49 | 0.528
R17C51 | 0.486
R17C27 | 0.458
R17C32 | 0.458
R10C16 | 0.444
R17C43 | 0.431

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---