@N: CD630 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/XCORR_1024-1_case/src/xcorr/temp/XCORR/rev_1/syntmp/gentmp2735XFQEN6":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0BTdBiJ":69:7:69:12|Synthesizing work.cmp_eq.cell_level.
@W: CD796 :"syng0BTdBiJ":92:11:92:18|Bit 5 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0BTdBiJ":92:11:92:18|Bit 6 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0BTdBiJ":92:11:92:18|Bit 7 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0BTdBiJ":92:11:92:18|Bit 8 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD796 :"syng0BTdBiJ":92:11:92:18|Bit 9 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@N: CD630 :"syng0BTdBiJ":6:7:6:16|Synthesizing work.eq_element.eqn.
@W: CD280 :"syng0BTdBiJ":15:11:15:17|Unbound component MUXCY_L mapped to black box
@N: CD630 :"syng0BTdBiJ":15:11:15:17|Synthesizing work.muxcy_l.syn_black_box.
Post processing for work.muxcy_l.syn_black_box
Running optimization stage 1 on MUXCY_L .......
Post processing for work.eq_element.eqn
Running optimization stage 1 on eq_element .......
Post processing for work.cmp_eq.cell_level
Running optimization stage 1 on CMP_EQ .......
Post processing for work.top.gen
Running optimization stage 1 on top .......
Running optimization stage 2 on MUXCY_L .......
Running optimization stage 2 on eq_element .......
Running optimization stage 2 on CMP_EQ .......
Running optimization stage 2 on top .......
