# Tue Feb 19 17:23:41 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-048

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1290R, Built Feb 12 2019 10:21:02


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\synplify\rev_1\XCORR_1024-1_case_scck.rpt 
Printing clock  summary report in "F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\synplify\rev_1\XCORR_1024-1_case_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 104MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 115MB peak: 117MB)

@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)



Clock Summary
******************

          Start       Requested     Requested     Clock        Clock                     Clock
Level     Clock       Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------
0 -       System      150.0 MHz     6.667         system       system_clkgroup           0    
                                                                                              
0 -       top|clk     81.2 MHz      12.314        inferred     Autoconstr_clkgroup_0     273  
==============================================================================================



Clock Load Summary
***********************

            Clock     Source        Clock Pin            Non-clock Pin     Non-clock Pin
Clock       Load      Pin           Seq Example          Seq Example       Comb Example 
----------------------------------------------------------------------------------------
System      0         -             -                    -                 -            
                                                                                        
top|clk     273       clk(port)     series_x[16:0].C     -                 -            
========================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 273 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       clk                 Unconstrained_port     273        ad[9]          
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\synplify\rev_1\XCORR_1024-1_case.sap.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 108MB peak: 195MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Tue Feb 19 17:23:43 2019

###########################################################]
