#Build: Synplify Pro (R) O-2018.09G-SP1, Build 099R, Feb 12 2019
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 7 6.1
#Hostname: GW-SW-048

# Tue Feb 19 17:24:15 2019

#Implementation: rev_1


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-048

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-048

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\gw_ao_parameter.v" (library work)
@I::"F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\gw_ao_top_define.v" (library work)
@I::"F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\gw_ao_expression.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":109:9:109:26|Net match_m0_en_reg_wr is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":110:9:110:26|Net match_m1_en_reg_wr is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":111:9:111:26|Net match_m2_en_reg_wr is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":112:9:112:27|Net match_ctl_en_reg_wr is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v":113:9:113:24|Net match_cnt_reg_wr is not declared.
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v":122:9:122:27|Net capture_length_zero is not declared.
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":500:9:500:20|Net start_reg_wr is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":503:9:503:29|Net trig_level_max_reg_wr is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":504:9:504:31|Net capture_mem_addr_max_wr is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":505:9:505:31|Net capture_mem_addr_rem_wr is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":506:9:506:30|Net capture_windows_num_wr is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1717:9:1717:18|Net match_en_0 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1718:9:1718:18|Net match_en_1 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1719:9:1719:18|Net match_en_2 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1720:9:1720:18|Net match_en_3 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1721:9:1721:18|Net match_en_4 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1722:9:1722:18|Net match_en_5 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1723:9:1723:18|Net match_en_6 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1724:9:1724:18|Net match_en_7 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1725:9:1725:18|Net match_en_8 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1726:9:1726:18|Net match_en_9 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1727:9:1727:19|Net match_en_10 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1728:9:1728:19|Net match_en_11 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1729:9:1729:19|Net match_en_12 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1730:9:1730:19|Net match_en_13 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1731:9:1731:19|Net match_en_14 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":1732:9:1732:19|Net match_en_15 is not declared.
@W: CG1337 :"C:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v":2213:9:2213:16|Net stop_reg is not declared.
Verilog syntax check successful!
@N: CG364 :"F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\gw_ao_parameter.v":1:0:1:8|Synthesizing module work_F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\gw_ao_parameter.v_unit in library work.
Selecting top level module ao_top_0
Running optimization stage 1 on ao_mem_ctrl_0_8192s_71s_13s .......
Running optimization stage 1 on ao_crc32_0 .......
Running optimization stage 1 on ao_match_0_0s_1s_71s_0_1_0_1_2_3_4 .......
Running optimization stage 1 on ao_top_0 .......
Running optimization stage 2 on ao_match_0_0s_1s_71s_0_1_0_1_2_3_4 .......
Running optimization stage 2 on ao_top_0 .......
Extracted state machine for register module_state
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1001
   1010
   1011
Running optimization stage 2 on ao_crc32_0 .......
Running optimization stage 2 on ao_mem_ctrl_0_8192s_71s_13s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\rev_1\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 84MB peak: 93MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Feb 19 17:24:16 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-048

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Feb 19 17:24:17 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Feb 19 17:24:17 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-048

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 115R, Built Feb 12 2019 09:25:38

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Feb 19 17:24:18 2019

###########################################################]
Premap Report

# Tue Feb 19 17:24:18 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-048

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1290R, Built Feb 12 2019 10:21:02


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\rev_1\ao_0_scck.rpt 
Printing clock  summary report in "F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\rev_1\ao_0_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

@N: BN133 |Ignoring syn_hier=hard property on top-level design.

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 103MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1001 -> 00100000000
   1010 -> 01000000000
   1011 -> 10000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 193MB)



Clock Summary
******************

          Start                   Requested     Requested     Clock        Clock                     Clock
Level     Clock                   Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------------------
0 -       ao_top_0|control[0]     186.5 MHz     5.362         inferred     Autoconstr_clkgroup_1     416  
                                                                                                          
0 -       ao_top_0|clk_i          237.7 MHz     4.207         inferred     Autoconstr_clkgroup_0     189  
==========================================================================================================



Clock Load Summary
***********************

                        Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin       
Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example        
--------------------------------------------------------------------------------------------------------------------------------------
ao_top_0|control[0]     416       control[0](port)     data_register[91:0].C                    -                 -                   
                                                                                                                                      
ao_top_0|clk_i          189       clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
======================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 535 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

============================= Non-Gated/Non-Generated Clocks =============================
Clock Tree ID     Driving Element     Drive Element Type        Fanout     Sample Instance
------------------------------------------------------------------------------------------
@KP:ckid0_0       ENCRYPTED           Unconstrained_port        119        ENCRYPTED      
@KP:ckid0_1       ENCRYPTED           Unconstrained_io_port     416        ENCRYPTED      
==========================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\rev_1\ao_0.sap.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 193MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 193MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Feb 19 17:24:20 2019

###########################################################]
Map & Optimize Report

# Tue Feb 19 17:24:21 2019


Copyright (C) 1994-2019 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-048

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1290R, Built Feb 12 2019 10:21:02


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N: MF284 |Setting synthesis effort to medium for the design


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 193MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 199MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 202MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 202MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 200MB peak: 202MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 200MB peak: 202MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 200MB peak: 202MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 200MB peak: 202MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 200MB peak: 202MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 219MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -2.53ns		 476 /       460
   2		0h:00m:03s		    -2.53ns		 482 /       460
   3		0h:00m:03s		    -2.47ns		 482 /       460
   4		0h:00m:03s		    -2.47ns		 482 /       460
Timing driven replication report
Added 2 Registers via timing driven replication
Added 2 LUTs via timing driven replication

   5		0h:00m:03s		    -2.33ns		 494 /       462
   6		0h:00m:03s		    -2.33ns		 494 /       462
   7		0h:00m:03s		    -2.30ns		 494 /       462


   8		0h:00m:03s		    -2.30ns		 493 /       462

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 218MB peak: 219MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 218MB peak: 219MB)


Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 145MB peak: 219MB)

Writing Analyst data base F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\impl\gao\ao_0\rev_1\synwork\ao_0_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 219MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 217MB peak: 219MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 215MB peak: 219MB)


Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 216MB peak: 219MB)

@W: MT420 |Found inferred clock ao_top_0|clk_i with period 4.47ns. Please declare a user-defined clock on port clk_i.
@W: MT420 |Found inferred clock ao_top_0|control[0] with period 5.41ns. Please declare a user-defined clock on port control[0].


##### START OF TIMING REPORT #####[
# Timing report written on Tue Feb 19 17:24:27 2019
#


Top view:               ao_top_0
Requested Frequency:    184.9 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -0.955

                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------
ao_top_0|clk_i          223.5 MHz     190.0 MHz     4.475         5.264         -0.790     inferred     Autoconstr_clkgroup_0
ao_top_0|control[0]     184.9 MHz     157.1 MHz     5.410         6.364         -0.955     inferred     Autoconstr_clkgroup_1
System                  150.0 MHz     230.7 MHz     6.667         4.334         2.333      system       system_clkgroup      
=============================================================================================================================





Clock Relationships
*******************

Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------
Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------
System               ao_top_0|clk_i       |  4.475       2.333   |  No paths    -      |  No paths    -      |  No paths    -    
System               ao_top_0|control[0]  |  5.410       3.389   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       System               |  4.475       3.514   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       ao_top_0|clk_i       |  4.475       -0.790  |  4.475       3.636  |  No paths    -      |  2.237       1.398
ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  System               |  5.410       4.632   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|control[0]  |  5.410       -0.955  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ao_top_0|clk_i
====================================



Starting Points with Worst Slack
********************************

                                     Starting                                                                 Arrival           
Instance                             Reference          Type     Pin     Net                                  Time        Slack 
                                     Clock                                                                                      
--------------------------------------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]     ao_top_0|clk_i     DFFC     Q       internal_reg_force_triger_syn[1]     0.243       -0.790
genblk1\.u_ao_match_0.match_sep      ao_top_0|clk_i     DFFC     Q       match                                0.243       -0.769
triger_level_cnt[2]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[2]                  0.243       -0.682
capture_window_sel[1]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[1]                0.243       -0.672
capture_window_sel[0]                ao_top_0|clk_i     DFFC     Q       capture_window_sel[0]                0.243       -0.651
u_ao_mem_ctrl.capture_length[0]      ao_top_0|clk_i     DFFC     Q       capture_length[0]                    0.243       -0.600
triger_level_cnt[3]                  ao_top_0|clk_i     DFFC     Q       triger_level_cnt[3]                  0.243       -0.591
u_ao_mem_ctrl.capture_length[1]      ao_top_0|clk_i     DFFC     Q       capture_length[1]                    0.243       -0.492
u_ao_mem_ctrl.capture_length[2]      ao_top_0|clk_i     DFFC     Q       capture_length[2]                    0.243       -0.457
u_ao_mem_ctrl.capture_length[3]      ao_top_0|clk_i     DFFP     Q       capture_length[3]                    0.243       -0.422
================================================================================================================================


Ending Points with Worst Slack
******************************

                                      Starting                                                         Required           
Instance                              Reference          Type      Pin     Net                         Time         Slack 
                                      Clock                                                                               
--------------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr          ao_top_0|clk_i     DFFCE     CE      g0                          4.414        -0.790
u_ao_mem_ctrl.mem_addr_inc_en         ao_top_0|clk_i     DFFCE     CE      un1_capture_length_zero     4.414        -0.654
u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     CE      un1_mem_addr_inc_en6        4.414        -0.059
u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[0]      4.414        -0.059
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[1]      4.414        -0.059
u_ao_mem_ctrl.capture_mem_addr[2]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[2]      4.414        -0.059
u_ao_mem_ctrl.capture_mem_addr[3]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[3]      4.414        -0.059
u_ao_mem_ctrl.capture_mem_addr[4]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[4]      4.414        -0.059
u_ao_mem_ctrl.capture_mem_addr[5]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[5]      4.414        -0.059
u_ao_mem_ctrl.capture_mem_addr[6]     ao_top_0|clk_i     DFFCE     D       capture_mem_addr_lm[6]      4.414        -0.059
==========================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.475
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.414

    - Propagation time:                      5.203
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.790

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                 Type      Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]     DFFC      Q        Out     0.243     0.243       -         
internal_reg_force_triger_syn[1]     Net       -        -       0.535     -           1         
un1_match_final_3                    LUT4      I1       In      -         0.778       -         
un1_match_final_3                    LUT4      F        Out     0.570     1.348       -         
un1_match_final_3                    Net       -        -       0.401     -           1         
match_final                          LUT4      I3       In      -         1.749       -         
match_final                          LUT4      F        Out     0.371     2.120       -         
match_final                          Net       -        -       0.535     -           6         
triger_level_cnt_0_sqmuxa            LUT4      I0       In      -         2.655       -         
triger_level_cnt_0_sqmuxa            LUT4      F        Out     0.549     3.204       -         
triger_level_cnt_0_sqmuxa            Net       -        -       0.657     -           21        
u_ao_mem_ctrl.g0_1                   LUT4      I3       In      -         3.861       -         
u_ao_mem_ctrl.g0_1                   LUT4      F        Out     0.371     4.232       -         
g0_1                                 Net       -        -       0.401     -           1         
u_ao_mem_ctrl.g0                     LUT4      I1       In      -         4.633       -         
u_ao_mem_ctrl.g0                     LUT4      F        Out     0.570     5.203       -         
g0                                   Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr         DFFCE     CE       In      -         5.203       -         
================================================================================================
Total path delay (propagation time + setup) of 5.264 is 2.735(52.0%) logic and 2.529(48.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.475
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.414

    - Propagation time:                      5.182
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.769

    Number of logic level(s):                5
    Starting point:                          genblk1\.u_ao_match_0.match_sep / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
genblk1\.u_ao_match_0.match_sep     DFFC      Q        Out     0.243     0.243       -         
match                               Net       -        -       0.535     -           1         
un1_match_final_3                   LUT4      I0       In      -         0.778       -         
un1_match_final_3                   LUT4      F        Out     0.549     1.327       -         
un1_match_final_3                   Net       -        -       0.401     -           1         
match_final                         LUT4      I3       In      -         1.728       -         
match_final                         LUT4      F        Out     0.371     2.099       -         
match_final                         Net       -        -       0.535     -           6         
triger_level_cnt_0_sqmuxa           LUT4      I0       In      -         2.634       -         
triger_level_cnt_0_sqmuxa           LUT4      F        Out     0.549     3.183       -         
triger_level_cnt_0_sqmuxa           Net       -        -       0.657     -           21        
u_ao_mem_ctrl.g0_1                  LUT4      I3       In      -         3.840       -         
u_ao_mem_ctrl.g0_1                  LUT4      F        Out     0.371     4.211       -         
g0_1                                Net       -        -       0.401     -           1         
u_ao_mem_ctrl.g0                    LUT4      I1       In      -         4.612       -         
u_ao_mem_ctrl.g0                    LUT4      F        Out     0.570     5.182       -         
g0                                  Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr        DFFCE     CE       In      -         5.182       -         
===============================================================================================
Total path delay (propagation time + setup) of 5.243 is 2.714(51.8%) logic and 2.529(48.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.475
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.414

    - Propagation time:                      5.095
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.682

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[2] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
triger_level_cnt[2]              DFFC      Q        Out     0.243     0.243       -         
triger_level_cnt[2]              Net       -        -       0.535     -           4         
un1_match_final_3                LUT4      I2       In      -         0.778       -         
un1_match_final_3                LUT4      F        Out     0.462     1.240       -         
un1_match_final_3                Net       -        -       0.401     -           1         
match_final                      LUT4      I3       In      -         1.641       -         
match_final                      LUT4      F        Out     0.371     2.012       -         
match_final                      Net       -        -       0.535     -           6         
triger_level_cnt_0_sqmuxa        LUT4      I0       In      -         2.547       -         
triger_level_cnt_0_sqmuxa        LUT4      F        Out     0.549     3.096       -         
triger_level_cnt_0_sqmuxa        Net       -        -       0.657     -           21        
u_ao_mem_ctrl.g0_1               LUT4      I3       In      -         3.753       -         
u_ao_mem_ctrl.g0_1               LUT4      F        Out     0.371     4.124       -         
g0_1                             Net       -        -       0.401     -           1         
u_ao_mem_ctrl.g0                 LUT4      I1       In      -         4.525       -         
u_ao_mem_ctrl.g0                 LUT4      F        Out     0.570     5.095       -         
g0                               Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr     DFFCE     CE       In      -         5.095       -         
============================================================================================
Total path delay (propagation time + setup) of 5.156 is 2.627(50.9%) logic and 2.529(49.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.475
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.414

    - Propagation time:                      5.085
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.672

    Number of logic level(s):                5
    Starting point:                          capture_window_sel[1] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
capture_window_sel[1]            DFFC      Q        Out     0.243     0.243       -         
capture_window_sel[1]            Net       -        -       0.535     -           5         
un6_start_reg_c2                 LUT4      I1       In      -         0.778       -         
un6_start_reg_c2                 LUT4      F        Out     0.570     1.348       -         
un6_start_reg_c2                 Net       -        -       0.401     -           1         
un6_start_reg_ac0_5_0            LUT4      I3       In      -         1.749       -         
un6_start_reg_ac0_5_0            LUT4      F        Out     0.371     2.120       -         
un6_start_reg_ac0_5_0            Net       -        -       0.535     -           3         
start_reg                        LUT3      I2       In      -         2.655       -         
start_reg                        LUT3      F        Out     0.462     3.117       -         
start_reg                        Net       -        -       0.535     -           3         
u_ao_mem_ctrl.g0_1               LUT4      I2       In      -         3.652       -         
u_ao_mem_ctrl.g0_1               LUT4      F        Out     0.462     4.114       -         
g0_1                             Net       -        -       0.401     -           1         
u_ao_mem_ctrl.g0                 LUT4      I1       In      -         4.515       -         
u_ao_mem_ctrl.g0                 LUT4      F        Out     0.570     5.085       -         
g0                               Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr     DFFCE     CE       In      -         5.085       -         
============================================================================================
Total path delay (propagation time + setup) of 5.146 is 2.739(53.2%) logic and 2.407(46.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.475
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.414

    - Propagation time:                      5.068
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.654

    Number of logic level(s):                6
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                          Type          Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]              DFFC          Q        Out     0.243     0.243       -         
internal_reg_force_triger_syn[1]              Net           -        -       0.535     -           1         
un1_match_final_3                             LUT4          I1       In      -         0.778       -         
un1_match_final_3                             LUT4          F        Out     0.570     1.348       -         
un1_match_final_3                             Net           -        -       0.401     -           1         
match_final                                   LUT4          I3       In      -         1.749       -         
match_final                                   LUT4          F        Out     0.371     2.120       -         
match_final                                   Net           -        -       0.535     -           6         
triger_level_cnt_0_sqmuxa                     LUT4          I0       In      -         2.655       -         
triger_level_cnt_0_sqmuxa                     LUT4          F        Out     0.549     3.204       -         
triger_level_cnt_0_sqmuxa                     Net           -        -       0.657     -           21        
u_ao_mem_ctrl.un1_capture_length_zero_0_1     LUT4          I2       In      -         3.861       -         
u_ao_mem_ctrl.un1_capture_length_zero_0_1     LUT4          F        Out     0.462     4.323       -         
un1_capture_length_zero_0_1                   Net           -        -       0.000     -           1         
u_ao_mem_ctrl.un1_capture_length_zero_0       MUX2_LUT5     I1       In      -         4.323       -         
u_ao_mem_ctrl.un1_capture_length_zero_0       MUX2_LUT5     O        Out     0.105     4.428       -         
un1_capture_length_zero_0                     Net           -        -       0.000     -           1         
u_ao_mem_ctrl.un1_capture_length_zero         MUX2_LUT6     I0       In      -         4.428       -         
u_ao_mem_ctrl.un1_capture_length_zero         MUX2_LUT6     O        Out     0.105     4.533       -         
un1_capture_length_zero                       Net           -        -       0.535     -           1         
u_ao_mem_ctrl.mem_addr_inc_en                 DFFCE         CE       In      -         5.068       -         
=============================================================================================================
Total path delay (propagation time + setup) of 5.129 is 2.466(48.1%) logic and 2.663(51.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: ao_top_0|control[0]
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                                   Arrival           
Instance                         Reference               Type      Pin     Net                              Time        Slack 
                                 Clock                                                                                        
------------------------------------------------------------------------------------------------------------------------------
internal_register_select[13]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[13]     0.243       -0.955
internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.243       -0.934
internal_register_select[12]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[12]     0.243       -0.934
internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.243       -0.913
internal_register_select[14]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[14]     0.243       -0.847
internal_register_select[10]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[10]     0.243       -0.826
internal_register_select[15]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[15]     0.243       -0.756
internal_register_select[11]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[11]     0.243       -0.735
word_count[10]                   ao_top_0|control[0]     DFFCE     Q       word_count[10]                   0.243       -0.706
word_count[0]                    ao_top_0|control[0]     DFFCE     Q       word_count[0]                    0.243       -0.685
==============================================================================================================================


Ending Points with Worst Slack
******************************

                          Starting                                                              Required           
Instance                  Reference               Type      Pin     Net                         Time         Slack 
                          Clock                                                                                    
-------------------------------------------------------------------------------------------------------------------
data_out_shift_reg[0]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[0]     5.349        -0.955
address_counter[0]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.349        -0.706
address_counter[1]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.349        -0.706
address_counter[2]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.349        -0.706
address_counter[3]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.349        -0.706
address_counter[4]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.349        -0.706
address_counter[5]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.349        -0.706
address_counter[6]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.349        -0.706
address_counter[7]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.349        -0.706
address_counter[8]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  5.349        -0.706
===================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      5.410
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.349

    - Propagation time:                      6.303
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.955

    Number of logic level(s):                6
    Starting point:                          internal_register_select[13] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
internal_register_select[13]     DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[13]     Net       -        -       0.535     -           1         
match_unit_rd_en_2_5[0]          LUT4      I1       In      -         0.778       -         
match_unit_rd_en_2_5[0]          LUT4      F        Out     0.570     1.348       -         
match_unit_rd_en_2_5[0]          Net       -        -       0.535     -           8         
match_unit_rd_en_2[0]            LUT2      I1       In      -         1.883       -         
match_unit_rd_en_2[0]            LUT2      F        Out     0.570     2.453       -         
internal_reg_start_m_14          Net       -        -       0.535     -           6         
match_unit_rd_en[0]              LUT4      I0       In      -         2.988       -         
match_unit_rd_en[0]              LUT4      F        Out     0.549     3.537       -         
match_unit_rd_en[0]              Net       -        -       0.535     -           1         
genblk1\.u_ao_match_0.N_88_i     LUT3      I2       In      -         4.072       -         
genblk1\.u_ao_match_0.N_88_i     LUT3      F        Out     0.462     4.534       -         
data_from_match_unit[0]          Net       -        -       0.535     -           1         
data_from_ao_reg_6[0]            LUT4      I3       In      -         5.069       -         
data_from_ao_reg_6[0]            LUT4      F        Out     0.371     5.440       -         
data_from_ao_reg_6[0]            Net       -        -       0.401     -           1         
data_out_shift_reg_4[0]          LUT4      I2       In      -         5.841       -         
data_out_shift_reg_4[0]          LUT4      F        Out     0.462     6.303       -         
data_out_shift_reg_4[0]          Net       -        -       0.000     -           1         
data_out_shift_reg[0]            DFFCE     D        In      -         6.303       -         
============================================================================================
Total path delay (propagation time + setup) of 6.364 is 3.288(51.7%) logic and 3.076(48.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.410
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.349

    - Propagation time:                      6.282
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.934

    Number of logic level(s):                6
    Starting point:                          internal_register_select[9] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
internal_register_select[9]      DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[9]      Net       -        -       0.535     -           1         
match_unit_rd_en_2_4[0]          LUT4      I1       In      -         0.778       -         
match_unit_rd_en_2_4[0]          LUT4      F        Out     0.570     1.348       -         
match_unit_rd_en_2_4[0]          Net       -        -       0.535     -           8         
match_unit_rd_en_2[0]            LUT2      I0       In      -         1.883       -         
match_unit_rd_en_2[0]            LUT2      F        Out     0.549     2.432       -         
internal_reg_start_m_14          Net       -        -       0.535     -           6         
match_unit_rd_en[0]              LUT4      I0       In      -         2.967       -         
match_unit_rd_en[0]              LUT4      F        Out     0.549     3.516       -         
match_unit_rd_en[0]              Net       -        -       0.535     -           1         
genblk1\.u_ao_match_0.N_88_i     LUT3      I2       In      -         4.051       -         
genblk1\.u_ao_match_0.N_88_i     LUT3      F        Out     0.462     4.513       -         
data_from_match_unit[0]          Net       -        -       0.535     -           1         
data_from_ao_reg_6[0]            LUT4      I3       In      -         5.048       -         
data_from_ao_reg_6[0]            LUT4      F        Out     0.371     5.419       -         
data_from_ao_reg_6[0]            Net       -        -       0.401     -           1         
data_out_shift_reg_4[0]          LUT4      I2       In      -         5.820       -         
data_out_shift_reg_4[0]          LUT4      F        Out     0.462     6.282       -         
data_out_shift_reg_4[0]          Net       -        -       0.000     -           1         
data_out_shift_reg[0]            DFFCE     D        In      -         6.282       -         
============================================================================================
Total path delay (propagation time + setup) of 6.343 is 3.267(51.5%) logic and 3.076(48.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.410
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.349

    - Propagation time:                      6.282
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.934

    Number of logic level(s):                6
    Starting point:                          internal_register_select[12] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
internal_register_select[12]     DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[12]     Net       -        -       0.535     -           1         
match_unit_rd_en_2_5[0]          LUT4      I0       In      -         0.778       -         
match_unit_rd_en_2_5[0]          LUT4      F        Out     0.549     1.327       -         
match_unit_rd_en_2_5[0]          Net       -        -       0.535     -           8         
match_unit_rd_en_2[0]            LUT2      I1       In      -         1.862       -         
match_unit_rd_en_2[0]            LUT2      F        Out     0.570     2.432       -         
internal_reg_start_m_14          Net       -        -       0.535     -           6         
match_unit_rd_en[0]              LUT4      I0       In      -         2.967       -         
match_unit_rd_en[0]              LUT4      F        Out     0.549     3.516       -         
match_unit_rd_en[0]              Net       -        -       0.535     -           1         
genblk1\.u_ao_match_0.N_88_i     LUT3      I2       In      -         4.051       -         
genblk1\.u_ao_match_0.N_88_i     LUT3      F        Out     0.462     4.513       -         
data_from_match_unit[0]          Net       -        -       0.535     -           1         
data_from_ao_reg_6[0]            LUT4      I3       In      -         5.048       -         
data_from_ao_reg_6[0]            LUT4      F        Out     0.371     5.419       -         
data_from_ao_reg_6[0]            Net       -        -       0.401     -           1         
data_out_shift_reg_4[0]          LUT4      I2       In      -         5.820       -         
data_out_shift_reg_4[0]          LUT4      F        Out     0.462     6.282       -         
data_out_shift_reg_4[0]          Net       -        -       0.000     -           1         
data_out_shift_reg[0]            DFFCE     D        In      -         6.282       -         
============================================================================================
Total path delay (propagation time + setup) of 6.343 is 3.267(51.5%) logic and 3.076(48.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.410
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.349

    - Propagation time:                      6.261
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.913

    Number of logic level(s):                6
    Starting point:                          internal_register_select[7] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
internal_register_select[7]      DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[7]      Net       -        -       0.535     -           1         
match_unit_rd_en_2_4[0]          LUT4      I0       In      -         0.778       -         
match_unit_rd_en_2_4[0]          LUT4      F        Out     0.549     1.327       -         
match_unit_rd_en_2_4[0]          Net       -        -       0.535     -           8         
match_unit_rd_en_2[0]            LUT2      I0       In      -         1.862       -         
match_unit_rd_en_2[0]            LUT2      F        Out     0.549     2.411       -         
internal_reg_start_m_14          Net       -        -       0.535     -           6         
match_unit_rd_en[0]              LUT4      I0       In      -         2.946       -         
match_unit_rd_en[0]              LUT4      F        Out     0.549     3.495       -         
match_unit_rd_en[0]              Net       -        -       0.535     -           1         
genblk1\.u_ao_match_0.N_88_i     LUT3      I2       In      -         4.030       -         
genblk1\.u_ao_match_0.N_88_i     LUT3      F        Out     0.462     4.492       -         
data_from_match_unit[0]          Net       -        -       0.535     -           1         
data_from_ao_reg_6[0]            LUT4      I3       In      -         5.027       -         
data_from_ao_reg_6[0]            LUT4      F        Out     0.371     5.398       -         
data_from_ao_reg_6[0]            Net       -        -       0.401     -           1         
data_out_shift_reg_4[0]          LUT4      I2       In      -         5.799       -         
data_out_shift_reg_4[0]          LUT4      F        Out     0.462     6.261       -         
data_out_shift_reg_4[0]          Net       -        -       0.000     -           1         
data_out_shift_reg[0]            DFFCE     D        In      -         6.261       -         
============================================================================================
Total path delay (propagation time + setup) of 6.322 is 3.246(51.3%) logic and 3.076(48.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.410
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.349

    - Propagation time:                      6.195
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.847

    Number of logic level(s):                6
    Starting point:                          internal_register_select[14] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                             Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
internal_register_select[14]     DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[14]     Net       -        -       0.535     -           1         
match_unit_rd_en_2_5[0]          LUT4      I2       In      -         0.778       -         
match_unit_rd_en_2_5[0]          LUT4      F        Out     0.462     1.240       -         
match_unit_rd_en_2_5[0]          Net       -        -       0.535     -           8         
match_unit_rd_en_2[0]            LUT2      I1       In      -         1.775       -         
match_unit_rd_en_2[0]            LUT2      F        Out     0.570     2.345       -         
internal_reg_start_m_14          Net       -        -       0.535     -           6         
match_unit_rd_en[0]              LUT4      I0       In      -         2.880       -         
match_unit_rd_en[0]              LUT4      F        Out     0.549     3.429       -         
match_unit_rd_en[0]              Net       -        -       0.535     -           1         
genblk1\.u_ao_match_0.N_88_i     LUT3      I2       In      -         3.964       -         
genblk1\.u_ao_match_0.N_88_i     LUT3      F        Out     0.462     4.426       -         
data_from_match_unit[0]          Net       -        -       0.535     -           1         
data_from_ao_reg_6[0]            LUT4      I3       In      -         4.961       -         
data_from_ao_reg_6[0]            LUT4      F        Out     0.371     5.332       -         
data_from_ao_reg_6[0]            Net       -        -       0.401     -           1         
data_out_shift_reg_4[0]          LUT4      I2       In      -         5.733       -         
data_out_shift_reg_4[0]          LUT4      F        Out     0.462     6.195       -         
data_out_shift_reg_4[0]          Net       -        -       0.000     -           1         
data_out_shift_reg[0]            DFFCE     D        In      -         6.195       -         
============================================================================================
Total path delay (propagation time + setup) of 6.256 is 3.180(50.8%) logic and 3.076(49.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                           Arrival          
Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                         Clock                                                               
-------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       2.333
address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       3.389
=============================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                                        Required          
Instance                      Reference     Type      Pin     Net                             Time         Slack
                              Clock                                                                             
----------------------------------------------------------------------------------------------------------------
capture_window_sel[2]         System        DFFC      D       capture_window_sel_3[2]         4.414        2.333
capture_window_sel[3]         System        DFFC      D       capture_window_sel_3[3]         4.414        2.333
capture_window_sel[1]         System        DFFC      D       capture_window_sel_3[1]         4.414        2.558
capture_window_sel[0]         System        DFFC      D       capture_window_sel_3[0]         4.414        3.330
internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]     4.414        3.330
address_counter[12]           System        DFFCE     D       address_counter_s[12]           5.349        3.389
address_counter[11]           System        DFFCE     D       address_counter_s[11]           5.349        3.424
address_counter[10]           System        DFFCE     D       address_counter_s[10]           5.349        3.459
address_counter[9]            System        DFFCE     D       address_counter_s[9]            5.349        3.494
address_counter[8]            System        DFFCE     D       address_counter_s[8]            5.349        3.529
================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      4.475
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.414

    - Propagation time:                      2.081
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 2.333

    Number of logic level(s):                2
    Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
    Ending point:                            capture_window_sel[2] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     INV      O        Out     0.000     0.000       -         
capture_end                              Net      -        -       0.535     -           6         
un1_capture_window_sel_ac0_1             LUT4     I0       In      -         0.535       -         
un1_capture_window_sel_ac0_1             LUT4     F        Out     0.549     1.084       -         
un1_capture_window_sel_c2                Net      -        -       0.535     -           2         
capture_window_sel_3[2]                  LUT3     I2       In      -         1.619       -         
capture_window_sel_3[2]                  LUT3     F        Out     0.462     2.081       -         
capture_window_sel_3[2]                  Net      -        -       0.000     -           1         
capture_window_sel[2]                    DFFC     D        In      -         2.081       -         
===================================================================================================
Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 216MB peak: 219MB)


Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 216MB peak: 219MB)

---------------------------------------
Resource Usage Report for ao_top_0 

Mapping to part: gw2a_55pbga484-8
Cell usage:
ALU             83 uses
DFF             70 uses
DFFC            47 uses
DFFCE           306 uses
DFFNP           2 uses
DFFP            5 uses
DFFPE           32 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       6 uses
MUX2_LUT6       3 uses
SDP             36 uses
LUT2            53 uses
LUT3            89 uses
LUT4            296 uses

I/O ports: 82
I/O primitives: 82
IBUF           80 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   462 of 41040 (1%)

RAM/ROM usage summary
Block Rams : 36 of 140 (25%)

Total load per clock:
   ao_top_0|clk_i: 1
   ao_top_0|control[0]: 380

@S |Mapping Summary:
Total  LUTs: 438 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 46MB peak: 219MB)

Process took 0h:00m:07s realtime, 0h:00m:06s cputime
# Tue Feb 19 17:24:28 2019

###########################################################]
