# Tue Dec 18 16:24:33 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1226R, Built Nov 21 2018 00:28:10


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synthesize/rev_1/XCORR_512-3_case_scck.rpt 
Printing clock  summary report in "/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synthesize/rev_1/XCORR_512-3_case_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 103MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)

@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.

Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

@N: MF974 |Total number of latches (multibit) processed = 0 
@N: MF975 |Total number of latches (bit blasted) processed = 0 
@N: MF976 |Total number of (multibit) opaque latches found = 0 
@N: MF977 |Total number of (bit blasted) opaque latches found = 0 

Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)







Detailed report for transparent and observable latches in design:
@L: /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synthesize/rev_1/synwork/XCORR_512-3_case_prem_latch_transparency_report.log

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

syn_allowed_resources : blockrams=140  set on top level netlist top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)



Clock Summary
******************

          Start       Requested     Requested     Clock        Clock                     Clock
Level     Clock       Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------
0 -       System      150.0 MHz     6.667         system       system_clkgroup           0    
                                                                                              
0 -       top|clk     79.3 MHz      12.607        inferred     Autoconstr_clkgroup_0     352  
==============================================================================================



Clock Load Summary
***********************

            Clock     Source        Clock Pin            Non-clock Pin     Non-clock Pin
Clock       Load      Pin           Seq Example          Seq Example       Comb Example 
----------------------------------------------------------------------------------------
System      0         -             -                    -                 -            
                                                                                        
top|clk     352       clk(port)     series_x[16:0].C     -                 -            
========================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 352 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       clk                 Unconstrained_port     352        ad[8]          
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_512-3_case/project/impl/synthesize/rev_1/XCORR_512-3_case.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 193MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 107MB peak: 193MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Dec 18 16:24:35 2018

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