Timing Analysis Report

# Timing Messages

Report Title | Gowin Timing Analysis Report
Design File | F:/user-bak/Users/FDELL/Desktop/IP/CrossCrorelation/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synplify/rev_1/XCORR_1024-1_case.vm
Physical Constraints File | F:\user-bak\Users\FDELL\Desktop\IP\CrossCrorelation\Gowin_XCORR_RefDesign\XCORR_1024-1_case\project\src\XCORR_1024-1_case.cst
Timing Constraints File | ---
GOWIN version | v1.9.0Beta
Part Number | GW2A-LV55PG484C8/I7
Created Time | Tue Feb 19 17:24:46 2019
Legal Announcement | Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 0.95V 85C
Hold Delay Model | Fast 1.05V 0C
Numbers of Paths Analyzed | 1606
Numbers of Endpoints Analyzed | 4594
Numbers of Falling Endpoints | 1
Numbers of Setup Violated Endpoints | 0
Numbers of Hold Violated Endpoints | 0

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
DEFAULT_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  |

## Max Frequency Summary:

NO. | Clock Name | Fmax | Entity
--- | --- | --- | ---
1 | DEFAULT_CLK | 124.676(MHz) | TOP

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
DEFAULT_CLK | Setup | 0.000 | 0
DEFAULT_CLK | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
2 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
3 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
4 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
5 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
6 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
7 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
8 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
9 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
10 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
11 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
12 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
13 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
14 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
15 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
16 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
17 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
18 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
19 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
20 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
21 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
22 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
23 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
24 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
25 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.213 | u_la0_top/u_ao_mem_ctrl/data_reg_Z[52]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/DI0 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.462
2 | 0.307 | u_la0_top/internal_reg_force_triger_syn_Z[0]/Q | u_la0_top/internal_reg_force_triger_syn_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.318
3 | 0.307 | ut/isOk_r_Z[0]/Q | ut/isOk_r_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.318
4 | 0.314 | uut/u_xcorr/memr_1_adreg_Z[9]/Q | uut/u_xcorr/memr_1_waddr_tmp_0[9]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.325
5 | 0.334 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/ADA10 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.452
6 | 0.335 | u_la0_top/u_ao_mem_ctrl/data_reg_Z[43]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/DI1 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.584
7 | 0.337 | u_la0_top/u_ao_mem_ctrl/data_reg_Z[53]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/DI1 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.586
8 | 0.342 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/ADA6 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.460
9 | 0.350 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/ADA5 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.468
10 | 0.351 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_31/ADA11 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.469
11 | 0.353 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/ADA7 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.471
12 | 0.359 | ad_Z[8]/Q | series_y_2_0_2/AD12 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.477
13 | 0.361 | ad_Z[9]/Q | series_y_2_0_2/AD13 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.479
14 | 0.363 | u_la0_top/u_ao_mem_ctrl/data_reg_Z[42]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/DI0 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.612
15 | 0.364 | uut/u_xcorr/cnt_1_0[0]/Q | uut/u_xcorr/memy_1_memy_1_0_0/ADB4 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.482
16 | 0.364 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA1 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.482
17 | 0.365 | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA12 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.483
18 | 0.378 | uut/u_xcorr/cnt_1_0[1]/Q | uut/u_xcorr/memy_1_memy_1_0_0/ADB5 | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.496
19 | 0.425 | ut/cnt_r_Z[3]/Q | ut/cnt_r_Z[3]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436
20 | 0.425 | ut/cnt_r_Z[0]/Q | ut/cnt_r_Z[0]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.436
21 | 0.427 | u_la0_top/triger_level_cnt_Z[2]/Q | u_la0_top/triger_level_cnt_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438
22 | 0.427 | uut/u_xcorr/delay_1_Z[4]/Q | uut/u_xcorr/delay_1_Z[4]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438
23 | 0.427 | uut/u_xcorr/delay_1_Z[6]/Q | uut/u_xcorr/delay_1_Z[6]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.438
24 | 0.428 | u_la0_top/capture_window_sel_Z[2]/Q | u_la0_top/capture_window_sel_Z[2]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.439
25 | 0.428 | u_la0_top/triger_level_cnt_Z[1]/Q | u_la0_top/triger_level_cnt_Z[1]/D | DEFAULT_CLK:[R] | DEFAULT_CLK:[R] | 0.000 | 0.000 | 0.439

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
2 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
3 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
4 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
5 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
6 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
7 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
8 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
9 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
10 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
11 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
12 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
13 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
14 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
15 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
16 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
17 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
18 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
19 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
20 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
21 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
22 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
23 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
24 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818
25 | 1.914 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | 5.000 | 0.033 | 2.818

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
2 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
3 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
4 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
5 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
6 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
7 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
8 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
9 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
10 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
11 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
12 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
13 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
14 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
15 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
16 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
17 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
18 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
19 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
20 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
21 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
22 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
23 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
24 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821
25 | 6.623 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR | DEFAULT_CLK:[F] | DEFAULT_CLK:[R] | -5.000 | 0.013 | 1.821

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | ad_Z[0]
2 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | ad_Z[2]
3 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | ad_Z[6]
4 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/memr_1_memr_1_0_1
5 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/cnt_1_0[0]
6 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/memr_1_din_tmp_0[2]
7 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/result_Z[20]
8 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | u_la0_top/capture_window_sel[3]
9 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | u_la0_top/internal_reg_start_dly_Z[0]
10 | 3.662 | 4.662 | 1.000 | Low Pulse Width | DEFAULT_CLK | uut/u_xcorr/result_Z[19]

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648 | -0.035 | tSu |  | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path2

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R4C5[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C5[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
11.648 | -0.035 | tSu |  | 1 | R4C5[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path3

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
11.648 | -0.035 | tSu |  | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path4

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
11.648 | -0.035 | tSu |  | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path5

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
11.648 | -0.035 | tSu |  | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path6

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648 | -0.035 | tSu |  | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path7

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648 | -0.035 | tSu |  | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path8

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648 | -0.035 | tSu |  | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path9

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
11.648 | -0.035 | tSu |  | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path10

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
11.648 | -0.035 | tSu |  | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path11

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648 | -0.035 | tSu |  | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path12

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
11.648 | -0.035 | tSu |  | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path13

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648 | -0.035 | tSu |  | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path14

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
11.648 | -0.035 | tSu |  | 1 | R7C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path15

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
11.648 | -0.035 | tSu |  | 1 | R7C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path16

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648 | -0.035 | tSu |  | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path17

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648 | -0.035 | tSu |  | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path18

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648 | -0.035 | tSu |  | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path19

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648 | -0.035 | tSu |  | 1 | R8C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path20

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648 | -0.035 | tSu |  | 1 | R8C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path21

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
11.648 | -0.035 | tSu |  | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path22

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
11.648 | -0.035 | tSu |  | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path23

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
11.648 | -0.035 | tSu |  | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path24

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R12C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
11.648 | -0.035 | tSu |  | 1 | R12C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path25

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R12C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648 | -0.035 | tSu |  | 1 | R12C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.213
Data Arrival Time | 2.040
Data Required Time | 1.826
From | u_la0_top/u_ao_mem_ctrl/data_reg_Z[52]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[52]/CLK
1.779 | 0.202 | tC2Q | RR | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[52]/Q
2.040 | 0.260 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/DI0

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
1.826 | 0.249 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path2

Path Summary:

Slack | 0.307
Data Arrival Time | 1.895
Data Required Time | 1.588
From | u_la0_top/internal_reg_force_triger_syn_Z[0]
To | u_la0_top/internal_reg_force_triger_syn_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R7C8[0][B] | u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
1.778 | 0.201 | tC2Q | RF | 1 | R7C8[0][B] | u_la0_top/internal_reg_force_triger_syn_Z[0]/Q
1.895 | 0.117 | tNET | FF | 1 | R7C8[0][A] | u_la0_top/internal_reg_force_triger_syn_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R7C8[0][A] | u_la0_top/internal_reg_force_triger_syn_Z[1]/CLK
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/internal_reg_force_triger_syn_Z[1]
1.588 | 0.011 | tHld |  | 1 | R7C8[0][A] | u_la0_top/internal_reg_force_triger_syn_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path3

Path Summary:

Slack | 0.307
Data Arrival Time | 1.895
Data Required Time | 1.588
From | ut/isOk_r_Z[0]
To | ut/isOk_r_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C36[2][A] | ut/isOk_r_Z[0]/CLK
1.778 | 0.201 | tC2Q | RF | 1 | R17C36[2][A] | ut/isOk_r_Z[0]/Q
1.895 | 0.117 | tNET | FF | 1 | R17C36[2][B] | ut/isOk_r_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C36[2][B] | ut/isOk_r_Z[1]/CLK
1.577 | 0.000 | tUnc |  |  |  | ut/isOk_r_Z[1]
1.588 | 0.011 | tHld |  | 1 | R17C36[2][B] | ut/isOk_r_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path4

Path Summary:

Slack | 0.314
Data Arrival Time | 1.902
Data Required Time | 1.588
From | uut/u_xcorr/memr_1_adreg_Z[9]
To | uut/u_xcorr/memr_1_waddr_tmp_0[9]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C45[1][A] | uut/u_xcorr/memr_1_adreg_Z[9]/CLK
1.778 | 0.201 | tC2Q | RF | 3 | R17C45[1][A] | uut/u_xcorr/memr_1_adreg_Z[9]/Q
1.902 | 0.124 | tNET | FF | 1 | R17C45[2][A] | uut/u_xcorr/memr_1_waddr_tmp_0[9]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C45[2][A] | uut/u_xcorr/memr_1_waddr_tmp_0[9]/CLK
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/memr_1_waddr_tmp_0[9]
1.588 | 0.011 | tHld |  | 1 | R17C45[2][A] | uut/u_xcorr/memr_1_waddr_tmp_0[9]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 38.064%; tC2Q: 0.201, 61.936%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path5

Path Summary:

Slack | 0.334
Data Arrival Time | 2.030
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R8C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/Q
2.030 | 0.250 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/ADA10

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.250, 55.321%; tC2Q: 0.202, 44.679%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path6

Path Summary:

Slack | 0.335
Data Arrival Time | 2.162
Data Required Time | 1.826
From | u_la0_top/u_ao_mem_ctrl/data_reg_Z[43]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R9C8[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[43]/CLK
1.779 | 0.202 | tC2Q | RR | 1 | R9C8[0][A] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[43]/Q
2.162 | 0.382 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/DI1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
1.826 | 0.249 | tHld |  | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path7

Path Summary:

Slack | 0.337
Data Arrival Time | 2.163
Data Required Time | 1.826
From | u_la0_top/u_ao_mem_ctrl/data_reg_Z[53]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C9[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[53]/CLK
1.778 | 0.201 | tC2Q | RF | 1 | R8C9[2][A] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[53]/Q
2.163 | 0.385 | tNET | FF | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/DI1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
1.826 | 0.249 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.385, 65.673%; tC2Q: 0.201, 34.327%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path8

Path Summary:

Slack | 0.342
Data Arrival Time | 2.037
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/Q
2.037 | 0.258 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/ADA6

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.258, 56.063%; tC2Q: 0.202, 43.937%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path9

Path Summary:

Slack | 0.350
Data Arrival Time | 2.046
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/Q
2.046 | 0.266 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/ADA5

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.266, 56.879%; tC2Q: 0.202, 43.121%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path10

Path Summary:

Slack | 0.351
Data Arrival Time | 2.046
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_31
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R8C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/Q
2.046 | 0.266 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_31/ADA11

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_31/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_31
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[2] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_31

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.266, 56.884%; tC2Q: 0.202, 43.116%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path11

Path Summary:

Slack | 0.353
Data Arrival Time | 2.048
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/Q
2.048 | 0.269 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/ADA7

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[1] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_26

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.102%; tC2Q: 0.202, 42.898%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path12

Path Summary:

Slack | 0.359
Data Arrival Time | 2.054
Data Required Time | 1.695
From | ad_Z[8]
To | series_y_2_0_2
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C21[2][A] | ad_Z[8]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R17C21[2][A] | ad_Z[8]/Q
2.054 | 0.275 | tNET | RR | 1 | BSRAM_R10[5] | series_y_2_0_2/AD12

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[5] | series_y_2_0_2/CLK
1.577 | 0.000 | tUnc |  |  |  | series_y_2_0_2
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[5] | series_y_2_0_2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.275, 57.645%; tC2Q: 0.202, 42.355%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path13

Path Summary:

Slack | 0.361
Data Arrival Time | 2.057
Data Required Time | 1.695
From | ad_Z[9]
To | series_y_2_0_2
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C21[2][B] | ad_Z[9]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R17C21[2][B] | ad_Z[9]/Q
2.057 | 0.277 | tNET | RR | 1 | BSRAM_R10[5] | series_y_2_0_2/AD13

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[5] | series_y_2_0_2/CLK
1.577 | 0.000 | tUnc |  |  |  | series_y_2_0_2
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[5] | series_y_2_0_2

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.277, 57.844%; tC2Q: 0.202, 42.156%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path14

Path Summary:

Slack | 0.363
Data Arrival Time | 2.189
Data Required Time | 1.826
From | u_la0_top/u_ao_mem_ctrl/data_reg_Z[42]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R9C10[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[42]/CLK
1.779 | 0.202 | tC2Q | RR | 1 | R9C10[2][B] | u_la0_top/u_ao_mem_ctrl/data_reg_Z[42]/Q
2.189 | 0.410 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/DI0

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
1.826 | 0.249 | tHld |  | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path15

Path Summary:

Slack | 0.364
Data Arrival Time | 2.059
Data Required Time | 1.695
From | uut/u_xcorr/cnt_1_0[0]
To | uut/u_xcorr/memy_1_memy_1_0_0
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C27[0][A] | uut/u_xcorr/cnt_1_0[0]/CLK
1.779 | 0.202 | tC2Q | RR | 9 | R18C27[0][A] | uut/u_xcorr/cnt_1_0[0]/Q
2.059 | 0.280 | tNET | RR | 1 | BSRAM_R10[7] | uut/u_xcorr/memy_1_memy_1_0_0/ADB4

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[7] | uut/u_xcorr/memy_1_memy_1_0_0/CLKB
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/memy_1_memy_1_0_0
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[7] | uut/u_xcorr/memy_1_memy_1_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.280, 58.058%; tC2Q: 0.202, 41.942%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path16

Path Summary:

Slack | 0.364
Data Arrival Time | 2.059
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/Q
2.059 | 0.280 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA1

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.280, 58.075%; tC2Q: 0.202, 41.925%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path17

Path Summary:

Slack | 0.365
Data Arrival Time | 2.060
Data Required Time | 1.695
From | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
To | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.779 | 0.202 | tC2Q | RR | 38 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/Q
2.060 | 0.281 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/ADA12

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21/CLKA
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[0] | u_la0_top/u_ao_mem_ctrl/mem_mem_0_21

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.281, 58.164%; tC2Q: 0.202, 41.836%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path18

Path Summary:

Slack | 0.378
Data Arrival Time | 2.073
Data Required Time | 1.695
From | uut/u_xcorr/cnt_1_0[1]
To | uut/u_xcorr/memy_1_memy_1_0_0
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R18C27[0][B] | uut/u_xcorr/cnt_1_0[1]/CLK
1.779 | 0.202 | tC2Q | RR | 10 | R18C27[0][B] | uut/u_xcorr/cnt_1_0[1]/Q
2.073 | 0.294 | tNET | RR | 1 | BSRAM_R10[7] | uut/u_xcorr/memy_1_memy_1_0_0/ADB5

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | BSRAM_R10[7] | uut/u_xcorr/memy_1_memy_1_0_0/CLKB
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/memy_1_memy_1_0_0
1.695 | 0.118 | tHld |  | 1 | BSRAM_R10[7] | uut/u_xcorr/memy_1_memy_1_0_0

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.294, 59.238%; tC2Q: 0.202, 40.762%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path19

Path Summary:

Slack | 0.425
Data Arrival Time | 2.014
Data Required Time | 1.588
From | ut/cnt_r_Z[3]
To | ut/cnt_r_Z[3]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C36[0][A] | ut/cnt_r_Z[3]/CLK
1.779 | 0.202 | tC2Q | RR | 2 | R17C36[0][A] | ut/cnt_r_Z[3]/Q
1.782 | 0.002 | tNET | RR | 1 | R17C36[0][A] | ut/cnt_r_RNO[3]/I1
2.014 | 0.232 | tINS | RF | 1 | R17C36[0][A] | ut/cnt_r_RNO[3]/F
2.014 | 0.000 | tNET | FF | 1 | R17C36[0][A] | ut/cnt_r_Z[3]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C36[0][A] | ut/cnt_r_Z[3]/CLK
1.577 | 0.000 | tUnc |  |  |  | ut/cnt_r_Z[3]
1.588 | 0.011 | tHld |  | 1 | R17C36[0][A] | ut/cnt_r_Z[3]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path20

Path Summary:

Slack | 0.425
Data Arrival Time | 2.014
Data Required Time | 1.588
From | ut/cnt_r_Z[0]
To | ut/cnt_r_Z[0]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C36[1][A] | ut/cnt_r_Z[0]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R17C36[1][A] | ut/cnt_r_Z[0]/Q
1.782 | 0.002 | tNET | RR | 1 | R17C36[1][A] | ut/cnt_r_RNO[0]/I0
2.014 | 0.232 | tINS | RF | 1 | R17C36[1][A] | ut/cnt_r_RNO[0]/F
2.014 | 0.000 | tNET | FF | 1 | R17C36[1][A] | ut/cnt_r_Z[0]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R17C36[1][A] | ut/cnt_r_Z[0]/CLK
1.577 | 0.000 | tUnc |  |  |  | ut/cnt_r_Z[0]
1.588 | 0.011 | tHld |  | 1 | R17C36[1][A] | ut/cnt_r_Z[0]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path21

Path Summary:

Slack | 0.427
Data Arrival Time | 2.015
Data Required Time | 1.588
From | u_la0_top/triger_level_cnt_Z[2]
To | u_la0_top/triger_level_cnt_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C7[1][A] | u_la0_top/triger_level_cnt_Z[2]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R8C7[1][A] | u_la0_top/triger_level_cnt_Z[2]/Q
1.783 | 0.004 | tNET | RR | 1 | R8C7[1][A] | u_la0_top/triger_level_cnt_4_cZ[2]/I0
2.015 | 0.232 | tINS | RF | 1 | R8C7[1][A] | u_la0_top/triger_level_cnt_4_cZ[2]/F
2.015 | 0.000 | tNET | FF | 1 | R8C7[1][A] | u_la0_top/triger_level_cnt_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C7[1][A] | u_la0_top/triger_level_cnt_Z[2]/CLK
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[2]
1.588 | 0.011 | tHld |  | 1 | R8C7[1][A] | u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path22

Path Summary:

Slack | 0.427
Data Arrival Time | 2.015
Data Required Time | 1.588
From | uut/u_xcorr/delay_1_Z[4]
To | uut/u_xcorr/delay_1_Z[4]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R20C55[0][A] | uut/u_xcorr/delay_1_Z[4]/CLK
1.779 | 0.202 | tC2Q | RR | 3 | R20C55[0][A] | uut/u_xcorr/delay_1_Z[4]/Q
1.783 | 0.004 | tNET | RR | 2 | R20C55[0][A] | uut/u_xcorr/un1_delay_1_3_cry_4_0/I1
2.015 | 0.232 | tINS | RF | 1 | R20C55[0][A] | uut/u_xcorr/un1_delay_1_3_cry_4_0/SUM
2.015 | 0.000 | tNET | FF | 1 | R20C55[0][A] | uut/u_xcorr/delay_1_Z[4]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R20C55[0][A] | uut/u_xcorr/delay_1_Z[4]/CLK
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/delay_1_Z[4]
1.588 | 0.011 | tHld |  | 1 | R20C55[0][A] | uut/u_xcorr/delay_1_Z[4]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path23

Path Summary:

Slack | 0.427
Data Arrival Time | 2.015
Data Required Time | 1.588
From | uut/u_xcorr/delay_1_Z[6]
To | uut/u_xcorr/delay_1_Z[6]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R20C55[1][A] | uut/u_xcorr/delay_1_Z[6]/CLK
1.779 | 0.202 | tC2Q | RR | 3 | R20C55[1][A] | uut/u_xcorr/delay_1_Z[6]/Q
1.783 | 0.004 | tNET | RR | 2 | R20C55[1][A] | uut/u_xcorr/un1_delay_1_3_cry_6_0/I1
2.015 | 0.232 | tINS | RF | 1 | R20C55[1][A] | uut/u_xcorr/un1_delay_1_3_cry_6_0/SUM
2.015 | 0.000 | tNET | FF | 1 | R20C55[1][A] | uut/u_xcorr/delay_1_Z[6]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R20C55[1][A] | uut/u_xcorr/delay_1_Z[6]/CLK
1.577 | 0.000 | tUnc |  |  |  | uut/u_xcorr/delay_1_Z[6]
1.588 | 0.011 | tHld |  | 1 | R20C55[1][A] | uut/u_xcorr/delay_1_Z[6]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path24

Path Summary:

Slack | 0.428
Data Arrival Time | 2.016
Data Required Time | 1.588
From | u_la0_top/capture_window_sel_Z[2]
To | u_la0_top/capture_window_sel_Z[2]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C5[0][A] | u_la0_top/capture_window_sel_Z[2]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R12C5[0][A] | u_la0_top/capture_window_sel_Z[2]/Q
1.784 | 0.005 | tNET | RR | 1 | R12C5[0][A] | u_la0_top/capture_window_sel_3_cZ[2]/I0
2.016 | 0.232 | tINS | RF | 1 | R12C5[0][A] | u_la0_top/capture_window_sel_3_cZ[2]/F
2.016 | 0.000 | tNET | FF | 1 | R12C5[0][A] | u_la0_top/capture_window_sel_Z[2]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C5[0][A] | u_la0_top/capture_window_sel_Z[2]/CLK
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/capture_window_sel_Z[2]
1.588 | 0.011 | tHld |  | 1 | R12C5[0][A] | u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path25

Path Summary:

Slack | 0.428
Data Arrival Time | 2.016
Data Required Time | 1.588
From | u_la0_top/triger_level_cnt_Z[1]
To | u_la0_top/triger_level_cnt_Z[1]
Launch Clk | DEFAULT_CLK:[R]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C3[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLK
1.779 | 0.202 | tC2Q | RR | 4 | R3C3[1][A] | u_la0_top/triger_level_cnt_Z[1]/Q
1.784 | 0.005 | tNET | RR | 1 | R3C3[1][A] | u_la0_top/triger_level_cnt_4_cZ[1]/I1
2.016 | 0.232 | tINS | RF | 1 | R3C3[1][A] | u_la0_top/triger_level_cnt_4_cZ[1]/F
2.016 | 0.000 | tNET | FF | 1 | R3C3[1][A] | u_la0_top/triger_level_cnt_Z[1]/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C3[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLK
1.577 | 0.000 | tUnc |  |  |  | u_la0_top/triger_level_cnt_Z[1]
1.588 | 0.011 | tHld |  | 1 | R3C3[1][A] | u_la0_top/triger_level_cnt_Z[1]

Path Statistics:

Clock Skew | 0.000
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay | cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
11.648 | -0.035 | tSu |  | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path2

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R4C5[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C5[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
11.648 | -0.035 | tSu |  | 1 | R4C5[0][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path3

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
11.648 | -0.035 | tSu |  | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path4

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
11.648 | -0.035 | tSu |  | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path5

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
11.648 | -0.035 | tSu |  | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path6

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
11.648 | -0.035 | tSu |  | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path7

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
11.648 | -0.035 | tSu |  | 1 | R11C10[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path8

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
11.648 | -0.035 | tSu |  | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path9

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
11.648 | -0.035 | tSu |  | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path10

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
11.648 | -0.035 | tSu |  | 1 | R3C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path11

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
11.648 | -0.035 | tSu |  | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path12

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
11.648 | -0.035 | tSu |  | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path13

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
11.648 | -0.035 | tSu |  | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path14

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
11.648 | -0.035 | tSu |  | 1 | R7C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path15

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R7C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R7C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
11.648 | -0.035 | tSu |  | 1 | R7C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path16

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
11.648 | -0.035 | tSu |  | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path17

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
11.648 | -0.035 | tSu |  | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path18

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
11.648 | -0.035 | tSu |  | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path19

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
11.648 | -0.035 | tSu |  | 1 | R8C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path20

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
11.648 | -0.035 | tSu |  | 1 | R8C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path21

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
11.648 | -0.035 | tSu |  | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path22

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
11.648 | -0.035 | tSu |  | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path23

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
11.648 | -0.035 | tSu |  | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path24

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R12C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
11.648 | -0.035 | tSu |  | 1 | R12C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Path25

Path Summary:

Slack | 1.914
Data Arrival Time | 9.734
Data Required Time | 11.648
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.688 | 0.688 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.916 | 1.228 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
7.148 | 0.232 | tC2Q | FF | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
9.734 | 2.586 | tNET | FF | 1 | R12C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
11.883 | 1.201 | tNET | RR | 1 | R12C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
11.683 | -0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
11.648 | -0.035 | tSu |  | 1 | R12C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew | -0.033
Setup Relationship | 5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.688, 35.884%; route: 1.228, 64.116%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.586, 91.769%; tC2Q: 0.232, 8.231%
Required Clock Path Delay | cell: 0.683, 36.242%; route: 1.201, 63.758%

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.788 | 0.011 | tHld |  | 1 | R4C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path2

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.788 | 0.011 | tHld |  | 1 | R4C4[1][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path3

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.788 | 0.011 | tHld |  | 1 | R4C11[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path4

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.788 | 0.011 | tHld |  | 1 | R7C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path5

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
1.788 | 0.011 | tHld |  | 1 | R11C10[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path6

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.788 | 0.011 | tHld |  | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path7

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.788 | 0.011 | tHld |  | 1 | R3C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path8

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.788 | 0.011 | tHld |  | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path9

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.788 | 0.011 | tHld |  | 1 | R7C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path10

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.788 | 0.011 | tHld |  | 1 | R8C7[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path11

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R7C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R7C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]
1.788 | 0.011 | tHld |  | 1 | R7C8[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[10]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path12

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R7C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R7C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]
1.788 | 0.011 | tHld |  | 1 | R7C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[11]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path13

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]
1.788 | 0.011 | tHld |  | 1 | R3C4[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[12]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path14

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.788 | 0.011 | tHld |  | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path15

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
1.788 | 0.011 | tHld |  | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path16

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R8C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.788 | 0.011 | tHld |  | 1 | R8C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path17

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R8C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
1.788 | 0.011 | tHld |  | 1 | R8C7[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path18

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.788 | 0.011 | tHld |  | 1 | R12C8[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path19

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.788 | 0.011 | tHld |  | 1 | R12C8[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path20

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.788 | 0.011 | tHld |  | 1 | R8C7[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path21

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
1.788 | 0.011 | tHld |  | 1 | R12C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path22

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R12C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R12C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.788 | 0.011 | tHld |  | 1 | R12C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path23

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R8C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
1.788 | 0.011 | tHld |  | 1 | R8C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path24

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R8C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R8C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]
1.788 | 0.011 | tHld |  | 1 | R8C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[10]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

### Path25

Path Summary:

Slack | 6.623
Data Arrival Time | 8.411
Data Required Time | 1.788
From | u_la0_top/rst_ao_Z
To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
Launch Clk | DEFAULT_CLK:[F]
Latch Clk | DEFAULT_CLK:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | 1 | IOT48[A] | clk_ibuf/I
5.677 | 0.678 | tINS | FF | 396 | IOT48[A] | clk_ibuf/O
6.590 | 0.913 | tNET | FF | 1 | R8C10[0][A] | u_la0_top/rst_ao_Z/CLK
6.792 | 0.202 | tC2Q | FR | 49 | R8C10[0][A] | u_la0_top/rst_ao_Z/Q
8.411 | 1.619 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | DEFAULT_CLK(clock)
0.000 | 0.000 | tCL | RR | 1 | IOT48[A] | clk_ibuf/I
0.675 | 0.675 | tINS | RR | 396 | IOT48[A] | clk_ibuf/O
1.577 | 0.902 | tNET | RR | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]/CLK
1.777 | 0.200 | tUnc |  |  |  | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]
1.788 | 0.011 | tHld |  | 1 | R6C4[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[11]

Path Statistics:

Clock Skew | -0.013
Hold Relationship | -5.000
Logic Level | 0
Arrival Clock Path Delay | cell: 0.678, 42.601%; route: 0.913, 57.399%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.619, 88.906%; tC2Q: 0.202, 11.094%
Required Clock Path Delay | cell: 0.675, 42.823%; route: 0.902, 57.177%

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | ad_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | ad_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | ad_Z[0]/CLK

### MPW2

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | ad_Z[2]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | ad_Z[2]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | ad_Z[2]/CLK

### MPW3

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | ad_Z[6]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | ad_Z[6]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | ad_Z[6]/CLK

### MPW4

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/memr_1_memr_1_0_1

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/memr_1_memr_1_0_1/CLKB

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/memr_1_memr_1_0_1/CLKB

### MPW5

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/cnt_1_0[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/cnt_1_0[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/cnt_1_0[0]/CLK

### MPW6

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/memr_1_din_tmp_0[2]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/memr_1_din_tmp_0[2]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/memr_1_din_tmp_0[2]/CLK

### MPW7

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/result_Z[20]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/result_Z[20]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/result_Z[20]/CLK

### MPW8

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | u_la0_top/capture_window_sel[3]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | u_la0_top/capture_window_sel[3]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | u_la0_top/capture_window_sel[3]/CLK

### MPW9

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | u_la0_top/internal_reg_start_dly_Z[0]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | u_la0_top/internal_reg_start_dly_Z[0]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | u_la0_top/internal_reg_start_dly_Z[0]/CLK

### MPW10

MPW Summary:

Slack: | 3.662
Actual Width: | 4.662
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | DEFAULT_CLK
Objects: | uut/u_xcorr/result_Z[19]

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | DEFAULT_CLK(clock)
5.000 | 0.000 | tCL | FF | clk_ibuf/I
5.688 | 0.688 | tINS | FF | clk_ibuf/O
6.916 | 1.228 | tNET | FF | uut/u_xcorr/result_Z[19]/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | DEFAULT_CLK(clock)
10.000 | 0.000 | tCL | RR | clk_ibuf/I
10.675 | 0.675 | tINS | RR | clk_ibuf/O
11.577 | 0.902 | tNET | RR | uut/u_xcorr/result_Z[19]/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
242 | clk_c | 1.979 | 1.228
167 | start | 3.639 | 2.078
35 | x_1_ret_33_0 | 6.643 | 1.897
34 | x_1_ret_19_0 | 5.776 | 1.143
34 | x_1_ret_1_0 | 5.313 | 1.607
34 | result_0_1[30] | 5.371 | 0.762
34 | cnt9 | 2.698 | 0.914
34 | N_1363 | 4.008 | 0.737
30 | memr_1_G_1 | 1.979 | 0.743
19 | delay_c[2] | 4.232 | 1.761

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R18C27 | 0.569
R17C52 | 0.528
R18C28 | 0.528
R18C46 | 0.500
R17C34 | 0.486
R17C44 | 0.486
R17C45 | 0.486
R17C47 | 0.486
R18C48 | 0.472
R10C23 | 0.472

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---