library verilog;
use verilog.vl_types.all;
entity tb is
    generic(
        VCS_SIM         : integer := 1;
        N               : integer := 1024;
        W               : integer := 17
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of VCS_SIM : constant is 1;
    attribute mti_svvh_generic_type of N : constant is 1;
    attribute mti_svvh_generic_type of W : constant is 1;
end tb;
