library verilog;
use verilog.vl_types.all;
entity top is
    generic(
        VCS_SIM         : integer := 0;
        N               : integer := 512
    );
    port(
        a               : out    vl_logic_vector(16 downto 0);
        b               : out    vl_logic_vector(16 downto 0);
        result          : out    vl_logic_vector(33 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        delay           : out    vl_logic_vector(9 downto 0);
        complete        : out    vl_logic;
        start_1         : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of VCS_SIM : constant is 1;
    attribute mti_svvh_generic_type of N : constant is 1;
end top;
