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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.1

Hostname: GW-SW-048

Implementation : rev_1

# Written on Tue Feb 19 17:24:02 2019

##### FILES SYNTAX CHECKED ##############################################
Constraint File(s):      (none)

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

          Start      Requested      Requested     Clock      Clock               Clock
Level     Clock      Frequency      Period        Type       Group               Load 
--------------------------------------------------------------------------------------
0 -       System     1521.8 MHz     0.657         system     system_clkgroup     14   
======================================================================================


Clock Load Summary
******************

           Clock     Source     Clock Pin                        Non-clock Pin     Non-clock Pin
Clock      Load      Pin        Seq Example                      Seq Example       Comb Example 
------------------------------------------------------------------------------------------------
System     14        -          shift_dr_capture_dr_dly[0].C     -                 -            
================================================================================================
