#Build: Synplify Pro (R) O-2018.09G-Beta3, Build 136R, Nov 19 2018
#install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
#OS: Linux 
#Hostname: jinan9110.sdgowin.com

# Tue Dec 18 16:27:06 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode

@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode

@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/generic/gw2a.v" (library work)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/xcorr/xcorr.v" (library work)
@I::"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v" (library work)
@I::"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/eliminate_shake.v" (library work)
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module top
@N: CG364 :"/share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro/lib/generic/gw2a.v":1597:7:1597:9|Synthesizing module GSR in library work.
Running optimization stage 1 on GSR .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on LUT4 .......
Running optimization stage 1 on LUT2 .......
Running optimization stage 1 on LUT3 .......
Running optimization stage 1 on MUX2_LUT5 .......
Running optimization stage 1 on MUX2_LUT6 .......
Running optimization stage 1 on DFF .......
Running optimization stage 1 on DFFS .......
Running optimization stage 1 on DFFE .......
Running optimization stage 1 on DFFR .......
Running optimization stage 1 on DPX9 .......
Running optimization stage 1 on SDPX9 .......
Running optimization stage 1 on ALU .......
Running optimization stage 1 on MULT18X18 .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on \(crosscorrelation)/(XCORR_Top)_17s_1024s_1s .......
@N: CG364 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/xcorr/xcorr.v":6068:7:6068:15|Synthesizing module XCORR_Top in library work.
Running optimization stage 1 on XCORR_Top .......
@N: CG364 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/eliminate_shake.v":2:7:2:12|Synthesizing module deUstb in library work.
@N: CG179 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/eliminate_shake.v":12:23:12:27|Removing redundant assignment.
Running optimization stage 1 on deUstb .......
@N: CG364 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":2:7:2:9|Synthesizing module top in library work.
Opening data file o_x.dat from directory ../../../data
Opening data file o_y.dat from directory ../../../data
@W: CG532 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":37:0:37:6|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
@W: CG532 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":45:0:45:6|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
Running optimization stage 1 on top .......
Running optimization stage 2 on top .......
Running optimization stage 2 on deUstb .......
Running optimization stage 2 on XCORR_Top .......
@N: CL159 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/xcorr/xcorr.v":6091:6:6091:8|Input rst is unused.
Running optimization stage 2 on \(crosscorrelation)/(XCORR_Top)_17s_1024s_1s .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on MULT18X18 .......
Running optimization stage 2 on ALU .......
Running optimization stage 2 on SDPX9 .......
Running optimization stage 2 on DPX9 .......
Running optimization stage 2 on DFFR .......
Running optimization stage 2 on DFFE .......
Running optimization stage 2 on DFFS .......
Running optimization stage 2 on DFF .......
Running optimization stage 2 on MUX2_LUT6 .......
Running optimization stage 2 on MUX2_LUT5 .......
Running optimization stage 2 on LUT3 .......
Running optimization stage 2 on LUT2 .......
Running optimization stage 2 on LUT4 .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on GSR .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/synwork/layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 82MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 18 16:27:06 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

@N|Running in 64-bit mode
File /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/synwork/layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 18 16:27:06 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 18 16:27:06 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com

Database state : /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/synwork/|rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 133R, Built Nov 19 2018 17:44:15

@N|Running in 64-bit mode
File /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/synwork/XCORR_1024-1_case_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 18 16:27:08 2018

###########################################################]
# Tue Dec 18 16:27:08 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1226R, Built Nov 21 2018 00:28:10


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A: MF827 |No constraint file specified.
@N: MF284 |Setting synthesis effort to medium for the design
@L: /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/XCORR_1024-1_case_scck.rpt 
Printing clock  summary report in "/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/XCORR_1024-1_case_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)

@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.

Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

@N: MF974 |Total number of latches (multibit) processed = 0 
@N: MF975 |Total number of latches (bit blasted) processed = 0 
@N: MF976 |Total number of (multibit) opaque latches found = 0 
@N: MF977 |Total number of (bit blasted) opaque latches found = 0 

Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)







Detailed report for transparent and observable latches in design:
@L: /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/synwork/XCORR_1024-1_case_prem_latch_transparency_report.log

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)

syn_allowed_resources : blockrams=140  set on top level netlist top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)



Clock Summary
******************

          Start       Requested     Requested     Clock        Clock                     Clock
Level     Clock       Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------
0 -       System      150.0 MHz     6.667         system       system_clkgroup           0    
                                                                                              
0 -       top|clk     81.2 MHz      12.314        inferred     Autoconstr_clkgroup_0     273  
==============================================================================================



Clock Load Summary
***********************

            Clock     Source        Clock Pin            Non-clock Pin     Non-clock Pin
Clock       Load      Pin           Seq Example          Seq Example       Comb Example 
----------------------------------------------------------------------------------------
System      0         -             -                    -                 -            
                                                                                        
top|clk     273       clk(port)     series_x[16:0].C     -                 -            
========================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 273 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       clk                 Unconstrained_port     273        ad[9]          
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/XCORR_1024-1_case.sap.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 194MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 194MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 194MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 107MB peak: 194MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Dec 18 16:27:10 2018

###########################################################]
# Tue Dec 18 16:27:10 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta3
Install: /share/gwsw/gui_proj/sw_test/Gowin/1.8/SynplifyPro
OS: CentOS release 6.8 (Final)
Hostname: jinan9110.sdgowin.com
max virtual memory: unlimited (bytes)
max user processes: 1024
max stack size: 10485760 (bytes)


Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1226R, Built Nov 21 2018 00:28:10


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N: MF284 |Setting synthesis effort to medium for the design


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB)


Available hyper_sources - for debug and ip models
	None Found

@N: MT206 |Auto Constrain mode is enabled
@N: FX493 |Applying initial value "00" on instance ut.isOk_r[1:0].
@N: FX493 |Applying initial value "0000" on instance ut.cnt_r[3:0].
@N: FX493 |Applying initial value "0000000000" on instance ad[9:0].

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 198MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 198MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 198MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 198MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 198MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 198MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 198MB)

@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[0] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[1] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[2] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[3] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[4] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[5] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[6] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[7] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[8] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[9] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[10] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[11] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[12] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[13] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[14] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[15] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[16] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[17] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[18] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[19] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[20] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[21] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[22] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[23] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[24] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[25] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[26] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[27] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[28] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[29] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[30] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[31] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[32] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A: BN291 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":52:0:52:5|Boundary register series_x[33] (in view: work.top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_00 = 11C1260830DD1F7A11921296DF2EED074B52E2CE1BDBCDE1E50B0851CDB5FF5D.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_01 = 0054DAA6DA700397022903BBE3362DDF01AD01C7D1352CEEF39604460E93F847.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_02 = 3774E71BC441E8A4F28432942606DD04086DE39B5A1A2D4AF913006C07610D5B.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_03 = F6810803FD48006ECE6029A82608DA6B32FD1733F5170E49285ED37FEE6E5684.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_04 = D403CD0DFA6F06445B08065902EEF8B81C6A44EF023029CADAA3F6630EBC0795.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_05 = 13030CF303A9F45FF412EA67F8C32772F76EFF31E65FF9120E061527EC3C2E0D.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_06 = 2171ED7EFF81CB69FA8D017204F9D1E829C4C94D0A1C24DB16A1E140CDF7E8F6.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_07 = B9F81E4931E21F6CDD5FF942E16FEC8E0B111D740367050FB1C403AADD58B216.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_08 = 26FD2C29E45D272DEB622A2A15503CF5F6BA01EAEB1015FFF8B504E4176C0F98.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_09 = 1CBFC753DD25DEA3151A0291F2CA21B3F86BB8D9E9D1F265C214160A17691EBA.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_0A = E35E1243E5AA1C69F9EDC19EEE97D731D923EA091E892CCC0143DD05EE5B1FC0.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_0B = 107EFB54005942A0F4EDD8E8F9D934AAE91AFA3FF1503728DB66D924044317CC.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_0C = 2E1D4C8EE634FE6AD6D2FDC6B941E8C20FA11368E839FC9CEC7CFC9CE6702EFC.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_0D = 0C800C21457DF48D0D710B77EC6DEB452439CA90106200B8FFBF08AB010024D8.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_0E = 06F9FADB24130AE6FFB4D9ECEADDE0D6E105CFF10EF10ED6F05705141F3A32E2.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_0F = E56EF00DFD0B16643CA20F1DF0A5D29D225F0479DFD7080AE474FAD7F3A0C7B0.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_10 = 02EDF1F019DE085115A3FD820ECFF3721B461574F4A521171F4C07FDDE33E25E.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_11 = FD6DFEE515EDE618E86AFAE9C327CEE31E6104EDD5C54265CB100B401479E295.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_12 = DD11FC2DF69C1DA2FE220F6AF240F6F205441E2BED74244F01078DE807B5F930.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_13 = 0C1CE85C1317F1B01BA30612EFE2F46B2CEE3322E290F1EADCA2B530BF782A25.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_14 = 01D90FA8C99D3F73F8DA0438E739E6BEDFB6DFDBF536F62C0E6FF50604710F81.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_15 = 01141469C4F1F15702F529BEFD8CF3E622E5243BF68B105CF55C117F0B8B0FAD.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_16 = E2571055F7431D800D8FFE46FB451E9824D3291DEF5CA1964334FFB1D4233652.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_17 = 2207FCADE8F8DA0FE93E1B53EFC509E03492341CDFD8D843EE080D57CBAA31C2.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_18 = FC31054E0E210836179B0F7DD162E7541CDA106B01B82876E5C22737EB881D15.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_19 = FC2B2A64E8E7FD9A2164AF0DE63609AC0E08DD73E5AEEDDE1EA9118C3224E1AF.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_1A = 4439B7AD129BF3AA05F01C90E8BAFCD3F4A9F178F440BEB7C9D02AC704A4CF7A.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_1B = D926DE9A08A900F2F96C01BCDF44FFF2281C07FAF05FDF80E6DFC25A15AF2F48.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_1C = FAFA3C350B0E2854E1D3F87BD69C05E908E5E9BD0DF4FF46102817E3FB4AEC69.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_1D = 12C3FD2BD028208F0FAD26F8C939E6552A6501AE00D23FA9E6A92845103C275A.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_1E = F172F9D1033F0000F19B252C2413F81814351C8BFFBCF420EFB2C87005A3DDC5.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_1F = E01CEA450AB506050D451D4DE3670A661C12F319CE13FD1303CE22C3EDF81638.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_20 = ECB805C4E80D008DFFDFCF4B21E2F8F314940B29ED86EBB3DCEA374FDEB0C7B3.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_21 = 1AF7BA60E291E9A8F34A30D0FABEB977DC850609B6BB165907641CF71F031EFA.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_22 = F8E8348E0FDE2FC316AA2F5BEC14E40F2468BF0CF3742414F6B9E464D004249B.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_23 = 00D7DEC20EEB0153FD111D83FDC7065D08A0391F3EF0CAD637DDF25DFD712365.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_24 = 2EA1F20C28E1ED3C0495262CF38711CC01FB310615B3E5C8E4EBD5D2C933E05E.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_25 = 3F69208EE930D677E4A510E50B9F0882F5DDDBB22D93F12FE98EDEC9AC0601C9.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_26 = D8C3F78705202B23F9C72249EDC70F33F680F00E17EEE205CFD4E3F9F8180F49.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_27 = B560167C115D231FC7D80E44047E307BE34118CD0E3BFA021844040FE133CC1E.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_28 = E627C9DEE7D1CE5D1AAFBB92FCFBF5BE1012283DEF8C2ED0DF2C0FC0196202F2.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_29 = 220528DF11C5E8C21E3CFDDAF1B5149808D623ED0E000A71158CFA67321AFF42.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_2A = 16FF026322335424195EF6350B16039E05D8A7B20636F77DF93E3092350CF50D.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_2B = E8392489E0710259F06E330C0DAFD55E2104E87BFE83D968EF67E6880A4018AF.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_2C = FB13D74A196CFBC01261F6E4127011ADFB4F56A0DE1D26FEFA27E3C7F5A8FA98.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_2D = DEE2FC08ACA5D199D941F778D9110AD2031D0EF4FE5D2DCEF290D35603F4EB32.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_2E = 1B0EED63EA032AD707880005119DE569243A544420F11DBB040B4DE1FD75F893.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_2F = EBF7D687236011B9DFACE908D12D00623921E3B642CE2B4FD80C1379ECD82579.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_30 = DDA0E57DEA3BDF26E1DED85043891697BB9E1F580254F3A70E1EFEEAEF6533B3.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_31 = E9C1E17FF5CBE6A2D9D4E60F13C2F81EFE44FFAD3310F1D4E344D61B3E170482.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_32 = 07101DEE0371C4B3BB0208A33D0D32272F12C77FEC3AF0A1E60FFACD053F01DA.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_33 = E651EB04F8C8EC4428EEDE620F9AE56127F0029ECD1915A20CD623FE060FE0C2.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_34 = FC7B0B0ADF86D059ED76F587FFD73C56D11DD7D0D983F438E148285CF6BCF7E2.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_35 = 2D8E129D079CBD3B2394EB4A1FA0DC6BECF71A40077E073AF2C511862418D49F.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_36 = 04C6193F35282E111F72F7E411D6069E1BF1F085F9DFEC05EABB21A5D8E8FA1B.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_37 = 14BDED08E200E1DFEB910AEEEEFDF9A0F5CB383906B0187DD4FBD59F026E2231.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_38 = 0E3FD1F9FFADDF5011F103E8D3F2447CE73DF2FAF0C3F3C2FC912954D6A1EC0E.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_39 = FF8EDEAA2F0BE9C32FE4E842EFC8FC25FA7AE336DAB7EC68E52900BE090704D1.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_3A = 1B280A05FB230816D6CBFE520DA5FCD6F2E82DB726700161FB4A2E2F0735D41A.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_3B = E65C17E2373A2A4AE332C876CF4D025DE9A9300B199237D4DE8AFEF63673ECA5.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_3C = 1118D40AD5BEEE632BC631FBF2CC082A2183F65A1587275B1DBD15A02E9C1B23.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_3D = CA28E8EBECF1E1FBD79D2032D0D70904F3E6F88709F505B211E70410F1DC1E7B.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_3E = D27DCEDACB8EDD090384EAFC3B9911E321F0EF9D0F7D010B009B054AD4C81A9C.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_0.INIT_RAM_3F = DF1BFA3B2BA80840F36B307D35F2E950F9D8E91FCA0328A2F465C5C3EEAE257C.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_00 = 4E1EE3A2C8A4BB5266C0E332ACE7F05F4EA4EDAD247ED343A371E5A21009C9A1.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_01 = 23ACC56FFB2D451ED274E568175D1D10E620FB8E6705E86C3EEBCED2DB5670DD.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_02 = 853CCB77F3DDC01DA7731B4EEFB00A4F4CF88C7BBFEC26D2E9D3DD10F9141E1C.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_03 = FC7D09F4A405D7B80B03F544AF0CF625A16CB6EC224F446C5BC4193DF3538FA0.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_04 = 9CA3E295BB550BEC81BEF6EE4D8C30631E5C238247EC05085D5DC98D081CCBE4.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_05 = B144D5989D58CD832361016FFC81C2566C8B8C7FC80F0955DE00B5FAC34F4386.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_06 = 43EA347F54B1131146EFDD280CE21019C00E36FBC528656E446885355C57EA97.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_07 = 1E1F3EA84DCAEF6AC42B28BD293327270138ECCE141ECF68C3EB74A04867E6F3.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_08 = E1C0F8C0F3F5825C1DB5BCCE993CC3F00A3F0EB0E5A73D6C246DFD18B65CC252.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_09 = FE1215D1C1F99345272CF4E4BF131B82A2835883CB47D2A7D393E732E6644C5C.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_0A = 532171A0B84169402E47ED4D0B9F0545E3CB7DC3B50AB7962C34FBEF601DDD0C.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_0B = 624E53131CDED926D759EFD5E6C3F1E66A017B951509465624F5032B8940E430.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_0C = 132EEC982181B0AF2647EB479A11A8B1E8EACA1E4EDD365FFB7F5993B12558DE.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_0D = 0FE6D142D5705ED1B00AE5240F4D1E7DC01C0857AEEE379C97550CA48554EEEA.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_0E = 30DE2F77FE5C6B5CEDC7B7C36B7B9251CD57E8BDC22601BC4945B542E88AEB0E.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_0F = 0E2F40C398D9E3D23734CD328C45AF81CD5441A61F7317BCAD9D6BB1AB5BE9BF.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_10 = 4DAC85B3CD442A84151E202348D4EFFFFE2CA11400371A7224CA208CF71900D3.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_11 = FF29F0D124340F03A8410AFDC9F9EADD01162CEAFB110342C2A58362CC56593B.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_12 = EE37BE9918073C421B8566F26B93ADBFF01233F01BCFB82E2D123D746092F137.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_13 = 25BADBE9D426B2B32AD831100667E337F5C4D4AC2005F931D3F5D1B3C0A33654.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_14 = EF5C217EB803A0547B49F4F80E09EB9BCDE16759EA4BDA1DE8140C95564871F6.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_15 = 0A4AEB1A60B37FEBA048FA7CB547F4430B64A8EEEE21D24A9D419F02FC64EEE0.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_16 = B4C7D0A82D25CF8AD3CC6E53FC27AD6E0422E82A7B8B73CD3FE2C0F9ECB986FE.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_17 = 7D0EC24994DB2CE9FD31E918C16BB58C240AD7902F3DD273D3AF4CA2F14960F8.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_18 = 15C59F1AEAA2176875EC4E504AD5C321210AFB46FEE20938F3511492DF0F3E94.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_19 = 6C1139B01A87B73FE32223A3B273D8A2CF34EC21B7B7B0D9E6E0EC18DC1A77F3.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_1A = FCC4DD37FCB4DED3A7F60A2AE57FFC0F0B110CD3462FCB1B0BE1E5EA64AAA11B.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_1B = 9825FE290014D0D0B48F8F842F1F6FD7F33C69740467F9230773DACBD17EC146.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_1C = 8265A986E15C34EE178B16834B6FE1A462541EC5E422EAAB000A0A28A3AD2DE5.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_1D = 1A1EF7CD95DB141A1E6C9F0A0623DC3D38B4F5863DE4109AF3D7B73CCEAAF7F2.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_1E = 6493E1031D12CAC0FA79108A32D4919BA09AD57A6F6D55BF08B7CDB7428AFDCF.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_1F = C489E613ECD0F8F8008A58E27B6D080655729D4FE599DDAFE45019D6DB5FA464.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_20 = 1AB7F4343DCDEFF0FFF771E16E5C2FEB3B7E769CFEF52CB1EE3B4E503399B4D7.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_21 = CFC0958FDC714F85D7FBCE9A820355E323F75AEE2E8125D80C0294E22E721360.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_22 = B061308EC6D0DD0860DC00428D6D1AA3DEACCB6D26EFFCDAEE4906472B91306C.
@N: FX276 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Initial value series_y_2_0_1.INIT_RAM_23 = C1AEDAB72DF6F1F0259D5856101DB008D8DC1E4E1E726CA5B74CD7A918A7FE0A.

Only the first 100 messages of id 'FX276' are reported. To see all messages use 'report_messages -log /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/synlog/XCORR_1024-1_case_fpga_mapper.srr -id FX276' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {FX276} -count unlimited' in the Tcl shell.
@N: FX211 |Packed ROM series_y_2_0[33:0] (10 input, 34 output) to Block SelectRAM 

Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 198MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 198MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		    -2.75ns		 359 /        16
   2		0h:00m:02s		    -2.75ns		 359 /        16

   3		0h:00m:03s		    -2.75ns		 359 /        16

   4		0h:00m:03s		    -2.75ns		 359 /        16

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 198MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@W: BN114 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Removing instance series_y_2_0_0 (in view: work.top(verilog)) of black box view:VIRTEX.RAMB16(PRIM) because it does not drive other instances.
@W: BN114 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Removing instance series_y_2_0_1 (in view: work.top(verilog)) of black box view:VIRTEX.RAMB16(PRIM) because it does not drive other instances.
@W: BN114 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":59:26:59:35|Removing instance series_y_2_0_2 (in view: work.top(verilog)) of black box view:VIRTEX.RAMB16(PRIM) because it does not drive other instances.

Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 198MB)


Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 120MB peak: 198MB)

Writing Analyst data base /home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/impl/synthesize/rev_1/synwork/XCORR_1024-1_case_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 192MB peak: 198MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 192MB peak: 198MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 191MB peak: 198MB)


Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 192MB peak: 198MB)

@W: MT420 |Found inferred clock top|clk with period 6.67ns. Please declare a user-defined clock on port clk.


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Dec 18 16:27:17 2018
#


Top view:               top
Requested Frequency:    150.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: -1.189

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
top|clk            150.0 MHz     127.3 MHz     6.667         7.856         -1.189     inferred     Autoconstr_clkgroup_0
System             150.0 MHz     384.6 MHz     6.667         2.600         4.067      system       system_clkgroup      
========================================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------
System    top|clk  |  6.667       4.067   |  No paths    -      |  No paths    -      |  No paths    -    
top|clk   System   |  6.667       5.706   |  No paths    -      |  No paths    -      |  No paths    -    
top|clk   top|clk  |  6.667       -1.189  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: top|clk
====================================



Starting Points with Worst Slack
********************************

                                           Starting                                                Arrival           
Instance                                   Reference     Type     Pin     Net                      Time        Slack 
                                           Clock                                                                     
---------------------------------------------------------------------------------------------------------------------
uut.u_xcorr.\\memr_1_adreg_fast_Z\[1\]     top|clk       DFFR     Q       memr_1_adreg_fast[1]     0.243       -1.189
uut.u_xcorr.\\memr_1_adreg_fast_Z\[0\]     top|clk       DFFR     Q       memr_1_adreg_fast[0]     0.243       -1.168
uut.u_xcorr.\\memr_1_waddr_tmp_0\[0\]      top|clk       DFF      Q       memr_1_waddr_tmp[0]      0.243       -1.081
uut.u_xcorr.\\memr_1_waddr_tmp_0\[1\]      top|clk       DFF      Q       memr_1_waddr_tmp[1]      0.243       -0.990
uut.u_xcorr.\\memr_1_adreg_Z\[3\]          top|clk       DFFR     Q       memr_1_adreg[3]          0.243       -0.584
uut.u_xcorr.\\memr_1_adreg_Z\[2\]          top|clk       DFFR     Q       memr_1_adreg[2]          0.243       -0.563
uut.u_xcorr.\\memr_1_adreg_Z\[5\]          top|clk       DFFR     Q       memr_1_adreg[5]          0.243       -0.563
uut.u_xcorr.\\memr_1_adreg_Z\[4\]          top|clk       DFFR     Q       memr_1_adreg[4]          0.243       -0.542
uut.u_xcorr.\\memr_1_adreg_fast_Z\[9\]     top|clk       DFFR     Q       memr_1_adreg_fast[9]     0.243       -0.490
uut.u_xcorr.\\memr_1_adreg_Z\[7\]          top|clk       DFFR     Q       memr_1_adreg[7]          0.243       -0.476
=====================================================================================================================


Ending Points with Worst Slack
******************************

                                 Starting                                  Required           
Instance                         Reference     Type     Pin     Net        Time         Slack 
                                 Clock                                                        
----------------------------------------------------------------------------------------------
uut.u_xcorr.\\result_Z\[33\]     top|clk       DFFR     D       N_21_0     6.606        -1.189
uut.u_xcorr.\\result_Z\[32\]     top|clk       DFFR     D       N_23_0     6.606        -1.154
uut.u_xcorr.\\result_Z\[31\]     top|clk       DFFR     D       N_25_0     6.606        -1.119
uut.u_xcorr.\\result_Z\[30\]     top|clk       DFFR     D       N_27_0     6.606        -1.084
uut.u_xcorr.\\result_Z\[29\]     top|clk       DFFR     D       N_29_0     6.606        -1.049
uut.u_xcorr.\\result_Z\[28\]     top|clk       DFFR     D       N_31_0     6.606        -1.014
uut.u_xcorr.\\result_Z\[27\]     top|clk       DFFR     D       N_33_0     6.606        -0.979
uut.u_xcorr.\\result_Z\[26\]     top|clk       DFFR     D       N_35_0     6.606        -0.944
uut.u_xcorr.\\result_Z\[25\]     top|clk       DFFR     D       N_37_0     6.606        -0.909
uut.u_xcorr.\\result_Z\[24\]     top|clk       DFFR     D       N_39_0     6.606        -0.874
==============================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      6.667
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.606

    - Propagation time:                      7.795
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.189

    Number of logic level(s):                35
    Starting point:                          uut.u_xcorr.\\memr_1_adreg_fast_Z\[1\] / Q
    Ending point:                            uut.u_xcorr.\\result_Z\[33\] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                       Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
uut.u_xcorr.\\memr_1_adreg_fast_Z\[1\]     DFFR          Q        Out     0.243     0.243       -         
memr_1_adreg_fast[1]                       Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          I1       In      -         0.778       -         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          F        Out     0.570     1.348       -         
memr_1_G_1_6_N_3L3                         Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     S0       In      -         1.883       -         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     O        Out     0.269     2.152       -         
memr_1_G_1_6                               Net           -        -       0.535     -           3         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          I3       In      -         2.687       -         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          F        Out     0.371     3.058       -         
memr_1_G_1                                 Net           -        -       0.657     -           30        
uut.u_xcorr.un2_result_s_4_sf_lofx_cZ      LUT3          I0       In      -         3.715       -         
uut.u_xcorr.un2_result_s_4_sf_lofx_cZ      LUT3          F        Out     0.549     4.264       -         
un2_result_s_4_sf_lofx_cZ                  Net           -        -       0.535     -           1         
uut.u_xcorr.un2_result_cry_4_0             ALU           I0       In      -         4.799       -         
uut.u_xcorr.un2_result_cry_4_0             ALU           COUT     Out     0.549     5.348       -         
un2_result_cry_4_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_5_0             ALU           CIN      In      -         5.348       -         
uut.u_xcorr.un2_result_cry_5_0             ALU           COUT     Out     0.035     5.383       -         
un2_result_cry_5_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_6_0             ALU           CIN      In      -         5.383       -         
uut.u_xcorr.un2_result_cry_6_0             ALU           COUT     Out     0.035     5.418       -         
un2_result_cry_6_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_7_0             ALU           CIN      In      -         5.418       -         
uut.u_xcorr.un2_result_cry_7_0             ALU           COUT     Out     0.035     5.453       -         
un2_result_cry_7_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_8_0             ALU           CIN      In      -         5.453       -         
uut.u_xcorr.un2_result_cry_8_0             ALU           COUT     Out     0.035     5.488       -         
un2_result_cry_8_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_9_0             ALU           CIN      In      -         5.488       -         
uut.u_xcorr.un2_result_cry_9_0             ALU           COUT     Out     0.035     5.523       -         
un2_result_cry_9_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_10_0            ALU           CIN      In      -         5.523       -         
uut.u_xcorr.un2_result_cry_10_0            ALU           COUT     Out     0.035     5.558       -         
un2_result_cry_10_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_11_0            ALU           CIN      In      -         5.558       -         
uut.u_xcorr.un2_result_cry_11_0            ALU           COUT     Out     0.035     5.593       -         
un2_result_cry_11_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_12_0            ALU           CIN      In      -         5.593       -         
uut.u_xcorr.un2_result_cry_12_0            ALU           COUT     Out     0.035     5.628       -         
un2_result_cry_12_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_13_0            ALU           CIN      In      -         5.628       -         
uut.u_xcorr.un2_result_cry_13_0            ALU           COUT     Out     0.035     5.663       -         
un2_result_cry_13_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_14_0            ALU           CIN      In      -         5.663       -         
uut.u_xcorr.un2_result_cry_14_0            ALU           COUT     Out     0.035     5.698       -         
un2_result_cry_14_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_15_0            ALU           CIN      In      -         5.698       -         
uut.u_xcorr.un2_result_cry_15_0            ALU           COUT     Out     0.035     5.733       -         
un2_result_cry_15_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_16_0            ALU           CIN      In      -         5.733       -         
uut.u_xcorr.un2_result_cry_16_0            ALU           COUT     Out     0.035     5.768       -         
un2_result_cry_16_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_17_0            ALU           CIN      In      -         5.768       -         
uut.u_xcorr.un2_result_cry_17_0            ALU           COUT     Out     0.035     5.803       -         
un2_result_cry_17_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_18_0            ALU           CIN      In      -         5.803       -         
uut.u_xcorr.un2_result_cry_18_0            ALU           COUT     Out     0.035     5.838       -         
un2_result_cry_18_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_19_0            ALU           CIN      In      -         5.838       -         
uut.u_xcorr.un2_result_cry_19_0            ALU           COUT     Out     0.035     5.873       -         
un2_result_cry_19_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_20_0            ALU           CIN      In      -         5.873       -         
uut.u_xcorr.un2_result_cry_20_0            ALU           COUT     Out     0.035     5.908       -         
un2_result_cry_20_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_21_0            ALU           CIN      In      -         5.908       -         
uut.u_xcorr.un2_result_cry_21_0            ALU           COUT     Out     0.035     5.943       -         
un2_result_cry_21_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_22_0            ALU           CIN      In      -         5.943       -         
uut.u_xcorr.un2_result_cry_22_0            ALU           COUT     Out     0.035     5.978       -         
un2_result_cry_22_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_23_0            ALU           CIN      In      -         5.978       -         
uut.u_xcorr.un2_result_cry_23_0            ALU           COUT     Out     0.035     6.013       -         
un2_result_cry_23_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_24_0            ALU           CIN      In      -         6.013       -         
uut.u_xcorr.un2_result_cry_24_0            ALU           COUT     Out     0.035     6.048       -         
un2_result_cry_24_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_25_0            ALU           CIN      In      -         6.048       -         
uut.u_xcorr.un2_result_cry_25_0            ALU           COUT     Out     0.035     6.083       -         
un2_result_cry_25_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_26_0            ALU           CIN      In      -         6.083       -         
uut.u_xcorr.un2_result_cry_26_0            ALU           COUT     Out     0.035     6.118       -         
un2_result_cry_26_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_27_0            ALU           CIN      In      -         6.118       -         
uut.u_xcorr.un2_result_cry_27_0            ALU           COUT     Out     0.035     6.153       -         
un2_result_cry_27_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_28_0            ALU           CIN      In      -         6.153       -         
uut.u_xcorr.un2_result_cry_28_0            ALU           COUT     Out     0.035     6.188       -         
un2_result_cry_28_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_29_0            ALU           CIN      In      -         6.188       -         
uut.u_xcorr.un2_result_cry_29_0            ALU           COUT     Out     0.035     6.223       -         
un2_result_cry_29_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_30_0            ALU           CIN      In      -         6.223       -         
uut.u_xcorr.un2_result_cry_30_0            ALU           COUT     Out     0.035     6.258       -         
un2_result_cry_30_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_31_0            ALU           CIN      In      -         6.258       -         
uut.u_xcorr.un2_result_cry_31_0            ALU           COUT     Out     0.035     6.293       -         
un2_result_cry_31_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_32_0            ALU           CIN      In      -         6.293       -         
uut.u_xcorr.un2_result_cry_32_0            ALU           COUT     Out     0.035     6.328       -         
un2_result_cry_32_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_s_33_0              ALU           CIN      In      -         6.328       -         
uut.u_xcorr.un2_result_s_33_0              ALU           SUM      Out     0.470     6.798       -         
un2_result_s_33_0_SUM                      Net           -        -       0.535     -           1         
uut.u_xcorr.\\result_0_0\[33\]             LUT3          I2       In      -         7.333       -         
uut.u_xcorr.\\result_0_0\[33\]             LUT3          F        Out     0.462     7.795       -         
N_21_0                                     Net           -        -       0.000     -           1         
uut.u_xcorr.\\result_Z\[33\]               DFFR          D        In      -         7.795       -         
==========================================================================================================
Total path delay (propagation time + setup) of 7.856 is 4.524(57.6%) logic and 3.332(42.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.667
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.606

    - Propagation time:                      7.774
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.168

    Number of logic level(s):                35
    Starting point:                          uut.u_xcorr.\\memr_1_adreg_fast_Z\[0\] / Q
    Ending point:                            uut.u_xcorr.\\result_Z\[33\] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                       Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
uut.u_xcorr.\\memr_1_adreg_fast_Z\[0\]     DFFR          Q        Out     0.243     0.243       -         
memr_1_adreg_fast[0]                       Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          I0       In      -         0.778       -         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          F        Out     0.549     1.327       -         
memr_1_G_1_6_N_3L3                         Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     S0       In      -         1.862       -         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     O        Out     0.269     2.131       -         
memr_1_G_1_6                               Net           -        -       0.535     -           3         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          I3       In      -         2.666       -         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          F        Out     0.371     3.037       -         
memr_1_G_1                                 Net           -        -       0.657     -           30        
uut.u_xcorr.un2_result_s_4_sf_lofx_cZ      LUT3          I0       In      -         3.694       -         
uut.u_xcorr.un2_result_s_4_sf_lofx_cZ      LUT3          F        Out     0.549     4.243       -         
un2_result_s_4_sf_lofx_cZ                  Net           -        -       0.535     -           1         
uut.u_xcorr.un2_result_cry_4_0             ALU           I0       In      -         4.778       -         
uut.u_xcorr.un2_result_cry_4_0             ALU           COUT     Out     0.549     5.327       -         
un2_result_cry_4_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_5_0             ALU           CIN      In      -         5.327       -         
uut.u_xcorr.un2_result_cry_5_0             ALU           COUT     Out     0.035     5.362       -         
un2_result_cry_5_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_6_0             ALU           CIN      In      -         5.362       -         
uut.u_xcorr.un2_result_cry_6_0             ALU           COUT     Out     0.035     5.397       -         
un2_result_cry_6_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_7_0             ALU           CIN      In      -         5.397       -         
uut.u_xcorr.un2_result_cry_7_0             ALU           COUT     Out     0.035     5.432       -         
un2_result_cry_7_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_8_0             ALU           CIN      In      -         5.432       -         
uut.u_xcorr.un2_result_cry_8_0             ALU           COUT     Out     0.035     5.467       -         
un2_result_cry_8_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_9_0             ALU           CIN      In      -         5.467       -         
uut.u_xcorr.un2_result_cry_9_0             ALU           COUT     Out     0.035     5.502       -         
un2_result_cry_9_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_10_0            ALU           CIN      In      -         5.502       -         
uut.u_xcorr.un2_result_cry_10_0            ALU           COUT     Out     0.035     5.537       -         
un2_result_cry_10_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_11_0            ALU           CIN      In      -         5.537       -         
uut.u_xcorr.un2_result_cry_11_0            ALU           COUT     Out     0.035     5.572       -         
un2_result_cry_11_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_12_0            ALU           CIN      In      -         5.572       -         
uut.u_xcorr.un2_result_cry_12_0            ALU           COUT     Out     0.035     5.607       -         
un2_result_cry_12_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_13_0            ALU           CIN      In      -         5.607       -         
uut.u_xcorr.un2_result_cry_13_0            ALU           COUT     Out     0.035     5.642       -         
un2_result_cry_13_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_14_0            ALU           CIN      In      -         5.642       -         
uut.u_xcorr.un2_result_cry_14_0            ALU           COUT     Out     0.035     5.677       -         
un2_result_cry_14_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_15_0            ALU           CIN      In      -         5.677       -         
uut.u_xcorr.un2_result_cry_15_0            ALU           COUT     Out     0.035     5.712       -         
un2_result_cry_15_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_16_0            ALU           CIN      In      -         5.712       -         
uut.u_xcorr.un2_result_cry_16_0            ALU           COUT     Out     0.035     5.747       -         
un2_result_cry_16_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_17_0            ALU           CIN      In      -         5.747       -         
uut.u_xcorr.un2_result_cry_17_0            ALU           COUT     Out     0.035     5.782       -         
un2_result_cry_17_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_18_0            ALU           CIN      In      -         5.782       -         
uut.u_xcorr.un2_result_cry_18_0            ALU           COUT     Out     0.035     5.817       -         
un2_result_cry_18_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_19_0            ALU           CIN      In      -         5.817       -         
uut.u_xcorr.un2_result_cry_19_0            ALU           COUT     Out     0.035     5.852       -         
un2_result_cry_19_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_20_0            ALU           CIN      In      -         5.852       -         
uut.u_xcorr.un2_result_cry_20_0            ALU           COUT     Out     0.035     5.887       -         
un2_result_cry_20_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_21_0            ALU           CIN      In      -         5.887       -         
uut.u_xcorr.un2_result_cry_21_0            ALU           COUT     Out     0.035     5.922       -         
un2_result_cry_21_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_22_0            ALU           CIN      In      -         5.922       -         
uut.u_xcorr.un2_result_cry_22_0            ALU           COUT     Out     0.035     5.957       -         
un2_result_cry_22_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_23_0            ALU           CIN      In      -         5.957       -         
uut.u_xcorr.un2_result_cry_23_0            ALU           COUT     Out     0.035     5.992       -         
un2_result_cry_23_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_24_0            ALU           CIN      In      -         5.992       -         
uut.u_xcorr.un2_result_cry_24_0            ALU           COUT     Out     0.035     6.027       -         
un2_result_cry_24_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_25_0            ALU           CIN      In      -         6.027       -         
uut.u_xcorr.un2_result_cry_25_0            ALU           COUT     Out     0.035     6.062       -         
un2_result_cry_25_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_26_0            ALU           CIN      In      -         6.062       -         
uut.u_xcorr.un2_result_cry_26_0            ALU           COUT     Out     0.035     6.097       -         
un2_result_cry_26_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_27_0            ALU           CIN      In      -         6.097       -         
uut.u_xcorr.un2_result_cry_27_0            ALU           COUT     Out     0.035     6.132       -         
un2_result_cry_27_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_28_0            ALU           CIN      In      -         6.132       -         
uut.u_xcorr.un2_result_cry_28_0            ALU           COUT     Out     0.035     6.167       -         
un2_result_cry_28_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_29_0            ALU           CIN      In      -         6.167       -         
uut.u_xcorr.un2_result_cry_29_0            ALU           COUT     Out     0.035     6.202       -         
un2_result_cry_29_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_30_0            ALU           CIN      In      -         6.202       -         
uut.u_xcorr.un2_result_cry_30_0            ALU           COUT     Out     0.035     6.237       -         
un2_result_cry_30_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_31_0            ALU           CIN      In      -         6.237       -         
uut.u_xcorr.un2_result_cry_31_0            ALU           COUT     Out     0.035     6.272       -         
un2_result_cry_31_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_32_0            ALU           CIN      In      -         6.272       -         
uut.u_xcorr.un2_result_cry_32_0            ALU           COUT     Out     0.035     6.307       -         
un2_result_cry_32_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_s_33_0              ALU           CIN      In      -         6.307       -         
uut.u_xcorr.un2_result_s_33_0              ALU           SUM      Out     0.470     6.777       -         
un2_result_s_33_0_SUM                      Net           -        -       0.535     -           1         
uut.u_xcorr.\\result_0_0\[33\]             LUT3          I2       In      -         7.312       -         
uut.u_xcorr.\\result_0_0\[33\]             LUT3          F        Out     0.462     7.774       -         
N_21_0                                     Net           -        -       0.000     -           1         
uut.u_xcorr.\\result_Z\[33\]               DFFR          D        In      -         7.774       -         
==========================================================================================================
Total path delay (propagation time + setup) of 7.835 is 4.503(57.5%) logic and 3.332(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.667
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.606

    - Propagation time:                      7.760
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.154

    Number of logic level(s):                34
    Starting point:                          uut.u_xcorr.\\memr_1_adreg_fast_Z\[1\] / Q
    Ending point:                            uut.u_xcorr.\\result_Z\[33\] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                       Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
uut.u_xcorr.\\memr_1_adreg_fast_Z\[1\]     DFFR          Q        Out     0.243     0.243       -         
memr_1_adreg_fast[1]                       Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          I1       In      -         0.778       -         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          F        Out     0.570     1.348       -         
memr_1_G_1_6_N_3L3                         Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     S0       In      -         1.883       -         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     O        Out     0.269     2.152       -         
memr_1_G_1_6                               Net           -        -       0.535     -           3         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          I3       In      -         2.687       -         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          F        Out     0.371     3.058       -         
memr_1_G_1                                 Net           -        -       0.657     -           30        
uut.u_xcorr.un2_result_s_5_sf_lofx_cZ      LUT3          I0       In      -         3.715       -         
uut.u_xcorr.un2_result_s_5_sf_lofx_cZ      LUT3          F        Out     0.549     4.264       -         
un2_result_s_5_sf_lofx_cZ                  Net           -        -       0.535     -           1         
uut.u_xcorr.un2_result_cry_5_0             ALU           I0       In      -         4.799       -         
uut.u_xcorr.un2_result_cry_5_0             ALU           COUT     Out     0.549     5.348       -         
un2_result_cry_5_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_6_0             ALU           CIN      In      -         5.348       -         
uut.u_xcorr.un2_result_cry_6_0             ALU           COUT     Out     0.035     5.383       -         
un2_result_cry_6_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_7_0             ALU           CIN      In      -         5.383       -         
uut.u_xcorr.un2_result_cry_7_0             ALU           COUT     Out     0.035     5.418       -         
un2_result_cry_7_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_8_0             ALU           CIN      In      -         5.418       -         
uut.u_xcorr.un2_result_cry_8_0             ALU           COUT     Out     0.035     5.453       -         
un2_result_cry_8_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_9_0             ALU           CIN      In      -         5.453       -         
uut.u_xcorr.un2_result_cry_9_0             ALU           COUT     Out     0.035     5.488       -         
un2_result_cry_9_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_10_0            ALU           CIN      In      -         5.488       -         
uut.u_xcorr.un2_result_cry_10_0            ALU           COUT     Out     0.035     5.523       -         
un2_result_cry_10_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_11_0            ALU           CIN      In      -         5.523       -         
uut.u_xcorr.un2_result_cry_11_0            ALU           COUT     Out     0.035     5.558       -         
un2_result_cry_11_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_12_0            ALU           CIN      In      -         5.558       -         
uut.u_xcorr.un2_result_cry_12_0            ALU           COUT     Out     0.035     5.593       -         
un2_result_cry_12_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_13_0            ALU           CIN      In      -         5.593       -         
uut.u_xcorr.un2_result_cry_13_0            ALU           COUT     Out     0.035     5.628       -         
un2_result_cry_13_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_14_0            ALU           CIN      In      -         5.628       -         
uut.u_xcorr.un2_result_cry_14_0            ALU           COUT     Out     0.035     5.663       -         
un2_result_cry_14_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_15_0            ALU           CIN      In      -         5.663       -         
uut.u_xcorr.un2_result_cry_15_0            ALU           COUT     Out     0.035     5.698       -         
un2_result_cry_15_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_16_0            ALU           CIN      In      -         5.698       -         
uut.u_xcorr.un2_result_cry_16_0            ALU           COUT     Out     0.035     5.733       -         
un2_result_cry_16_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_17_0            ALU           CIN      In      -         5.733       -         
uut.u_xcorr.un2_result_cry_17_0            ALU           COUT     Out     0.035     5.768       -         
un2_result_cry_17_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_18_0            ALU           CIN      In      -         5.768       -         
uut.u_xcorr.un2_result_cry_18_0            ALU           COUT     Out     0.035     5.803       -         
un2_result_cry_18_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_19_0            ALU           CIN      In      -         5.803       -         
uut.u_xcorr.un2_result_cry_19_0            ALU           COUT     Out     0.035     5.838       -         
un2_result_cry_19_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_20_0            ALU           CIN      In      -         5.838       -         
uut.u_xcorr.un2_result_cry_20_0            ALU           COUT     Out     0.035     5.873       -         
un2_result_cry_20_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_21_0            ALU           CIN      In      -         5.873       -         
uut.u_xcorr.un2_result_cry_21_0            ALU           COUT     Out     0.035     5.908       -         
un2_result_cry_21_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_22_0            ALU           CIN      In      -         5.908       -         
uut.u_xcorr.un2_result_cry_22_0            ALU           COUT     Out     0.035     5.943       -         
un2_result_cry_22_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_23_0            ALU           CIN      In      -         5.943       -         
uut.u_xcorr.un2_result_cry_23_0            ALU           COUT     Out     0.035     5.978       -         
un2_result_cry_23_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_24_0            ALU           CIN      In      -         5.978       -         
uut.u_xcorr.un2_result_cry_24_0            ALU           COUT     Out     0.035     6.013       -         
un2_result_cry_24_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_25_0            ALU           CIN      In      -         6.013       -         
uut.u_xcorr.un2_result_cry_25_0            ALU           COUT     Out     0.035     6.048       -         
un2_result_cry_25_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_26_0            ALU           CIN      In      -         6.048       -         
uut.u_xcorr.un2_result_cry_26_0            ALU           COUT     Out     0.035     6.083       -         
un2_result_cry_26_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_27_0            ALU           CIN      In      -         6.083       -         
uut.u_xcorr.un2_result_cry_27_0            ALU           COUT     Out     0.035     6.118       -         
un2_result_cry_27_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_28_0            ALU           CIN      In      -         6.118       -         
uut.u_xcorr.un2_result_cry_28_0            ALU           COUT     Out     0.035     6.153       -         
un2_result_cry_28_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_29_0            ALU           CIN      In      -         6.153       -         
uut.u_xcorr.un2_result_cry_29_0            ALU           COUT     Out     0.035     6.188       -         
un2_result_cry_29_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_30_0            ALU           CIN      In      -         6.188       -         
uut.u_xcorr.un2_result_cry_30_0            ALU           COUT     Out     0.035     6.223       -         
un2_result_cry_30_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_31_0            ALU           CIN      In      -         6.223       -         
uut.u_xcorr.un2_result_cry_31_0            ALU           COUT     Out     0.035     6.258       -         
un2_result_cry_31_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_32_0            ALU           CIN      In      -         6.258       -         
uut.u_xcorr.un2_result_cry_32_0            ALU           COUT     Out     0.035     6.293       -         
un2_result_cry_32_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_s_33_0              ALU           CIN      In      -         6.293       -         
uut.u_xcorr.un2_result_s_33_0              ALU           SUM      Out     0.470     6.763       -         
un2_result_s_33_0_SUM                      Net           -        -       0.535     -           1         
uut.u_xcorr.\\result_0_0\[33\]             LUT3          I2       In      -         7.298       -         
uut.u_xcorr.\\result_0_0\[33\]             LUT3          F        Out     0.462     7.760       -         
N_21_0                                     Net           -        -       0.000     -           1         
uut.u_xcorr.\\result_Z\[33\]               DFFR          D        In      -         7.760       -         
==========================================================================================================
Total path delay (propagation time + setup) of 7.821 is 4.489(57.4%) logic and 3.332(42.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.667
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.606

    - Propagation time:                      7.760
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.154

    Number of logic level(s):                34
    Starting point:                          uut.u_xcorr.\\memr_1_adreg_fast_Z\[1\] / Q
    Ending point:                            uut.u_xcorr.\\result_Z\[32\] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                       Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
uut.u_xcorr.\\memr_1_adreg_fast_Z\[1\]     DFFR          Q        Out     0.243     0.243       -         
memr_1_adreg_fast[1]                       Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          I1       In      -         0.778       -         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          F        Out     0.570     1.348       -         
memr_1_G_1_6_N_3L3                         Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     S0       In      -         1.883       -         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     O        Out     0.269     2.152       -         
memr_1_G_1_6                               Net           -        -       0.535     -           3         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          I3       In      -         2.687       -         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          F        Out     0.371     3.058       -         
memr_1_G_1                                 Net           -        -       0.657     -           30        
uut.u_xcorr.un2_result_s_4_sf_lofx_cZ      LUT3          I0       In      -         3.715       -         
uut.u_xcorr.un2_result_s_4_sf_lofx_cZ      LUT3          F        Out     0.549     4.264       -         
un2_result_s_4_sf_lofx_cZ                  Net           -        -       0.535     -           1         
uut.u_xcorr.un2_result_cry_4_0             ALU           I0       In      -         4.799       -         
uut.u_xcorr.un2_result_cry_4_0             ALU           COUT     Out     0.549     5.348       -         
un2_result_cry_4_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_5_0             ALU           CIN      In      -         5.348       -         
uut.u_xcorr.un2_result_cry_5_0             ALU           COUT     Out     0.035     5.383       -         
un2_result_cry_5_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_6_0             ALU           CIN      In      -         5.383       -         
uut.u_xcorr.un2_result_cry_6_0             ALU           COUT     Out     0.035     5.418       -         
un2_result_cry_6_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_7_0             ALU           CIN      In      -         5.418       -         
uut.u_xcorr.un2_result_cry_7_0             ALU           COUT     Out     0.035     5.453       -         
un2_result_cry_7_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_8_0             ALU           CIN      In      -         5.453       -         
uut.u_xcorr.un2_result_cry_8_0             ALU           COUT     Out     0.035     5.488       -         
un2_result_cry_8_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_9_0             ALU           CIN      In      -         5.488       -         
uut.u_xcorr.un2_result_cry_9_0             ALU           COUT     Out     0.035     5.523       -         
un2_result_cry_9_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_10_0            ALU           CIN      In      -         5.523       -         
uut.u_xcorr.un2_result_cry_10_0            ALU           COUT     Out     0.035     5.558       -         
un2_result_cry_10_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_11_0            ALU           CIN      In      -         5.558       -         
uut.u_xcorr.un2_result_cry_11_0            ALU           COUT     Out     0.035     5.593       -         
un2_result_cry_11_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_12_0            ALU           CIN      In      -         5.593       -         
uut.u_xcorr.un2_result_cry_12_0            ALU           COUT     Out     0.035     5.628       -         
un2_result_cry_12_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_13_0            ALU           CIN      In      -         5.628       -         
uut.u_xcorr.un2_result_cry_13_0            ALU           COUT     Out     0.035     5.663       -         
un2_result_cry_13_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_14_0            ALU           CIN      In      -         5.663       -         
uut.u_xcorr.un2_result_cry_14_0            ALU           COUT     Out     0.035     5.698       -         
un2_result_cry_14_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_15_0            ALU           CIN      In      -         5.698       -         
uut.u_xcorr.un2_result_cry_15_0            ALU           COUT     Out     0.035     5.733       -         
un2_result_cry_15_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_16_0            ALU           CIN      In      -         5.733       -         
uut.u_xcorr.un2_result_cry_16_0            ALU           COUT     Out     0.035     5.768       -         
un2_result_cry_16_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_17_0            ALU           CIN      In      -         5.768       -         
uut.u_xcorr.un2_result_cry_17_0            ALU           COUT     Out     0.035     5.803       -         
un2_result_cry_17_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_18_0            ALU           CIN      In      -         5.803       -         
uut.u_xcorr.un2_result_cry_18_0            ALU           COUT     Out     0.035     5.838       -         
un2_result_cry_18_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_19_0            ALU           CIN      In      -         5.838       -         
uut.u_xcorr.un2_result_cry_19_0            ALU           COUT     Out     0.035     5.873       -         
un2_result_cry_19_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_20_0            ALU           CIN      In      -         5.873       -         
uut.u_xcorr.un2_result_cry_20_0            ALU           COUT     Out     0.035     5.908       -         
un2_result_cry_20_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_21_0            ALU           CIN      In      -         5.908       -         
uut.u_xcorr.un2_result_cry_21_0            ALU           COUT     Out     0.035     5.943       -         
un2_result_cry_21_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_22_0            ALU           CIN      In      -         5.943       -         
uut.u_xcorr.un2_result_cry_22_0            ALU           COUT     Out     0.035     5.978       -         
un2_result_cry_22_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_23_0            ALU           CIN      In      -         5.978       -         
uut.u_xcorr.un2_result_cry_23_0            ALU           COUT     Out     0.035     6.013       -         
un2_result_cry_23_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_24_0            ALU           CIN      In      -         6.013       -         
uut.u_xcorr.un2_result_cry_24_0            ALU           COUT     Out     0.035     6.048       -         
un2_result_cry_24_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_25_0            ALU           CIN      In      -         6.048       -         
uut.u_xcorr.un2_result_cry_25_0            ALU           COUT     Out     0.035     6.083       -         
un2_result_cry_25_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_26_0            ALU           CIN      In      -         6.083       -         
uut.u_xcorr.un2_result_cry_26_0            ALU           COUT     Out     0.035     6.118       -         
un2_result_cry_26_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_27_0            ALU           CIN      In      -         6.118       -         
uut.u_xcorr.un2_result_cry_27_0            ALU           COUT     Out     0.035     6.153       -         
un2_result_cry_27_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_28_0            ALU           CIN      In      -         6.153       -         
uut.u_xcorr.un2_result_cry_28_0            ALU           COUT     Out     0.035     6.188       -         
un2_result_cry_28_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_29_0            ALU           CIN      In      -         6.188       -         
uut.u_xcorr.un2_result_cry_29_0            ALU           COUT     Out     0.035     6.223       -         
un2_result_cry_29_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_30_0            ALU           CIN      In      -         6.223       -         
uut.u_xcorr.un2_result_cry_30_0            ALU           COUT     Out     0.035     6.258       -         
un2_result_cry_30_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_31_0            ALU           CIN      In      -         6.258       -         
uut.u_xcorr.un2_result_cry_31_0            ALU           COUT     Out     0.035     6.293       -         
un2_result_cry_31_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_32_0            ALU           CIN      In      -         6.293       -         
uut.u_xcorr.un2_result_cry_32_0            ALU           SUM      Out     0.470     6.763       -         
un2_result_cry_32_0_SUM                    Net           -        -       0.535     -           1         
uut.u_xcorr.\\result_0_0\[32\]             LUT3          I2       In      -         7.298       -         
uut.u_xcorr.\\result_0_0\[32\]             LUT3          F        Out     0.462     7.760       -         
N_23_0                                     Net           -        -       0.000     -           1         
uut.u_xcorr.\\result_Z\[32\]               DFFR          D        In      -         7.760       -         
==========================================================================================================
Total path delay (propagation time + setup) of 7.821 is 4.489(57.4%) logic and 3.332(42.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.667
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.606

    - Propagation time:                      7.739
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.133

    Number of logic level(s):                34
    Starting point:                          uut.u_xcorr.\\memr_1_adreg_fast_Z\[0\] / Q
    Ending point:                            uut.u_xcorr.\\result_Z\[33\] / D
    The start point is clocked by            top|clk [rising] on pin CLK
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                           Pin      Pin               Arrival     No. of    
Name                                       Type          Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
uut.u_xcorr.\\memr_1_adreg_fast_Z\[0\]     DFFR          Q        Out     0.243     0.243       -         
memr_1_adreg_fast[0]                       Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          I0       In      -         0.778       -         
uut.u_xcorr.memr_1_G_1_6_N_3L3_cZ          LUT4          F        Out     0.549     1.327       -         
memr_1_G_1_6_N_3L3                         Net           -        -       0.535     -           1         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     S0       In      -         1.862       -         
uut.u_xcorr.memr_1_G_1_6_cZ                MUX2_LUT5     O        Out     0.269     2.131       -         
memr_1_G_1_6                               Net           -        -       0.535     -           3         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          I3       In      -         2.666       -         
uut.u_xcorr.memr_1_G_1_cZ                  LUT4          F        Out     0.371     3.037       -         
memr_1_G_1                                 Net           -        -       0.657     -           30        
uut.u_xcorr.un2_result_s_5_sf_lofx_cZ      LUT3          I0       In      -         3.694       -         
uut.u_xcorr.un2_result_s_5_sf_lofx_cZ      LUT3          F        Out     0.549     4.243       -         
un2_result_s_5_sf_lofx_cZ                  Net           -        -       0.535     -           1         
uut.u_xcorr.un2_result_cry_5_0             ALU           I0       In      -         4.778       -         
uut.u_xcorr.un2_result_cry_5_0             ALU           COUT     Out     0.549     5.327       -         
un2_result_cry_5_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_6_0             ALU           CIN      In      -         5.327       -         
uut.u_xcorr.un2_result_cry_6_0             ALU           COUT     Out     0.035     5.362       -         
un2_result_cry_6_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_7_0             ALU           CIN      In      -         5.362       -         
uut.u_xcorr.un2_result_cry_7_0             ALU           COUT     Out     0.035     5.397       -         
un2_result_cry_7_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_8_0             ALU           CIN      In      -         5.397       -         
uut.u_xcorr.un2_result_cry_8_0             ALU           COUT     Out     0.035     5.432       -         
un2_result_cry_8_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_9_0             ALU           CIN      In      -         5.432       -         
uut.u_xcorr.un2_result_cry_9_0             ALU           COUT     Out     0.035     5.467       -         
un2_result_cry_9_0_COUT                    Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_10_0            ALU           CIN      In      -         5.467       -         
uut.u_xcorr.un2_result_cry_10_0            ALU           COUT     Out     0.035     5.502       -         
un2_result_cry_10_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_11_0            ALU           CIN      In      -         5.502       -         
uut.u_xcorr.un2_result_cry_11_0            ALU           COUT     Out     0.035     5.537       -         
un2_result_cry_11_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_12_0            ALU           CIN      In      -         5.537       -         
uut.u_xcorr.un2_result_cry_12_0            ALU           COUT     Out     0.035     5.572       -         
un2_result_cry_12_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_13_0            ALU           CIN      In      -         5.572       -         
uut.u_xcorr.un2_result_cry_13_0            ALU           COUT     Out     0.035     5.607       -         
un2_result_cry_13_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_14_0            ALU           CIN      In      -         5.607       -         
uut.u_xcorr.un2_result_cry_14_0            ALU           COUT     Out     0.035     5.642       -         
un2_result_cry_14_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_15_0            ALU           CIN      In      -         5.642       -         
uut.u_xcorr.un2_result_cry_15_0            ALU           COUT     Out     0.035     5.677       -         
un2_result_cry_15_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_16_0            ALU           CIN      In      -         5.677       -         
uut.u_xcorr.un2_result_cry_16_0            ALU           COUT     Out     0.035     5.712       -         
un2_result_cry_16_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_17_0            ALU           CIN      In      -         5.712       -         
uut.u_xcorr.un2_result_cry_17_0            ALU           COUT     Out     0.035     5.747       -         
un2_result_cry_17_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_18_0            ALU           CIN      In      -         5.747       -         
uut.u_xcorr.un2_result_cry_18_0            ALU           COUT     Out     0.035     5.782       -         
un2_result_cry_18_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_19_0            ALU           CIN      In      -         5.782       -         
uut.u_xcorr.un2_result_cry_19_0            ALU           COUT     Out     0.035     5.817       -         
un2_result_cry_19_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_20_0            ALU           CIN      In      -         5.817       -         
uut.u_xcorr.un2_result_cry_20_0            ALU           COUT     Out     0.035     5.852       -         
un2_result_cry_20_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_21_0            ALU           CIN      In      -         5.852       -         
uut.u_xcorr.un2_result_cry_21_0            ALU           COUT     Out     0.035     5.887       -         
un2_result_cry_21_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_22_0            ALU           CIN      In      -         5.887       -         
uut.u_xcorr.un2_result_cry_22_0            ALU           COUT     Out     0.035     5.922       -         
un2_result_cry_22_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_23_0            ALU           CIN      In      -         5.922       -         
uut.u_xcorr.un2_result_cry_23_0            ALU           COUT     Out     0.035     5.957       -         
un2_result_cry_23_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_24_0            ALU           CIN      In      -         5.957       -         
uut.u_xcorr.un2_result_cry_24_0            ALU           COUT     Out     0.035     5.992       -         
un2_result_cry_24_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_25_0            ALU           CIN      In      -         5.992       -         
uut.u_xcorr.un2_result_cry_25_0            ALU           COUT     Out     0.035     6.027       -         
un2_result_cry_25_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_26_0            ALU           CIN      In      -         6.027       -         
uut.u_xcorr.un2_result_cry_26_0            ALU           COUT     Out     0.035     6.062       -         
un2_result_cry_26_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_27_0            ALU           CIN      In      -         6.062       -         
uut.u_xcorr.un2_result_cry_27_0            ALU           COUT     Out     0.035     6.097       -         
un2_result_cry_27_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_28_0            ALU           CIN      In      -         6.097       -         
uut.u_xcorr.un2_result_cry_28_0            ALU           COUT     Out     0.035     6.132       -         
un2_result_cry_28_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_29_0            ALU           CIN      In      -         6.132       -         
uut.u_xcorr.un2_result_cry_29_0            ALU           COUT     Out     0.035     6.167       -         
un2_result_cry_29_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_30_0            ALU           CIN      In      -         6.167       -         
uut.u_xcorr.un2_result_cry_30_0            ALU           COUT     Out     0.035     6.202       -         
un2_result_cry_30_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_31_0            ALU           CIN      In      -         6.202       -         
uut.u_xcorr.un2_result_cry_31_0            ALU           COUT     Out     0.035     6.237       -         
un2_result_cry_31_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_cry_32_0            ALU           CIN      In      -         6.237       -         
uut.u_xcorr.un2_result_cry_32_0            ALU           COUT     Out     0.035     6.272       -         
un2_result_cry_32_0_COUT                   Net           -        -       0.000     -           1         
uut.u_xcorr.un2_result_s_33_0              ALU           CIN      In      -         6.272       -         
uut.u_xcorr.un2_result_s_33_0              ALU           SUM      Out     0.470     6.742       -         
un2_result_s_33_0_SUM                      Net           -        -       0.535     -           1         
uut.u_xcorr.\\result_0_0\[33\]             LUT3          I2       In      -         7.277       -         
uut.u_xcorr.\\result_0_0\[33\]             LUT3          F        Out     0.462     7.739       -         
N_21_0                                     Net           -        -       0.000     -           1         
uut.u_xcorr.\\result_Z\[33\]               DFFR          D        In      -         7.739       -         
==========================================================================================================
Total path delay (propagation time + setup) of 7.800 is 4.468(57.3%) logic and 3.332(42.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                              Starting                                                         Arrival          
Instance                                      Reference     Type     Pin     Net                               Time        Slack
                                              Clock                                                                             
--------------------------------------------------------------------------------------------------------------------------------
uut.u_xcorr.un1_delay_22_cry_4_0_RNO_0_cZ     System        INV      O       un1_delay_22_cry_4_0_RNO_0_cZ     0.000       4.067
uut.u_xcorr.x_1_ret_33_0_RNI69O7              System        INV      O       x_1_ret_33_0_RNI69O7              0.000       5.888
ut.cnt_r_RNO[2]                               System        INV      O       N_3_0                             0.000       6.071
================================================================================================================================


Ending Points with Worst Slack
******************************

                                 Starting                                                Required          
Instance                         Reference     Type     Pin     Net                      Time         Slack
                                 Clock                                                                     
-----------------------------------------------------------------------------------------------------------
uut.u_xcorr.x_1_ret_33_0         System        DFF      D       un1_x_112_0_0_cZ         6.606        4.067
uut.u_xcorr.\\x_1_ret_0\[0\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.606        5.888
uut.u_xcorr.\\x_1_ret_0\[1\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.606        5.888
uut.u_xcorr.\\x_1_ret_0\[2\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.606        5.888
uut.u_xcorr.\\x_1_ret_0\[3\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.606        5.888
uut.u_xcorr.\\x_1_ret_0\[4\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.606        5.888
uut.u_xcorr.\\x_1_ret_0\[5\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.606        5.888
uut.u_xcorr.\\x_1_ret_0\[6\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.606        5.888
uut.u_xcorr.\\x_1_ret_0\[7\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.606        5.888
uut.u_xcorr.\\x_1_ret_0\[8\]     System        DFFE     CE      x_1_ret_33_0_RNI69O7     6.606        5.888
===========================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      6.667
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.606

    - Propagation time:                      2.539
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 4.067

    Number of logic level(s):                8
    Starting point:                          uut.u_xcorr.un1_delay_22_cry_4_0_RNO_0_cZ / O
    Ending point:                            uut.u_xcorr.x_1_ret_33_0 / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            top|clk [rising] on pin CLK

Instance / Net                                         Pin      Pin               Arrival     No. of    
Name                                          Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------
uut.u_xcorr.un1_delay_22_cry_4_0_RNO_0_cZ     INV      O        Out     0.000     0.000       -         
un1_delay_22_cry_4_0_RNO_0_cZ                 Net      -        -       0.535     -           1         
uut.u_xcorr.un1_delay_22_cry_4_0              ALU      I3       In      -         0.535       -         
uut.u_xcorr.un1_delay_22_cry_4_0              ALU      COUT     Out     0.371     0.906       -         
un1_delay_22_cry_4_0_COUT                     Net      -        -       0.000     -           1         
uut.u_xcorr.un1_delay_22_cry_5_0              ALU      CIN      In      -         0.906       -         
uut.u_xcorr.un1_delay_22_cry_5_0              ALU      COUT     Out     0.035     0.941       -         
un1_delay_22_cry_5_0_COUT                     Net      -        -       0.000     -           1         
uut.u_xcorr.un1_delay_22_cry_6_0              ALU      CIN      In      -         0.941       -         
uut.u_xcorr.un1_delay_22_cry_6_0              ALU      COUT     Out     0.035     0.976       -         
un1_delay_22_cry_6_0_COUT                     Net      -        -       0.000     -           1         
uut.u_xcorr.un1_delay_22_cry_7_0              ALU      CIN      In      -         0.976       -         
uut.u_xcorr.un1_delay_22_cry_7_0              ALU      COUT     Out     0.035     1.011       -         
un1_delay_22_cry_7_0_COUT                     Net      -        -       0.000     -           1         
uut.u_xcorr.un1_delay_22_cry_8_0              ALU      CIN      In      -         1.011       -         
uut.u_xcorr.un1_delay_22_cry_8_0              ALU      COUT     Out     0.035     1.046       -         
un1_delay_22_cry_8_0_COUT                     Net      -        -       0.000     -           1         
uut.u_xcorr.un1_delay_22_cry_9_0              ALU      CIN      In      -         1.046       -         
uut.u_xcorr.un1_delay_22_cry_9_0              ALU      COUT     Out     0.035     1.081       -         
un1_delay_22_cry_9_0_COUT                     Net      -        -       0.000     -           1         
uut.u_xcorr.un1_delay_22_cry_10_0             ALU      CIN      In      -         1.081       -         
uut.u_xcorr.un1_delay_22_cry_10_0             ALU      COUT     Out     0.035     1.116       -         
un1_delay_22_cry_10_0_COUT                    Net      -        -       0.961     -           1         
uut.u_xcorr.un1_x_112_0_0_cZ                  LUT4     I2       In      -         2.077       -         
uut.u_xcorr.un1_x_112_0_0_cZ                  LUT4     F        Out     0.462     2.539       -         
un1_x_112_0_0_cZ                              Net      -        -       0.000     -           1         
uut.u_xcorr.x_1_ret_33_0                      DFF      D        In      -         2.539       -         
========================================================================================================
Total path delay (propagation time + setup) of 2.600 is 1.104(42.5%) logic and 1.496(57.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 192MB peak: 198MB)


Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 192MB peak: 198MB)

---------------------------------------
Resource Usage Report for top 

Mapping to part: gw2a_55pbga484-8
Cell usage:
ALU             144 uses
DFF             59 uses
DFFE            34 uses
DFFR            134 uses
DFFRE           2 uses
DFFS            2 uses
DPX9            2 uses
GSR             1 use
INV             3 uses
MUX2_LUT5       3 uses
MUX2_LUT6       1 use
ROM             3 uses
SDPX9           2 uses
LUT2            118 uses
LUT3            123 uses
LUT4            97 uses
MULT18X18      1 use

I/O ports: 82
I/O primitives: 81
IBUF           2 uses
OBUF           79 uses

I/O Register bits:                  0
Register bits not including I/Os:   231 of 41040 (0%)

RAM/ROM usage summary
Block Rams : 7 of 140 (5%)


Block Multipliers: 1 of 20 (5%)
Total load per clock:
   top|clk: 242

@S |Mapping Summary:
Total  LUTs: 338 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 41MB peak: 198MB)

Process took 0h:00m:07s realtime, 0h:00m:07s cputime
# Tue Dec 18 16:27:18 2018

###########################################################]
