@W: CG532 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":37:0:37:6|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
@W: CG532 :"/home/wenbo/Desktop/Gowin_XCORR_RefDesign/XCORR_1024-1_case/project/src/top.v":45:0:45:6|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.

