`timescale 1ns / 1ps
module tb();
parameter VCS_SIM=1;
parameter N=512;
parameter W=17;

function integer clogb2(input integer N);
        begin
                for(clogb2=0;N>1;clogb2=clogb2+1)
                        N = N >> 1;
        end
endfunction
GSR GSR(1'b1);
reg clk;
reg rst;
reg start_1=1;
wire signed [W-1:0]a;
wire signed [W-1:0]b;
wire complete;
wire [9:0] delay;
wire signed [2*W-1:0]result;
reg [clogb2(N)-1:0] ad=0;

initial begin
        rst = 0;
        #10 rst = 1;
        #20 rst = 0;
        start_1 = 1;
        #20 start_1 = 0;
end
initial begin
        clk = 0;
end
always #10 clk = ~clk;

top
#(
        .VCS_SIM(1)
)
uut
(
        .complete(complete),
        .delay(delay),
        .clk(clk),
        .rst(rst),
        .a(a),
        .b(b),
        .result(result),
        .start_1(start_1)
);

initial begin
        $fsdbDumpfile("tb.fsdb");
        $fsdbDumpvars;
end
initial #500000 $finish;
endmodule
