library verilog;
use verilog.vl_types.all;
entity ADC is
    generic(
        VREF_EN         : vl_logic := Hi0;
        VREF_SEL        : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0)
    );
    port(
        ADOUT           : out    vl_logic_vector(11 downto 0);
        EOC             : out    vl_logic;
        CLK             : in     vl_logic;
        PD              : in     vl_logic;
        SOC             : in     vl_logic;
        SEL             : in     vl_logic_vector(2 downto 0);
        CH              : in     vl_logic_vector(7 downto 0);
        VREF            : in     vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of VREF_EN : constant is 1;
    attribute mti_svvh_generic_type of VREF_SEL : constant is 1;
end ADC;
