`timescale 1ns / 1ps
module top(a,b,result,clk,rst,delay,complete,start_1);
parameter VCS_SIM=0;
parameter N=512;
input clk,rst;
input start_1;
output signed [33:0] result;
output signed [16:0] a,b;
output [9:0] delay;
output complete;
wire [9:0] delay;
wire complete;
wire signed [16:0] a,b;
reg signed [16:0] series_x,series_y;
wire signed [33:0] result;
wire clk,rst;
wire start;
reg [8:0] ad=0;
XCORR_Top uut
(
    .series_x(series_x),
    .series_y(series_y),
    .result(result),
    .clk(clk),
    .rst(rst),
    .delay(delay),
    .complete(complete),
    .start(start)
);
deUstb ut
(
    .in(start_1),
    .out(start),
    .clk(clk)
);
reg signed [16:0] memx [0:N-1];
initial
        if(VCS_SIM==1) begin
        $readmemb("../../project/data/o_x.dat",memx);
      end
        else begin
        $readmemb("o_x.dat",memx);
      end
reg signed [16:0] memy [0:N-1];
initial
        if(VCS_SIM==1) begin
        $readmemb("../../project/data/o_y.dat",memy);
      end
        else begin
        $readmemb("o_y.dat",memy);
      end
always @(posedge clk) begin
        if(start) begin
                series_x<=0;
                series_y<=0;
        end
        else begin
                series_x<=memx [ad];
                series_y<=memy [ad];
        end
end
always @(posedge clk) begin
        if(start) begin
                ad<=0;
        end
        else
                ad<=ad+1;
end
assign a=series_x;
assign b=series_y;
endmodule

