Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\XCORR\data\xcorr_wrap.v
C:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\XCORR\data\xcorr.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.10
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Created Time Mon Dec 19 10:54:18 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module XCORR_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.219s, Peak memory usage = 35.191MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 35.191MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 35.191MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 35.191MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 35.191MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 35.191MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 35.191MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 35.191MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 35.191MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 35.191MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 35.191MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 35.191MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.878s, Peak memory usage = 46.066MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 46.066MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 46.066MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 46.066MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 77
I/O Buf 77
    IBUF 36
    OBUF 41
Register 163
    DFF 12
    DFFS 2
    DFFSE 1
    DFFR 99
    DFFRE 49
LUT 316
    LUT2 95
    LUT3 96
    LUT4 125
ALU 77
    ALU 77
INV 40
    INV 40
DSP 1
    MULT18X18 1
BSRAM 4
    SDPX9B 2
    DPX9B 2

Resource Utilization Summary

Resource Usage Utilization
Logic 433(356 LUTs, 77 ALUs) / 54720 <1%
Register 163 / 41997 <1%
  --Register as Latch 0 / 41997 0%
  --Register as FF 163 / 41997 <1%
BSRAM 4 / 140 3%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 170.3(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.129
Data Arrival Time 6.699
Data Required Time 10.828
From u_xcorr/memr_1_n833_ADAREG_G_0_s
To u_xcorr/result_33_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 172 clk_ibuf/O
0.863 0.180 tNET RR 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/CLK
1.095 0.232 tC2Q RF 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/Q
1.332 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/I1
1.887 0.555 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/F
2.124 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/I2
2.577 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/F
2.814 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s1/I1
3.369 0.555 tINS FF 34 u_xcorr/memr_1_n833_DOAL_G_0_s1/F
3.606 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/I2
4.059 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/F
4.296 0.237 tNET FF 2 u_xcorr/n868_s/I1
4.866 0.570 tINS FR 1 u_xcorr/n868_s/COUT
4.866 0.000 tNET RR 2 u_xcorr/n867_s/CIN
4.901 0.035 tINS RF 1 u_xcorr/n867_s/COUT
4.901 0.000 tNET FF 2 u_xcorr/n866_s/CIN
4.936 0.035 tINS FF 1 u_xcorr/n866_s/COUT
4.936 0.000 tNET FF 2 u_xcorr/n865_s/CIN
4.971 0.035 tINS FF 1 u_xcorr/n865_s/COUT
4.971 0.000 tNET FF 2 u_xcorr/n864_s/CIN
5.006 0.035 tINS FF 1 u_xcorr/n864_s/COUT
5.006 0.000 tNET FF 2 u_xcorr/n863_s/CIN
5.042 0.035 tINS FF 1 u_xcorr/n863_s/COUT
5.042 0.000 tNET FF 2 u_xcorr/n862_s/CIN
5.077 0.035 tINS FF 1 u_xcorr/n862_s/COUT
5.077 0.000 tNET FF 2 u_xcorr/n861_s/CIN
5.112 0.035 tINS FF 1 u_xcorr/n861_s/COUT
5.112 0.000 tNET FF 2 u_xcorr/n860_s/CIN
5.147 0.035 tINS FF 1 u_xcorr/n860_s/COUT
5.147 0.000 tNET FF 2 u_xcorr/n859_s/CIN
5.182 0.035 tINS FF 1 u_xcorr/n859_s/COUT
5.182 0.000 tNET FF 2 u_xcorr/n858_s/CIN
5.218 0.035 tINS FF 1 u_xcorr/n858_s/COUT
5.218 0.000 tNET FF 2 u_xcorr/n857_s/CIN
5.253 0.035 tINS FF 1 u_xcorr/n857_s/COUT
5.253 0.000 tNET FF 2 u_xcorr/n856_s/CIN
5.288 0.035 tINS FF 1 u_xcorr/n856_s/COUT
5.288 0.000 tNET FF 2 u_xcorr/n855_s/CIN
5.323 0.035 tINS FF 1 u_xcorr/n855_s/COUT
5.323 0.000 tNET FF 2 u_xcorr/n854_s/CIN
5.358 0.035 tINS FF 1 u_xcorr/n854_s/COUT
5.358 0.000 tNET FF 2 u_xcorr/n853_s/CIN
5.394 0.035 tINS FF 1 u_xcorr/n853_s/COUT
5.394 0.000 tNET FF 2 u_xcorr/n852_s/CIN
5.429 0.035 tINS FF 1 u_xcorr/n852_s/COUT
5.429 0.000 tNET FF 2 u_xcorr/n851_s/CIN
5.464 0.035 tINS FF 1 u_xcorr/n851_s/COUT
5.464 0.000 tNET FF 2 u_xcorr/n850_s/CIN
5.499 0.035 tINS FF 1 u_xcorr/n850_s/COUT
5.499 0.000 tNET FF 2 u_xcorr/n849_s/CIN
5.534 0.035 tINS FF 1 u_xcorr/n849_s/COUT
5.534 0.000 tNET FF 2 u_xcorr/n848_s/CIN
5.570 0.035 tINS FF 1 u_xcorr/n848_s/COUT
5.570 0.000 tNET FF 2 u_xcorr/n847_s/CIN
5.605 0.035 tINS FF 1 u_xcorr/n847_s/COUT
5.605 0.000 tNET FF 2 u_xcorr/n846_s/CIN
5.640 0.035 tINS FF 1 u_xcorr/n846_s/COUT
5.640 0.000 tNET FF 2 u_xcorr/n845_s/CIN
5.675 0.035 tINS FF 1 u_xcorr/n845_s/COUT
5.675 0.000 tNET FF 2 u_xcorr/n844_s/CIN
5.710 0.035 tINS FF 1 u_xcorr/n844_s/COUT
5.710 0.000 tNET FF 2 u_xcorr/n843_s/CIN
5.746 0.035 tINS FF 1 u_xcorr/n843_s/COUT
5.746 0.000 tNET FF 2 u_xcorr/n842_s/CIN
5.781 0.035 tINS FF 1 u_xcorr/n842_s/COUT
5.781 0.000 tNET FF 2 u_xcorr/n841_s/CIN
5.816 0.035 tINS FF 1 u_xcorr/n841_s/COUT
5.816 0.000 tNET FF 2 u_xcorr/n840_s/CIN
5.851 0.035 tINS FF 1 u_xcorr/n840_s/COUT
5.851 0.000 tNET FF 2 u_xcorr/n839_s/CIN
5.886 0.035 tINS FF 1 u_xcorr/n839_s/COUT
5.886 0.000 tNET FF 2 u_xcorr/n838_s/CIN
5.922 0.035 tINS FF 1 u_xcorr/n838_s/COUT
5.922 0.000 tNET FF 2 u_xcorr/n837_s/CIN
5.957 0.035 tINS FF 1 u_xcorr/n837_s/COUT
5.957 0.000 tNET FF 2 u_xcorr/n836_s/CIN
5.992 0.035 tINS FF 1 u_xcorr/n836_s/COUT
5.992 0.000 tNET FF 2 u_xcorr/n835_s/CIN
6.462 0.470 tINS FF 1 u_xcorr/n835_s/SUM
6.699 0.237 tNET FF 1 u_xcorr/result_33_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 172 clk_ibuf/O
10.863 0.180 tNET RR 1 u_xcorr/result_33_s0/CLK
10.828 -0.035 tSu 1 u_xcorr/result_33_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.182, 71.661%; route: 1.422, 24.364%; tC2Q: 0.232, 3.975%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.164
Data Arrival Time 6.664
Data Required Time 10.828
From u_xcorr/memr_1_n833_ADAREG_G_0_s
To u_xcorr/result_32_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 172 clk_ibuf/O
0.863 0.180 tNET RR 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/CLK
1.095 0.232 tC2Q RF 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/Q
1.332 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/I1
1.887 0.555 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/F
2.124 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/I2
2.577 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/F
2.814 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s1/I1
3.369 0.555 tINS FF 34 u_xcorr/memr_1_n833_DOAL_G_0_s1/F
3.606 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/I2
4.059 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/F
4.296 0.237 tNET FF 2 u_xcorr/n868_s/I1
4.866 0.570 tINS FR 1 u_xcorr/n868_s/COUT
4.866 0.000 tNET RR 2 u_xcorr/n867_s/CIN
4.901 0.035 tINS RF 1 u_xcorr/n867_s/COUT
4.901 0.000 tNET FF 2 u_xcorr/n866_s/CIN
4.936 0.035 tINS FF 1 u_xcorr/n866_s/COUT
4.936 0.000 tNET FF 2 u_xcorr/n865_s/CIN
4.971 0.035 tINS FF 1 u_xcorr/n865_s/COUT
4.971 0.000 tNET FF 2 u_xcorr/n864_s/CIN
5.006 0.035 tINS FF 1 u_xcorr/n864_s/COUT
5.006 0.000 tNET FF 2 u_xcorr/n863_s/CIN
5.042 0.035 tINS FF 1 u_xcorr/n863_s/COUT
5.042 0.000 tNET FF 2 u_xcorr/n862_s/CIN
5.077 0.035 tINS FF 1 u_xcorr/n862_s/COUT
5.077 0.000 tNET FF 2 u_xcorr/n861_s/CIN
5.112 0.035 tINS FF 1 u_xcorr/n861_s/COUT
5.112 0.000 tNET FF 2 u_xcorr/n860_s/CIN
5.147 0.035 tINS FF 1 u_xcorr/n860_s/COUT
5.147 0.000 tNET FF 2 u_xcorr/n859_s/CIN
5.182 0.035 tINS FF 1 u_xcorr/n859_s/COUT
5.182 0.000 tNET FF 2 u_xcorr/n858_s/CIN
5.218 0.035 tINS FF 1 u_xcorr/n858_s/COUT
5.218 0.000 tNET FF 2 u_xcorr/n857_s/CIN
5.253 0.035 tINS FF 1 u_xcorr/n857_s/COUT
5.253 0.000 tNET FF 2 u_xcorr/n856_s/CIN
5.288 0.035 tINS FF 1 u_xcorr/n856_s/COUT
5.288 0.000 tNET FF 2 u_xcorr/n855_s/CIN
5.323 0.035 tINS FF 1 u_xcorr/n855_s/COUT
5.323 0.000 tNET FF 2 u_xcorr/n854_s/CIN
5.358 0.035 tINS FF 1 u_xcorr/n854_s/COUT
5.358 0.000 tNET FF 2 u_xcorr/n853_s/CIN
5.394 0.035 tINS FF 1 u_xcorr/n853_s/COUT
5.394 0.000 tNET FF 2 u_xcorr/n852_s/CIN
5.429 0.035 tINS FF 1 u_xcorr/n852_s/COUT
5.429 0.000 tNET FF 2 u_xcorr/n851_s/CIN
5.464 0.035 tINS FF 1 u_xcorr/n851_s/COUT
5.464 0.000 tNET FF 2 u_xcorr/n850_s/CIN
5.499 0.035 tINS FF 1 u_xcorr/n850_s/COUT
5.499 0.000 tNET FF 2 u_xcorr/n849_s/CIN
5.534 0.035 tINS FF 1 u_xcorr/n849_s/COUT
5.534 0.000 tNET FF 2 u_xcorr/n848_s/CIN
5.570 0.035 tINS FF 1 u_xcorr/n848_s/COUT
5.570 0.000 tNET FF 2 u_xcorr/n847_s/CIN
5.605 0.035 tINS FF 1 u_xcorr/n847_s/COUT
5.605 0.000 tNET FF 2 u_xcorr/n846_s/CIN
5.640 0.035 tINS FF 1 u_xcorr/n846_s/COUT
5.640 0.000 tNET FF 2 u_xcorr/n845_s/CIN
5.675 0.035 tINS FF 1 u_xcorr/n845_s/COUT
5.675 0.000 tNET FF 2 u_xcorr/n844_s/CIN
5.710 0.035 tINS FF 1 u_xcorr/n844_s/COUT
5.710 0.000 tNET FF 2 u_xcorr/n843_s/CIN
5.746 0.035 tINS FF 1 u_xcorr/n843_s/COUT
5.746 0.000 tNET FF 2 u_xcorr/n842_s/CIN
5.781 0.035 tINS FF 1 u_xcorr/n842_s/COUT
5.781 0.000 tNET FF 2 u_xcorr/n841_s/CIN
5.816 0.035 tINS FF 1 u_xcorr/n841_s/COUT
5.816 0.000 tNET FF 2 u_xcorr/n840_s/CIN
5.851 0.035 tINS FF 1 u_xcorr/n840_s/COUT
5.851 0.000 tNET FF 2 u_xcorr/n839_s/CIN
5.886 0.035 tINS FF 1 u_xcorr/n839_s/COUT
5.886 0.000 tNET FF 2 u_xcorr/n838_s/CIN
5.922 0.035 tINS FF 1 u_xcorr/n838_s/COUT
5.922 0.000 tNET FF 2 u_xcorr/n837_s/CIN
5.957 0.035 tINS FF 1 u_xcorr/n837_s/COUT
5.957 0.000 tNET FF 2 u_xcorr/n836_s/CIN
6.427 0.470 tINS FF 1 u_xcorr/n836_s/SUM
6.664 0.237 tNET FF 1 u_xcorr/result_32_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 172 clk_ibuf/O
10.863 0.180 tNET RR 1 u_xcorr/result_32_s0/CLK
10.828 -0.035 tSu 1 u_xcorr/result_32_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.147, 71.489%; route: 1.422, 24.512%; tC2Q: 0.232, 3.999%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 4.199
Data Arrival Time 6.629
Data Required Time 10.828
From u_xcorr/memr_1_n833_ADAREG_G_0_s
To u_xcorr/result_31_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 172 clk_ibuf/O
0.863 0.180 tNET RR 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/CLK
1.095 0.232 tC2Q RF 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/Q
1.332 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/I1
1.887 0.555 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/F
2.124 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/I2
2.577 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/F
2.814 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s1/I1
3.369 0.555 tINS FF 34 u_xcorr/memr_1_n833_DOAL_G_0_s1/F
3.606 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/I2
4.059 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/F
4.296 0.237 tNET FF 2 u_xcorr/n868_s/I1
4.866 0.570 tINS FR 1 u_xcorr/n868_s/COUT
4.866 0.000 tNET RR 2 u_xcorr/n867_s/CIN
4.901 0.035 tINS RF 1 u_xcorr/n867_s/COUT
4.901 0.000 tNET FF 2 u_xcorr/n866_s/CIN
4.936 0.035 tINS FF 1 u_xcorr/n866_s/COUT
4.936 0.000 tNET FF 2 u_xcorr/n865_s/CIN
4.971 0.035 tINS FF 1 u_xcorr/n865_s/COUT
4.971 0.000 tNET FF 2 u_xcorr/n864_s/CIN
5.006 0.035 tINS FF 1 u_xcorr/n864_s/COUT
5.006 0.000 tNET FF 2 u_xcorr/n863_s/CIN
5.042 0.035 tINS FF 1 u_xcorr/n863_s/COUT
5.042 0.000 tNET FF 2 u_xcorr/n862_s/CIN
5.077 0.035 tINS FF 1 u_xcorr/n862_s/COUT
5.077 0.000 tNET FF 2 u_xcorr/n861_s/CIN
5.112 0.035 tINS FF 1 u_xcorr/n861_s/COUT
5.112 0.000 tNET FF 2 u_xcorr/n860_s/CIN
5.147 0.035 tINS FF 1 u_xcorr/n860_s/COUT
5.147 0.000 tNET FF 2 u_xcorr/n859_s/CIN
5.182 0.035 tINS FF 1 u_xcorr/n859_s/COUT
5.182 0.000 tNET FF 2 u_xcorr/n858_s/CIN
5.218 0.035 tINS FF 1 u_xcorr/n858_s/COUT
5.218 0.000 tNET FF 2 u_xcorr/n857_s/CIN
5.253 0.035 tINS FF 1 u_xcorr/n857_s/COUT
5.253 0.000 tNET FF 2 u_xcorr/n856_s/CIN
5.288 0.035 tINS FF 1 u_xcorr/n856_s/COUT
5.288 0.000 tNET FF 2 u_xcorr/n855_s/CIN
5.323 0.035 tINS FF 1 u_xcorr/n855_s/COUT
5.323 0.000 tNET FF 2 u_xcorr/n854_s/CIN
5.358 0.035 tINS FF 1 u_xcorr/n854_s/COUT
5.358 0.000 tNET FF 2 u_xcorr/n853_s/CIN
5.394 0.035 tINS FF 1 u_xcorr/n853_s/COUT
5.394 0.000 tNET FF 2 u_xcorr/n852_s/CIN
5.429 0.035 tINS FF 1 u_xcorr/n852_s/COUT
5.429 0.000 tNET FF 2 u_xcorr/n851_s/CIN
5.464 0.035 tINS FF 1 u_xcorr/n851_s/COUT
5.464 0.000 tNET FF 2 u_xcorr/n850_s/CIN
5.499 0.035 tINS FF 1 u_xcorr/n850_s/COUT
5.499 0.000 tNET FF 2 u_xcorr/n849_s/CIN
5.534 0.035 tINS FF 1 u_xcorr/n849_s/COUT
5.534 0.000 tNET FF 2 u_xcorr/n848_s/CIN
5.570 0.035 tINS FF 1 u_xcorr/n848_s/COUT
5.570 0.000 tNET FF 2 u_xcorr/n847_s/CIN
5.605 0.035 tINS FF 1 u_xcorr/n847_s/COUT
5.605 0.000 tNET FF 2 u_xcorr/n846_s/CIN
5.640 0.035 tINS FF 1 u_xcorr/n846_s/COUT
5.640 0.000 tNET FF 2 u_xcorr/n845_s/CIN
5.675 0.035 tINS FF 1 u_xcorr/n845_s/COUT
5.675 0.000 tNET FF 2 u_xcorr/n844_s/CIN
5.710 0.035 tINS FF 1 u_xcorr/n844_s/COUT
5.710 0.000 tNET FF 2 u_xcorr/n843_s/CIN
5.746 0.035 tINS FF 1 u_xcorr/n843_s/COUT
5.746 0.000 tNET FF 2 u_xcorr/n842_s/CIN
5.781 0.035 tINS FF 1 u_xcorr/n842_s/COUT
5.781 0.000 tNET FF 2 u_xcorr/n841_s/CIN
5.816 0.035 tINS FF 1 u_xcorr/n841_s/COUT
5.816 0.000 tNET FF 2 u_xcorr/n840_s/CIN
5.851 0.035 tINS FF 1 u_xcorr/n840_s/COUT
5.851 0.000 tNET FF 2 u_xcorr/n839_s/CIN
5.886 0.035 tINS FF 1 u_xcorr/n839_s/COUT
5.886 0.000 tNET FF 2 u_xcorr/n838_s/CIN
5.922 0.035 tINS FF 1 u_xcorr/n838_s/COUT
5.922 0.000 tNET FF 2 u_xcorr/n837_s/CIN
6.392 0.470 tINS FF 1 u_xcorr/n837_s/SUM
6.629 0.237 tNET FF 1 u_xcorr/result_31_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 172 clk_ibuf/O
10.863 0.180 tNET RR 1 u_xcorr/result_31_s0/CLK
10.828 -0.035 tSu 1 u_xcorr/result_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.112, 71.314%; route: 1.422, 24.662%; tC2Q: 0.232, 4.024%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 4.234
Data Arrival Time 6.593
Data Required Time 10.828
From u_xcorr/memr_1_n833_ADAREG_G_0_s
To u_xcorr/result_30_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 172 clk_ibuf/O
0.863 0.180 tNET RR 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/CLK
1.095 0.232 tC2Q RF 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/Q
1.332 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/I1
1.887 0.555 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/F
2.124 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/I2
2.577 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/F
2.814 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s1/I1
3.369 0.555 tINS FF 34 u_xcorr/memr_1_n833_DOAL_G_0_s1/F
3.606 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/I2
4.059 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/F
4.296 0.237 tNET FF 2 u_xcorr/n868_s/I1
4.866 0.570 tINS FR 1 u_xcorr/n868_s/COUT
4.866 0.000 tNET RR 2 u_xcorr/n867_s/CIN
4.901 0.035 tINS RF 1 u_xcorr/n867_s/COUT
4.901 0.000 tNET FF 2 u_xcorr/n866_s/CIN
4.936 0.035 tINS FF 1 u_xcorr/n866_s/COUT
4.936 0.000 tNET FF 2 u_xcorr/n865_s/CIN
4.971 0.035 tINS FF 1 u_xcorr/n865_s/COUT
4.971 0.000 tNET FF 2 u_xcorr/n864_s/CIN
5.006 0.035 tINS FF 1 u_xcorr/n864_s/COUT
5.006 0.000 tNET FF 2 u_xcorr/n863_s/CIN
5.042 0.035 tINS FF 1 u_xcorr/n863_s/COUT
5.042 0.000 tNET FF 2 u_xcorr/n862_s/CIN
5.077 0.035 tINS FF 1 u_xcorr/n862_s/COUT
5.077 0.000 tNET FF 2 u_xcorr/n861_s/CIN
5.112 0.035 tINS FF 1 u_xcorr/n861_s/COUT
5.112 0.000 tNET FF 2 u_xcorr/n860_s/CIN
5.147 0.035 tINS FF 1 u_xcorr/n860_s/COUT
5.147 0.000 tNET FF 2 u_xcorr/n859_s/CIN
5.182 0.035 tINS FF 1 u_xcorr/n859_s/COUT
5.182 0.000 tNET FF 2 u_xcorr/n858_s/CIN
5.218 0.035 tINS FF 1 u_xcorr/n858_s/COUT
5.218 0.000 tNET FF 2 u_xcorr/n857_s/CIN
5.253 0.035 tINS FF 1 u_xcorr/n857_s/COUT
5.253 0.000 tNET FF 2 u_xcorr/n856_s/CIN
5.288 0.035 tINS FF 1 u_xcorr/n856_s/COUT
5.288 0.000 tNET FF 2 u_xcorr/n855_s/CIN
5.323 0.035 tINS FF 1 u_xcorr/n855_s/COUT
5.323 0.000 tNET FF 2 u_xcorr/n854_s/CIN
5.358 0.035 tINS FF 1 u_xcorr/n854_s/COUT
5.358 0.000 tNET FF 2 u_xcorr/n853_s/CIN
5.394 0.035 tINS FF 1 u_xcorr/n853_s/COUT
5.394 0.000 tNET FF 2 u_xcorr/n852_s/CIN
5.429 0.035 tINS FF 1 u_xcorr/n852_s/COUT
5.429 0.000 tNET FF 2 u_xcorr/n851_s/CIN
5.464 0.035 tINS FF 1 u_xcorr/n851_s/COUT
5.464 0.000 tNET FF 2 u_xcorr/n850_s/CIN
5.499 0.035 tINS FF 1 u_xcorr/n850_s/COUT
5.499 0.000 tNET FF 2 u_xcorr/n849_s/CIN
5.534 0.035 tINS FF 1 u_xcorr/n849_s/COUT
5.534 0.000 tNET FF 2 u_xcorr/n848_s/CIN
5.570 0.035 tINS FF 1 u_xcorr/n848_s/COUT
5.570 0.000 tNET FF 2 u_xcorr/n847_s/CIN
5.605 0.035 tINS FF 1 u_xcorr/n847_s/COUT
5.605 0.000 tNET FF 2 u_xcorr/n846_s/CIN
5.640 0.035 tINS FF 1 u_xcorr/n846_s/COUT
5.640 0.000 tNET FF 2 u_xcorr/n845_s/CIN
5.675 0.035 tINS FF 1 u_xcorr/n845_s/COUT
5.675 0.000 tNET FF 2 u_xcorr/n844_s/CIN
5.710 0.035 tINS FF 1 u_xcorr/n844_s/COUT
5.710 0.000 tNET FF 2 u_xcorr/n843_s/CIN
5.746 0.035 tINS FF 1 u_xcorr/n843_s/COUT
5.746 0.000 tNET FF 2 u_xcorr/n842_s/CIN
5.781 0.035 tINS FF 1 u_xcorr/n842_s/COUT
5.781 0.000 tNET FF 2 u_xcorr/n841_s/CIN
5.816 0.035 tINS FF 1 u_xcorr/n841_s/COUT
5.816 0.000 tNET FF 2 u_xcorr/n840_s/CIN
5.851 0.035 tINS FF 1 u_xcorr/n840_s/COUT
5.851 0.000 tNET FF 2 u_xcorr/n839_s/CIN
5.886 0.035 tINS FF 1 u_xcorr/n839_s/COUT
5.886 0.000 tNET FF 2 u_xcorr/n838_s/CIN
6.356 0.470 tINS FF 1 u_xcorr/n838_s/SUM
6.593 0.237 tNET FF 1 u_xcorr/result_30_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 172 clk_ibuf/O
10.863 0.180 tNET RR 1 u_xcorr/result_30_s0/CLK
10.828 -0.035 tSu 1 u_xcorr/result_30_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.077, 71.139%; route: 1.422, 24.813%; tC2Q: 0.232, 4.048%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 4.269
Data Arrival Time 6.558
Data Required Time 10.828
From u_xcorr/memr_1_n833_ADAREG_G_0_s
To u_xcorr/result_29_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 172 clk_ibuf/O
0.863 0.180 tNET RR 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/CLK
1.095 0.232 tC2Q RF 1 u_xcorr/memr_1_n833_ADAREG_G_0_s/Q
1.332 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/I1
1.887 0.555 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s6/F
2.124 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/I2
2.577 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s3/F
2.814 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s1/I1
3.369 0.555 tINS FF 34 u_xcorr/memr_1_n833_DOAL_G_0_s1/F
3.606 0.237 tNET FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/I2
4.059 0.453 tINS FF 1 u_xcorr/memr_1_n833_DOAL_G_0_s0/F
4.296 0.237 tNET FF 2 u_xcorr/n868_s/I1
4.866 0.570 tINS FR 1 u_xcorr/n868_s/COUT
4.866 0.000 tNET RR 2 u_xcorr/n867_s/CIN
4.901 0.035 tINS RF 1 u_xcorr/n867_s/COUT
4.901 0.000 tNET FF 2 u_xcorr/n866_s/CIN
4.936 0.035 tINS FF 1 u_xcorr/n866_s/COUT
4.936 0.000 tNET FF 2 u_xcorr/n865_s/CIN
4.971 0.035 tINS FF 1 u_xcorr/n865_s/COUT
4.971 0.000 tNET FF 2 u_xcorr/n864_s/CIN
5.006 0.035 tINS FF 1 u_xcorr/n864_s/COUT
5.006 0.000 tNET FF 2 u_xcorr/n863_s/CIN
5.042 0.035 tINS FF 1 u_xcorr/n863_s/COUT
5.042 0.000 tNET FF 2 u_xcorr/n862_s/CIN
5.077 0.035 tINS FF 1 u_xcorr/n862_s/COUT
5.077 0.000 tNET FF 2 u_xcorr/n861_s/CIN
5.112 0.035 tINS FF 1 u_xcorr/n861_s/COUT
5.112 0.000 tNET FF 2 u_xcorr/n860_s/CIN
5.147 0.035 tINS FF 1 u_xcorr/n860_s/COUT
5.147 0.000 tNET FF 2 u_xcorr/n859_s/CIN
5.182 0.035 tINS FF 1 u_xcorr/n859_s/COUT
5.182 0.000 tNET FF 2 u_xcorr/n858_s/CIN
5.218 0.035 tINS FF 1 u_xcorr/n858_s/COUT
5.218 0.000 tNET FF 2 u_xcorr/n857_s/CIN
5.253 0.035 tINS FF 1 u_xcorr/n857_s/COUT
5.253 0.000 tNET FF 2 u_xcorr/n856_s/CIN
5.288 0.035 tINS FF 1 u_xcorr/n856_s/COUT
5.288 0.000 tNET FF 2 u_xcorr/n855_s/CIN
5.323 0.035 tINS FF 1 u_xcorr/n855_s/COUT
5.323 0.000 tNET FF 2 u_xcorr/n854_s/CIN
5.358 0.035 tINS FF 1 u_xcorr/n854_s/COUT
5.358 0.000 tNET FF 2 u_xcorr/n853_s/CIN
5.394 0.035 tINS FF 1 u_xcorr/n853_s/COUT
5.394 0.000 tNET FF 2 u_xcorr/n852_s/CIN
5.429 0.035 tINS FF 1 u_xcorr/n852_s/COUT
5.429 0.000 tNET FF 2 u_xcorr/n851_s/CIN
5.464 0.035 tINS FF 1 u_xcorr/n851_s/COUT
5.464 0.000 tNET FF 2 u_xcorr/n850_s/CIN
5.499 0.035 tINS FF 1 u_xcorr/n850_s/COUT
5.499 0.000 tNET FF 2 u_xcorr/n849_s/CIN
5.534 0.035 tINS FF 1 u_xcorr/n849_s/COUT
5.534 0.000 tNET FF 2 u_xcorr/n848_s/CIN
5.570 0.035 tINS FF 1 u_xcorr/n848_s/COUT
5.570 0.000 tNET FF 2 u_xcorr/n847_s/CIN
5.605 0.035 tINS FF 1 u_xcorr/n847_s/COUT
5.605 0.000 tNET FF 2 u_xcorr/n846_s/CIN
5.640 0.035 tINS FF 1 u_xcorr/n846_s/COUT
5.640 0.000 tNET FF 2 u_xcorr/n845_s/CIN
5.675 0.035 tINS FF 1 u_xcorr/n845_s/COUT
5.675 0.000 tNET FF 2 u_xcorr/n844_s/CIN
5.710 0.035 tINS FF 1 u_xcorr/n844_s/COUT
5.710 0.000 tNET FF 2 u_xcorr/n843_s/CIN
5.746 0.035 tINS FF 1 u_xcorr/n843_s/COUT
5.746 0.000 tNET FF 2 u_xcorr/n842_s/CIN
5.781 0.035 tINS FF 1 u_xcorr/n842_s/COUT
5.781 0.000 tNET FF 2 u_xcorr/n841_s/CIN
5.816 0.035 tINS FF 1 u_xcorr/n841_s/COUT
5.816 0.000 tNET FF 2 u_xcorr/n840_s/CIN
5.851 0.035 tINS FF 1 u_xcorr/n840_s/COUT
5.851 0.000 tNET FF 2 u_xcorr/n839_s/CIN
6.321 0.470 tINS FF 1 u_xcorr/n839_s/SUM
6.558 0.237 tNET FF 1 u_xcorr/result_29_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 172 clk_ibuf/O
10.863 0.180 tNET RR 1 u_xcorr/result_29_s0/CLK
10.828 -0.035 tSu 1 u_xcorr/result_29_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.042, 70.960%; route: 1.422, 24.967%; tC2Q: 0.232, 4.073%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%