Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\XCORR\data\xcorr_wrap.v C:\Gowin\Gowin_V1.9.8.10\IDE\ipcore\XCORR\data\xcorr.v |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.8.10 |
Part Number | GW2A-LV55PG484C8/I7 |
Device | GW2A-55 |
Created Time | Mon Dec 19 09:54:30 2022 |
Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | XCORR_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 35.180MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 35.180MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 35.180MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 35.180MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 35.180MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 35.180MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 35.180MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 35.180MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 35.180MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 35.180MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 35.180MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 35.180MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.679s, Peak memory usage = 45.801MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 45.801MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 45.801MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 45.801MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 77 |
I/O Buf | 77 |
    IBUF | 36 |
    OBUF | 41 |
Register | 159 |
    DFF | 11 |
    DFFS | 2 |
    DFFSE | 1 |
    DFFR | 96 |
    DFFRE | 49 |
LUT | 292 |
    LUT2 | 91 |
    LUT3 | 95 |
    LUT4 | 106 |
ALU | 82 |
    ALU | 82 |
INV | 40 |
    INV | 40 |
DSP | 1 |
    MULT18X18 | 1 |
BSRAM | 3 |
    SDPX9B | 1 |
    DPX9B | 2 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 414(332 LUTs, 82 ALUs) / 54720 | <1% |
Register | 159 / 41997 | <1% |
  --Register as Latch | 0 / 41997 | 0% |
  --Register as FF | 159 / 41997 | <1% |
BSRAM | 3 / 140 | 3% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 175.8(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.313 |
Data Arrival Time | 6.515 |
Data Required Time | 10.828 |
From | u_xcorr/memr_1_n831_ADAREG_G_1_s |
To | u_xcorr/result_33_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/CLK |
1.095 | 0.232 | tC2Q | RF | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/Q |
1.332 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/F |
2.124 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/I2 |
2.577 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/F |
2.814 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s1/I3 |
3.185 | 0.371 | tINS | FF | 34 | u_xcorr/memr_1_n831_DOAL_G_0_s1/F |
3.422 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/I2 |
3.875 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/F |
4.112 | 0.237 | tNET | FF | 2 | u_xcorr/n866_s/I1 |
4.682 | 0.570 | tINS | FR | 1 | u_xcorr/n866_s/COUT |
4.682 | 0.000 | tNET | RR | 2 | u_xcorr/n865_s/CIN |
4.717 | 0.035 | tINS | RF | 1 | u_xcorr/n865_s/COUT |
4.717 | 0.000 | tNET | FF | 2 | u_xcorr/n864_s/CIN |
4.752 | 0.035 | tINS | FF | 1 | u_xcorr/n864_s/COUT |
4.752 | 0.000 | tNET | FF | 2 | u_xcorr/n863_s/CIN |
4.787 | 0.035 | tINS | FF | 1 | u_xcorr/n863_s/COUT |
4.787 | 0.000 | tNET | FF | 2 | u_xcorr/n862_s/CIN |
4.822 | 0.035 | tINS | FF | 1 | u_xcorr/n862_s/COUT |
4.822 | 0.000 | tNET | FF | 2 | u_xcorr/n861_s/CIN |
4.858 | 0.035 | tINS | FF | 1 | u_xcorr/n861_s/COUT |
4.858 | 0.000 | tNET | FF | 2 | u_xcorr/n860_s/CIN |
4.893 | 0.035 | tINS | FF | 1 | u_xcorr/n860_s/COUT |
4.893 | 0.000 | tNET | FF | 2 | u_xcorr/n859_s/CIN |
4.928 | 0.035 | tINS | FF | 1 | u_xcorr/n859_s/COUT |
4.928 | 0.000 | tNET | FF | 2 | u_xcorr/n858_s/CIN |
4.963 | 0.035 | tINS | FF | 1 | u_xcorr/n858_s/COUT |
4.963 | 0.000 | tNET | FF | 2 | u_xcorr/n857_s/CIN |
4.998 | 0.035 | tINS | FF | 1 | u_xcorr/n857_s/COUT |
4.998 | 0.000 | tNET | FF | 2 | u_xcorr/n856_s/CIN |
5.034 | 0.035 | tINS | FF | 1 | u_xcorr/n856_s/COUT |
5.034 | 0.000 | tNET | FF | 2 | u_xcorr/n855_s/CIN |
5.069 | 0.035 | tINS | FF | 1 | u_xcorr/n855_s/COUT |
5.069 | 0.000 | tNET | FF | 2 | u_xcorr/n854_s/CIN |
5.104 | 0.035 | tINS | FF | 1 | u_xcorr/n854_s/COUT |
5.104 | 0.000 | tNET | FF | 2 | u_xcorr/n853_s/CIN |
5.139 | 0.035 | tINS | FF | 1 | u_xcorr/n853_s/COUT |
5.139 | 0.000 | tNET | FF | 2 | u_xcorr/n852_s/CIN |
5.174 | 0.035 | tINS | FF | 1 | u_xcorr/n852_s/COUT |
5.174 | 0.000 | tNET | FF | 2 | u_xcorr/n851_s/CIN |
5.210 | 0.035 | tINS | FF | 1 | u_xcorr/n851_s/COUT |
5.210 | 0.000 | tNET | FF | 2 | u_xcorr/n850_s/CIN |
5.245 | 0.035 | tINS | FF | 1 | u_xcorr/n850_s/COUT |
5.245 | 0.000 | tNET | FF | 2 | u_xcorr/n849_s/CIN |
5.280 | 0.035 | tINS | FF | 1 | u_xcorr/n849_s/COUT |
5.280 | 0.000 | tNET | FF | 2 | u_xcorr/n848_s/CIN |
5.315 | 0.035 | tINS | FF | 1 | u_xcorr/n848_s/COUT |
5.315 | 0.000 | tNET | FF | 2 | u_xcorr/n847_s/CIN |
5.350 | 0.035 | tINS | FF | 1 | u_xcorr/n847_s/COUT |
5.350 | 0.000 | tNET | FF | 2 | u_xcorr/n846_s/CIN |
5.386 | 0.035 | tINS | FF | 1 | u_xcorr/n846_s/COUT |
5.386 | 0.000 | tNET | FF | 2 | u_xcorr/n845_s/CIN |
5.421 | 0.035 | tINS | FF | 1 | u_xcorr/n845_s/COUT |
5.421 | 0.000 | tNET | FF | 2 | u_xcorr/n844_s/CIN |
5.456 | 0.035 | tINS | FF | 1 | u_xcorr/n844_s/COUT |
5.456 | 0.000 | tNET | FF | 2 | u_xcorr/n843_s/CIN |
5.491 | 0.035 | tINS | FF | 1 | u_xcorr/n843_s/COUT |
5.491 | 0.000 | tNET | FF | 2 | u_xcorr/n842_s/CIN |
5.526 | 0.035 | tINS | FF | 1 | u_xcorr/n842_s/COUT |
5.526 | 0.000 | tNET | FF | 2 | u_xcorr/n841_s/CIN |
5.562 | 0.035 | tINS | FF | 1 | u_xcorr/n841_s/COUT |
5.562 | 0.000 | tNET | FF | 2 | u_xcorr/n840_s/CIN |
5.597 | 0.035 | tINS | FF | 1 | u_xcorr/n840_s/COUT |
5.597 | 0.000 | tNET | FF | 2 | u_xcorr/n839_s/CIN |
5.632 | 0.035 | tINS | FF | 1 | u_xcorr/n839_s/COUT |
5.632 | 0.000 | tNET | FF | 2 | u_xcorr/n838_s/CIN |
5.667 | 0.035 | tINS | FF | 1 | u_xcorr/n838_s/COUT |
5.667 | 0.000 | tNET | FF | 2 | u_xcorr/n837_s/CIN |
5.702 | 0.035 | tINS | FF | 1 | u_xcorr/n837_s/COUT |
5.702 | 0.000 | tNET | FF | 2 | u_xcorr/n836_s/CIN |
5.738 | 0.035 | tINS | FF | 1 | u_xcorr/n836_s/COUT |
5.738 | 0.000 | tNET | FF | 2 | u_xcorr/n835_s/CIN |
5.773 | 0.035 | tINS | FF | 1 | u_xcorr/n835_s/COUT |
5.773 | 0.000 | tNET | FF | 2 | u_xcorr/n834_s/CIN |
5.808 | 0.035 | tINS | FF | 1 | u_xcorr/n834_s/COUT |
5.808 | 0.000 | tNET | FF | 2 | u_xcorr/n833_s/CIN |
6.278 | 0.470 | tINS | FF | 1 | u_xcorr/n833_s/SUM |
6.515 | 0.237 | tNET | FF | 1 | u_xcorr/result_33_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_xcorr/result_33_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_xcorr/result_33_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.998, 70.739%; route: 1.422, 25.157%; tC2Q: 0.232, 4.104% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 4.348 |
Data Arrival Time | 6.480 |
Data Required Time | 10.828 |
From | u_xcorr/memr_1_n831_ADAREG_G_1_s |
To | u_xcorr/result_32_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/CLK |
1.095 | 0.232 | tC2Q | RF | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/Q |
1.332 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/F |
2.124 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/I2 |
2.577 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/F |
2.814 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s1/I3 |
3.185 | 0.371 | tINS | FF | 34 | u_xcorr/memr_1_n831_DOAL_G_0_s1/F |
3.422 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/I2 |
3.875 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/F |
4.112 | 0.237 | tNET | FF | 2 | u_xcorr/n866_s/I1 |
4.682 | 0.570 | tINS | FR | 1 | u_xcorr/n866_s/COUT |
4.682 | 0.000 | tNET | RR | 2 | u_xcorr/n865_s/CIN |
4.717 | 0.035 | tINS | RF | 1 | u_xcorr/n865_s/COUT |
4.717 | 0.000 | tNET | FF | 2 | u_xcorr/n864_s/CIN |
4.752 | 0.035 | tINS | FF | 1 | u_xcorr/n864_s/COUT |
4.752 | 0.000 | tNET | FF | 2 | u_xcorr/n863_s/CIN |
4.787 | 0.035 | tINS | FF | 1 | u_xcorr/n863_s/COUT |
4.787 | 0.000 | tNET | FF | 2 | u_xcorr/n862_s/CIN |
4.822 | 0.035 | tINS | FF | 1 | u_xcorr/n862_s/COUT |
4.822 | 0.000 | tNET | FF | 2 | u_xcorr/n861_s/CIN |
4.858 | 0.035 | tINS | FF | 1 | u_xcorr/n861_s/COUT |
4.858 | 0.000 | tNET | FF | 2 | u_xcorr/n860_s/CIN |
4.893 | 0.035 | tINS | FF | 1 | u_xcorr/n860_s/COUT |
4.893 | 0.000 | tNET | FF | 2 | u_xcorr/n859_s/CIN |
4.928 | 0.035 | tINS | FF | 1 | u_xcorr/n859_s/COUT |
4.928 | 0.000 | tNET | FF | 2 | u_xcorr/n858_s/CIN |
4.963 | 0.035 | tINS | FF | 1 | u_xcorr/n858_s/COUT |
4.963 | 0.000 | tNET | FF | 2 | u_xcorr/n857_s/CIN |
4.998 | 0.035 | tINS | FF | 1 | u_xcorr/n857_s/COUT |
4.998 | 0.000 | tNET | FF | 2 | u_xcorr/n856_s/CIN |
5.034 | 0.035 | tINS | FF | 1 | u_xcorr/n856_s/COUT |
5.034 | 0.000 | tNET | FF | 2 | u_xcorr/n855_s/CIN |
5.069 | 0.035 | tINS | FF | 1 | u_xcorr/n855_s/COUT |
5.069 | 0.000 | tNET | FF | 2 | u_xcorr/n854_s/CIN |
5.104 | 0.035 | tINS | FF | 1 | u_xcorr/n854_s/COUT |
5.104 | 0.000 | tNET | FF | 2 | u_xcorr/n853_s/CIN |
5.139 | 0.035 | tINS | FF | 1 | u_xcorr/n853_s/COUT |
5.139 | 0.000 | tNET | FF | 2 | u_xcorr/n852_s/CIN |
5.174 | 0.035 | tINS | FF | 1 | u_xcorr/n852_s/COUT |
5.174 | 0.000 | tNET | FF | 2 | u_xcorr/n851_s/CIN |
5.210 | 0.035 | tINS | FF | 1 | u_xcorr/n851_s/COUT |
5.210 | 0.000 | tNET | FF | 2 | u_xcorr/n850_s/CIN |
5.245 | 0.035 | tINS | FF | 1 | u_xcorr/n850_s/COUT |
5.245 | 0.000 | tNET | FF | 2 | u_xcorr/n849_s/CIN |
5.280 | 0.035 | tINS | FF | 1 | u_xcorr/n849_s/COUT |
5.280 | 0.000 | tNET | FF | 2 | u_xcorr/n848_s/CIN |
5.315 | 0.035 | tINS | FF | 1 | u_xcorr/n848_s/COUT |
5.315 | 0.000 | tNET | FF | 2 | u_xcorr/n847_s/CIN |
5.350 | 0.035 | tINS | FF | 1 | u_xcorr/n847_s/COUT |
5.350 | 0.000 | tNET | FF | 2 | u_xcorr/n846_s/CIN |
5.386 | 0.035 | tINS | FF | 1 | u_xcorr/n846_s/COUT |
5.386 | 0.000 | tNET | FF | 2 | u_xcorr/n845_s/CIN |
5.421 | 0.035 | tINS | FF | 1 | u_xcorr/n845_s/COUT |
5.421 | 0.000 | tNET | FF | 2 | u_xcorr/n844_s/CIN |
5.456 | 0.035 | tINS | FF | 1 | u_xcorr/n844_s/COUT |
5.456 | 0.000 | tNET | FF | 2 | u_xcorr/n843_s/CIN |
5.491 | 0.035 | tINS | FF | 1 | u_xcorr/n843_s/COUT |
5.491 | 0.000 | tNET | FF | 2 | u_xcorr/n842_s/CIN |
5.526 | 0.035 | tINS | FF | 1 | u_xcorr/n842_s/COUT |
5.526 | 0.000 | tNET | FF | 2 | u_xcorr/n841_s/CIN |
5.562 | 0.035 | tINS | FF | 1 | u_xcorr/n841_s/COUT |
5.562 | 0.000 | tNET | FF | 2 | u_xcorr/n840_s/CIN |
5.597 | 0.035 | tINS | FF | 1 | u_xcorr/n840_s/COUT |
5.597 | 0.000 | tNET | FF | 2 | u_xcorr/n839_s/CIN |
5.632 | 0.035 | tINS | FF | 1 | u_xcorr/n839_s/COUT |
5.632 | 0.000 | tNET | FF | 2 | u_xcorr/n838_s/CIN |
5.667 | 0.035 | tINS | FF | 1 | u_xcorr/n838_s/COUT |
5.667 | 0.000 | tNET | FF | 2 | u_xcorr/n837_s/CIN |
5.702 | 0.035 | tINS | FF | 1 | u_xcorr/n837_s/COUT |
5.702 | 0.000 | tNET | FF | 2 | u_xcorr/n836_s/CIN |
5.738 | 0.035 | tINS | FF | 1 | u_xcorr/n836_s/COUT |
5.738 | 0.000 | tNET | FF | 2 | u_xcorr/n835_s/CIN |
5.773 | 0.035 | tINS | FF | 1 | u_xcorr/n835_s/COUT |
5.773 | 0.000 | tNET | FF | 2 | u_xcorr/n834_s/CIN |
6.243 | 0.470 | tINS | FF | 1 | u_xcorr/n834_s/SUM |
6.480 | 0.237 | tNET | FF | 1 | u_xcorr/result_32_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_xcorr/result_32_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_xcorr/result_32_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.963, 70.555%; route: 1.422, 25.315%; tC2Q: 0.232, 4.130% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 4.383 |
Data Arrival Time | 6.445 |
Data Required Time | 10.828 |
From | u_xcorr/memr_1_n831_ADAREG_G_1_s |
To | u_xcorr/result_31_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/CLK |
1.095 | 0.232 | tC2Q | RF | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/Q |
1.332 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/F |
2.124 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/I2 |
2.577 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/F |
2.814 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s1/I3 |
3.185 | 0.371 | tINS | FF | 34 | u_xcorr/memr_1_n831_DOAL_G_0_s1/F |
3.422 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/I2 |
3.875 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/F |
4.112 | 0.237 | tNET | FF | 2 | u_xcorr/n866_s/I1 |
4.682 | 0.570 | tINS | FR | 1 | u_xcorr/n866_s/COUT |
4.682 | 0.000 | tNET | RR | 2 | u_xcorr/n865_s/CIN |
4.717 | 0.035 | tINS | RF | 1 | u_xcorr/n865_s/COUT |
4.717 | 0.000 | tNET | FF | 2 | u_xcorr/n864_s/CIN |
4.752 | 0.035 | tINS | FF | 1 | u_xcorr/n864_s/COUT |
4.752 | 0.000 | tNET | FF | 2 | u_xcorr/n863_s/CIN |
4.787 | 0.035 | tINS | FF | 1 | u_xcorr/n863_s/COUT |
4.787 | 0.000 | tNET | FF | 2 | u_xcorr/n862_s/CIN |
4.822 | 0.035 | tINS | FF | 1 | u_xcorr/n862_s/COUT |
4.822 | 0.000 | tNET | FF | 2 | u_xcorr/n861_s/CIN |
4.858 | 0.035 | tINS | FF | 1 | u_xcorr/n861_s/COUT |
4.858 | 0.000 | tNET | FF | 2 | u_xcorr/n860_s/CIN |
4.893 | 0.035 | tINS | FF | 1 | u_xcorr/n860_s/COUT |
4.893 | 0.000 | tNET | FF | 2 | u_xcorr/n859_s/CIN |
4.928 | 0.035 | tINS | FF | 1 | u_xcorr/n859_s/COUT |
4.928 | 0.000 | tNET | FF | 2 | u_xcorr/n858_s/CIN |
4.963 | 0.035 | tINS | FF | 1 | u_xcorr/n858_s/COUT |
4.963 | 0.000 | tNET | FF | 2 | u_xcorr/n857_s/CIN |
4.998 | 0.035 | tINS | FF | 1 | u_xcorr/n857_s/COUT |
4.998 | 0.000 | tNET | FF | 2 | u_xcorr/n856_s/CIN |
5.034 | 0.035 | tINS | FF | 1 | u_xcorr/n856_s/COUT |
5.034 | 0.000 | tNET | FF | 2 | u_xcorr/n855_s/CIN |
5.069 | 0.035 | tINS | FF | 1 | u_xcorr/n855_s/COUT |
5.069 | 0.000 | tNET | FF | 2 | u_xcorr/n854_s/CIN |
5.104 | 0.035 | tINS | FF | 1 | u_xcorr/n854_s/COUT |
5.104 | 0.000 | tNET | FF | 2 | u_xcorr/n853_s/CIN |
5.139 | 0.035 | tINS | FF | 1 | u_xcorr/n853_s/COUT |
5.139 | 0.000 | tNET | FF | 2 | u_xcorr/n852_s/CIN |
5.174 | 0.035 | tINS | FF | 1 | u_xcorr/n852_s/COUT |
5.174 | 0.000 | tNET | FF | 2 | u_xcorr/n851_s/CIN |
5.210 | 0.035 | tINS | FF | 1 | u_xcorr/n851_s/COUT |
5.210 | 0.000 | tNET | FF | 2 | u_xcorr/n850_s/CIN |
5.245 | 0.035 | tINS | FF | 1 | u_xcorr/n850_s/COUT |
5.245 | 0.000 | tNET | FF | 2 | u_xcorr/n849_s/CIN |
5.280 | 0.035 | tINS | FF | 1 | u_xcorr/n849_s/COUT |
5.280 | 0.000 | tNET | FF | 2 | u_xcorr/n848_s/CIN |
5.315 | 0.035 | tINS | FF | 1 | u_xcorr/n848_s/COUT |
5.315 | 0.000 | tNET | FF | 2 | u_xcorr/n847_s/CIN |
5.350 | 0.035 | tINS | FF | 1 | u_xcorr/n847_s/COUT |
5.350 | 0.000 | tNET | FF | 2 | u_xcorr/n846_s/CIN |
5.386 | 0.035 | tINS | FF | 1 | u_xcorr/n846_s/COUT |
5.386 | 0.000 | tNET | FF | 2 | u_xcorr/n845_s/CIN |
5.421 | 0.035 | tINS | FF | 1 | u_xcorr/n845_s/COUT |
5.421 | 0.000 | tNET | FF | 2 | u_xcorr/n844_s/CIN |
5.456 | 0.035 | tINS | FF | 1 | u_xcorr/n844_s/COUT |
5.456 | 0.000 | tNET | FF | 2 | u_xcorr/n843_s/CIN |
5.491 | 0.035 | tINS | FF | 1 | u_xcorr/n843_s/COUT |
5.491 | 0.000 | tNET | FF | 2 | u_xcorr/n842_s/CIN |
5.526 | 0.035 | tINS | FF | 1 | u_xcorr/n842_s/COUT |
5.526 | 0.000 | tNET | FF | 2 | u_xcorr/n841_s/CIN |
5.562 | 0.035 | tINS | FF | 1 | u_xcorr/n841_s/COUT |
5.562 | 0.000 | tNET | FF | 2 | u_xcorr/n840_s/CIN |
5.597 | 0.035 | tINS | FF | 1 | u_xcorr/n840_s/COUT |
5.597 | 0.000 | tNET | FF | 2 | u_xcorr/n839_s/CIN |
5.632 | 0.035 | tINS | FF | 1 | u_xcorr/n839_s/COUT |
5.632 | 0.000 | tNET | FF | 2 | u_xcorr/n838_s/CIN |
5.667 | 0.035 | tINS | FF | 1 | u_xcorr/n838_s/COUT |
5.667 | 0.000 | tNET | FF | 2 | u_xcorr/n837_s/CIN |
5.702 | 0.035 | tINS | FF | 1 | u_xcorr/n837_s/COUT |
5.702 | 0.000 | tNET | FF | 2 | u_xcorr/n836_s/CIN |
5.738 | 0.035 | tINS | FF | 1 | u_xcorr/n836_s/COUT |
5.738 | 0.000 | tNET | FF | 2 | u_xcorr/n835_s/CIN |
6.208 | 0.470 | tINS | FF | 1 | u_xcorr/n835_s/SUM |
6.445 | 0.237 | tNET | FF | 1 | u_xcorr/result_31_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_xcorr/result_31_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_xcorr/result_31_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.928, 70.369%; route: 1.422, 25.475%; tC2Q: 0.232, 4.156% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 4.418 |
Data Arrival Time | 6.409 |
Data Required Time | 10.828 |
From | u_xcorr/memr_1_n831_ADAREG_G_1_s |
To | u_xcorr/result_30_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/CLK |
1.095 | 0.232 | tC2Q | RF | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/Q |
1.332 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/F |
2.124 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/I2 |
2.577 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/F |
2.814 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s1/I3 |
3.185 | 0.371 | tINS | FF | 34 | u_xcorr/memr_1_n831_DOAL_G_0_s1/F |
3.422 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/I2 |
3.875 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/F |
4.112 | 0.237 | tNET | FF | 2 | u_xcorr/n866_s/I1 |
4.682 | 0.570 | tINS | FR | 1 | u_xcorr/n866_s/COUT |
4.682 | 0.000 | tNET | RR | 2 | u_xcorr/n865_s/CIN |
4.717 | 0.035 | tINS | RF | 1 | u_xcorr/n865_s/COUT |
4.717 | 0.000 | tNET | FF | 2 | u_xcorr/n864_s/CIN |
4.752 | 0.035 | tINS | FF | 1 | u_xcorr/n864_s/COUT |
4.752 | 0.000 | tNET | FF | 2 | u_xcorr/n863_s/CIN |
4.787 | 0.035 | tINS | FF | 1 | u_xcorr/n863_s/COUT |
4.787 | 0.000 | tNET | FF | 2 | u_xcorr/n862_s/CIN |
4.822 | 0.035 | tINS | FF | 1 | u_xcorr/n862_s/COUT |
4.822 | 0.000 | tNET | FF | 2 | u_xcorr/n861_s/CIN |
4.858 | 0.035 | tINS | FF | 1 | u_xcorr/n861_s/COUT |
4.858 | 0.000 | tNET | FF | 2 | u_xcorr/n860_s/CIN |
4.893 | 0.035 | tINS | FF | 1 | u_xcorr/n860_s/COUT |
4.893 | 0.000 | tNET | FF | 2 | u_xcorr/n859_s/CIN |
4.928 | 0.035 | tINS | FF | 1 | u_xcorr/n859_s/COUT |
4.928 | 0.000 | tNET | FF | 2 | u_xcorr/n858_s/CIN |
4.963 | 0.035 | tINS | FF | 1 | u_xcorr/n858_s/COUT |
4.963 | 0.000 | tNET | FF | 2 | u_xcorr/n857_s/CIN |
4.998 | 0.035 | tINS | FF | 1 | u_xcorr/n857_s/COUT |
4.998 | 0.000 | tNET | FF | 2 | u_xcorr/n856_s/CIN |
5.034 | 0.035 | tINS | FF | 1 | u_xcorr/n856_s/COUT |
5.034 | 0.000 | tNET | FF | 2 | u_xcorr/n855_s/CIN |
5.069 | 0.035 | tINS | FF | 1 | u_xcorr/n855_s/COUT |
5.069 | 0.000 | tNET | FF | 2 | u_xcorr/n854_s/CIN |
5.104 | 0.035 | tINS | FF | 1 | u_xcorr/n854_s/COUT |
5.104 | 0.000 | tNET | FF | 2 | u_xcorr/n853_s/CIN |
5.139 | 0.035 | tINS | FF | 1 | u_xcorr/n853_s/COUT |
5.139 | 0.000 | tNET | FF | 2 | u_xcorr/n852_s/CIN |
5.174 | 0.035 | tINS | FF | 1 | u_xcorr/n852_s/COUT |
5.174 | 0.000 | tNET | FF | 2 | u_xcorr/n851_s/CIN |
5.210 | 0.035 | tINS | FF | 1 | u_xcorr/n851_s/COUT |
5.210 | 0.000 | tNET | FF | 2 | u_xcorr/n850_s/CIN |
5.245 | 0.035 | tINS | FF | 1 | u_xcorr/n850_s/COUT |
5.245 | 0.000 | tNET | FF | 2 | u_xcorr/n849_s/CIN |
5.280 | 0.035 | tINS | FF | 1 | u_xcorr/n849_s/COUT |
5.280 | 0.000 | tNET | FF | 2 | u_xcorr/n848_s/CIN |
5.315 | 0.035 | tINS | FF | 1 | u_xcorr/n848_s/COUT |
5.315 | 0.000 | tNET | FF | 2 | u_xcorr/n847_s/CIN |
5.350 | 0.035 | tINS | FF | 1 | u_xcorr/n847_s/COUT |
5.350 | 0.000 | tNET | FF | 2 | u_xcorr/n846_s/CIN |
5.386 | 0.035 | tINS | FF | 1 | u_xcorr/n846_s/COUT |
5.386 | 0.000 | tNET | FF | 2 | u_xcorr/n845_s/CIN |
5.421 | 0.035 | tINS | FF | 1 | u_xcorr/n845_s/COUT |
5.421 | 0.000 | tNET | FF | 2 | u_xcorr/n844_s/CIN |
5.456 | 0.035 | tINS | FF | 1 | u_xcorr/n844_s/COUT |
5.456 | 0.000 | tNET | FF | 2 | u_xcorr/n843_s/CIN |
5.491 | 0.035 | tINS | FF | 1 | u_xcorr/n843_s/COUT |
5.491 | 0.000 | tNET | FF | 2 | u_xcorr/n842_s/CIN |
5.526 | 0.035 | tINS | FF | 1 | u_xcorr/n842_s/COUT |
5.526 | 0.000 | tNET | FF | 2 | u_xcorr/n841_s/CIN |
5.562 | 0.035 | tINS | FF | 1 | u_xcorr/n841_s/COUT |
5.562 | 0.000 | tNET | FF | 2 | u_xcorr/n840_s/CIN |
5.597 | 0.035 | tINS | FF | 1 | u_xcorr/n840_s/COUT |
5.597 | 0.000 | tNET | FF | 2 | u_xcorr/n839_s/CIN |
5.632 | 0.035 | tINS | FF | 1 | u_xcorr/n839_s/COUT |
5.632 | 0.000 | tNET | FF | 2 | u_xcorr/n838_s/CIN |
5.667 | 0.035 | tINS | FF | 1 | u_xcorr/n838_s/COUT |
5.667 | 0.000 | tNET | FF | 2 | u_xcorr/n837_s/CIN |
5.702 | 0.035 | tINS | FF | 1 | u_xcorr/n837_s/COUT |
5.702 | 0.000 | tNET | FF | 2 | u_xcorr/n836_s/CIN |
6.172 | 0.470 | tINS | FF | 1 | u_xcorr/n836_s/SUM |
6.409 | 0.237 | tNET | FF | 1 | u_xcorr/result_30_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_xcorr/result_30_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_xcorr/result_30_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.893, 70.181%; route: 1.422, 25.636%; tC2Q: 0.232, 4.183% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 4.453 |
Data Arrival Time | 6.374 |
Data Required Time | 10.828 |
From | u_xcorr/memr_1_n831_ADAREG_G_1_s |
To | u_xcorr/result_29_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/CLK |
1.095 | 0.232 | tC2Q | RF | 1 | u_xcorr/memr_1_n831_ADAREG_G_1_s/Q |
1.332 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s5/F |
2.124 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/I2 |
2.577 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s4/F |
2.814 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s1/I3 |
3.185 | 0.371 | tINS | FF | 34 | u_xcorr/memr_1_n831_DOAL_G_0_s1/F |
3.422 | 0.237 | tNET | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/I2 |
3.875 | 0.453 | tINS | FF | 1 | u_xcorr/memr_1_n831_DOAL_G_0_s0/F |
4.112 | 0.237 | tNET | FF | 2 | u_xcorr/n866_s/I1 |
4.682 | 0.570 | tINS | FR | 1 | u_xcorr/n866_s/COUT |
4.682 | 0.000 | tNET | RR | 2 | u_xcorr/n865_s/CIN |
4.717 | 0.035 | tINS | RF | 1 | u_xcorr/n865_s/COUT |
4.717 | 0.000 | tNET | FF | 2 | u_xcorr/n864_s/CIN |
4.752 | 0.035 | tINS | FF | 1 | u_xcorr/n864_s/COUT |
4.752 | 0.000 | tNET | FF | 2 | u_xcorr/n863_s/CIN |
4.787 | 0.035 | tINS | FF | 1 | u_xcorr/n863_s/COUT |
4.787 | 0.000 | tNET | FF | 2 | u_xcorr/n862_s/CIN |
4.822 | 0.035 | tINS | FF | 1 | u_xcorr/n862_s/COUT |
4.822 | 0.000 | tNET | FF | 2 | u_xcorr/n861_s/CIN |
4.858 | 0.035 | tINS | FF | 1 | u_xcorr/n861_s/COUT |
4.858 | 0.000 | tNET | FF | 2 | u_xcorr/n860_s/CIN |
4.893 | 0.035 | tINS | FF | 1 | u_xcorr/n860_s/COUT |
4.893 | 0.000 | tNET | FF | 2 | u_xcorr/n859_s/CIN |
4.928 | 0.035 | tINS | FF | 1 | u_xcorr/n859_s/COUT |
4.928 | 0.000 | tNET | FF | 2 | u_xcorr/n858_s/CIN |
4.963 | 0.035 | tINS | FF | 1 | u_xcorr/n858_s/COUT |
4.963 | 0.000 | tNET | FF | 2 | u_xcorr/n857_s/CIN |
4.998 | 0.035 | tINS | FF | 1 | u_xcorr/n857_s/COUT |
4.998 | 0.000 | tNET | FF | 2 | u_xcorr/n856_s/CIN |
5.034 | 0.035 | tINS | FF | 1 | u_xcorr/n856_s/COUT |
5.034 | 0.000 | tNET | FF | 2 | u_xcorr/n855_s/CIN |
5.069 | 0.035 | tINS | FF | 1 | u_xcorr/n855_s/COUT |
5.069 | 0.000 | tNET | FF | 2 | u_xcorr/n854_s/CIN |
5.104 | 0.035 | tINS | FF | 1 | u_xcorr/n854_s/COUT |
5.104 | 0.000 | tNET | FF | 2 | u_xcorr/n853_s/CIN |
5.139 | 0.035 | tINS | FF | 1 | u_xcorr/n853_s/COUT |
5.139 | 0.000 | tNET | FF | 2 | u_xcorr/n852_s/CIN |
5.174 | 0.035 | tINS | FF | 1 | u_xcorr/n852_s/COUT |
5.174 | 0.000 | tNET | FF | 2 | u_xcorr/n851_s/CIN |
5.210 | 0.035 | tINS | FF | 1 | u_xcorr/n851_s/COUT |
5.210 | 0.000 | tNET | FF | 2 | u_xcorr/n850_s/CIN |
5.245 | 0.035 | tINS | FF | 1 | u_xcorr/n850_s/COUT |
5.245 | 0.000 | tNET | FF | 2 | u_xcorr/n849_s/CIN |
5.280 | 0.035 | tINS | FF | 1 | u_xcorr/n849_s/COUT |
5.280 | 0.000 | tNET | FF | 2 | u_xcorr/n848_s/CIN |
5.315 | 0.035 | tINS | FF | 1 | u_xcorr/n848_s/COUT |
5.315 | 0.000 | tNET | FF | 2 | u_xcorr/n847_s/CIN |
5.350 | 0.035 | tINS | FF | 1 | u_xcorr/n847_s/COUT |
5.350 | 0.000 | tNET | FF | 2 | u_xcorr/n846_s/CIN |
5.386 | 0.035 | tINS | FF | 1 | u_xcorr/n846_s/COUT |
5.386 | 0.000 | tNET | FF | 2 | u_xcorr/n845_s/CIN |
5.421 | 0.035 | tINS | FF | 1 | u_xcorr/n845_s/COUT |
5.421 | 0.000 | tNET | FF | 2 | u_xcorr/n844_s/CIN |
5.456 | 0.035 | tINS | FF | 1 | u_xcorr/n844_s/COUT |
5.456 | 0.000 | tNET | FF | 2 | u_xcorr/n843_s/CIN |
5.491 | 0.035 | tINS | FF | 1 | u_xcorr/n843_s/COUT |
5.491 | 0.000 | tNET | FF | 2 | u_xcorr/n842_s/CIN |
5.526 | 0.035 | tINS | FF | 1 | u_xcorr/n842_s/COUT |
5.526 | 0.000 | tNET | FF | 2 | u_xcorr/n841_s/CIN |
5.562 | 0.035 | tINS | FF | 1 | u_xcorr/n841_s/COUT |
5.562 | 0.000 | tNET | FF | 2 | u_xcorr/n840_s/CIN |
5.597 | 0.035 | tINS | FF | 1 | u_xcorr/n840_s/COUT |
5.597 | 0.000 | tNET | FF | 2 | u_xcorr/n839_s/CIN |
5.632 | 0.035 | tINS | FF | 1 | u_xcorr/n839_s/COUT |
5.632 | 0.000 | tNET | FF | 2 | u_xcorr/n838_s/CIN |
5.667 | 0.035 | tINS | FF | 1 | u_xcorr/n838_s/COUT |
5.667 | 0.000 | tNET | FF | 2 | u_xcorr/n837_s/CIN |
6.137 | 0.470 | tINS | FF | 1 | u_xcorr/n837_s/SUM |
6.374 | 0.237 | tNET | FF | 1 | u_xcorr/result_29_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 166 | clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_xcorr/result_29_s0/CLK |
10.828 | -0.035 | tSu | 1 | u_xcorr/result_29_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.858, 69.991%; route: 1.422, 25.800%; tC2Q: 0.232, 4.209% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |