Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW1N : GW1N_9
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:02s - 2019/2/12
16:22:01
(premap)Complete 10 0 0 0m:02s 0m:02s 192MB 2019/2/12
16:22:06
(fpga_mapper)Complete 11 2 0 0m:10s 0m:11s 223MB 2019/2/12
16:22:19
Multi-srs Generator Complete00m:01s2019/2/12
16:22:03

Area Summary
I/O ports (io_port) 27 Non I/O Register bits (non_io_reg) 306 (4%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 1 (26)
Block Multipliers (dsp_used) 0 (10) LUTs (total_luts) 476 (5%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i121.2 MHz103.0 MHz-1.456
ao_top_0|control[0]93.6 MHz79.6 MHz-1.885
System100.0 MHz173.1 MHz4.222

Optimizations Summary
Combined Clock Conversion 2 / 0