#Build: Synplify Pro (R) O-2018.09G-SP1-Beta4, Build 017R, Dec 17 2018
#install: C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro
#OS: Windows 8 6.2
#Hostname: GW-SW-023

# Tue Feb 12 16:21:59 2019

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-Beta4
Install: C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q4p1, Build 033R, Built Dec 17 2018 09:33:25

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-Beta4
Install: C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q4p1, Build 033R, Built Dec 17 2018 09:33:25

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Pico\picosoc_demo_1n9\impl\temp\gao\ao_0\gw_ao_parameter.v" (library work)
@I::"D:\Pico\picosoc_demo_1n9\impl\temp\gao\ao_0\gw_ao_top_define.v" (library work)
@I::"D:\Pico\picosoc_demo_1n9\impl\temp\gao\ao_0\gw_ao_expression.v" (library work)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
@W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
@W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
@I::"C:\Gowin\Gowin_YunYuan_V1.8.4Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
@W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
@W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
@W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
@W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
@W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
@W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
@W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
@W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
@W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
@W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
@W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
@W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
@W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
@W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
@W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
@W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
@W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
@W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
@W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
@W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
Verilog syntax check successful!
@N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_D:\Pico\picosoc_demo_1n9\impl\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
Selecting top level module ao_top_0
Running optimization stage 1 on ao_mem_ctrl_0_1024s_9s_10s .......
Running optimization stage 1 on ao_crc32_0 .......
Running optimization stage 1 on ao_match_0_0s_8s_16s_0_1_0_1_2_3_4 .......
Running optimization stage 1 on ao_top_0 .......
Running optimization stage 2 on ao_match_0_0s_8s_16s_0_1_0_1_2_3_4 .......
Running optimization stage 2 on ao_top_0 .......
Extracted state machine for register module_state
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1001
   1010
   1011
Running optimization stage 2 on ao_crc32_0 .......
Running optimization stage 2 on ao_mem_ctrl_0_1024s_9s_10s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 85MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Feb 12 16:22:01 2019

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-Beta4
Install: C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 033R, Built Dec 17 2018 09:33:25

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Feb 12 16:22:01 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Feb 12 16:22:01 2019

###########################################################]


###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-Beta4
Install: C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 033R, Built Dec 17 2018 09:33:25

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Feb 12 16:22:03 2019

###########################################################]


Premap Report



# Tue Feb 12 16:22:03 2019


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-Beta4
Install: C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1255R, Built Dec 27 2018 06:03:23


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  ao_0_scck.rpt
Printing clock  summary report in "D:\Pico\picosoc_demo_1n9\impl\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

@N:BN133 :  | Ignoring syn_hier=hard property on top-level design. 

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1001 -> 00100000000
   1010 -> 01000000000
   1011 -> 10000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)



Clock Summary
******************

          Start                   Requested     Requested     Clock        Clock                     Clock
Level     Clock                   Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------------------
0 -       ao_top_0|control[0]     138.6 MHz     7.216         inferred     Autoconstr_clkgroup_1     255  
                                                                                                          
0 -       ao_top_0|clk_i          168.2 MHz     5.946         inferred     Autoconstr_clkgroup_0     59   
==========================================================================================================



Clock Load Summary
***********************

                        Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin       
Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example        
--------------------------------------------------------------------------------------------------------------------------------------
ao_top_0|control[0]     255       control[0](port)     data_register[36:0].C                    -                 -                   
                                                                                                                                      
ao_top_0|clk_i          59        clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
======================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 306 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

============================= Non-Gated/Non-Generated Clocks =============================
Clock Tree ID     Driving Element     Drive Element Type        Fanout     Sample Instance
------------------------------------------------------------------------------------------
ClockId_0_0       ENCRYPTED           Unconstrained_port        51         ENCRYPTED      
ClockId_0_1       ENCRYPTED           Unconstrained_io_port     255        ENCRYPTED      
==========================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\Pico\picosoc_demo_1n9\impl\temp\gao\ao_0\rev_1\ao_0.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 192MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 192MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 192MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 106MB peak: 192MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Feb 12 16:22:06 2019

###########################################################]


Map & Optimize Report



# Tue Feb 12 16:22:07 2019


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-SP1-Beta4
Install: C:\Gowin\Gowin_YunYuan_V1.8.4Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1255R, Built Dec 27 2018 06:03:23


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)


Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 199MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 199MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 199MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)


Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)


Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 204MB peak: 223MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:04s		    -3.48ns		 453 /       290
   2		0h:00m:04s		    -3.48ns		 457 /       290
   3		0h:00m:04s		    -3.48ns		 456 /       290
   4		0h:00m:04s		    -3.08ns		 456 /       290
Timing driven replication report
Added 11 Registers via timing driven replication
Added 2 LUTs via timing driven replication

   5		0h:00m:05s		    -2.58ns		 479 /       301
   6		0h:00m:05s		    -2.30ns		 485 /       301
   7		0h:00m:05s		    -2.36ns		 486 /       301
   8		0h:00m:05s		    -2.36ns		 488 /       301
   9		0h:00m:05s		    -2.36ns		 489 /       301
  10		0h:00m:05s		    -2.30ns		 490 /       301
  11		0h:00m:05s		    -2.30ns		 490 /       301
  12		0h:00m:05s		    -2.30ns		 490 /       301
  13		0h:00m:06s		    -2.30ns		 490 /       301
  14		0h:00m:06s		    -2.30ns		 490 /       301
Timing driven replication report
Added 5 Registers via timing driven replication
Added 2 LUTs via timing driven replication


  15		0h:00m:06s		    -2.45ns		 495 /       306
  16		0h:00m:06s		    -2.52ns		 497 /       306
  17		0h:00m:06s		    -2.71ns		 498 /       306
  18		0h:00m:06s		    -2.22ns		 502 /       306
  19		0h:00m:06s		    -2.56ns		 515 /       306
  20		0h:00m:06s		    -2.38ns		 515 /       306
  21		0h:00m:06s		    -2.24ns		 518 /       306
  22		0h:00m:06s		    -2.22ns		 519 /       306

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:06s; Memory used current: 207MB peak: 223MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 206MB peak: 223MB)


Start Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 136MB peak: 223MB)

Writing Analyst data base D:\Pico\picosoc_demo_1n9\impl\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 206MB peak: 223MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 207MB peak: 223MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 205MB peak: 223MB)


Start final timing analysis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 205MB peak: 223MB)

@W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 8.25ns. Please declare a user-defined clock on port clk_i. 
@W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 10.68ns. Please declare a user-defined clock on port control[0]. 


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Feb 12 16:22:18 2019
#


Top view:               ao_top_0
Requested Frequency:    93.6 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.885

                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------
ao_top_0|clk_i          121.2 MHz     103.0 MHz     8.251         9.707         -1.456     inferred     Autoconstr_clkgroup_0
ao_top_0|control[0]     93.6 MHz      79.6 MHz      10.684        12.570        -1.885     inferred     Autoconstr_clkgroup_1
System                  100.0 MHz     173.1 MHz     10.000        5.778         4.222      system       system_clkgroup      
=============================================================================================================================





Clock Relationships
*******************

Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------
Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------
System               ao_top_0|clk_i       |  8.251       4.222   |  No paths    -      |  No paths    -      |  No paths    -    
System               ao_top_0|control[0]  |  10.684      7.434   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       System               |  8.251       6.863   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       ao_top_0|clk_i       |  8.251       -1.456  |  8.251       6.730  |  No paths    -      |  4.126       2.605
ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  System               |  10.684      9.296   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|control[0]  |  10.684      -1.886  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ao_top_0|clk_i
====================================



Starting Points with Worst Slack
********************************

                                      Starting                                                                  Arrival           
Instance                              Reference          Type      Pin     Net                                  Time        Slack 
                                      Clock                                                                                       
----------------------------------------------------------------------------------------------------------------------------------
triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[1]                  0.367       -1.456
internal_reg_force_triger_syn[1]      ao_top_0|clk_i     DFFC      Q       internal_reg_force_triger_syn[1]     0.367       -1.389
triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[2]                  0.367       -1.179
triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[3]                  0.367       -0.983
triger_level_cnt[0]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[0]                  0.367       -0.130
u_ao_mem_ctrl.capture_loop            ao_top_0|clk_i     DFFCE     Q       capture_loop                         0.367       0.132 
genblk1\.u_ao_match_0.match_sep       ao_top_0|clk_i     DFFC      Q       match                                0.367       0.342 
internal_reg_start_dly[1]             ao_top_0|clk_i     DFFC      Q       internal_reg_start_dly[1]            0.367       0.409 
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     Q       capture_mem_addr[1]                  0.367       0.457 
capture_window_sel[1]                 ao_top_0|clk_i     DFFC      Q       capture_window_sel[1]                0.367       0.472 
==================================================================================================================================


Ending Points with Worst Slack
******************************

                                    Starting                                                         Required           
Instance                            Reference          Type      Pin     Net                         Time         Slack 
                                    Clock                                                                               
------------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.mem_addr_inc_en       ao_top_0|clk_i     DFFCE     CE      un1_capture_length_zero     8.118        -1.456
u_ao_mem_ctrl.capture_mem_wr        ao_top_0|clk_i     DFFCE     CE      un1_start_reg               8.118        -1.050
triger_level_cnt[0]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[0]       8.118        -0.130
trigger_seq_start                   ao_top_0|clk_i     DFFCE     CE      un2_start_reg_0             8.118        -0.063
u_ao_mem_ctrl.mem_addr_inc_en       ao_top_0|clk_i     DFFCE     D       mem_addr_inc_en7            8.118        0.065 
triger_level_cnt[1]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[1]       8.118        0.133 
triger_level_cnt[2]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]       8.118        0.133 
triger_level_cnt[3]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]       8.118        0.193 
u_ao_mem_ctrl.capture_length[0]     ao_top_0|clk_i     DFFC      D       capture_length_5[0]         8.118        0.342 
u_ao_mem_ctrl.capture_length[1]     ao_top_0|clk_i     DFFC      D       capture_length_5[1]         8.118        0.342 
========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      8.251
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.118

    - Propagation time:                      9.574
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.456

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[1] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
triger_level_cnt[1]                               DFFC      Q        Out     0.367     0.367       -         
triger_level_cnt[1]                               Net       -        -       1.021     -           6         
N_31_i_N_2L1_0                                    LUT4      I1       In      -         1.388       -         
N_31_i_N_2L1_0                                    LUT4      F        Out     1.099     2.487       -         
N_31_i_N_2L1_0                                    Net       -        -       0.766     -           1         
N_31_i_N_3L3_0                                    LUT4      I0       In      -         3.253       -         
N_31_i_N_3L3_0                                    LUT4      F        Out     1.032     4.285       -         
N_31_i_N_3L3_0                                    Net       -        -       0.766     -           1         
N_31_i                                            LUT4      I2       In      -         5.050       -         
N_31_i                                            LUT4      F        Out     0.822     5.872       -         
N_31_i                                            Net       -        -       1.082     -           14        
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1_0     LUT2      I0       In      -         6.954       -         
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1_0     LUT2      F        Out     1.032     7.986       -         
un1_capture_length_zero_1                         Net       -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_length_zero             LUT4      I2       In      -         8.752       -         
u_ao_mem_ctrl.un1_capture_length_zero             LUT4      F        Out     0.822     9.574       -         
un1_capture_length_zero                           Net       -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en                     DFFCE     CE       In      -         9.574       -         
=============================================================================================================
Total path delay (propagation time + setup) of 9.707 is 5.307(54.7%) logic and 4.400(45.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      8.251
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.118

    - Propagation time:                      9.507
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.389

    Number of logic level(s):                5
    Starting point:                          internal_reg_force_triger_syn[1] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
internal_reg_force_triger_syn[1]                  DFFC      Q        Out     0.367     0.367       -         
internal_reg_force_triger_syn[1]                  Net       -        -       1.021     -           2         
N_31_i_N_2L1_0                                    LUT4      I0       In      -         1.388       -         
N_31_i_N_2L1_0                                    LUT4      F        Out     1.032     2.420       -         
N_31_i_N_2L1_0                                    Net       -        -       0.766     -           1         
N_31_i_N_3L3_0                                    LUT4      I0       In      -         3.186       -         
N_31_i_N_3L3_0                                    LUT4      F        Out     1.032     4.218       -         
N_31_i_N_3L3_0                                    Net       -        -       0.766     -           1         
N_31_i                                            LUT4      I2       In      -         4.983       -         
N_31_i                                            LUT4      F        Out     0.822     5.805       -         
N_31_i                                            Net       -        -       1.082     -           14        
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1_0     LUT2      I0       In      -         6.887       -         
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1_0     LUT2      F        Out     1.032     7.919       -         
un1_capture_length_zero_1                         Net       -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_length_zero             LUT4      I2       In      -         8.685       -         
u_ao_mem_ctrl.un1_capture_length_zero             LUT4      F        Out     0.822     9.507       -         
un1_capture_length_zero                           Net       -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en                     DFFCE     CE       In      -         9.507       -         
=============================================================================================================
Total path delay (propagation time + setup) of 9.640 is 5.240(54.4%) logic and 4.400(45.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      8.251
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.118

    - Propagation time:                      9.297
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.179

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[2] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
triger_level_cnt[2]                               DFFC      Q        Out     0.367     0.367       -         
triger_level_cnt[2]                               Net       -        -       1.021     -           6         
N_31_i_N_2L1_0                                    LUT4      I2       In      -         1.388       -         
N_31_i_N_2L1_0                                    LUT4      F        Out     0.822     2.210       -         
N_31_i_N_2L1_0                                    Net       -        -       0.766     -           1         
N_31_i_N_3L3_0                                    LUT4      I0       In      -         2.976       -         
N_31_i_N_3L3_0                                    LUT4      F        Out     1.032     4.008       -         
N_31_i_N_3L3_0                                    Net       -        -       0.766     -           1         
N_31_i                                            LUT4      I2       In      -         4.773       -         
N_31_i                                            LUT4      F        Out     0.822     5.595       -         
N_31_i                                            Net       -        -       1.082     -           14        
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1_0     LUT2      I0       In      -         6.677       -         
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1_0     LUT2      F        Out     1.032     7.709       -         
un1_capture_length_zero_1                         Net       -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_length_zero             LUT4      I2       In      -         8.475       -         
u_ao_mem_ctrl.un1_capture_length_zero             LUT4      F        Out     0.822     9.297       -         
un1_capture_length_zero                           Net       -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en                     DFFCE     CE       In      -         9.297       -         
=============================================================================================================
Total path delay (propagation time + setup) of 9.430 is 5.030(53.3%) logic and 4.400(46.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      8.251
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.118

    - Propagation time:                      9.168
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.050

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[1] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                    Type      Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
triger_level_cnt[1]                     DFFC      Q        Out     0.367     0.367       -         
triger_level_cnt[1]                     Net       -        -       1.021     -           6         
N_31_i_N_2L1_0                          LUT4      I1       In      -         1.388       -         
N_31_i_N_2L1_0                          LUT4      F        Out     1.099     2.487       -         
N_31_i_N_2L1_0                          Net       -        -       0.766     -           1         
N_31_i_N_3L3_0                          LUT4      I0       In      -         3.253       -         
N_31_i_N_3L3_0                          LUT4      F        Out     1.032     4.285       -         
N_31_i_N_3L3_0                          Net       -        -       0.766     -           1         
N_31_i                                  LUT4      I2       In      -         5.050       -         
N_31_i                                  LUT4      F        Out     0.822     5.872       -         
N_31_i                                  Net       -        -       1.082     -           14        
u_ao_mem_ctrl.un1_start_reg_N_2L1_0     LUT4      I2       In      -         6.954       -         
u_ao_mem_ctrl.un1_start_reg_N_2L1_0     LUT4      F        Out     0.822     7.776       -         
un1_start_reg_N_2L1_0                   Net       -        -       0.766     -           1         
u_ao_mem_ctrl.un1_start_reg             LUT4      I3       In      -         8.542       -         
u_ao_mem_ctrl.un1_start_reg             LUT4      F        Out     0.626     9.168       -         
un1_start_reg                           Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr            DFFCE     CE       In      -         9.168       -         
===================================================================================================
Total path delay (propagation time + setup) of 9.301 is 4.901(52.7%) logic and 4.400(47.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      8.251
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.118

    - Propagation time:                      9.101
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.983

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[3] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
triger_level_cnt[3]                               DFFC      Q        Out     0.367     0.367       -         
triger_level_cnt[3]                               Net       -        -       1.021     -           6         
N_31_i_N_2L1_0                                    LUT4      I3       In      -         1.388       -         
N_31_i_N_2L1_0                                    LUT4      F        Out     0.626     2.014       -         
N_31_i_N_2L1_0                                    Net       -        -       0.766     -           1         
N_31_i_N_3L3_0                                    LUT4      I0       In      -         2.780       -         
N_31_i_N_3L3_0                                    LUT4      F        Out     1.032     3.812       -         
N_31_i_N_3L3_0                                    Net       -        -       0.766     -           1         
N_31_i                                            LUT4      I2       In      -         4.577       -         
N_31_i                                            LUT4      F        Out     0.822     5.399       -         
N_31_i                                            Net       -        -       1.082     -           14        
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1_0     LUT2      I0       In      -         6.481       -         
u_ao_mem_ctrl.un1_capture_length_zero_N_2L1_0     LUT2      F        Out     1.032     7.513       -         
un1_capture_length_zero_1                         Net       -        -       0.766     -           1         
u_ao_mem_ctrl.un1_capture_length_zero             LUT4      I2       In      -         8.279       -         
u_ao_mem_ctrl.un1_capture_length_zero             LUT4      F        Out     0.822     9.101       -         
un1_capture_length_zero                           Net       -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en                     DFFCE     CE       In      -         9.101       -         
=============================================================================================================
Total path delay (propagation time + setup) of 9.234 is 4.834(52.3%) logic and 4.400(47.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: ao_top_0|control[0]
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                                   Arrival           
Instance                         Reference               Type      Pin     Net                              Time        Slack 
                                 Clock                                                                                        
------------------------------------------------------------------------------------------------------------------------------
internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.367       -1.885
internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.367       -1.818
internal_register_select[13]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[13]     0.367       -1.614
internal_register_select[12]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[12]     0.367       -1.547
bit_count[1]                     ao_top_0|control[0]     DFFC      Q       bit_count[1]                     0.367       -1.530
internal_register_select[3]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[3]      0.367       -1.486
data_register_fast[33]           ao_top_0|control[0]     DFFCE     Q       data_register_fast[33]           0.367       -1.471
bit_count[0]                     ao_top_0|control[0]     DFFC      Q       bit_count[0]                     0.367       -1.463
internal_register_select[2]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[2]      0.367       -1.419
data_register_fast[32]           ao_top_0|control[0]     DFFCE     Q       data_register_fast[32]           0.367       -1.404
==============================================================================================================================


Ending Points with Worst Slack
******************************

                           Starting                                                               Required           
Instance                   Reference               Type      Pin     Net                          Time         Slack 
                           Clock                                                                                     
---------------------------------------------------------------------------------------------------------------------
data_out_shift_reg[2]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[2]      10.552       -1.885
data_out_shift_reg[0]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[0]      10.552       -1.614
data_out_shift_reg[10]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[10]     10.552       -1.530
data_out_shift_reg[12]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[12]     10.552       -1.530
data_out_shift_reg[14]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[14]     10.552       -1.530
data_out_shift_reg[4]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[4]      10.552       -1.486
bit_count[1]               ao_top_0|control[0]     DFFC      D       bit_count_3[1]               10.552       -1.358
bit_count[3]               ao_top_0|control[0]     DFFC      D       bit_count_3[3]               10.552       -1.358
data_out_shift_reg[9]      ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[9]      10.552       -1.285
data_out_shift_reg[11]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[11]     10.552       -1.285
=====================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.684
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.552

    - Propagation time:                      12.437
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.885

    Number of logic level(s):                6
    Starting point:                          internal_register_select[9] / Q
    Ending point:                            data_out_shift_reg[2] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                                                   Pin      Pin               Arrival     No. of    
Name                                                                   Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------
internal_register_select[9]                                            DFFCE     Q        Out     0.367     0.367       -         
internal_register_select[9]                                            Net       -        -       1.021     -           2         
internal_reg_start_m_11_0                                              LUT2      I1       In      -         1.388       -         
internal_reg_start_m_11_0                                              LUT2      F        Out     1.099     2.487       -         
internal_reg_start_m_11_0                                              Net       -        -       1.021     -           3         
data_from_internal_reg77_14                                            LUT4      I0       In      -         3.508       -         
data_from_internal_reg77_14                                            LUT4      F        Out     1.032     4.540       -         
internal_reg_start_m_14                                                Net       -        -       1.204     -           33        
TRIGER_SEL_LEVEL_REG\[0\]\.internal_reg_trig_level_sel\[0\]_m_1[2]     LUT3      I1       In      -         5.744       -         
TRIGER_SEL_LEVEL_REG\[0\]\.internal_reg_trig_level_sel\[0\]_m_1[2]     LUT3      F        Out     1.099     6.843       -         
TRIGER_SEL_LEVEL_REG\[0\]\.internal_reg_trig_level_sel\[0\]_m_1[2]     Net       -        -       0.766     -           1         
data_from_ao_reg_1_1[2]                                                LUT4      I1       In      -         7.609       -         
data_from_ao_reg_1_1[2]                                                LUT4      F        Out     1.099     8.708       -         
data_from_ao_reg_1_1[2]                                                Net       -        -       0.766     -           1         
data_from_ao_reg[2]                                                    LUT4      I1       In      -         9.473       -         
data_from_ao_reg[2]                                                    LUT4      F        Out     1.099     10.572      -         
data_from_ao_reg[2]                                                    Net       -        -       0.766     -           1         
data_out_shift_reg_4[2]                                                LUT4      I1       In      -         11.338      -         
data_out_shift_reg_4[2]                                                LUT4      F        Out     1.099     12.437      -         
data_out_shift_reg_4[2]                                                Net       -        -       0.000     -           1         
data_out_shift_reg[2]                                                  DFFCE     D        In      -         12.437      -         
==================================================================================================================================
Total path delay (propagation time + setup) of 12.570 is 7.027(55.9%) logic and 5.543(44.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.684
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.552

    - Propagation time:                      12.370
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.818

    Number of logic level(s):                6
    Starting point:                          internal_register_select[7] / Q
    Ending point:                            data_out_shift_reg[2] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                                                   Pin      Pin               Arrival     No. of    
Name                                                                   Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------
internal_register_select[7]                                            DFFCE     Q        Out     0.367     0.367       -         
internal_register_select[7]                                            Net       -        -       1.021     -           2         
internal_reg_start_m_11_0                                              LUT2      I0       In      -         1.388       -         
internal_reg_start_m_11_0                                              LUT2      F        Out     1.032     2.420       -         
internal_reg_start_m_11_0                                              Net       -        -       1.021     -           3         
data_from_internal_reg77_14                                            LUT4      I0       In      -         3.441       -         
data_from_internal_reg77_14                                            LUT4      F        Out     1.032     4.473       -         
internal_reg_start_m_14                                                Net       -        -       1.204     -           33        
TRIGER_SEL_LEVEL_REG\[0\]\.internal_reg_trig_level_sel\[0\]_m_1[2]     LUT3      I1       In      -         5.677       -         
TRIGER_SEL_LEVEL_REG\[0\]\.internal_reg_trig_level_sel\[0\]_m_1[2]     LUT3      F        Out     1.099     6.776       -         
TRIGER_SEL_LEVEL_REG\[0\]\.internal_reg_trig_level_sel\[0\]_m_1[2]     Net       -        -       0.766     -           1         
data_from_ao_reg_1_1[2]                                                LUT4      I1       In      -         7.542       -         
data_from_ao_reg_1_1[2]                                                LUT4      F        Out     1.099     8.640       -         
data_from_ao_reg_1_1[2]                                                Net       -        -       0.766     -           1         
data_from_ao_reg[2]                                                    LUT4      I1       In      -         9.406       -         
data_from_ao_reg[2]                                                    LUT4      F        Out     1.099     10.505      -         
data_from_ao_reg[2]                                                    Net       -        -       0.766     -           1         
data_out_shift_reg_4[2]                                                LUT4      I1       In      -         11.271      -         
data_out_shift_reg_4[2]                                                LUT4      F        Out     1.099     12.370      -         
data_out_shift_reg_4[2]                                                Net       -        -       0.000     -           1         
data_out_shift_reg[2]                                                  DFFCE     D        In      -         12.370      -         
==================================================================================================================================
Total path delay (propagation time + setup) of 12.503 is 6.960(55.7%) logic and 5.543(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.684
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.552

    - Propagation time:                      12.165
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.614

    Number of logic level(s):                6
    Starting point:                          internal_register_select[13] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                               Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
internal_register_select[13]       DFFCE     Q        Out     0.367     0.367       -         
internal_register_select[13]       Net       -        -       1.021     -           1         
internal_reg_start_m_12            LUT4      I1       In      -         1.388       -         
internal_reg_start_m_12            LUT4      F        Out     1.099     2.487       -         
match_unit_rd_en_9[0]              Net       -        -       1.021     -           7         
match_unit_rd_en[0]                LUT4      I1       In      -         3.508       -         
match_unit_rd_en[0]                LUT4      F        Out     1.099     4.607       -         
match_unit_rd_en[0]                Net       -        -       1.021     -           8         
genblk1\.u_ao_match_0.N_27_i       LUT3      I2       In      -         5.628       -         
genblk1\.u_ao_match_0.N_27_i       LUT3      F        Out     0.822     6.450       -         
data_from_match_unit[0]            Net       -        -       1.021     -           1         
data_out_shift_reg_4_1_a4_2[0]     LUT3      I0       In      -         7.471       -         
data_out_shift_reg_4_1_a4_2[0]     LUT3      F        Out     1.032     8.503       -         
N_120                              Net       -        -       0.766     -           1         
data_out_shift_reg_4_1_3[0]        LUT4      I0       In      -         9.269       -         
data_out_shift_reg_4_1_3[0]        LUT4      F        Out     1.032     10.300      -         
data_out_shift_reg_4_1_3[0]        Net       -        -       0.766     -           1         
data_out_shift_reg_4_1[0]          LUT4      I1       In      -         11.066      -         
data_out_shift_reg_4_1[0]          LUT4      F        Out     1.099     12.165      -         
data_out_shift_reg_4[0]            Net       -        -       0.000     -           1         
data_out_shift_reg[0]              DFFCE     D        In      -         12.165      -         
==============================================================================================
Total path delay (propagation time + setup) of 12.298 is 6.683(54.3%) logic and 5.615(45.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.684
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.552

    - Propagation time:                      12.098
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.547

    Number of logic level(s):                6
    Starting point:                          internal_register_select[12] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                               Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
internal_register_select[12]       DFFCE     Q        Out     0.367     0.367       -         
internal_register_select[12]       Net       -        -       1.021     -           1         
internal_reg_start_m_12            LUT4      I0       In      -         1.388       -         
internal_reg_start_m_12            LUT4      F        Out     1.032     2.420       -         
match_unit_rd_en_9[0]              Net       -        -       1.021     -           7         
match_unit_rd_en[0]                LUT4      I1       In      -         3.441       -         
match_unit_rd_en[0]                LUT4      F        Out     1.099     4.540       -         
match_unit_rd_en[0]                Net       -        -       1.021     -           8         
genblk1\.u_ao_match_0.N_27_i       LUT3      I2       In      -         5.561       -         
genblk1\.u_ao_match_0.N_27_i       LUT3      F        Out     0.822     6.383       -         
data_from_match_unit[0]            Net       -        -       1.021     -           1         
data_out_shift_reg_4_1_a4_2[0]     LUT3      I0       In      -         7.404       -         
data_out_shift_reg_4_1_a4_2[0]     LUT3      F        Out     1.032     8.436       -         
N_120                              Net       -        -       0.766     -           1         
data_out_shift_reg_4_1_3[0]        LUT4      I0       In      -         9.201       -         
data_out_shift_reg_4_1_3[0]        LUT4      F        Out     1.032     10.233      -         
data_out_shift_reg_4_1_3[0]        Net       -        -       0.766     -           1         
data_out_shift_reg_4_1[0]          LUT4      I1       In      -         10.999      -         
data_out_shift_reg_4_1[0]          LUT4      F        Out     1.099     12.098      -         
data_out_shift_reg_4[0]            Net       -        -       0.000     -           1         
data_out_shift_reg[0]              DFFCE     D        In      -         12.098      -         
==============================================================================================
Total path delay (propagation time + setup) of 12.231 is 6.616(54.1%) logic and 5.615(45.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.684
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.552

    - Propagation time:                      12.098
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.547

    Number of logic level(s):                6
    Starting point:                          internal_register_select[9] / Q
    Ending point:                            data_out_shift_reg[0] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                               Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
internal_register_select[9]        DFFCE     Q        Out     0.367     0.367       -         
internal_register_select[9]        Net       -        -       1.021     -           2         
internal_reg_start_m_11_0          LUT2      I1       In      -         1.388       -         
internal_reg_start_m_11_0          LUT2      F        Out     1.099     2.487       -         
internal_reg_start_m_11_0          Net       -        -       1.021     -           3         
match_unit_rd_en[0]                LUT4      I0       In      -         3.508       -         
match_unit_rd_en[0]                LUT4      F        Out     1.032     4.540       -         
match_unit_rd_en[0]                Net       -        -       1.021     -           8         
genblk1\.u_ao_match_0.N_27_i       LUT3      I2       In      -         5.561       -         
genblk1\.u_ao_match_0.N_27_i       LUT3      F        Out     0.822     6.383       -         
data_from_match_unit[0]            Net       -        -       1.021     -           1         
data_out_shift_reg_4_1_a4_2[0]     LUT3      I0       In      -         7.404       -         
data_out_shift_reg_4_1_a4_2[0]     LUT3      F        Out     1.032     8.436       -         
N_120                              Net       -        -       0.766     -           1         
data_out_shift_reg_4_1_3[0]        LUT4      I0       In      -         9.201       -         
data_out_shift_reg_4_1_3[0]        LUT4      F        Out     1.032     10.233      -         
data_out_shift_reg_4_1_3[0]        Net       -        -       0.766     -           1         
data_out_shift_reg_4_1[0]          LUT4      I1       In      -         10.999      -         
data_out_shift_reg_4_1[0]          LUT4      F        Out     1.099     12.098      -         
data_out_shift_reg_4[0]            Net       -        -       0.000     -           1         
data_out_shift_reg[0]              DFFCE     D        In      -         12.098      -         
==============================================================================================
Total path delay (propagation time + setup) of 12.231 is 6.616(54.1%) logic and 5.615(45.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                   Starting                                           Arrival          
Instance                           Reference     Type     Pin     Net                 Time        Slack
                                   Clock                                                               
-------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_i     System        INV      O       capture_end         0.000       4.222
module_state_i[0]                  System        INV      O       address_counter     0.000       7.434
=======================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                                        Required          
Instance                      Reference     Type      Pin     Net                             Time         Slack
                              Clock                                                                             
----------------------------------------------------------------------------------------------------------------
capture_window_sel[2]         System        DFFC      D       capture_window_sel_3[2]         8.118        4.222
capture_window_sel[3]         System        DFFC      D       capture_window_sel_3[3]         8.118        4.222
capture_window_sel[1]         System        DFFC      D       capture_window_sel_3[1]         8.118        4.673
capture_window_sel[0]         System        DFFC      D       capture_window_sel_3[0]         8.118        6.065
internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]     8.118        6.065
capture_end_dly               System        DFFP      D       capture_end                     8.118        7.097
address_counter[9]            System        DFFCE     D       address_counter_s[9]            10.552       7.434
address_counter[8]            System        DFFCE     D       address_counter_s[8]            10.552       7.490
address_counter[7]            System        DFFCE     D       address_counter_s[7]            10.552       7.548
address_counter[6]            System        DFFCE     D       address_counter_s[6]            10.552       7.604
================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      8.251
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.118

    - Propagation time:                      3.896
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 4.222

    Number of logic level(s):                2
    Starting point:                          u_ao_mem_ctrl.capture_mem_wr_i / O
    Ending point:                            capture_window_sel[2] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                              Pin      Pin               Arrival     No. of    
Name                               Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_i     INV      O        Out     0.000     0.000       -         
capture_end                        Net      -        -       1.021     -           6         
un1_capture_window_sel_ac0_1       LUT4     I0       In      -         1.021       -         
un1_capture_window_sel_ac0_1       LUT4     F        Out     1.032     2.053       -         
un1_capture_window_sel_c2          Net      -        -       1.021     -           2         
capture_window_sel_3[2]            LUT3     I2       In      -         3.074       -         
capture_window_sel_3[2]            LUT3     F        Out     0.822     3.896       -         
capture_window_sel_3[2]            Net      -        -       0.000     -           1         
capture_window_sel[2]              DFFC     D        In      -         3.896       -         
=============================================================================================
Total path delay (propagation time + setup) of 4.029 is 1.987(49.3%) logic and 2.042(50.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 206MB peak: 223MB)


Finished timing report (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 206MB peak: 223MB)

---------------------------------------
Resource Usage Report for ao_top_0 

Mapping to part: gw1n_9qfn88-6
Cell usage:
ALU             64 uses
DFF             8 uses
DFFC            51 uses
DFFCE           208 uses
DFFNP           2 uses
DFFP            5 uses
DFFPE           32 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       6 uses
MUX2_LUT6       3 uses
SDPX9           1 use
LUT2            64 uses
LUT3            122 uses
LUT4            290 uses

I/O ports: 27
I/O primitives: 27
IBUF           25 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   306 of 6480 (4%)

RAM/ROM usage summary
Block Rams : 1 of 26 (3%)

Total load per clock:
   ao_top_0|clk_i: 1
   ao_top_0|control[0]: 257

@S |Mapping Summary:
Total  LUTs: 476 (5%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 44MB peak: 223MB)

Process took 0h:00m:11s realtime, 0h:00m:10s cputime
# Tue Feb 12 16:22:19 2019

###########################################################]