#Build: Synplify Pro (R) O-2018.09G-Beta2, Build 039R, Sep 17 2018
#install: C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro
#OS: Windows 8 6.2
#Hostname: GW-SW-023

# Tue Dec 11 10:06:22 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta2
Install: C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys HDL Compiler, Version comp2018q3p1, Build 039R, Built Sep 17 2018 09:15:09

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta2
Install: C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys Verilog Compiler, Version comp2018q3p1, Build 039R, Built Sep 17 2018 09:15:09

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro\lib\generic\gw2a.v" (library work)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Pico\picosoc_demo\impl\temp\gao\ao_0\gw_ao_parameter.v" (library work)
@I::"D:\Pico\picosoc_demo\impl\temp\gao\ao_0\gw_ao_top_define.v" (library work)
@I::"D:\Pico\picosoc_demo\impl\temp\gao\ao_0\gw_ao_expression.v" (library work)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work)
@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work)
@W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared.
@W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared.
@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work)
@W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared.
@I::"C:\Gowin\Gowin_YunYuan_V1.8.2Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work)
@W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared.
@W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared.
@W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared.
@W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared.
@W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared.
@W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared.
@W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared.
@W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared.
@W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared.
@W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared.
@W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared.
@W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared.
@W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared.
@W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared.
@W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared.
@W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared.
@W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared.
@W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared.
@W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared.
@W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared.
@W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared.
Verilog syntax check successful!
@N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_D:\Pico\picosoc_demo\impl\temp\gao\ao_0\gw_ao_parameter.v_unit in library work.
Selecting top level module ao_top_0
Running optimization stage 1 on ao_mem_ctrl_0_1024s_9s_10s .......
Running optimization stage 1 on ao_crc32_0 .......
Running optimization stage 1 on ao_match_0_0s_8s_16s_0_1_0_1_2_3_4 .......
Running optimization stage 1 on ao_top_0 .......
Running optimization stage 2 on ao_match_0_0s_8s_16s_0_1_0_1_2_3_4 .......
Running optimization stage 2 on ao_top_0 .......
Extracted state machine for register module_state
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1001
   1010
   1011
Running optimization stage 2 on ao_crc32_0 .......
Running optimization stage 2 on ao_mem_ctrl_0_1024s_9s_10s .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 85MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 11 10:06:23 2018

###########################################################]
###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta2
Install: C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 039R, Built Sep 17 2018 09:15:09

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 11 10:06:23 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 11 10:06:23 2018

###########################################################]


###########################################################[

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta2
Install: C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Database state : D:\Pico\picosoc_demo\impl\temp\gao\ao_0\rev_1\synwork\|rev_1
Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 039R, Built Sep 17 2018 09:15:09

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Dec 11 10:06:25 2018

###########################################################]


Premap Report



# Tue Dec 11 10:06:25 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta2
Install: C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1176R, Built Sep 17 2018 09:44:14


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:MF827 :  | No constraint file specified. 
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  ao_0_scck.rpt
Printing clock  summary report in "D:\Pico\picosoc_demo\impl\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)

@N:BN133 :  | Ignoring syn_hier=hard property on top-level design. 

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 

Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)


Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

Rerun analysis in 0 latches

Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

@N:MF974 :  | Total number of latches (multibit) processed = 0  
@N:MF975 :  | Total number of latches (bit blasted) processed = 0  
@N:MF976 :  | Total number of (multibit) opaque latches found = 0  
@N:MF977 :  | Total number of (bit blasted) opaque latches found = 0  

Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)







Detailed report for transparent and observable latches in design:
Linked File:  ao_0_prem_latch_transparency_report.log
Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog))
original code -> new code
   0000 -> 00000000001
   0001 -> 00000000010
   0010 -> 00000000100
   0011 -> 00000001000
   0100 -> 00000010000
   0101 -> 00000100000
   0110 -> 00001000000
   0111 -> 00010000000
   1001 -> 00100000000
   1010 -> 01000000000
   1011 -> 10000000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 192MB)

syn_allowed_resources : blockrams=46  set on top level netlist ao_top_0

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)



Clock Summary
******************

          Start                   Requested     Requested     Clock        Clock                     Clock
Level     Clock                   Frequency     Period        Type         Group                     Load 
----------------------------------------------------------------------------------------------------------
0 -       ao_top_0|control[0]     186.5 MHz     5.362         inferred     Autoconstr_clkgroup_1     255  
                                                                                                          
0 -       ao_top_0|clk_i          237.7 MHz     4.207         inferred     Autoconstr_clkgroup_0     59   
==========================================================================================================



Clock Load Summary
***********************

                        Clock     Source               Clock Pin                                Non-clock Pin     Non-clock Pin       
Clock                   Load      Pin                  Seq Example                              Seq Example       Comb Example        
--------------------------------------------------------------------------------------------------------------------------------------
ao_top_0|control[0]     255       control[0](port)     data_register[36:0].C                    -                 -                   
                                                                                                                                      
ao_top_0|clk_i          59        clk_i(port)          internal_reg_force_triger_syn[1:0].C     -                 clk_ao.I[0](keepbuf)
======================================================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 306 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

============================= Non-Gated/Non-Generated Clocks =============================
Clock Tree ID     Driving Element     Drive Element Type        Fanout     Sample Instance
------------------------------------------------------------------------------------------
ClockId_0_0       ENCRYPTED           Unconstrained_port        51         ENCRYPTED      
ClockId_0_1       ENCRYPTED           Unconstrained_io_port     255        ENCRYPTED      
==========================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\Pico\picosoc_demo\impl\temp\gao\ao_0\rev_1\ao_0.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 192MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 106MB peak: 192MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Dec 11 10:06:28 2018

###########################################################]


Map & Optimize Report



# Tue Dec 11 10:06:28 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: O-2018.09G-Beta2
Install: C:\Gowin\Gowin_YunYuan_V1.8.2Beta\SynplifyPro
OS: Windows 6.2

Hostname: GW-SW-023

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw, Build 1176R, Built Sep 17 2018 09:44:14


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 192MB)


Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 199MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 199MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 199MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 199MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 199MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 199MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 218MB peak: 219MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:02s		    -2.82ns		 431 /       290
   2		0h:00m:02s		    -2.82ns		 439 /       290
   3		0h:00m:02s		    -2.95ns		 434 /       290
   4		0h:00m:02s		    -2.75ns		 434 /       290
   5		0h:00m:02s		    -2.62ns		 434 /       290
Timing driven replication report
Added 2 Registers via timing driven replication
Added 2 LUTs via timing driven replication

   6		0h:00m:02s		    -2.62ns		 441 /       292
   7		0h:00m:03s		    -2.75ns		 444 /       292
   8		0h:00m:03s		    -2.75ns		 445 /       292


   9		0h:00m:03s		    -2.62ns		 444 /       292
  10		0h:00m:03s		    -2.75ns		 444 /       292
  11		0h:00m:03s		    -2.75ns		 445 /       292

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 219MB peak: 220MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 219MB peak: 220MB)


Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 220MB)

Writing Analyst data base D:\Pico\picosoc_demo\impl\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 219MB peak: 221MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 219MB peak: 221MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 217MB peak: 221MB)


Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 218MB peak: 221MB)

@W:MT420 :  | Found inferred clock ao_top_0|clk_i with period 4.57ns. Please declare a user-defined clock on port clk_i. 
@W:MT420 :  | Found inferred clock ao_top_0|control[0] with period 6.42ns. Please declare a user-defined clock on port control[0]. 


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Dec 11 10:06:35 2018
#


Top view:               ao_top_0
Requested Frequency:    155.7 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.133

                        Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock          Frequency     Frequency     Period        Period        Slack      Type         Group                
-----------------------------------------------------------------------------------------------------------------------------
ao_top_0|clk_i          218.6 MHz     185.8 MHz     4.574         5.381         -0.807     inferred     Autoconstr_clkgroup_0
ao_top_0|control[0]     155.7 MHz     132.4 MHz     6.421         7.554         -1.133     inferred     Autoconstr_clkgroup_1
System                  150.0 MHz     236.2 MHz     6.667         4.234         2.432      system       system_clkgroup      
=============================================================================================================================





Clock Relationships
*******************

Clocks                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------
Starting             Ending               |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------
System               ao_top_0|clk_i       |  4.574       2.432   |  No paths    -      |  No paths    -      |  No paths    -    
System               ao_top_0|control[0]  |  6.421       4.505   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       System               |  4.574       3.796   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|clk_i       ao_top_0|clk_i       |  4.574       -0.807  |  4.574       3.735  |  No paths    -      |  2.287       1.448
ao_top_0|clk_i       ao_top_0|control[0]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  System               |  6.421       5.643   |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|clk_i       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
ao_top_0|control[0]  ao_top_0|control[0]  |  6.421       -1.133  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: ao_top_0|clk_i
====================================



Starting Points with Worst Slack
********************************

                                      Starting                                                                  Arrival           
Instance                              Reference          Type      Pin     Net                                  Time        Slack 
                                      Clock                                                                                       
----------------------------------------------------------------------------------------------------------------------------------
triger_level_cnt[0]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[0]                  0.243       -0.807
triger_level_cnt[2]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[2]                  0.243       -0.772
triger_level_cnt[1]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[1]                  0.243       -0.751
triger_level_cnt[3]                   ao_top_0|clk_i     DFFC      Q       triger_level_cnt[3]                  0.243       -0.664
internal_reg_force_triger_syn[1]      ao_top_0|clk_i     DFFC      Q       internal_reg_force_triger_syn[1]     0.243       0.000 
genblk1\.u_ao_match_0.match_sep       ao_top_0|clk_i     DFFC      Q       match                                0.243       0.021 
u_ao_mem_ctrl.capture_mem_addr[1]     ao_top_0|clk_i     DFFCE     Q       capture_mem_addr[1]                  0.243       0.223 
internal_reg_start_dly[1]             ao_top_0|clk_i     DFFC      Q       internal_reg_start_dly[1]            0.243       0.233 
u_ao_mem_ctrl.capture_mem_addr[0]     ao_top_0|clk_i     DFFCE     Q       capture_mem_addr[0]                  0.243       0.244 
u_ao_mem_ctrl.capture_mem_addr[3]     ao_top_0|clk_i     DFFCE     Q       capture_mem_addr[3]                  0.243       0.258 
==================================================================================================================================


Ending Points with Worst Slack
******************************

                                    Starting                                                         Required           
Instance                            Reference          Type      Pin     Net                         Time         Slack 
                                    Clock                                                                               
------------------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.mem_addr_inc_en       ao_top_0|clk_i     DFFCE     CE      un1_capture_length_zero     4.513        -0.807
u_ao_mem_ctrl.capture_mem_wr        ao_top_0|clk_i     DFFCE     CE      capture_mem_wr_RNO          4.513        -0.786
triger_level_cnt[2]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[2]       4.513        -0.772
triger_level_cnt[3]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[3]       4.513        -0.681
u_ao_mem_ctrl.mem_addr_inc_en       ao_top_0|clk_i     DFFCE     D       mem_addr_inc_en7            4.513        -0.035
triger_level_cnt[0]                 ao_top_0|clk_i     DFFC      D       triger_level_cnt_4[0]       4.513        -0.021
trigger_seq_start                   ao_top_0|clk_i     DFFCE     CE      un2_start_reg_0             4.513        0.000 
u_ao_mem_ctrl.capture_length[0]     ao_top_0|clk_i     DFFC      D       capture_length_5[0]         4.513        0.073 
u_ao_mem_ctrl.capture_length[1]     ao_top_0|clk_i     DFFC      D       capture_length_5[1]         4.513        0.073 
u_ao_mem_ctrl.capture_length[2]     ao_top_0|clk_i     DFFC      D       capture_length_5[2]         4.513        0.073 
========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.574
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.513

    - Propagation time:                      5.320
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.807

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[0] / Q
    Ending point:                            u_ao_mem_ctrl.mem_addr_inc_en / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                        Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
triger_level_cnt[0]                         DFFC      Q        Out     0.243     0.243       -         
triger_level_cnt[0]                         Net       -        -       0.535     -           5         
triger_level_cnt8_0_0_x2                    LUT2      I1       In      -         0.778       -         
triger_level_cnt8_0_0_x2                    LUT2      F        Out     0.570     1.348       -         
N_59_i                                      Net       -        -       0.535     -           2         
triger_level_cnt8_NE_0_RNIFCLU              LUT4      I0       In      -         1.883       -         
triger_level_cnt8_NE_0_RNIFCLU              LUT4      F        Out     0.549     2.432       -         
N_31_i_1                                    Net       -        -       0.401     -           1         
un1_triger_level_cnt12_0_o3_RNI8CL02        LUT4      I0       In      -         2.833       -         
un1_triger_level_cnt12_0_o3_RNI8CL02        LUT4      F        Out     0.549     3.382       -         
N_31_i                                      Net       -        -       0.596     -           14        
u_ao_mem_ctrl.un1_capture_length_zero_0     LUT3      I1       In      -         3.978       -         
u_ao_mem_ctrl.un1_capture_length_zero_0     LUT3      F        Out     0.570     4.548       -         
un1_capture_length_zero_0                   Net       -        -       0.401     -           1         
u_ao_mem_ctrl.un1_capture_length_zero       LUT4      I3       In      -         4.949       -         
u_ao_mem_ctrl.un1_capture_length_zero       LUT4      F        Out     0.371     5.320       -         
un1_capture_length_zero                     Net       -        -       0.000     -           1         
u_ao_mem_ctrl.mem_addr_inc_en               DFFCE     CE       In      -         5.320       -         
=======================================================================================================
Total path delay (propagation time + setup) of 5.381 is 2.913(54.1%) logic and 2.468(45.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      4.574
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.513

    - Propagation time:                      5.299
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.786

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[0] / Q
    Ending point:                            u_ao_mem_ctrl.capture_mem_wr / CE
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                     Pin      Pin               Arrival     No. of    
Name                                     Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------
triger_level_cnt[0]                      DFFC      Q        Out     0.243     0.243       -         
triger_level_cnt[0]                      Net       -        -       0.535     -           5         
triger_level_cnt8_0_0_x2                 LUT2      I1       In      -         0.778       -         
triger_level_cnt8_0_0_x2                 LUT2      F        Out     0.570     1.348       -         
N_59_i                                   Net       -        -       0.535     -           2         
triger_level_cnt8_NE_0_RNIFCLU           LUT4      I0       In      -         1.883       -         
triger_level_cnt8_NE_0_RNIFCLU           LUT4      F        Out     0.549     2.432       -         
N_31_i_1                                 Net       -        -       0.401     -           1         
un1_triger_level_cnt12_0_o3_RNI8CL02     LUT4      I0       In      -         2.833       -         
un1_triger_level_cnt12_0_o3_RNI8CL02     LUT4      F        Out     0.549     3.382       -         
N_31_i                                   Net       -        -       0.596     -           14        
u_ao_mem_ctrl.capture_mem_wr_RNO_0       LUT4      I3       In      -         3.978       -         
u_ao_mem_ctrl.capture_mem_wr_RNO_0       LUT4      F        Out     0.371     4.349       -         
g0_1                                     Net       -        -       0.401     -           1         
u_ao_mem_ctrl.capture_mem_wr_RNO         LUT4      I0       In      -         4.750       -         
u_ao_mem_ctrl.capture_mem_wr_RNO         LUT4      F        Out     0.549     5.299       -         
capture_mem_wr_RNO                       Net       -        -       0.000     -           1         
u_ao_mem_ctrl.capture_mem_wr             DFFCE     CE       In      -         5.299       -         
====================================================================================================
Total path delay (propagation time + setup) of 5.360 is 2.892(54.0%) logic and 2.468(46.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      4.574
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.513

    - Propagation time:                      5.285
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.772

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[2] / Q
    Ending point:                            triger_level_cnt[2] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                              Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
triger_level_cnt[2]               DFFC     Q        Out     0.243     0.243       -         
triger_level_cnt[2]               Net      -        -       0.535     -           5         
un1_triger_level_cnt12_0_o3_3     LUT3     I1       In      -         0.778       -         
un1_triger_level_cnt12_0_o3_3     LUT3     F        Out     0.570     1.348       -         
un1_triger_level_cnt12_0_o3_3     Net      -        -       0.401     -           1         
un1_triger_level_cnt12_0_o3       LUT4     I3       In      -         1.749       -         
un1_triger_level_cnt12_0_o3       LUT4     F        Out     0.371     2.120       -         
N_656                             Net      -        -       0.535     -           4         
triger_level_cnt13_i              LUT3     I0       In      -         2.655       -         
triger_level_cnt13_i              LUT3     F        Out     0.549     3.204       -         
N_33                              Net      -        -       0.535     -           3         
un1_triger_level_cnt_ac0_1        LUT3     I0       In      -         3.739       -         
un1_triger_level_cnt_ac0_1        LUT3     F        Out     0.549     4.288       -         
un1_triger_level_cnt_c2           Net      -        -       0.535     -           2         
triger_level_cnt_4[2]             LUT3     I2       In      -         4.823       -         
triger_level_cnt_4[2]             LUT3     F        Out     0.462     5.285       -         
triger_level_cnt_4[2]             Net      -        -       0.000     -           1         
triger_level_cnt[2]               DFFC     D        In      -         5.285       -         
============================================================================================
Total path delay (propagation time + setup) of 5.346 is 2.805(52.5%) logic and 2.541(47.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      4.574
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.513

    - Propagation time:                      5.264
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.751

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[1] / Q
    Ending point:                            triger_level_cnt[2] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                              Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
triger_level_cnt[1]               DFFC     Q        Out     0.243     0.243       -         
triger_level_cnt[1]               Net      -        -       0.535     -           4         
un1_triger_level_cnt12_0_o3_3     LUT3     I0       In      -         0.778       -         
un1_triger_level_cnt12_0_o3_3     LUT3     F        Out     0.549     1.327       -         
un1_triger_level_cnt12_0_o3_3     Net      -        -       0.401     -           1         
un1_triger_level_cnt12_0_o3       LUT4     I3       In      -         1.728       -         
un1_triger_level_cnt12_0_o3       LUT4     F        Out     0.371     2.099       -         
N_656                             Net      -        -       0.535     -           4         
triger_level_cnt13_i              LUT3     I0       In      -         2.634       -         
triger_level_cnt13_i              LUT3     F        Out     0.549     3.183       -         
N_33                              Net      -        -       0.535     -           3         
un1_triger_level_cnt_ac0_1        LUT3     I0       In      -         3.718       -         
un1_triger_level_cnt_ac0_1        LUT3     F        Out     0.549     4.267       -         
un1_triger_level_cnt_c2           Net      -        -       0.535     -           2         
triger_level_cnt_4[2]             LUT3     I2       In      -         4.802       -         
triger_level_cnt_4[2]             LUT3     F        Out     0.462     5.264       -         
triger_level_cnt_4[2]             Net      -        -       0.000     -           1         
triger_level_cnt[2]               DFFC     D        In      -         5.264       -         
============================================================================================
Total path delay (propagation time + setup) of 5.325 is 2.784(52.3%) logic and 2.541(47.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      4.574
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.513

    - Propagation time:                      5.194
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.681

    Number of logic level(s):                5
    Starting point:                          triger_level_cnt[2] / Q
    Ending point:                            triger_level_cnt[3] / D
    The start point is clocked by            ao_top_0|clk_i [rising] on pin CLK
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                              Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
triger_level_cnt[2]               DFFC     Q        Out     0.243     0.243       -         
triger_level_cnt[2]               Net      -        -       0.535     -           5         
un1_triger_level_cnt12_0_o3_3     LUT3     I1       In      -         0.778       -         
un1_triger_level_cnt12_0_o3_3     LUT3     F        Out     0.570     1.348       -         
un1_triger_level_cnt12_0_o3_3     Net      -        -       0.401     -           1         
un1_triger_level_cnt12_0_o3       LUT4     I3       In      -         1.749       -         
un1_triger_level_cnt12_0_o3       LUT4     F        Out     0.371     2.120       -         
N_656                             Net      -        -       0.535     -           4         
triger_level_cnt13_i              LUT3     I0       In      -         2.655       -         
triger_level_cnt13_i              LUT3     F        Out     0.549     3.204       -         
N_33                              Net      -        -       0.535     -           3         
un1_triger_level_cnt_ac0_1        LUT3     I0       In      -         3.739       -         
un1_triger_level_cnt_ac0_1        LUT3     F        Out     0.549     4.288       -         
un1_triger_level_cnt_c2           Net      -        -       0.535     -           2         
triger_level_cnt_4[3]             LUT4     I3       In      -         4.823       -         
triger_level_cnt_4[3]             LUT4     F        Out     0.371     5.194       -         
triger_level_cnt_4[3]             Net      -        -       0.000     -           1         
triger_level_cnt[3]               DFFC     D        In      -         5.194       -         
============================================================================================
Total path delay (propagation time + setup) of 5.255 is 2.714(51.6%) logic and 2.541(48.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: ao_top_0|control[0]
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                                   Arrival           
Instance                         Reference               Type      Pin     Net                              Time        Slack 
                                 Clock                                                                                        
------------------------------------------------------------------------------------------------------------------------------
internal_register_select[3]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[3]      0.243       -1.133
internal_register_select[13]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[13]     0.243       -1.128
internal_register_select[2]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[2]      0.243       -1.112
internal_register_select[9]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[9]      0.243       -1.107
internal_register_select[12]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[12]     0.243       -1.107
internal_register_select[7]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[7]      0.243       -1.086
internal_register_select[14]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[14]     0.243       -1.020
internal_register_select[10]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[10]     0.243       -0.999
internal_register_select[1]      ao_top_0|control[0]     DFFCE     Q       internal_register_select[1]      0.243       -0.931
internal_register_select[15]     ao_top_0|control[0]     DFFCE     Q       internal_register_select[15]     0.243       -0.929
==============================================================================================================================


Ending Points with Worst Slack
******************************

                          Starting                                                              Required           
Instance                  Reference               Type      Pin     Net                         Time         Slack 
                          Clock                                                                                    
-------------------------------------------------------------------------------------------------------------------
data_out_shift_reg[5]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[5]     6.360        -1.133
data_out_shift_reg[7]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[7]     6.360        -1.133
data_out_shift_reg[6]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[6]     6.360        -1.112
data_out_shift_reg[2]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[2]     6.360        -0.912
data_out_shift_reg[1]     ao_top_0|control[0]     DFFCE     D       data_out_shift_reg_4[1]     6.360        -0.861
address_counter[0]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  6.360        -0.605
address_counter[1]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  6.360        -0.605
address_counter[2]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  6.360        -0.605
address_counter[3]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  6.360        -0.605
address_counter[4]        ao_top_0|control[0]     DFFCE     CE      addr_ct_en                  6.360        -0.605
===================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.421
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.360

    - Propagation time:                      7.493
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.133

    Number of logic level(s):                7
    Starting point:                          internal_register_select[3] / Q
    Ending point:                            data_out_shift_reg[5] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_register_select[3]         DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[3]         Net       -        -       0.535     -           4         
data_from_internal_reg78_13_3_0     LUT2      I1       In      -         0.778       -         
data_from_internal_reg78_13_3_0     LUT2      F        Out     0.570     1.348       -         
data_from_internal_reg78_13_3_0     Net       -        -       0.535     -           3         
data_from_internal_reg77_0_a2_1     LUT4      I0       In      -         1.883       -         
data_from_internal_reg77_0_a2_1     LUT4      F        Out     0.549     2.432       -         
N_132                               Net       -        -       0.535     -           8         
data_from_internal_reg97_0_a4       LUT4      I0       In      -         2.967       -         
data_from_internal_reg97_0_a4       LUT4      F        Out     0.549     3.516       -         
data_from_internal_reg97            Net       -        -       0.535     -           9         
data_from_ao_reg_2_RNO[5]           LUT2      I1       In      -         4.051       -         
data_from_ao_reg_2_RNO[5]           LUT2      F        Out     0.570     4.621       -         
capture_mem_addr_rem_m[5]           Net       -        -       0.401     -           1         
data_from_ao_reg_2[5]               LUT4      I1       In      -         5.022       -         
data_from_ao_reg_2[5]               LUT4      F        Out     0.570     5.592       -         
data_from_ao_reg_2[5]               Net       -        -       0.401     -           1         
data_out_shift_reg_4_0[5]           LUT4      I0       In      -         5.993       -         
data_out_shift_reg_4_0[5]           LUT4      F        Out     0.549     6.542       -         
N_407                               Net       -        -       0.401     -           1         
data_out_shift_reg_4[5]             LUT3      I0       In      -         6.944       -         
data_out_shift_reg_4[5]             LUT3      F        Out     0.549     7.493       -         
data_out_shift_reg_4[5]             Net       -        -       0.000     -           1         
data_out_shift_reg[5]               DFFCE     D        In      -         7.493       -         
===============================================================================================
Total path delay (propagation time + setup) of 7.554 is 4.210(55.7%) logic and 3.344(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.421
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.360

    - Propagation time:                      7.493
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.133

    Number of logic level(s):                7
    Starting point:                          internal_register_select[3] / Q
    Ending point:                            data_out_shift_reg[7] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_register_select[3]         DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[3]         Net       -        -       0.535     -           4         
data_from_internal_reg78_13_3_0     LUT2      I1       In      -         0.778       -         
data_from_internal_reg78_13_3_0     LUT2      F        Out     0.570     1.348       -         
data_from_internal_reg78_13_3_0     Net       -        -       0.535     -           3         
data_from_internal_reg77_0_a2_1     LUT4      I0       In      -         1.883       -         
data_from_internal_reg77_0_a2_1     LUT4      F        Out     0.549     2.432       -         
N_132                               Net       -        -       0.535     -           8         
data_from_internal_reg97_0_a4       LUT4      I0       In      -         2.967       -         
data_from_internal_reg97_0_a4       LUT4      F        Out     0.549     3.516       -         
data_from_internal_reg97            Net       -        -       0.535     -           9         
data_from_ao_reg_2_RNO[7]           LUT2      I1       In      -         4.051       -         
data_from_ao_reg_2_RNO[7]           LUT2      F        Out     0.570     4.621       -         
capture_mem_addr_rem_m[7]           Net       -        -       0.401     -           1         
data_from_ao_reg_2[7]               LUT4      I1       In      -         5.022       -         
data_from_ao_reg_2[7]               LUT4      F        Out     0.570     5.592       -         
data_from_ao_reg_2[7]               Net       -        -       0.401     -           1         
data_out_shift_reg_4_0[7]           LUT4      I0       In      -         5.993       -         
data_out_shift_reg_4_0[7]           LUT4      F        Out     0.549     6.542       -         
N_409                               Net       -        -       0.401     -           1         
data_out_shift_reg_4[7]             LUT3      I0       In      -         6.944       -         
data_out_shift_reg_4[7]             LUT3      F        Out     0.549     7.493       -         
data_out_shift_reg_4[7]             Net       -        -       0.000     -           1         
data_out_shift_reg[7]               DFFCE     D        In      -         7.493       -         
===============================================================================================
Total path delay (propagation time + setup) of 7.554 is 4.210(55.7%) logic and 3.344(44.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.421
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.360

    - Propagation time:                      7.488
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.128

    Number of logic level(s):                7
    Starting point:                          internal_register_select[13] / Q
    Ending point:                            data_out_shift_reg[5] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                     Pin      Pin               Arrival     No. of    
Name                                     Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------
internal_register_select[13]             DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[13]             Net       -        -       0.535     -           1         
internal_register_select_RNII1H4[12]     LUT4      I1       In      -         0.778       -         
internal_register_select_RNII1H4[12]     LUT4      F        Out     0.570     1.348       -         
match_unit_rd_en_9[0]                    Net       -        -       0.535     -           4         
data_from_internal_reg77_14              LUT2      I1       In      -         1.883       -         
data_from_internal_reg77_14              LUT2      F        Out     0.570     2.453       -         
internal_reg_start_m_14                  Net       -        -       0.596     -           11        
data_from_internal_reg97_0_a4            LUT4      I2       In      -         3.049       -         
data_from_internal_reg97_0_a4            LUT4      F        Out     0.462     3.511       -         
data_from_internal_reg97                 Net       -        -       0.535     -           9         
data_from_ao_reg_2_RNO[5]                LUT2      I1       In      -         4.046       -         
data_from_ao_reg_2_RNO[5]                LUT2      F        Out     0.570     4.616       -         
capture_mem_addr_rem_m[5]                Net       -        -       0.401     -           1         
data_from_ao_reg_2[5]                    LUT4      I1       In      -         5.017       -         
data_from_ao_reg_2[5]                    LUT4      F        Out     0.570     5.587       -         
data_from_ao_reg_2[5]                    Net       -        -       0.401     -           1         
data_out_shift_reg_4_0[5]                LUT4      I0       In      -         5.988       -         
data_out_shift_reg_4_0[5]                LUT4      F        Out     0.549     6.537       -         
N_407                                    Net       -        -       0.401     -           1         
data_out_shift_reg_4[5]                  LUT3      I0       In      -         6.939       -         
data_out_shift_reg_4[5]                  LUT3      F        Out     0.549     7.488       -         
data_out_shift_reg_4[5]                  Net       -        -       0.000     -           1         
data_out_shift_reg[5]                    DFFCE     D        In      -         7.488       -         
====================================================================================================
Total path delay (propagation time + setup) of 7.549 is 4.144(54.9%) logic and 3.405(45.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.421
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.360

    - Propagation time:                      7.488
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.128

    Number of logic level(s):                7
    Starting point:                          internal_register_select[13] / Q
    Ending point:                            data_out_shift_reg[7] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                     Pin      Pin               Arrival     No. of    
Name                                     Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------
internal_register_select[13]             DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[13]             Net       -        -       0.535     -           1         
internal_register_select_RNII1H4[12]     LUT4      I1       In      -         0.778       -         
internal_register_select_RNII1H4[12]     LUT4      F        Out     0.570     1.348       -         
match_unit_rd_en_9[0]                    Net       -        -       0.535     -           4         
data_from_internal_reg77_14              LUT2      I1       In      -         1.883       -         
data_from_internal_reg77_14              LUT2      F        Out     0.570     2.453       -         
internal_reg_start_m_14                  Net       -        -       0.596     -           11        
data_from_internal_reg97_0_a4            LUT4      I2       In      -         3.049       -         
data_from_internal_reg97_0_a4            LUT4      F        Out     0.462     3.511       -         
data_from_internal_reg97                 Net       -        -       0.535     -           9         
data_from_ao_reg_2_RNO[7]                LUT2      I1       In      -         4.046       -         
data_from_ao_reg_2_RNO[7]                LUT2      F        Out     0.570     4.616       -         
capture_mem_addr_rem_m[7]                Net       -        -       0.401     -           1         
data_from_ao_reg_2[7]                    LUT4      I1       In      -         5.017       -         
data_from_ao_reg_2[7]                    LUT4      F        Out     0.570     5.587       -         
data_from_ao_reg_2[7]                    Net       -        -       0.401     -           1         
data_out_shift_reg_4_0[7]                LUT4      I0       In      -         5.988       -         
data_out_shift_reg_4_0[7]                LUT4      F        Out     0.549     6.537       -         
N_409                                    Net       -        -       0.401     -           1         
data_out_shift_reg_4[7]                  LUT3      I0       In      -         6.939       -         
data_out_shift_reg_4[7]                  LUT3      F        Out     0.549     7.488       -         
data_out_shift_reg_4[7]                  Net       -        -       0.000     -           1         
data_out_shift_reg[7]                    DFFCE     D        In      -         7.488       -         
====================================================================================================
Total path delay (propagation time + setup) of 7.549 is 4.144(54.9%) logic and 3.405(45.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.421
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.360

    - Propagation time:                      7.472
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.112

    Number of logic level(s):                7
    Starting point:                          internal_register_select[2] / Q
    Ending point:                            data_out_shift_reg[5] / D
    The start point is clocked by            ao_top_0|control[0] [rising] on pin CLK
    The end   point is clocked by            ao_top_0|control[0] [rising] on pin CLK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                                Type      Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
internal_register_select[2]         DFFCE     Q        Out     0.243     0.243       -         
internal_register_select[2]         Net       -        -       0.535     -           4         
data_from_internal_reg78_13_3_0     LUT2      I0       In      -         0.778       -         
data_from_internal_reg78_13_3_0     LUT2      F        Out     0.549     1.327       -         
data_from_internal_reg78_13_3_0     Net       -        -       0.535     -           3         
data_from_internal_reg77_0_a2_1     LUT4      I0       In      -         1.862       -         
data_from_internal_reg77_0_a2_1     LUT4      F        Out     0.549     2.411       -         
N_132                               Net       -        -       0.535     -           8         
data_from_internal_reg97_0_a4       LUT4      I0       In      -         2.946       -         
data_from_internal_reg97_0_a4       LUT4      F        Out     0.549     3.495       -         
data_from_internal_reg97            Net       -        -       0.535     -           9         
data_from_ao_reg_2_RNO[5]           LUT2      I1       In      -         4.030       -         
data_from_ao_reg_2_RNO[5]           LUT2      F        Out     0.570     4.600       -         
capture_mem_addr_rem_m[5]           Net       -        -       0.401     -           1         
data_from_ao_reg_2[5]               LUT4      I1       In      -         5.001       -         
data_from_ao_reg_2[5]               LUT4      F        Out     0.570     5.571       -         
data_from_ao_reg_2[5]               Net       -        -       0.401     -           1         
data_out_shift_reg_4_0[5]           LUT4      I0       In      -         5.972       -         
data_out_shift_reg_4_0[5]           LUT4      F        Out     0.549     6.521       -         
N_407                               Net       -        -       0.401     -           1         
data_out_shift_reg_4[5]             LUT3      I0       In      -         6.923       -         
data_out_shift_reg_4[5]             LUT3      F        Out     0.549     7.472       -         
data_out_shift_reg_4[5]             Net       -        -       0.000     -           1         
data_out_shift_reg[5]               DFFCE     D        In      -         7.472       -         
===============================================================================================
Total path delay (propagation time + setup) of 7.533 is 4.189(55.6%) logic and 3.344(44.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                           Arrival          
Instance                                 Reference     Type     Pin     Net                 Time        Slack
                                         Clock                                                               
-------------------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     System        INV      O       capture_end         0.000       2.432
address_counter_cry_0_RNO[0]             System        INV      O       address_counter     0.000       4.505
=============================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                                        Required          
Instance                      Reference     Type      Pin     Net                             Time         Slack
                              Clock                                                                             
----------------------------------------------------------------------------------------------------------------
capture_window_sel[2]         System        DFFC      D       capture_window_sel_3[2]         4.513        2.432
capture_window_sel[3]         System        DFFC      D       capture_window_sel_3[3]         4.513        2.432
capture_window_sel[1]         System        DFFC      D       capture_window_sel_3[1]         4.513        2.657
capture_window_sel[0]         System        DFFC      D       capture_window_sel_3[0]         4.513        3.429
internal_reg_start_dly[0]     System        DFFC      D       internal_reg_start_dly_2[0]     4.513        3.429
capture_end_dly               System        DFFP      D       capture_end                     4.513        3.978
address_counter[9]            System        DFFCE     D       address_counter_s[9]            6.360        4.505
address_counter[8]            System        DFFCE     D       address_counter_s[8]            6.360        4.540
address_counter[7]            System        DFFCE     D       address_counter_s[7]            6.360        4.575
address_counter[6]            System        DFFCE     D       address_counter_s[6]            6.360        4.610
================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.574
    - Setup time:                            0.061
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.513

    - Propagation time:                      2.081
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 2.432

    Number of logic level(s):                2
    Starting point:                          u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O
    Ending point:                            capture_window_sel[2] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            ao_top_0|clk_i [rising] on pin CLK

Instance / Net                                    Pin      Pin               Arrival     No. of    
Name                                     Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------
u_ao_mem_ctrl.capture_mem_wr_RNIQKR6     INV      O        Out     0.000     0.000       -         
capture_end                              Net      -        -       0.535     -           6         
un1_capture_window_sel_ac0_1             LUT4     I0       In      -         0.535       -         
un1_capture_window_sel_ac0_1             LUT4     F        Out     0.549     1.084       -         
un1_capture_window_sel_c2                Net      -        -       0.535     -           2         
capture_window_sel_3[2]                  LUT3     I2       In      -         1.619       -         
capture_window_sel_3[2]                  LUT3     F        Out     0.462     2.081       -         
capture_window_sel_3[2]                  Net      -        -       0.000     -           1         
capture_window_sel[2]                    DFFC     D        In      -         2.081       -         
===================================================================================================
Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 219MB peak: 221MB)


Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 219MB peak: 221MB)

---------------------------------------
Resource Usage Report for ao_top_0 

Mapping to part: gw2a_18pbga256-8
Cell usage:
ALU             64 uses
DFF             8 uses
DFFC            48 uses
DFFCE           197 uses
DFFNP           2 uses
DFFP            5 uses
DFFPE           32 uses
GSR             1 use
INV             2 uses
MUX2_LUT5       10 uses
MUX2_LUT6       4 uses
SDPX9           1 use
LUT2            61 uses
LUT3            101 uses
LUT4            245 uses

I/O ports: 27
I/O primitives: 27
IBUF           25 uses
OBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   292 of 15552 (1%)

RAM/ROM usage summary
Block Rams : 1 of 46 (2%)

Total load per clock:
   ao_top_0|clk_i: 1
   ao_top_0|control[0]: 243

@S |Mapping Summary:
Total  LUTs: 407 (1%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 43MB peak: 221MB)

Process took 0h:00m:07s realtime, 0h:00m:06s cputime
# Tue Dec 11 10:06:36 2018

###########################################################]