Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\TENGETHERNETMAC\data\xgmac_wrapper.v
D:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\TENGETHERNETMAC\data\xgmac.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version B
Created Time Thu Jan 4 10:17:08 2024
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Ten_Giga_Ethernet_MAC_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.616s, Peak memory usage = 76.812MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 76.812MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 76.812MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 76.812MB
    Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 76.812MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 76.812MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 76.812MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 76.812MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 76.812MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 76.812MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 76.812MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 76.812MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.218s, Peak memory usage = 86.965MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 86.965MB
Generate output files:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.243s, Peak memory usage = 95.363MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 95.363MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 357
I/O Buf 357
    IBUF 164
    OBUF 193
Register 1947
    DFFPE 66
    DFFCE 1881
LUT 4879
    LUT2 851
    LUT3 1126
    LUT4 2902
ALU 14
    ALU 14
INV 5
    INV 5

Resource Utilization Summary

Resource Usage Utilization
Logic 4898(4884 LUT, 14 ALU) / 138240 4%
Register 1947 / 139140 2%
  --Register as Latch 0 / 139140 0%
  --Register as FF 1947 / 139140 2%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
xgmii_rx_clk_i Base 10.000 100.0 0.000 5.000 xgmii_rx_clk_i_ibuf/I
xgtx_clk_i Base 10.000 100.0 0.000 5.000 xgtx_clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 xgmii_rx_clk_i 100.0(MHz) 243.3(MHz) 7 TOP
2 xgtx_clk_i 100.0(MHz) 174.5(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.268
Data Arrival Time 6.433
Data Required Time 10.701
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_4_s1
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
0.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/CLK
1.058 0.306 tC2Q RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/Q
1.223 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/I0
1.686 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/F
1.851 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/I0
2.314 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/F
2.479 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/I0
2.942 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/F
3.107 0.165 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/I1
3.587 0.480 tINS RF 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/COUT
3.587 0.000 tNET FF 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/CIN
3.627 0.040 tINS FR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/COUT
3.627 0.000 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/CIN
3.822 0.195 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/SUM
3.987 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/I0
4.450 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/F
4.615 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s4/I1
5.069 0.454 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s4/F
5.234 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s1/I2
5.640 0.406 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s1/F
5.805 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s0/I0
6.268 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s0/F
6.433 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
10.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_4_s1/CLK
10.701 -0.051 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.890, 68.474%; route: 1.485, 26.140%; tC2Q: 0.306, 5.386%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 2

Path Summary:
Slack 4.316
Data Arrival Time 6.385
Data Required Time 10.701
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_5_s1
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
0.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/CLK
1.058 0.306 tC2Q RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/Q
1.223 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/I0
1.686 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/F
1.851 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/I0
2.314 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/F
2.479 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/I0
2.942 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/F
3.107 0.165 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/I1
3.587 0.480 tINS RF 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/COUT
3.587 0.000 tNET FF 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/CIN
3.627 0.040 tINS FR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/COUT
3.627 0.000 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/CIN
3.822 0.195 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/SUM
3.987 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/I0
4.450 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/F
4.615 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n104_s5/I2
5.021 0.406 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n104_s5/F
5.186 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n104_s1/I2
5.592 0.406 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n104_s1/F
5.757 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n104_s7/I0
6.220 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n104_s7/F
6.385 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_5_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
10.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_5_s1/CLK
10.701 -0.051 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.842, 68.205%; route: 1.485, 26.363%; tC2Q: 0.306, 5.432%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 3

Path Summary:
Slack 4.452
Data Arrival Time 6.249
Data Required Time 10.701
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_6_s1
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
0.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/CLK
1.058 0.306 tC2Q RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/Q
1.223 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/I0
1.686 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/F
1.851 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/I0
2.314 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/F
2.479 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/I0
2.942 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/F
3.107 0.165 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/I1
3.587 0.480 tINS RF 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/COUT
3.587 0.000 tNET FF 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/CIN
3.627 0.040 tINS FR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/COUT
3.627 0.000 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/CIN
3.822 0.195 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/SUM
3.987 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/I0
4.450 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/F
4.615 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s8/I3
4.846 0.231 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s8/F
5.011 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n103_s2/I1
5.465 0.454 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n103_s2/F
5.630 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n103_s0/I1
6.084 0.454 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n103_s0/F
6.249 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
10.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_6_s1/CLK
10.701 -0.051 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.706, 67.418%; route: 1.485, 27.015%; tC2Q: 0.306, 5.567%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 4

Path Summary:
Slack 4.452
Data Arrival Time 6.249
Data Required Time 10.701
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_7_s1
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
0.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/CLK
1.058 0.306 tC2Q RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/Q
1.223 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/I0
1.686 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/F
1.851 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/I0
2.314 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/F
2.479 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/I0
2.942 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/F
3.107 0.165 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/I1
3.587 0.480 tINS RF 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/COUT
3.587 0.000 tNET FF 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/CIN
3.627 0.040 tINS FR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/COUT
3.627 0.000 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/CIN
3.822 0.195 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/SUM
3.987 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/I0
4.450 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/F
4.615 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s8/I3
4.846 0.231 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s8/F
5.011 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s2/I1
5.465 0.454 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s2/F
5.630 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s0/I1
6.084 0.454 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s0/F
6.249 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
10.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_7_s1/CLK
10.701 -0.051 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.706, 67.418%; route: 1.485, 27.015%; tC2Q: 0.306, 5.567%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%

Path 5

Path Summary:
Slack 4.887
Data Arrival Time 5.814
Data Required Time 10.701
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_3_s1
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
0.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/CLK
1.058 0.306 tC2Q RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/dword_cnt_0_s3/Q
1.223 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/I0
1.686 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s2/F
1.851 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/I0
2.314 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/F
2.479 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/I0
2.942 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/F
3.107 0.165 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/I1
3.587 0.480 tINS RF 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/COUT
3.587 0.000 tNET FF 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/CIN
3.627 0.040 tINS FR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n53_s/COUT
3.627 0.000 tNET RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/CIN
3.822 0.195 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n52_s/SUM
3.987 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/I0
4.450 0.463 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/F
4.615 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s1/I2
5.021 0.406 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s1/F
5.186 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s6/I0
5.649 0.463 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s6/F
5.814 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.587 0.587 tINS RR 965 xgtx_clk_i_ibuf/O
10.752 0.165 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_3_s1/CLK
10.701 -0.051 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%
Arrival Data Path Delay: cell: 3.436, 67.878%; route: 1.320, 26.077%; tC2Q: 0.306, 6.045%
Required Clock Path Delay: cell: 0.587, 78.057%; route: 0.165, 21.943%