Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\work\2023\6_GW5AT-138K_XGMAC\code\Reference_Design\V1.0\Reference_Design\fpga_project\src\serdes\serdes.v E:\work\2023\6_GW5AT-138K_XGMAC\code\Reference_Design\V1.0\Reference_Design\fpga_project\src\serdes\ten_giga_serial_ethernet\ten_giga_serial_ethernet.v E:\work\2023\6_GW5AT-138K_XGMAC\code\Reference_Design\V1.0\Reference_Design\fpga_project\src\Ten_Giga_Ethernet_MAC\Ten_Giga_Ethernet_MAC.v E:\work\2023\6_GW5AT-138K_XGMAC\code\Reference_Design\V1.0\Reference_Design\fpga_project\src\top.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v D:\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v E:\work\2023\6_GW5AT-138K_XGMAC\code\Reference_Design\V1.0\Reference_Design\fpga_project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Thu Jan 4 17:40:18 2024 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 584.691MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.374s, Peak memory usage = 584.691MB Optimizing Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.26s, Peak memory usage = 584.691MB Optimizing Phase 2: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.488s, Peak memory usage = 584.691MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.231s, Peak memory usage = 584.691MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 584.691MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 584.691MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 584.691MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.319s, Peak memory usage = 584.691MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 584.691MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 584.691MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 584.691MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.335s, Peak memory usage = 584.691MB Generate output files: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.49s, Peak memory usage = 600.168MB |
| Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 600.168MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 30 |
| I/O Buf | 27 |
| IBUF | 5 |
| OBUF | 18 |
| TBUF | 4 |
| Register | 6947 |
| DFFSE | 71 |
| DFFRE | 233 |
| DFFPE | 720 |
| DFFCE | 5923 |
| LUT | 8740 |
| LUT2 | 1274 |
| LUT3 | 2703 |
| LUT4 | 4763 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 59 |
| ALU | 59 |
| INV | 172 |
| INV | 172 |
| BSRAM | 7 |
| SDPB | 3 |
| SDPX9B | 4 |
| Black Box | 2 |
| GW_JTAG | 1 |
| GTR12_QUAD | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 8979(8920 LUT, 59 ALU) / 138240 | 7% |
| Register | 6947 / 139140 | 5% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 6947 / 139140 | 5% |
| BSRAM | 7 / 340 | 3% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| gw_gao_inst_0/u_icon_top/n31_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw_gao_inst_0/u_icon_top/n31_s2/O | ||
| gw_gao_inst_0/u_la0_top/n15_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | gw_gao_inst_0/u_la0_top/n15_s2/O |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | gw_gao_inst_0/u_icon_top/n31_6 | 100.0(MHz) | 741.8(MHz) | 2 | TOP |
| 2 | gw_gao_inst_0/u_la0_top/n15_6 | 100.0(MHz) | 1915.7(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 8.652 |
| Data Arrival Time | 1.264 |
| Data Required Time | 9.916 |
| From | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1 |
| Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 0.000 | 0.000 | tCL | RR | 9 | gw_gao_inst_0/u_icon_top/n31_s2/O |
| 0.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK |
| 0.471 | 0.306 | tC2Q | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/Q |
| 0.636 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I0 |
| 1.099 | 0.463 | tINS | RR | 2 | gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F |
| 1.264 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 10.000 | 0.000 | tCL | RR | 9 | gw_gao_inst_0/u_icon_top/n31_s2/O |
| 10.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CLK |
| 9.916 | -0.249 | tSu | 1 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
| Arrival Data Path Delay: | cell: 0.463, 42.130%; route: 0.330, 30.027%; tC2Q: 0.306, 27.843% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Path 2
Path Summary:| Slack | 8.652 |
| Data Arrival Time | 1.264 |
| Data Required Time | 9.916 |
| From | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_start_s1 |
| Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 0.000 | 0.000 | tCL | RR | 9 | gw_gao_inst_0/u_icon_top/n31_s2/O |
| 0.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK |
| 0.471 | 0.306 | tC2Q | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/Q |
| 0.636 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I0 |
| 1.099 | 0.463 | tINS | RR | 2 | gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F |
| 1.264 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 10.000 | 0.000 | tCL | RR | 9 | gw_gao_inst_0/u_icon_top/n31_s2/O |
| 10.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK |
| 9.916 | -0.249 | tSu | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
| Arrival Data Path Delay: | cell: 0.463, 42.130%; route: 0.330, 30.027%; tC2Q: 0.306, 27.843% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Path 3
Path Summary:| Slack | 9.478 |
| Data Arrival Time | 0.636 |
| Data Required Time | 10.114 |
| From | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
| Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 0.000 | 0.000 | tCL | RR | 9 | gw_gao_inst_0/u_icon_top/n31_s2/O |
| 0.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK |
| 0.471 | 0.306 | tC2Q | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/Q |
| 0.636 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 10.000 | 0.000 | tCL | RR | 9 | gw_gao_inst_0/u_icon_top/n31_s2/O |
| 10.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK |
| 10.114 | -0.051 | tSu | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.165, 35.032%; tC2Q: 0.306, 64.968% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Path 4
Path Summary:| Slack | 9.478 |
| Data Arrival Time | 0.636 |
| Data Required Time | 10.114 |
| From | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
| Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 0.000 | 0.000 | tCL | RR | 9 | gw_gao_inst_0/u_icon_top/n31_s2/O |
| 0.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK |
| 0.471 | 0.306 | tC2Q | RR | 2 | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/Q |
| 0.636 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 10.000 | 0.000 | tCL | RR | 9 | gw_gao_inst_0/u_icon_top/n31_s2/O |
| 10.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK |
| 10.114 | -0.051 | tSu | 1 | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.165, 35.032%; tC2Q: 0.306, 64.968% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
Path 5
Path Summary:| Slack | 9.478 |
| Data Arrival Time | 0.636 |
| Data Required Time | 10.114 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0 |
| To | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| Launch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
| Latch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
| 0.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/O |
| 0.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/CLK |
| 0.471 | 0.306 | tC2Q | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/Q |
| 0.636 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
| 10.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/O |
| 10.165 | 0.165 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 10.114 | -0.051 | tSu | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.165, 35.032%; tC2Q: 0.306, 64.968% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.165, 100.000% |