Hierarchy Module Resource
MODULE NAME |
REG NUMBER |
ALU NUMBER |
LUT NUMBER |
DSP NUMBER |
BSRAM NUMBER |
SSRAM NUMBER |
top (E:/work/2023/6_GW5AT-138K_XGMAC/code/Reference_Design/V1.0/Reference_Design/fpga_project/src/top.v) |
22 |
- |
40 |
- |
- |
- |
    |--u_SerDes_Top
(E:/work/2023/6_GW5AT-138K_XGMAC/code/Reference_Design/V1.0/Reference_Design/fpga_project/src/top.v) |
- |
- |
- |
- |
- |
- |
        |--Ten_Giga_Serial_Ethernet_Top_inst
(E:/work/2023/6_GW5AT-138K_XGMAC/code/Reference_Design/V1.0/Reference_Design/fpga_project/src/serdes/serdes.v) |
4461 |
34 |
3621 |
- |
4 |
- |
    |--u_Ten_Giga_Ethernet_MAC_Top
(E:/work/2023/6_GW5AT-138K_XGMAC/code/Reference_Design/V1.0/Reference_Design/fpga_project/src/top.v) |
1883 |
14 |
4763 |
- |
- |
- |
    |--gw_gao_inst_0
(E:/work/2023/6_GW5AT-138K_XGMAC/code/Reference_Design/V1.0/Reference_Design/fpga_project/impl/gwsynthesis/RTL_GAO/gw_gao_top.v) |
581 |
11 |
496 |
- |
3 |
- |