Timing Messages

Report Title Timing Analysis Report
Design File E:\work\2023\6_GW5AT-138K_XGMAC\code\Reference_Design\V1.0\Reference_Design\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\work\2023\6_GW5AT-138K_XGMAC\code\Reference_Design\V1.0\Reference_Design\fpga_project\src\fpga_project.cst
Timing Constraint File E:\work\2023\6_GW5AT-138K_XGMAC\code\Reference_Design\V1.0\Reference_Design\fpga_project\src\fpga_project.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version B
Created Time Thu Jan 4 17:43:05 2024
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C C2/I1
Hold Delay Model Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed 15251
Numbers of Endpoints Analyzed 21325
Numbers of Falling Endpoints 10
Numbers of Setup Violated Endpoints 320
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
serdes_tx_clk Base 6.173 161.996 0.000 3.087 u_SerDes_Top/q1_lane1_fabric_tx_clk
serdes_rx_clk Base 6.173 161.996 0.000 3.087 u_SerDes_Top/q1_lane1_fabric_rx_clk
tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i
xgmii_clk Base 6.400 156.250 0.000 3.200 tx_mac_clk

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 serdes_tx_clk 161.996(MHz) 153.069(MHz) 4 TOP
2 serdes_rx_clk 161.996(MHz) 187.108(MHz) 5 TOP
3 tck_pad_i 20.000(MHz) 111.653(MHz) 5 TOP
4 xgmii_clk 156.250(MHz) 143.400(MHz) 5 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
serdes_tx_clk Setup -0.885 6
serdes_tx_clk Hold 0.000 0
serdes_rx_clk Setup 0.000 0
serdes_rx_clk Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0
xgmii_clk Setup -92.615 314
xgmii_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Setup Paths Table[1]:

Report Command:report_timing -setup -from_clock [get_clocks {serdes_rx_clk}] -to_clock [get_clocks {serdes_rx_clk}] -max_paths 50 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.828 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_44_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.022 5.315
2 0.842 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_0_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.013 5.293
3 0.853 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.010 5.278
4 0.892 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxc_tmp_2_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.040 5.270
5 0.895 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_9_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.002 5.229
6 0.936 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/dout_valid_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.000 5.186
7 0.939 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.052 5.235
8 0.958 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.005 5.169
9 0.972 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_17_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.040 4.912
10 0.972 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.040 4.912
11 0.972 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_49_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.040 4.912
12 0.972 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_63_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.040 4.912
13 0.976 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.054 4.894
14 0.976 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.054 4.894
15 0.979 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_16_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.033 4.912
16 0.979 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.033 4.912
17 0.979 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.033 4.912
18 0.979 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.033 4.912
19 0.981 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.040 5.101
20 0.982 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_29_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.033 5.107
21 0.984 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_4_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.046 4.894
22 0.984 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.046 4.894
23 1.003 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.005 5.124
24 1.040 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.032 5.114
25 1.057 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.023 5.088
26 1.063 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.054 5.005
27 1.063 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.054 5.005
28 1.070 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.005 5.047
29 1.070 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_52_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.005 5.047
30 1.077 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.010 5.054
31 1.085 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.004 5.041
32 1.163 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.033 4.926
33 1.182 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_0_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.054 4.688
34 1.182 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_31_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.054 4.688
35 1.189 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/I3_hit_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d3_2_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.044 4.889
36 1.189 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/I3_hit_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_d3_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.044 4.889
37 1.195 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.042 4.969
38 1.196 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_17_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.040 4.688
39 1.204 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.012 4.906
40 1.207 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_26_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.007 4.922
41 1.213 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/din_d1_41_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_29_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.002 4.907
42 1.223 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_23_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.005 4.904
43 1.234 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.000 4.888
44 1.240 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.059 4.941
45 1.240 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.059 4.941
46 1.251 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_34_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.042 4.913
47 1.252 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/din_d1_50_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_46_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 -0.015 4.885
48 1.265 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.023 4.636
49 1.265 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0/CE serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.023 4.636
50 1.266 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_3_s0/D serdes_rx_clk:[R] serdes_rx_clk:[R] 6.173 0.017 4.838

Setup Paths Table[2]:

Report Command:report_timing -setup -from_clock [get_clocks {serdes_tx_clk}] -to_clock [get_clocks {serdes_tx_clk}] -max_paths 50 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.360 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_39_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.006 6.488
2 -0.192 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_17_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.022 6.335
3 -0.184 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_47_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.006 6.312
4 -0.066 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.010 6.178
5 -0.046 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_57_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.009 6.177
6 -0.037 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_35_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.000 6.159
7 0.099 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_0_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.025 5.998
8 0.106 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_41_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.006 6.010
9 0.107 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_25_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.007 6.008
10 0.107 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_36_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.017 5.998
11 0.111 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_52_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.009 6.002
12 0.116 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_49_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.002 6.008
13 0.157 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_43_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.009 5.974
14 0.271 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.020 5.831
15 0.272 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_58_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.009 5.841
16 0.279 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.012 5.831
17 0.280 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_56_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.001 5.841
18 0.304 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_4_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.010 5.808
19 0.309 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_27_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.006 5.807
20 0.309 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.006 5.807
21 0.431 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_31_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.018 5.709
22 0.444 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_54_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.003 5.675
23 0.448 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_8_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.012 5.662
24 0.459 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_33_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.009 5.672
25 0.470 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_25_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.007 5.645
26 0.470 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_62_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.001 5.650
27 0.477 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.009 5.636
28 0.479 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.007 5.636
29 0.479 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_35_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.007 5.636
30 0.482 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.005 5.635
31 0.487 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.005 5.630
32 0.555 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.001 5.566
33 0.594 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_21_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.027 5.555
34 0.614 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.015 5.493
35 0.629 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_28_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.025 5.468
36 0.630 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_38_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.003 5.489
37 0.637 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.005 5.489
38 0.638 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_20_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.025 5.459
39 0.641 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_0_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.025 5.457
40 0.643 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_16_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.020 5.459
41 0.643 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_15_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 -0.033 5.511
42 0.645 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.010 5.466
43 0.648 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.025 5.455
44 0.650 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_30_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.010 5.461
45 0.653 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_40_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.012 5.457
46 0.664 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_22_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.009 5.455
47 0.674 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.017 5.431
48 0.674 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.017 5.431
49 0.676 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_12_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.020 5.426
50 0.682 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_6_s0/D serdes_tx_clk:[R] serdes_tx_clk:[R] 6.173 0.005 5.434

Setup Paths Table[3]:

Report Command:report_timing -setup -from_clock [get_clocks {xgmii_clk}] -to_clock [get_clocks {xgmii_clk}] -max_paths 50 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.573 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_10_s3/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_1_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.012 6.911
2 -0.571 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_58_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.004 6.921
3 -0.569 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_10_s3/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_23_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.025 6.893
4 -0.568 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.008 6.926
5 -0.566 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.016 6.931
6 -0.564 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_22_s3/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_5_s3/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.042 6.872
7 -0.564 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_17_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_1_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.020 6.893
8 -0.560 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_13_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_11_s1/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.000 6.909
9 -0.559 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/store_data_crc_12_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_error_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.020 6.888
10 -0.558 byte_cnt_9_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_2_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.018 6.890
11 -0.556 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_29_s3/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_10_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.020 6.925
12 -0.556 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_51_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.036 6.941
13 -0.555 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_31_s5/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result4_13_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.019 6.923
14 -0.554 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_19_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.031 6.674
15 -0.553 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_63_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.033 6.936
16 -0.553 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_1_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_25_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.011 6.913
17 -0.546 byte_cnt_9_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_31_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.030 6.866
18 -0.545 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_54_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_22_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.040 6.854
19 -0.542 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_32_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_12_s1/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.010 6.901
20 -0.539 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_35_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/remote_fault_pipe1_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.013 6.875
21 -0.534 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_25_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.033 6.916
22 -0.534 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_57_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.033 6.916
23 -0.534 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/last_valid_num_pipe3_0_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.032 6.915
24 -0.534 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_62_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.023 6.906
25 -0.533 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_54_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.023 6.906
26 -0.533 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_23_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.038 6.646
27 -0.532 c_tx_state_0_s5/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_6_s1/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.006 6.887
28 -0.530 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_35_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.021 6.900
29 -0.529 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_pipe2_25_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_23_s3/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.038 6.916
30 -0.528 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_30_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.021 6.898
31 -0.526 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_8_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.031 6.646
32 -0.526 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_24_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.031 6.646
33 -0.525 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_26_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.046 6.630
34 -0.525 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_24_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_20_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.020 6.854
35 -0.524 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_pipe2_0_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_14_s3/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.001 6.872
36 -0.521 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_25_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.013 6.659
37 -0.520 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_23_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_15_s1/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.017 6.887
38 -0.520 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_42_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.023 6.892
39 -0.519 c_tx_state_0_s5/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_7_s1/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.006 6.879
40 -0.511 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_61_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.021 6.881
41 -0.507 byte_cnt_9_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_30_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 0.034 6.827
42 -0.505 c_tx_state_0_s5/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_4_s1/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.008 6.862
43 -0.501 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_43_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.037 6.887
44 -0.495 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_10_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.045 6.601
45 -0.495 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_17_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.045 6.601
46 -0.495 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_6_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.045 6.601
47 -0.495 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_28_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 0.045 6.601
48 -0.495 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_59_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.019 6.863
49 -0.493 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe2_s1/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_8_s0/CE xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.042 6.686
50 -0.493 u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_31_s0/Q u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_16_s0/D xgmii_clk:[R] xgmii_clk:[R] 6.400 -0.026 6.868

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.023 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_20_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[20] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.001 0.237
2 0.023 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_19_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[19] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.001 0.237
3 0.051 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.021 0.245
4 0.113 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_34_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[34] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.010 0.318
5 0.113 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[2] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.010 0.318
6 0.119 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_22_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[22] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.001 0.333
7 0.119 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_54_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/DI[18] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.001 0.333
8 0.119 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_52_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/DI[16] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.001 0.333
9 0.122 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_61_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[29] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.017 0.320
10 0.123 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[5] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.005 0.333
11 0.123 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_4_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/DI[32] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.005 0.333
12 0.123 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[35] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.005 0.333
13 0.124 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_38_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/DI[2] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.006 0.333
14 0.127 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_25_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[25] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.009 0.333
15 0.129 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.011 0.333
16 0.129 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.011 0.333
17 0.130 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[5] serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.006 0.339
18 0.135 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.015 0.335
19 0.135 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.015 0.335
20 0.135 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[21] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.015 0.335
21 0.135 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[20] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.015 0.335
22 0.135 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.015 0.335
23 0.137 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[19] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.017 0.335
24 0.139 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[9] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.018 0.335
25 0.142 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_25_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[25] xgmii_clk:[R] xgmii_clk:[R] 0.000 0.009 0.348

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.147 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.264 3.333
2 -0.140 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.271 3.333
3 -0.140 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.271 3.333
4 -0.140 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.271 3.333
5 -0.140 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.271 3.333
6 -0.140 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.271 3.333
7 -0.134 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.256 3.312
8 0.027 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.256 3.151
9 0.027 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.256 3.151
10 0.034 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.243 3.131
11 0.034 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.243 3.131
12 0.035 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.264 3.151
13 0.035 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.264 3.151
14 0.035 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.264 3.151
15 0.040 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/gt_flag_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.249 3.131
16 0.040 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/lt_flag_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.249 3.131
17 0.040 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/ge_flag_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.249 3.131
18 0.040 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/le_flag_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.249 3.131
19 0.220 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.254 2.956
20 0.228 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.262 2.956
21 0.267 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.264 2.919
22 0.267 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.264 2.919
23 0.267 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.264 2.919
24 0.548 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.262 2.636
25 0.548 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR xgmii_clk:[F] xgmii_clk:[R] 3.200 -0.262 2.636

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.467 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/RESET serdes_tx_clk:[R] serdes_tx_clk:[R] 0.000 0.022 0.455
2 0.487 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_14_s0/CLEAR serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 0.000 0.336
3 0.489 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_0_s0/PRESET xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.346
4 0.489 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_0_s0/PRESET xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.346
5 0.489 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_12_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.346
6 0.489 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_0_s0/PRESET xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.346
7 0.489 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_12_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.346
8 0.489 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0/PRESET xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.346
9 0.489 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_12_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.346
10 0.491 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_CL_s56/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.348
11 0.491 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_13_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.348
12 0.491 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_46_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.008 0.348
13 0.493 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_9_s0/CLEAR serdes_rx_clk:[R] serdes_rx_clk:[R] 0.000 -0.001 0.343
14 0.493 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/sync_header_tmp_0_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.346
15 0.493 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/idle_char_d2_5_s0/PRESET xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.346
16 0.493 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_46_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.346
17 0.493 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_46_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.346
18 0.493 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_45_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.346
19 0.495 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_11_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.348
20 0.495 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_15_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.348
21 0.495 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_19_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.348
22 0.495 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_21_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.348
23 0.495 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_44_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.348
24 0.495 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_52_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.348
25 0.495 u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_62_s0/CLEAR xgmii_clk:[R] xgmii_clk:[R] 0.000 -0.004 0.348

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 1.277 2.139 0.862 Low Pulse Width xgmii_clk u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s
2 1.277 2.139 0.862 Low Pulse Width xgmii_clk u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s
3 1.277 2.139 0.862 Low Pulse Width xgmii_clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
4 1.281 2.143 0.862 Low Pulse Width xgmii_clk u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s
5 1.281 2.143 0.862 Low Pulse Width xgmii_clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
6 1.281 2.143 0.862 Low Pulse Width xgmii_clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
7 1.281 2.143 0.862 Low Pulse Width xgmii_clk u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s
8 1.290 2.152 0.862 High Pulse Width xgmii_clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
9 1.290 2.152 0.862 High Pulse Width xgmii_clk u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s
10 1.290 2.152 0.862 High Pulse Width xgmii_clk u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s

Timing Report By Analysis Type:

Setup Analysis Report

Setup Analysis Report[1]:

Report Command:report_timing -setup -from_clock [get_clocks {serdes_rx_clk}] -to_clock [get_clocks {serdes_rx_clk}] -max_paths 50 -max_common_paths 1

Path1

Path Summary:

Slack 0.828
Data Arrival Time 6.887
Data Required Time 7.715
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_44_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.572 1.572 tNET RR 1 R47C96[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0/CLK
1.878 0.306 tC2Q RR 31 R47C96[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0/Q
3.014 1.136 tNET RR 1 R45C102[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3106_s11/I2
3.473 0.459 tINS RR 11 R45C102[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3106_s11/F
4.960 1.487 tNET RR 1 R40C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s13/I0
5.366 0.406 tINS RR 5 R40C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s13/F
5.660 0.294 tNET RR 1 R38C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3130_s11/I2
6.119 0.459 tINS RR 1 R38C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3130_s11/F
6.424 0.305 tNET RR 1 R40C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3130_s10/I2
6.887 0.463 tINS RR 1 R40C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3130_s10/F
6.887 0.000 tNET RR 1 R40C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_44_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.766 1.594 tNET RR 1 R40C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_44_s0/CLK
7.715 -0.051 tSu 1 R40C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_44_s0

Path Statistics:

Clock Skew 0.022
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.572, 100.000%
Arrival Data Path Delay cell: 1.787, 33.622%; route: 3.222, 60.621%; tC2Q: 0.306, 5.757%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.594, 100.000%

Path2

Path Summary:

Slack 0.842
Data Arrival Time 6.881
Data Required Time 7.723
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_0_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.587 1.587 tNET RR 1 R43C95[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_0_s0/CLK
1.893 0.306 tC2Q RR 10 R43C95[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_0_s0/Q
3.309 1.415 tNET RR 1 R40C97[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3110_s13/I2
3.674 0.365 tINS RR 10 R40C97[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3110_s13/F
4.851 1.177 tNET RR 1 R34C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s15/I0
5.310 0.459 tINS RR 1 R34C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s15/F
5.448 0.138 tNET RR 1 R35C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s14/I3
5.902 0.454 tINS RR 1 R35C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s14/F
6.650 0.748 tNET RR 1 R40C100[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s13/I1
6.881 0.231 tINS RR 1 R40C100[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s13/F
6.881 0.000 tNET RR 1 R40C100[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.774 1.601 tNET RR 1 R40C100[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0/CLK
7.723 -0.051 tSu 1 R40C100[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0

Path Statistics:

Clock Skew 0.013
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.587, 100.000%
Arrival Data Path Delay cell: 1.509, 28.509%; route: 3.478, 65.709%; tC2Q: 0.306, 5.781%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.601, 100.000%

Path3

Path Summary:

Slack 0.853
Data Arrival Time 6.866
Data Required Time 7.719
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.588 1.588 tNET RR 1 R39C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK
1.882 0.294 tC2Q RF 16 R39C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q
2.502 0.620 tNET FF 1 R41C99[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0
2.961 0.459 tINS FR 11 R41C99[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F
3.303 0.342 tNET RR 1 R45C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2
3.766 0.463 tINS RR 14 R45C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F
4.077 0.311 tNET RR 1 R45C96[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/I2
4.531 0.454 tINS RR 4 R45C96[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/F
4.706 0.175 tNET RR 1 R45C98[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/I3
5.144 0.438 tINS RR 16 R45C98[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/F
6.412 1.268 tNET RR 1 R38C99[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s10/I0
6.866 0.454 tINS RR 1 R38C99[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s10/F
6.866 0.000 tNET RR 1 R38C99[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.770 1.597 tNET RR 1 R38C99[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0/CLK
7.719 -0.051 tSu 1 R38C99[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0

Path Statistics:

Clock Skew 0.010
Setup Relationship 6.173
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.588, 100.000%
Arrival Data Path Delay cell: 2.268, 42.971%; route: 2.716, 51.459%; tC2Q: 0.294, 5.570%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%

Path4

Path Summary:

Slack 0.892
Data Arrival Time 6.814
Data Required Time 7.706
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxc_tmp_2_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.544 1.544 tNET RR 1 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/CLK
1.850 0.306 tC2Q RR 10 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q
3.061 1.211 tNET RR 1 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/I0
3.515 0.454 tINS RR 2 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/F
3.519 0.004 tNET RR 1 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/I0
3.978 0.459 tINS RR 4 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/F
5.058 1.080 tNET RR 1 R45C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3109_s11/I3
5.496 0.438 tINS RR 3 R45C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3109_s11/F
6.351 0.855 tNET RR 1 R41C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3108_s8/I0
6.814 0.463 tINS RR 1 R41C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3108_s8/F
6.814 0.000 tNET RR 1 R41C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxc_tmp_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.757 1.584 tNET RR 1 R41C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxc_tmp_2_s0/CLK
7.706 -0.051 tSu 1 R41C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxc_tmp_2_s0

Path Statistics:

Clock Skew 0.040
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%
Arrival Data Path Delay cell: 1.814, 34.421%; route: 3.150, 59.772%; tC2Q: 0.306, 5.806%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.584, 100.000%

Path5

Path Summary:

Slack 0.895
Data Arrival Time 6.817
Data Required Time 7.711
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_9_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.588 1.588 tNET RR 1 R39C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK
1.894 0.306 tC2Q RR 16 R39C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q
3.270 1.376 tNET RR 1 R45C100[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3164_s16/I1
3.733 0.463 tINS RR 9 R45C100[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3164_s16/F
4.879 1.146 tNET RR 1 R39C101[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3165_s13/I0
5.342 0.463 tINS RR 1 R39C101[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3165_s13/F
5.480 0.138 tNET RR 1 R38C101[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3165_s11/I1
5.934 0.454 tINS RR 1 R38C101[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3165_s11/F
6.363 0.429 tNET RR 1 R42C101[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3165_s9/I3
6.817 0.454 tINS RR 1 R42C101[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3165_s9/F
6.817 0.000 tNET RR 1 R42C101[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.762 1.590 tNET RR 1 R42C101[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_9_s0/CLK
7.711 -0.051 tSu 1 R42C101[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_9_s0

Path Statistics:

Clock Skew 0.002
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.588, 100.000%
Arrival Data Path Delay cell: 1.834, 35.074%; route: 3.089, 59.074%; tC2Q: 0.306, 5.852%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.590, 100.000%

Path6

Path Summary:

Slack 0.936
Data Arrival Time 6.775
Data Required Time 7.711
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/dout_valid_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.590 1.590 tNET RR 1 R24C115[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_1_s0/CLK
1.884 0.294 tC2Q RF 84 R24C115[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_1_s0/Q
3.170 1.286 tNET FF 1 R23C108[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/I0
3.576 0.406 tINS FR 1614 R23C108[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/F
6.775 3.200 tNET RR 1 R26C108[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/dout_valid_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.762 1.589 tNET RR 1 R26C108[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/dout_valid_s0/CLK
7.711 -0.051 tSu 1 R26C108[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/dout_valid_s0

Path Statistics:

Clock Skew -0.000
Setup Relationship 6.173
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.590, 100.000%
Arrival Data Path Delay cell: 0.406, 7.829%; route: 4.486, 86.501%; tC2Q: 0.294, 5.669%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.589, 100.000%

Path7

Path Summary:

Slack 0.939
Data Arrival Time 6.779
Data Required Time 7.717
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.544 1.544 tNET RR 1 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/CLK
1.850 0.306 tC2Q RR 10 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q
3.061 1.211 tNET RR 1 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/I0
3.515 0.454 tINS RR 2 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/F
3.519 0.004 tNET RR 1 R47C99[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s15/I3
3.978 0.459 tINS RR 5 R47C99[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s15/F
4.755 0.777 tNET RR 1 R42C100[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3141_s11/I2
5.214 0.459 tINS RR 7 R42C100[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3141_s11/F
5.917 0.703 tNET RR 1 R39C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3117_s10/I3
6.371 0.454 tINS RR 1 R39C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3117_s10/F
6.373 0.002 tNET RR 1 R39C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3117_s9/I2
6.779 0.406 tINS RR 1 R39C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3117_s9/F
6.779 0.000 tNET RR 1 R39C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.768 1.596 tNET RR 1 R39C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0/CLK
7.717 -0.051 tSu 1 R39C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0

Path Statistics:

Clock Skew 0.052
Setup Relationship 6.173
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%
Arrival Data Path Delay cell: 2.232, 42.636%; route: 2.697, 51.519%; tC2Q: 0.306, 5.845%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.596, 100.000%

Path8

Path Summary:

Slack 0.958
Data Arrival Time 6.751
Data Required Time 7.709
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.582 1.582 tNET RR 1 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK
1.888 0.306 tC2Q RR 54 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q
3.454 1.566 tNET RR 1 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/I1
3.860 0.406 tINS RR 19 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/F
4.722 0.862 tNET RR 1 R40C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/I2
5.185 0.463 tINS RR 5 R40C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/F
5.514 0.329 tNET RR 1 R42C100[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3120_s11/I3
5.977 0.463 tINS RR 1 R42C100[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3120_s11/F
6.313 0.336 tNET RR 1 R43C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3120_s10/I2
6.751 0.438 tINS RR 1 R43C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3120_s10/F
6.751 0.000 tNET RR 1 R43C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.760 1.587 tNET RR 1 R43C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0/CLK
7.709 -0.051 tSu 1 R43C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.582, 100.000%
Arrival Data Path Delay cell: 1.770, 34.243%; route: 3.093, 59.837%; tC2Q: 0.306, 5.920%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.587, 100.000%

Path9

Path Summary:

Slack 0.972
Data Arrival Time 6.509
Data Required Time 7.481
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_17_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.509 1.079 tNET RR 1 R47C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_17_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.730 1.557 tNET RR 1 R47C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_17_s0/CLK
7.481 -0.249 tSu 1 R47C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_17_s0

Path Statistics:

Clock Skew -0.040
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.392%; route: 3.457, 70.379%; tC2Q: 0.306, 6.230%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%

Path10

Path Summary:

Slack 0.972
Data Arrival Time 6.509
Data Required Time 7.481
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.509 1.079 tNET RR 1 R47C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.730 1.557 tNET RR 1 R47C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/CLK
7.481 -0.249 tSu 1 R47C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0

Path Statistics:

Clock Skew -0.040
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.392%; route: 3.457, 70.379%; tC2Q: 0.306, 6.230%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%

Path11

Path Summary:

Slack 0.972
Data Arrival Time 6.509
Data Required Time 7.481
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_49_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.509 1.079 tNET RR 1 R47C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_49_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.730 1.557 tNET RR 1 R47C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_49_s0/CLK
7.481 -0.249 tSu 1 R47C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_49_s0

Path Statistics:

Clock Skew -0.040
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.392%; route: 3.457, 70.379%; tC2Q: 0.306, 6.230%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%

Path12

Path Summary:

Slack 0.972
Data Arrival Time 6.509
Data Required Time 7.481
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_63_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.509 1.079 tNET RR 1 R47C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_63_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.730 1.557 tNET RR 1 R47C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_63_s0/CLK
7.481 -0.249 tSu 1 R47C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_63_s0

Path Statistics:

Clock Skew -0.040
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.392%; route: 3.457, 70.379%; tC2Q: 0.306, 6.230%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%

Path13

Path Summary:

Slack 0.976
Data Arrival Time 6.491
Data Required Time 7.468
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.491 1.061 tNET RR 1 R48C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R48C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0/CLK
7.468 -0.249 tSu 1 R48C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0

Path Statistics:

Clock Skew -0.054
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.478%; route: 3.439, 70.270%; tC2Q: 0.306, 6.253%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path14

Path Summary:

Slack 0.976
Data Arrival Time 6.491
Data Required Time 7.468
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.491 1.061 tNET RR 1 R48C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R48C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0/CLK
7.468 -0.249 tSu 1 R48C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0

Path Statistics:

Clock Skew -0.054
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.478%; route: 3.439, 70.270%; tC2Q: 0.306, 6.253%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path15

Path Summary:

Slack 0.979
Data Arrival Time 6.509
Data Required Time 7.488
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_16_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.509 1.079 tNET RR 1 R47C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_16_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.737 1.564 tNET RR 1 R47C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_16_s0/CLK
7.488 -0.249 tSu 1 R47C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_16_s0

Path Statistics:

Clock Skew -0.033
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.392%; route: 3.457, 70.379%; tC2Q: 0.306, 6.230%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Path16

Path Summary:

Slack 0.979
Data Arrival Time 6.509
Data Required Time 7.488
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.509 1.079 tNET RR 1 R47C113[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.737 1.564 tNET RR 1 R47C113[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0/CLK
7.488 -0.249 tSu 1 R47C113[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0

Path Statistics:

Clock Skew -0.033
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.392%; route: 3.457, 70.379%; tC2Q: 0.306, 6.230%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Path17

Path Summary:

Slack 0.979
Data Arrival Time 6.509
Data Required Time 7.488
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.509 1.079 tNET RR 1 R47C113[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.737 1.564 tNET RR 1 R47C113[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0/CLK
7.488 -0.249 tSu 1 R47C113[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0

Path Statistics:

Clock Skew -0.033
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.392%; route: 3.457, 70.379%; tC2Q: 0.306, 6.230%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Path18

Path Summary:

Slack 0.979
Data Arrival Time 6.509
Data Required Time 7.488
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.509 1.079 tNET RR 1 R47C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.737 1.564 tNET RR 1 R47C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0/CLK
7.488 -0.249 tSu 1 R47C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0

Path Statistics:

Clock Skew -0.033
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.392%; route: 3.457, 70.379%; tC2Q: 0.306, 6.230%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Path19

Path Summary:

Slack 0.981
Data Arrival Time 6.698
Data Required Time 7.679
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
4.686 0.572 tNET RR 1 R45C111[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1
5.145 0.459 tINS RR 36 R45C111[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F
6.292 1.147 tNET RR 1 R47C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1626_s1/I2
6.698 0.406 tINS RR 1 R47C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1626_s1/F
6.698 0.000 tNET RR 1 R47C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.730 1.557 tNET RR 1 R47C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/CLK
7.679 -0.051 tSu 1 R47C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0

Path Statistics:

Clock Skew -0.040
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.783, 34.954%; route: 3.012, 59.047%; tC2Q: 0.306, 5.999%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%

Path20

Path Summary:

Slack 0.982
Data Arrival Time 6.704
Data Required Time 7.686
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_29_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
4.686 0.572 tNET RR 1 R45C111[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/I2
5.145 0.459 tINS RR 36 R45C111[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/F
6.241 1.096 tNET RR 1 R47C115[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1629_s1/I2
6.704 0.463 tINS RR 1 R47C115[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1629_s1/F
6.704 0.000 tNET RR 1 R47C115[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_29_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.737 1.564 tNET RR 1 R47C115[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_29_s0/CLK
7.686 -0.051 tSu 1 R47C115[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_29_s0

Path Statistics:

Clock Skew -0.033
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.840, 36.029%; route: 2.961, 57.979%; tC2Q: 0.306, 5.992%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Path21

Path Summary:

Slack 0.984
Data Arrival Time 6.491
Data Required Time 7.475
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_4_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.491 1.061 tNET RR 1 R48C113[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.724 1.551 tNET RR 1 R48C113[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_4_s0/CLK
7.475 -0.249 tSu 1 R48C113[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_4_s0

Path Statistics:

Clock Skew -0.046
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.478%; route: 3.439, 70.270%; tC2Q: 0.306, 6.253%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.551, 100.000%

Path22

Path Summary:

Slack 0.984
Data Arrival Time 6.491
Data Required Time 7.475
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.491 1.061 tNET RR 1 R48C113[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.724 1.551 tNET RR 1 R48C113[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0/CLK
7.475 -0.249 tSu 1 R48C113[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0

Path Statistics:

Clock Skew -0.046
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 23.478%; route: 3.439, 70.270%; tC2Q: 0.306, 6.253%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.551, 100.000%

Path23

Path Summary:

Slack 1.003
Data Arrival Time 6.706
Data Required Time 7.709
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.582 1.582 tNET RR 1 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK
1.888 0.306 tC2Q RR 54 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q
3.454 1.566 tNET RR 1 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/I1
3.860 0.406 tINS RR 19 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/F
5.222 1.362 tNET RR 1 R42C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1541_s5/I2
5.628 0.406 tINS RR 1 R42C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1541_s5/F
5.933 0.305 tNET RR 1 R43C103[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1541_s3/I3
6.298 0.365 tINS RR 1 R43C103[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1541_s3/F
6.300 0.002 tNET RR 1 R43C103[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1541_s2/I0
6.706 0.406 tINS RR 1 R43C103[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1541_s2/F
6.706 0.000 tNET RR 1 R43C103[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.760 1.587 tNET RR 1 R43C103[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/CLK
7.709 -0.051 tSu 1 R43C103[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.582, 100.000%
Arrival Data Path Delay cell: 1.583, 30.894%; route: 3.235, 63.134%; tC2Q: 0.306, 5.972%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.587, 100.000%

Path24

Path Summary:

Slack 1.040
Data Arrival Time 6.658
Data Required Time 7.698
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.544 1.544 tNET RR 1 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/CLK
1.850 0.306 tC2Q RR 10 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q
3.061 1.211 tNET RR 1 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/I0
3.515 0.454 tINS RR 2 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/F
3.519 0.004 tNET RR 1 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/I0
3.978 0.459 tINS RR 4 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/F
5.058 1.080 tNET RR 1 R45C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/I0
5.289 0.231 tINS RR 16 R45C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/F
6.204 0.915 tNET RR 1 R35C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3163_s10/I0
6.658 0.454 tINS RR 1 R35C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3163_s10/F
6.658 0.000 tNET RR 1 R35C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.749 1.576 tNET RR 1 R35C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0/CLK
7.698 -0.051 tSu 1 R35C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0

Path Statistics:

Clock Skew 0.032
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%
Arrival Data Path Delay cell: 1.598, 31.248%; route: 3.210, 62.769%; tC2Q: 0.306, 5.984%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.576, 100.000%

Path25

Path Summary:

Slack 1.057
Data Arrival Time 6.660
Data Required Time 7.717
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.572 1.572 tNET RR 1 R47C96[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0/CLK
1.878 0.306 tC2Q RR 31 R47C96[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0/Q
3.382 1.504 tNET RR 1 R38C97[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s13/I1
3.820 0.438 tINS RR 12 R38C97[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s13/F
4.696 0.876 tNET RR 1 R43C99[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s13/I2
5.102 0.406 tINS RR 5 R43C99[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s13/F
5.442 0.340 tNET RR 1 R41C97[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3161_s12/I3
5.901 0.459 tINS RR 1 R41C97[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3161_s12/F
6.206 0.305 tNET RR 1 R43C96[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3161_s10/I2
6.660 0.454 tINS RR 1 R43C96[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3161_s10/F
6.660 0.000 tNET RR 1 R43C96[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.768 1.595 tNET RR 1 R43C96[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0/CLK
7.717 -0.051 tSu 1 R43C96[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0

Path Statistics:

Clock Skew 0.023
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.572, 100.000%
Arrival Data Path Delay cell: 1.757, 34.532%; route: 3.025, 59.454%; tC2Q: 0.306, 6.014%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.595, 100.000%

Path26

Path Summary:

Slack 1.063
Data Arrival Time 6.602
Data Required Time 7.666
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
4.686 0.572 tNET RR 1 R45C111[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/I2
5.145 0.459 tINS RR 36 R45C111[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/F
6.196 1.051 tNET RR 1 R48C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1658_s1/I2
6.602 0.406 tINS RR 1 R48C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1658_s1/F
6.602 0.000 tNET RR 1 R48C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R48C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0/CLK
7.666 -0.051 tSu 1 R48C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_0_s0

Path Statistics:

Clock Skew -0.054
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.783, 35.624%; route: 2.916, 58.262%; tC2Q: 0.306, 6.114%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path27

Path Summary:

Slack 1.063
Data Arrival Time 6.602
Data Required Time 7.666
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
4.686 0.572 tNET RR 1 R45C111[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/I2
5.145 0.459 tINS RR 36 R45C111[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/F
6.196 1.051 tNET RR 1 R48C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1627_s1/I2
6.602 0.406 tINS RR 1 R48C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1627_s1/F
6.602 0.000 tNET RR 1 R48C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R48C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0/CLK
7.666 -0.051 tSu 1 R48C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0

Path Statistics:

Clock Skew -0.054
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.783, 35.624%; route: 2.916, 58.262%; tC2Q: 0.306, 6.114%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path28

Path Summary:

Slack 1.070
Data Arrival Time 6.629
Data Required Time 7.699
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.582 1.582 tNET RR 1 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK
1.888 0.306 tC2Q RR 54 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q
3.454 1.566 tNET RR 1 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/I1
3.860 0.406 tINS RR 19 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/F
4.722 0.862 tNET RR 1 R40C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/I2
5.185 0.463 tINS RR 5 R40C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/F
5.942 0.757 tNET RR 1 R36C100[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3123_s11/I3
6.173 0.231 tINS RR 1 R36C100[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3123_s11/F
6.175 0.002 tNET RR 1 R36C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3123_s10/I2
6.629 0.454 tINS RR 1 R36C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3123_s10/F
6.629 0.000 tNET RR 1 R36C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.750 1.577 tNET RR 1 R36C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0/CLK
7.699 -0.051 tSu 1 R36C100[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0

Path Statistics:

Clock Skew -0.005
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.582, 100.000%
Arrival Data Path Delay cell: 1.554, 30.791%; route: 3.187, 63.146%; tC2Q: 0.306, 6.063%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.577, 100.000%

Path29

Path Summary:

Slack 1.070
Data Arrival Time 6.629
Data Required Time 7.699
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_52_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.582 1.582 tNET RR 1 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK
1.888 0.306 tC2Q RR 54 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q
3.454 1.566 tNET RR 1 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/I1
3.860 0.406 tINS RR 19 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/F
4.722 0.862 tNET RR 1 R40C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/I2
5.185 0.463 tINS RR 5 R40C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/F
5.942 0.757 tNET RR 1 R36C100[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3122_s11/I3
6.173 0.231 tINS RR 1 R36C100[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3122_s11/F
6.175 0.002 tNET RR 1 R36C100[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3122_s10/I2
6.629 0.454 tINS RR 1 R36C100[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3122_s10/F
6.629 0.000 tNET RR 1 R36C100[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_52_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.750 1.577 tNET RR 1 R36C100[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_52_s0/CLK
7.699 -0.051 tSu 1 R36C100[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_52_s0

Path Statistics:

Clock Skew -0.005
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.582, 100.000%
Arrival Data Path Delay cell: 1.554, 30.791%; route: 3.187, 63.146%; tC2Q: 0.306, 6.063%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.577, 100.000%

Path30

Path Summary:

Slack 1.077
Data Arrival Time 6.642
Data Required Time 7.719
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.588 1.588 tNET RR 1 R39C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK
1.882 0.294 tC2Q RF 16 R39C102[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q
2.502 0.620 tNET FF 1 R41C99[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0
2.961 0.459 tINS FR 11 R41C99[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F
3.303 0.342 tNET RR 1 R45C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2
3.766 0.463 tINS RR 14 R45C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F
4.077 0.311 tNET RR 1 R45C96[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/I2
4.531 0.454 tINS RR 4 R45C96[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/F
4.706 0.175 tNET RR 1 R45C98[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/I3
5.144 0.438 tINS RR 16 R45C98[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/F
6.236 1.092 tNET RR 1 R38C99[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3131_s10/I0
6.642 0.406 tINS RR 1 R38C99[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3131_s10/F
6.642 0.000 tNET RR 1 R38C99[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.770 1.597 tNET RR 1 R38C99[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0/CLK
7.719 -0.051 tSu 1 R38C99[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0

Path Statistics:

Clock Skew 0.010
Setup Relationship 6.173
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.588, 100.000%
Arrival Data Path Delay cell: 2.220, 43.926%; route: 2.540, 50.257%; tC2Q: 0.294, 5.817%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%

Path31

Path Summary:

Slack 1.085
Data Arrival Time 6.613
Data Required Time 7.698
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.572 1.572 tNET RR 1 R47C96[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0/CLK
1.878 0.306 tC2Q RR 31 R47C96[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d5_2_s0/Q
3.382 1.504 tNET RR 1 R38C97[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s13/I1
3.820 0.438 tINS RR 12 R38C97[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s13/F
4.696 0.876 tNET RR 1 R43C99[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s13/I2
5.102 0.406 tINS RR 5 R43C99[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s13/F
5.783 0.681 tNET RR 1 R35C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3160_s12/I3
6.148 0.365 tINS RR 1 R35C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3160_s12/F
6.150 0.002 tNET RR 1 R35C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3160_s10/I2
6.613 0.463 tINS RR 1 R35C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3160_s10/F
6.613 0.000 tNET RR 1 R35C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.749 1.576 tNET RR 1 R35C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0/CLK
7.698 -0.051 tSu 1 R35C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0

Path Statistics:

Clock Skew 0.004
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.572, 100.000%
Arrival Data Path Delay cell: 1.672, 33.168%; route: 3.063, 60.762%; tC2Q: 0.306, 6.070%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.576, 100.000%

Path32

Path Summary:

Slack 1.163
Data Arrival Time 6.523
Data Required Time 7.686
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
4.686 0.572 tNET RR 1 R45C111[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1
5.145 0.459 tINS RR 36 R45C111[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F
6.292 1.147 tNET RR 1 R47C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1610_s1/I2
6.523 0.231 tINS RR 1 R47C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1610_s1/F
6.523 0.000 tNET RR 1 R47C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.737 1.564 tNET RR 1 R47C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0/CLK
7.686 -0.051 tSu 1 R47C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_48_s0

Path Statistics:

Clock Skew -0.033
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.608, 32.643%; route: 3.012, 61.145%; tC2Q: 0.306, 6.212%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Path33

Path Summary:

Slack 1.182
Data Arrival Time 6.285
Data Required Time 7.468
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_0_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
4.958 0.844 tNET RR 1 R45C111[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_d4_extra_3_s3/I2
5.189 0.231 tINS RR 36 R45C111[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_d4_extra_3_s3/F
6.285 1.096 tNET RR 1 R48C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R48C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_0_s0/CLK
7.468 -0.249 tSu 1 R48C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_0_s0

Path Statistics:

Clock Skew -0.054
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 24.509%; route: 3.233, 68.963%; tC2Q: 0.306, 6.527%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path34

Path Summary:

Slack 1.182
Data Arrival Time 6.285
Data Required Time 7.468
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_31_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
4.958 0.844 tNET RR 1 R45C111[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_d4_extra_3_s3/I2
5.189 0.231 tINS RR 36 R45C111[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_d4_extra_3_s3/F
6.285 1.096 tNET RR 1 R48C114[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_31_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R48C114[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_31_s0/CLK
7.468 -0.249 tSu 1 R48C114[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_31_s0

Path Statistics:

Clock Skew -0.054
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 24.509%; route: 3.233, 68.963%; tC2Q: 0.306, 6.527%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path35

Path Summary:

Slack 1.189
Data Arrival Time 6.490
Data Required Time 7.679
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/I3_hit_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d3_2_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.601 1.601 tNET RR 1 R40C96[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/I3_hit_d2_s0/CLK
1.907 0.306 tC2Q RR 4 R40C96[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/I3_hit_d2_s0/Q
2.778 0.871 tNET RR 1 R36C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n4205_s4/I0
3.184 0.406 tINS RR 5 R36C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n4205_s4/F
3.937 0.753 tNET RR 1 R42C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1453_s12/I3
4.400 0.463 tINS RR 3 R42C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1453_s12/F
4.874 0.474 tNET RR 1 R44C98[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1452_s5/I1
5.333 0.459 tINS RR 3 R44C98[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1452_s5/F
6.027 0.694 tNET RR 1 R47C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1451_s1/I0
6.490 0.463 tINS RR 1 R47C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1451_s1/F
6.490 0.000 tNET RR 1 R47C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d3_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.730 1.557 tNET RR 1 R47C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d3_2_s0/CLK
7.679 -0.051 tSu 1 R47C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_location_d3_2_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.601, 100.000%
Arrival Data Path Delay cell: 1.791, 36.633%; route: 2.792, 57.108%; tC2Q: 0.306, 6.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%

Path36

Path Summary:

Slack 1.189
Data Arrival Time 6.490
Data Required Time 7.679
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/I3_hit_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_d3_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.601 1.601 tNET RR 1 R40C96[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/I3_hit_d2_s0/CLK
1.907 0.306 tC2Q RR 4 R40C96[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/I3_hit_d2_s0/Q
2.778 0.871 tNET RR 1 R36C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n4205_s4/I0
3.184 0.406 tINS RR 5 R36C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n4205_s4/F
3.937 0.753 tNET RR 1 R42C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1453_s12/I3
4.400 0.463 tINS RR 3 R42C99[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1453_s12/F
4.874 0.474 tNET RR 1 R44C98[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1452_s5/I1
5.333 0.459 tINS RR 3 R44C98[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1452_s5/F
6.027 0.694 tNET RR 1 R47C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1450_s1/I0
6.490 0.463 tINS RR 1 R47C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n1450_s1/F
6.490 0.000 tNET RR 1 R47C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_d3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.730 1.557 tNET RR 1 R47C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_d3_s0/CLK
7.679 -0.051 tSu 1 R47C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/T_d3_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.601, 100.000%
Arrival Data Path Delay cell: 1.791, 36.633%; route: 2.792, 57.108%; tC2Q: 0.306, 6.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%

Path37

Path Summary:

Slack 1.195
Data Arrival Time 6.513
Data Required Time 7.708
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.544 1.544 tNET RR 1 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/CLK
1.850 0.306 tC2Q RR 10 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q
3.061 1.211 tNET RR 1 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/I0
3.515 0.454 tINS RR 2 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/F
3.519 0.004 tNET RR 1 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/I0
3.978 0.459 tINS RR 4 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/F
5.058 1.080 tNET RR 1 R45C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/I0
5.289 0.231 tINS RR 16 R45C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/F
6.059 0.770 tNET RR 1 R40C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3155_s10/I0
6.513 0.454 tINS RR 1 R40C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3155_s10/F
6.513 0.000 tNET RR 1 R40C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.759 1.586 tNET RR 1 R40C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0/CLK
7.708 -0.051 tSu 1 R40C98[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0

Path Statistics:

Clock Skew 0.042
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%
Arrival Data Path Delay cell: 1.598, 32.159%; route: 3.065, 61.682%; tC2Q: 0.306, 6.158%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.586, 100.000%

Path38

Path Summary:

Slack 1.196
Data Arrival Time 6.285
Data Required Time 7.481
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_17_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
4.958 0.844 tNET RR 1 R45C111[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_d4_extra_3_s3/I2
5.189 0.231 tINS RR 36 R45C111[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_d4_extra_3_s3/F
6.285 1.096 tNET RR 1 R47C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_17_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.730 1.557 tNET RR 1 R47C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_17_s0/CLK
7.481 -0.249 tSu 1 R47C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_d4_extra_17_s0

Path Statistics:

Clock Skew -0.040
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 24.509%; route: 3.233, 68.963%; tC2Q: 0.306, 6.527%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%

Path39

Path Summary:

Slack 1.204
Data Arrival Time 6.488
Data Required Time 7.692
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.582 1.582 tNET RR 1 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK
1.888 0.306 tC2Q RR 54 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q
3.454 1.566 tNET RR 1 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/I1
3.860 0.406 tINS RR 19 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/F
4.722 0.862 tNET RR 1 R40C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/I2
5.185 0.463 tINS RR 5 R40C101[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/F
5.801 0.616 tNET RR 1 R36C101[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s11/I3
6.032 0.231 tINS RR 1 R36C101[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s11/F
6.034 0.002 tNET RR 1 R36C101[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s10/I2
6.488 0.454 tINS RR 1 R36C101[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s10/F
6.488 0.000 tNET RR 1 R36C101[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.743 1.570 tNET RR 1 R36C101[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0/CLK
7.692 -0.051 tSu 1 R36C101[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.582, 100.000%
Arrival Data Path Delay cell: 1.554, 31.675%; route: 3.046, 62.087%; tC2Q: 0.306, 6.237%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.570, 100.000%

Path40

Path Summary:

Slack 1.207
Data Arrival Time 6.504
Data Required Time 7.711
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_26_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.582 1.582 tNET RR 1 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK
1.888 0.306 tC2Q RR 54 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q
3.454 1.566 tNET RR 1 R47C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s18/I1
3.860 0.406 tINS RR 7 R47C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s18/F
4.973 1.113 tNET RR 1 R45C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3173_s10/I3
5.427 0.454 tINS RR 7 R45C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3173_s10/F
6.050 0.623 tNET RR 1 R42C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3148_s9/I2
6.504 0.454 tINS RR 1 R42C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3148_s9/F
6.504 0.000 tNET RR 1 R42C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_26_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.762 1.590 tNET RR 1 R42C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_26_s0/CLK
7.711 -0.051 tSu 1 R42C101[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_26_s0

Path Statistics:

Clock Skew 0.007
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.582, 100.000%
Arrival Data Path Delay cell: 1.314, 26.696%; route: 3.302, 67.087%; tC2Q: 0.306, 6.217%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.590, 100.000%

Path41

Path Summary:

Slack 1.213
Data Arrival Time 6.498
Data Required Time 7.711
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/din_d1_41_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_29_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.591 1.591 tNET RR 1 R23C109[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/din_d1_41_s0/CLK
1.897 0.306 tC2Q RR 2 R23C109[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/din_d1_41_s0/Q
3.484 1.587 tNET RR 1 R26C106[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n972_s5/I1
3.849 0.365 tINS RR 2 R26C106[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n972_s5/F
4.599 0.750 tNET RR 1 R31C106[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n970_s3/I0
5.005 0.406 tINS RR 5 R31C106[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n970_s3/F
6.036 1.030 tNET RR 1 R24C103[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n540_s2/I1
6.498 0.463 tINS RR 1 R24C103[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n540_s2/F
6.498 0.000 tNET RR 1 R24C103[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_29_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.762 1.590 tNET RR 1 R24C103[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_29_s0/CLK
7.711 -0.051 tSu 1 R24C103[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_29_s0

Path Statistics:

Clock Skew -0.002
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.591, 100.000%
Arrival Data Path Delay cell: 1.234, 25.148%; route: 3.367, 68.616%; tC2Q: 0.306, 6.236%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.590, 100.000%

Path42

Path Summary:

Slack 1.223
Data Arrival Time 6.486
Data Required Time 7.709
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_23_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.582 1.582 tNET RR 1 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK
1.888 0.306 tC2Q RR 54 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q
3.454 1.566 tNET RR 1 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/I1
3.860 0.406 tINS RR 19 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/F
5.076 1.216 tNET RR 1 R42C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s12/I2
5.441 0.365 tINS RR 5 R42C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s12/F
6.032 0.591 tNET RR 1 R43C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s10/I3
6.486 0.454 tINS RR 1 R43C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s10/F
6.486 0.000 tNET RR 1 R43C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.760 1.587 tNET RR 1 R43C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_23_s0/CLK
7.709 -0.051 tSu 1 R43C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_23_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.582, 100.000%
Arrival Data Path Delay cell: 1.225, 24.980%; route: 3.373, 68.781%; tC2Q: 0.306, 6.240%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.587, 100.000%

Path43

Path Summary:

Slack 1.234
Data Arrival Time 6.470
Data Required Time 7.704
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.582 1.582 tNET RR 1 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK
1.888 0.306 tC2Q RR 54 R42C102[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q
3.454 1.566 tNET RR 1 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/I1
3.860 0.406 tINS RR 19 R47C97[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s14/F
5.076 1.216 tNET RR 1 R42C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s12/I2
5.441 0.365 tINS RR 5 R42C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s12/F
6.032 0.591 tNET RR 1 R44C97[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3154_s10/I3
6.470 0.438 tINS RR 1 R44C97[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3154_s10/F
6.470 0.000 tNET RR 1 R44C97[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.755 1.582 tNET RR 1 R44C97[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0/CLK
7.704 -0.051 tSu 1 R44C97[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0

Path Statistics:

Clock Skew -0.000
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.582, 100.000%
Arrival Data Path Delay cell: 1.209, 24.734%; route: 3.373, 69.006%; tC2Q: 0.306, 6.260%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.582, 100.000%

Path44

Path Summary:

Slack 1.240
Data Arrival Time 6.485
Data Required Time 7.725
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.544 1.544 tNET RR 1 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/CLK
1.850 0.306 tC2Q RR 10 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q
3.061 1.211 tNET RR 1 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/I0
3.515 0.454 tINS RR 2 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/F
3.519 0.004 tNET RR 1 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/I0
3.978 0.459 tINS RR 4 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/F
5.058 1.080 tNET RR 1 R45C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/I0
5.289 0.231 tINS RR 16 R45C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/F
6.254 0.965 tNET RR 1 R39C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3153_s10/I0
6.485 0.231 tINS RR 1 R39C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3153_s10/F
6.485 0.000 tNET RR 1 R39C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.776 1.603 tNET RR 1 R39C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0/CLK
7.725 -0.051 tSu 1 R39C100[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0

Path Statistics:

Clock Skew 0.059
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%
Arrival Data Path Delay cell: 1.375, 27.828%; route: 3.260, 65.979%; tC2Q: 0.306, 6.193%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.603, 100.000%

Path45

Path Summary:

Slack 1.240
Data Arrival Time 6.485
Data Required Time 7.725
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.544 1.544 tNET RR 1 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/CLK
1.850 0.306 tC2Q RR 10 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q
3.061 1.211 tNET RR 1 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/I0
3.515 0.454 tINS RR 2 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/F
3.519 0.004 tNET RR 1 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/I0
3.978 0.459 tINS RR 4 R47C99[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s19/F
5.058 1.080 tNET RR 1 R45C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/I0
5.289 0.231 tINS RR 16 R45C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/F
6.254 0.965 tNET RR 1 R39C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3152_s10/I0
6.485 0.231 tINS RR 1 R39C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3152_s10/F
6.485 0.000 tNET RR 1 R39C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.776 1.603 tNET RR 1 R39C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0/CLK
7.725 -0.051 tSu 1 R39C100[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0

Path Statistics:

Clock Skew 0.059
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%
Arrival Data Path Delay cell: 1.375, 27.828%; route: 3.260, 65.979%; tC2Q: 0.306, 6.193%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.603, 100.000%

Path46

Path Summary:

Slack 1.251
Data Arrival Time 6.457
Data Required Time 7.708
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_34_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.544 1.544 tNET RR 1 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/CLK
1.850 0.306 tC2Q RR 10 R48C98[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/CCCC_CCCC_hit_d5_s0/Q
3.061 1.211 tNET RR 1 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/I0
3.515 0.454 tINS RR 2 R47C99[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s17/F
3.519 0.004 tNET RR 1 R47C99[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s15/I3
3.978 0.459 tINS RR 5 R47C99[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3142_s15/F
4.755 0.777 tNET RR 1 R41C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3172_s13/I2
5.214 0.459 tINS RR 2 R41C100[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3172_s13/F
5.994 0.780 tNET RR 1 R40C102[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3140_s10/I2
6.457 0.463 tINS RR 1 R40C102[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3140_s10/F
6.457 0.000 tNET RR 1 R40C102[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_34_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.759 1.586 tNET RR 1 R40C102[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_34_s0/CLK
7.708 -0.051 tSu 1 R40C102[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_34_s0

Path Statistics:

Clock Skew 0.042
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%
Arrival Data Path Delay cell: 1.835, 37.350%; route: 2.772, 56.422%; tC2Q: 0.306, 6.228%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.586, 100.000%

Path47

Path Summary:

Slack 1.252
Data Arrival Time 6.459
Data Required Time 7.711
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/din_d1_50_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_46_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.574 1.574 tNET RR 1 R26C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/din_d1_50_s0/CLK
1.880 0.306 tC2Q RR 2 R26C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/din_d1_50_s0/Q
3.342 1.462 tNET RR 1 R29C105[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s6/I1
3.805 0.463 tINS RR 2 R29C105[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s6/F
4.112 0.307 tNET RR 1 R29C102[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n969_s4/I0
4.566 0.454 tINS RR 6 R29C102[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n969_s4/F
6.005 1.439 tNET RR 1 R24C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n523_s2/I0
6.459 0.454 tINS RR 1 R24C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n523_s2/F
6.459 0.000 tNET RR 1 R24C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_46_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.762 1.590 tNET RR 1 R24C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_46_s0/CLK
7.711 -0.051 tSu 1 R24C97[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_46_s0

Path Statistics:

Clock Skew 0.015
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.574, 100.000%
Arrival Data Path Delay cell: 1.371, 28.066%; route: 3.208, 65.670%; tC2Q: 0.306, 6.264%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.590, 100.000%

Path48

Path Summary:

Slack 1.265
Data Arrival Time 6.233
Data Required Time 7.498
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.233 0.803 tNET RR 1 R44C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.747 1.574 tNET RR 1 R44C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0/CLK
7.498 -0.249 tSu 1 R44C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 24.784%; route: 3.181, 68.615%; tC2Q: 0.306, 6.601%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.574, 100.000%

Path49

Path Summary:

Slack 1.265
Data Arrival Time 6.233
Data Required Time 7.498
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
5.199 1.085 tNET RR 1 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2
5.430 0.231 tINS RR 73 R45C111[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F
6.233 0.803 tNET RR 1 R44C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.747 1.574 tNET RR 1 R44C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0/CLK
7.498 -0.249 tSu 1 R44C114[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0

Path Statistics:

Clock Skew -0.023
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.149, 24.784%; route: 3.181, 68.615%; tC2Q: 0.306, 6.601%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.574, 100.000%

Path50

Path Summary:

Slack 1.266
Data Arrival Time 6.435
Data Required Time 7.702
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_3_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.597 1.597 tNET RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/CLK
1.903 0.306 tC2Q RR 1 R38C113[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/above_upper_threshold_s0/Q
2.902 0.999 tNET RR 1 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/I3
3.361 0.459 tINS RR 4 R41C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n967_s1/F
3.655 0.294 tNET RR 1 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I3
4.114 0.459 tINS RR 45 R41C113[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F
4.686 0.572 tNET RR 1 R45C111[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/I2
5.145 0.459 tINS RR 36 R45C111[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/F
5.981 0.836 tNET RR 1 R43C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s1/I2
6.435 0.454 tINS RR 1 R43C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s1/F
6.435 0.000 tNET RR 1 R43C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_rx_clk
6.173 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.753 1.580 tNET RR 1 R43C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_3_s0/CLK
7.702 -0.051 tSu 1 R43C114[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_3_s0

Path Statistics:

Clock Skew -0.017
Setup Relationship 6.173
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.597, 100.000%
Arrival Data Path Delay cell: 1.831, 37.846%; route: 2.701, 55.829%; tC2Q: 0.306, 6.325%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.580, 100.000%

Setup Analysis Report[2]:

Report Command:report_timing -setup -from_clock [get_clocks {serdes_tx_clk}] -to_clock [get_clocks {serdes_tx_clk}] -max_paths 50 -max_common_paths 1

Path1

Path Summary:

Slack -0.360
Data Arrival Time 8.057
Data Required Time 7.696
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_39_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
4.068 2.193 tNET RR 1 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/I2
4.432 0.365 tINS RR 2 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/F
5.036 0.604 tNET RR 1 R12C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s3/I0
5.496 0.459 tINS RR 8 R12C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s3/F
7.594 2.098 tNET RR 1 R16C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n805_s2/I0
8.057 0.463 tINS RR 1 R16C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n805_s2/F
8.057 0.000 tNET RR 1 R16C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_39_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.747 1.574 tNET RR 1 R16C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_39_s0/CLK
7.696 -0.051 tSu 1 R16C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_39_s0

Path Statistics:

Clock Skew 0.006
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 1.287, 19.837%; route: 4.895, 75.447%; tC2Q: 0.306, 4.716%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.574, 100.000%

Path2

Path Summary:

Slack -0.192
Data Arrival Time 7.904
Data Required Time 7.712
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_17_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
4.068 2.193 tNET RR 1 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/I2
4.432 0.365 tINS RR 2 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/F
5.036 0.604 tNET RR 1 R12C112[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n985_s3/I1
5.499 0.463 tINS RR 7 R12C112[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n985_s3/F
7.497 1.998 tNET RR 1 R20C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n433_s2/I1
7.904 0.406 tINS RR 1 R20C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n433_s2/F
7.904 0.000 tNET RR 1 R20C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.763 1.590 tNET RR 1 R20C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_17_s0/CLK
7.712 -0.051 tSu 1 R20C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_17_s0

Path Statistics:

Clock Skew 0.022
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 1.234, 19.479%; route: 4.795, 75.691%; tC2Q: 0.306, 4.830%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.590, 100.000%

Path3

Path Summary:

Slack -0.184
Data Arrival Time 7.881
Data Required Time 7.696
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_47_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
4.068 2.193 tNET RR 1 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/I2
4.432 0.365 tINS RR 2 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/F
5.036 0.604 tNET RR 1 R12C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s3/I0
5.496 0.459 tINS RR 8 R12C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s3/F
7.427 1.931 tNET RR 1 R16C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n797_s2/I1
7.881 0.454 tINS RR 1 R16C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n797_s2/F
7.881 0.000 tNET RR 1 R16C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_47_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.747 1.574 tNET RR 1 R16C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_47_s0/CLK
7.696 -0.051 tSu 1 R16C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_47_s0

Path Statistics:

Clock Skew 0.006
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 1.278, 20.247%; route: 4.728, 74.905%; tC2Q: 0.306, 4.848%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.574, 100.000%

Path4

Path Summary:

Slack -0.066
Data Arrival Time 7.746
Data Required Time 7.680
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
7.283 3.142 tNET RR 1 R15C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s5/I3
7.746 0.463 tINS RR 1 R15C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s5/F
7.746 0.000 tNET RR 1 R15C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.731 1.558 tNET RR 1 R15C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0/CLK
7.680 -0.051 tSu 1 R15C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.694, 11.233%; route: 5.178, 83.814%; tC2Q: 0.306, 4.953%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.558, 100.000%

Path5

Path Summary:

Slack -0.046
Data Arrival Time 7.745
Data Required Time 7.699
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_57_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
7.292 3.150 tNET RR 1 R18C113[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n787_s5/I3
7.746 0.454 tINS RR 1 R18C113[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n787_s5/F
7.746 0.000 tNET RR 1 R18C113[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_57_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.750 1.577 tNET RR 1 R18C113[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_57_s0/CLK
7.699 -0.051 tSu 1 R18C113[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_57_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.090%; route: 5.186, 83.957%; tC2Q: 0.306, 4.954%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.577, 100.000%

Path6

Path Summary:

Slack -0.037
Data Arrival Time 7.727
Data Required Time 7.690
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_35_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
3.897 2.022 tNET RR 1 R9C113[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/I2
4.129 0.233 tINS RR 2 R9C113[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/F
4.870 0.740 tNET RR 1 R13C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s3/I0
5.332 0.463 tINS RR 7 R13C113[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s3/F
7.321 1.989 tNET RR 1 R17C108[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n612_s2/I1
7.727 0.406 tINS RR 1 R17C108[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n612_s2/F
7.727 0.000 tNET RR 1 R17C108[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_35_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.741 1.568 tNET RR 1 R17C108[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_35_s0/CLK
7.690 -0.051 tSu 1 R17C108[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_35_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 1.102, 17.893%; route: 4.751, 77.139%; tC2Q: 0.306, 4.968%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%

Path7

Path Summary:

Slack 0.099
Data Arrival Time 7.567
Data Required Time 7.666
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_0_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
7.113 2.971 tNET RR 1 R12C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s3/I3
7.567 0.454 tINS RR 1 R12C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s3/F
7.567 0.000 tNET RR 1 R12C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R12C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_0_s0/CLK
7.666 -0.051 tSu 1 R12C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_0_s0

Path Statistics:

Clock Skew -0.025
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.420%; route: 5.007, 83.478%; tC2Q: 0.306, 5.102%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path8

Path Summary:

Slack 0.106
Data Arrival Time 7.579
Data Required Time 7.684
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_41_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
7.125 2.983 tNET RR 1 R18C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n803_s2/I3
7.579 0.454 tINS RR 1 R18C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n803_s2/F
7.579 0.000 tNET RR 1 R18C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_41_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.735 1.563 tNET RR 1 R18C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_41_s0/CLK
7.684 -0.051 tSu 1 R18C111[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_41_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.398%; route: 5.019, 83.511%; tC2Q: 0.306, 5.092%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.563, 100.000%

Path9

Path Summary:

Slack 0.107
Data Arrival Time 7.576
Data Required Time 7.683
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_25_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
4.068 2.193 tNET RR 1 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/I2
4.432 0.365 tINS RR 2 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/F
5.036 0.604 tNET RR 1 R12C112[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n985_s3/I1
5.499 0.463 tINS RR 7 R12C112[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n985_s3/F
7.113 1.614 tNET RR 1 R17C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n622_s2/I0
7.576 0.463 tINS RR 1 R17C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n622_s2/F
7.576 0.000 tNET RR 1 R17C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.734 1.561 tNET RR 1 R17C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_25_s0/CLK
7.683 -0.051 tSu 1 R17C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_25_s0

Path Statistics:

Clock Skew -0.007
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 1.291, 21.488%; route: 4.411, 73.419%; tC2Q: 0.306, 5.093%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.561, 100.000%

Path10

Path Summary:

Slack 0.107
Data Arrival Time 7.566
Data Required Time 7.673
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_36_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
7.113 2.971 tNET RR 1 R12C110[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n808_s2/I3
7.567 0.454 tINS RR 1 R12C110[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n808_s2/F
7.567 0.000 tNET RR 1 R12C110[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_36_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.724 1.551 tNET RR 1 R12C110[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_36_s0/CLK
7.673 -0.051 tSu 1 R12C110[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_36_s0

Path Statistics:

Clock Skew -0.017
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.420%; route: 5.007, 83.478%; tC2Q: 0.306, 5.102%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.551, 100.000%

Path11

Path Summary:

Slack 0.111
Data Arrival Time 7.570
Data Required Time 7.681
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_52_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
7.116 2.975 tNET RR 1 R16C115[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n792_s5/I3
7.570 0.454 tINS RR 1 R16C115[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n792_s5/F
7.570 0.000 tNET RR 1 R16C115[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_52_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.733 1.560 tNET RR 1 R16C115[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_52_s0/CLK
7.681 -0.051 tSu 1 R16C115[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_52_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.413%; route: 5.011, 83.489%; tC2Q: 0.306, 5.098%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.560, 100.000%

Path12

Path Summary:

Slack 0.116
Data Arrival Time 7.576
Data Required Time 7.692
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_49_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
7.122 2.981 tNET RR 1 R18C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n795_s5/I3
7.576 0.454 tINS RR 1 R18C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n795_s5/F
7.576 0.000 tNET RR 1 R18C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_49_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.743 1.570 tNET RR 1 R18C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_49_s0/CLK
7.692 -0.051 tSu 1 R18C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_49_s0

Path Statistics:

Clock Skew 0.002
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.401%; route: 5.017, 83.505%; tC2Q: 0.306, 5.093%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.570, 100.000%

Path13

Path Summary:

Slack 0.157
Data Arrival Time 7.542
Data Required Time 7.699
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_43_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
7.089 2.947 tNET RR 1 R18C109[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n801_s2/I3
7.543 0.454 tINS RR 1 R18C109[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n801_s2/F
7.543 0.000 tNET RR 1 R18C109[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_43_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.750 1.577 tNET RR 1 R18C109[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_43_s0/CLK
7.699 -0.051 tSu 1 R18C109[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_43_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.466%; route: 4.983, 83.411%; tC2Q: 0.306, 5.122%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.577, 100.000%

Path14

Path Summary:

Slack 0.271
Data Arrival Time 7.399
Data Required Time 7.670
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.945 2.804 tNET RR 1 R13C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n800_s2/I3
7.399 0.454 tINS RR 1 R13C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n800_s2/F
7.399 0.000 tNET RR 1 R13C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.721 1.548 tNET RR 1 R13C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0/CLK
7.670 -0.051 tSu 1 R13C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0

Path Statistics:

Clock Skew -0.020
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.748%; route: 4.840, 83.005%; tC2Q: 0.306, 5.248%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.548, 100.000%

Path15

Path Summary:

Slack 0.272
Data Arrival Time 7.409
Data Required Time 7.681
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_58_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.955 2.814 tNET RR 1 R16C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s5/I3
7.409 0.454 tINS RR 1 R16C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s5/F
7.409 0.000 tNET RR 1 R16C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_58_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.733 1.560 tNET RR 1 R16C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_58_s0/CLK
7.681 -0.051 tSu 1 R16C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_58_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.727%; route: 4.850, 83.034%; tC2Q: 0.306, 5.239%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.560, 100.000%

Path16

Path Summary:

Slack 0.279
Data Arrival Time 7.399
Data Required Time 7.678
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.945 2.804 tNET RR 1 R13C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n796_s5/I3
7.399 0.454 tINS RR 1 R13C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n796_s5/F
7.399 0.000 tNET RR 1 R13C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.729 1.556 tNET RR 1 R13C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0/CLK
7.678 -0.051 tSu 1 R13C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.748%; route: 4.840, 83.005%; tC2Q: 0.306, 5.248%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.556, 100.000%

Path17

Path Summary:

Slack 0.280
Data Arrival Time 7.409
Data Required Time 7.689
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_56_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.955 2.814 tNET RR 1 R16C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s5/I3
7.409 0.454 tINS RR 1 R16C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s5/F
7.409 0.000 tNET RR 1 R16C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_56_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.740 1.567 tNET RR 1 R16C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_56_s0/CLK
7.689 -0.051 tSu 1 R16C110[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_56_s0

Path Statistics:

Clock Skew -0.001
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.727%; route: 4.850, 83.034%; tC2Q: 0.306, 5.239%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.567, 100.000%

Path18

Path Summary:

Slack 0.304
Data Arrival Time 7.376
Data Required Time 7.681
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_4_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.913 2.772 tNET RR 1 R12C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n840_s2/I3
7.376 0.463 tINS RR 1 R12C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n840_s2/F
7.376 0.000 tNET RR 1 R12C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.732 1.559 tNET RR 1 R12C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_4_s0/CLK
7.681 -0.051 tSu 1 R12C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_4_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.694, 11.949%; route: 4.808, 82.782%; tC2Q: 0.306, 5.269%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.559, 100.000%

Path19

Path Summary:

Slack 0.309
Data Arrival Time 7.376
Data Required Time 7.684
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_27_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.922 2.780 tNET RR 1 R18C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n817_s2/I3
7.376 0.454 tINS RR 1 R18C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n817_s2/F
7.376 0.000 tNET RR 1 R18C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_27_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.735 1.563 tNET RR 1 R18C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_27_s0/CLK
7.684 -0.051 tSu 1 R18C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_27_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.796%; route: 4.816, 82.934%; tC2Q: 0.306, 5.270%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.563, 100.000%

Path20

Path Summary:

Slack 0.309
Data Arrival Time 7.376
Data Required Time 7.684
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.922 2.780 tNET RR 1 R18C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n815_s2/I3
7.376 0.454 tINS RR 1 R18C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n815_s2/F
7.376 0.000 tNET RR 1 R18C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.735 1.563 tNET RR 1 R18C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0/CLK
7.684 -0.051 tSu 1 R18C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 11.796%; route: 4.816, 82.934%; tC2Q: 0.306, 5.270%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.563, 100.000%

Path21

Path Summary:

Slack 0.431
Data Arrival Time 7.277
Data Required Time 7.708
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_31_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
4.068 2.193 tNET RR 1 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/I2
4.432 0.365 tINS RR 2 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/F
5.036 0.604 tNET RR 1 R12C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s3/I0
5.496 0.459 tINS RR 8 R12C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s3/F
6.814 1.319 tNET RR 1 R22C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n616_s2/I1
7.277 0.463 tINS RR 1 R22C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n616_s2/F
7.277 0.000 tNET RR 1 R22C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_31_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.759 1.586 tNET RR 1 R22C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_31_s0/CLK
7.708 -0.051 tSu 1 R22C111[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_31_s0

Path Statistics:

Clock Skew 0.018
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 1.287, 22.543%; route: 4.116, 72.097%; tC2Q: 0.306, 5.360%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.586, 100.000%

Path22

Path Summary:

Slack 0.444
Data Arrival Time 7.243
Data Required Time 7.688
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_54_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.780 2.639 tNET RR 1 R15C112[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n790_s5/I3
7.243 0.463 tINS RR 1 R15C112[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n790_s5/F
7.243 0.000 tNET RR 1 R15C112[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_54_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.739 1.566 tNET RR 1 R15C112[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_54_s0/CLK
7.688 -0.051 tSu 1 R15C112[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_54_s0

Path Statistics:

Clock Skew -0.003
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.694, 12.229%; route: 4.675, 82.379%; tC2Q: 0.306, 5.392%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.566, 100.000%

Path23

Path Summary:

Slack 0.448
Data Arrival Time 7.230
Data Required Time 7.678
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_8_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.776 2.635 tNET RR 1 R13C112[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n836_s2/I3
7.230 0.454 tINS RR 1 R13C112[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n836_s2/F
7.230 0.000 tNET RR 1 R13C112[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.729 1.556 tNET RR 1 R13C112[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_8_s0/CLK
7.678 -0.051 tSu 1 R13C112[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_8_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.098%; route: 4.671, 82.497%; tC2Q: 0.306, 5.404%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.556, 100.000%

Path24

Path Summary:

Slack 0.459
Data Arrival Time 7.240
Data Required Time 7.699
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_33_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
4.068 2.193 tNET RR 1 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/I2
4.432 0.365 tINS RR 2 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/F
5.036 0.604 tNET RR 1 R12C112[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n985_s3/I1
5.499 0.463 tINS RR 7 R12C112[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n985_s3/F
6.777 1.278 tNET RR 1 R18C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n614_s2/I1
7.240 0.463 tINS RR 1 R18C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n614_s2/F
7.240 0.000 tNET RR 1 R18C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_33_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.750 1.577 tNET RR 1 R18C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_33_s0/CLK
7.699 -0.051 tSu 1 R18C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_33_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 1.291, 22.761%; route: 4.075, 71.844%; tC2Q: 0.306, 5.395%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.577, 100.000%

Path25

Path Summary:

Slack 0.470
Data Arrival Time 7.213
Data Required Time 7.683
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_25_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.750 2.609 tNET RR 1 R17C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n819_s2/I3
7.213 0.463 tINS RR 1 R17C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n819_s2/F
7.213 0.000 tNET RR 1 R17C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.734 1.561 tNET RR 1 R17C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_25_s0/CLK
7.683 -0.051 tSu 1 R17C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_25_s0

Path Statistics:

Clock Skew -0.007
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.694, 12.294%; route: 4.645, 82.285%; tC2Q: 0.306, 5.421%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.561, 100.000%

Path26

Path Summary:

Slack 0.470
Data Arrival Time 7.219
Data Required Time 7.689
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_62_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.780 2.639 tNET RR 1 R16C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n782_s5/I3
7.219 0.438 tINS RR 1 R16C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n782_s5/F
7.219 0.000 tNET RR 1 R16C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_62_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.740 1.567 tNET RR 1 R16C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_62_s0/CLK
7.689 -0.051 tSu 1 R16C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_62_s0

Path Statistics:

Clock Skew -0.001
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.669, 11.841%; route: 4.675, 82.743%; tC2Q: 0.306, 5.416%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.567, 100.000%

Path27

Path Summary:

Slack 0.477
Data Arrival Time 7.204
Data Required Time 7.681
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.750 2.609 tNET RR 1 R16C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n822_s2/I3
7.204 0.454 tINS RR 1 R16C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n822_s2/F
7.204 0.000 tNET RR 1 R16C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.733 1.560 tNET RR 1 R16C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0/CLK
7.681 -0.051 tSu 1 R16C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.154%; route: 4.645, 82.417%; tC2Q: 0.306, 5.429%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.560, 100.000%

Path28

Path Summary:

Slack 0.479
Data Arrival Time 7.204
Data Required Time 7.683
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.750 2.609 tNET RR 1 R17C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n811_s2/I3
7.204 0.454 tINS RR 1 R17C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n811_s2/F
7.204 0.000 tNET RR 1 R17C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.734 1.561 tNET RR 1 R17C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0/CLK
7.683 -0.051 tSu 1 R17C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0

Path Statistics:

Clock Skew -0.007
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.154%; route: 4.645, 82.417%; tC2Q: 0.306, 5.429%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.561, 100.000%

Path29

Path Summary:

Slack 0.479
Data Arrival Time 7.204
Data Required Time 7.683
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_35_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.750 2.609 tNET RR 1 R17C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n809_s2/I3
7.204 0.454 tINS RR 1 R17C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n809_s2/F
7.204 0.000 tNET RR 1 R17C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_35_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.734 1.561 tNET RR 1 R17C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_35_s0/CLK
7.683 -0.051 tSu 1 R17C107[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_35_s0

Path Statistics:

Clock Skew -0.007
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.154%; route: 4.645, 82.417%; tC2Q: 0.306, 5.429%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.561, 100.000%

Path30

Path Summary:

Slack 0.482
Data Arrival Time 7.203
Data Required Time 7.685
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.745 2.603 tNET RR 1 R13C109[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n804_s2/I3
7.204 0.459 tINS RR 1 R13C109[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n804_s2/F
7.204 0.000 tNET RR 1 R13C109[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.736 1.564 tNET RR 1 R13C109[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0/CLK
7.685 -0.051 tSu 1 R13C109[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0

Path Statistics:

Clock Skew -0.005
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.690, 12.245%; route: 4.639, 82.325%; tC2Q: 0.306, 5.430%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Path31

Path Summary:

Slack 0.487
Data Arrival Time 7.198
Data Required Time 7.685
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.745 2.603 tNET RR 1 R13C109[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n838_s2/I3
7.199 0.454 tINS RR 1 R13C109[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n838_s2/F
7.199 0.000 tNET RR 1 R13C109[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.736 1.564 tNET RR 1 R13C109[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0/CLK
7.685 -0.051 tSu 1 R13C109[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0

Path Statistics:

Clock Skew -0.005
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.167%; route: 4.639, 82.398%; tC2Q: 0.306, 5.435%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Path32

Path Summary:

Slack 0.555
Data Arrival Time 7.134
Data Required Time 7.689
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
3.897 2.022 tNET RR 1 R9C113[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/I2
4.129 0.233 tINS RR 2 R9C113[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/F
4.988 0.859 tNET RR 1 R13C113[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/I1
5.219 0.231 tINS RR 7 R13C113[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/F
6.680 1.461 tNET RR 1 R16C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n610_s2/I1
7.134 0.454 tINS RR 1 R16C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n610_s2/F
7.134 0.000 tNET RR 1 R16C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.740 1.567 tNET RR 1 R16C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0/CLK
7.689 -0.051 tSu 1 R16C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0

Path Statistics:

Clock Skew -0.001
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.918, 16.493%; route: 4.342, 78.009%; tC2Q: 0.306, 5.498%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.567, 100.000%

Path33

Path Summary:

Slack 0.594
Data Arrival Time 7.123
Data Required Time 7.717
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_21_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
3.897 2.022 tNET RR 1 R9C113[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/I2
4.129 0.233 tINS RR 2 R9C113[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/F
4.988 0.859 tNET RR 1 R13C113[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/I1
5.219 0.231 tINS RR 7 R13C113[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/F
6.660 1.441 tNET RR 1 R21C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n429_s2/I1
7.123 0.463 tINS RR 1 R21C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n429_s2/F
7.123 0.000 tNET RR 1 R21C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.768 1.596 tNET RR 1 R21C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_21_s0/CLK
7.717 -0.051 tSu 1 R21C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_21_s0

Path Statistics:

Clock Skew 0.027
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.927, 16.688%; route: 4.322, 77.804%; tC2Q: 0.306, 5.509%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.596, 100.000%

Path34

Path Summary:

Slack 0.614
Data Arrival Time 7.061
Data Required Time 7.675
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.608 2.466 tNET RR 1 R14C111[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n794_s5/I3
7.062 0.454 tINS RR 1 R14C111[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n794_s5/F
7.062 0.000 tNET RR 1 R14C111[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.726 1.553 tNET RR 1 R14C111[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0/CLK
7.675 -0.051 tSu 1 R14C111[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0

Path Statistics:

Clock Skew -0.015
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.470%; route: 4.502, 81.959%; tC2Q: 0.306, 5.571%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path35

Path Summary:

Slack 0.629
Data Arrival Time 7.036
Data Required Time 7.666
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_28_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.573 2.432 tNET RR 1 R12C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n816_s2/I3
7.036 0.463 tINS RR 1 R12C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n816_s2/F
7.036 0.000 tNET RR 1 R12C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_28_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R12C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_28_s0/CLK
7.666 -0.051 tSu 1 R12C107[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_28_s0

Path Statistics:

Clock Skew -0.025
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.694, 12.692%; route: 4.468, 81.712%; tC2Q: 0.306, 5.596%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path36

Path Summary:

Slack 0.630
Data Arrival Time 7.057
Data Required Time 7.688
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_38_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.603 2.462 tNET RR 1 R15C110[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n806_s2/I3
7.057 0.454 tINS RR 1 R15C110[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n806_s2/F
7.057 0.000 tNET RR 1 R15C110[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_38_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.739 1.566 tNET RR 1 R15C110[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_38_s0/CLK
7.688 -0.051 tSu 1 R15C110[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_38_s0

Path Statistics:

Clock Skew -0.003
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.480%; route: 4.498, 81.946%; tC2Q: 0.306, 5.575%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.566, 100.000%

Path37

Path Summary:

Slack 0.637
Data Arrival Time 7.057
Data Required Time 7.695
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.603 2.462 tNET RR 1 R15C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n810_s2/I3
7.057 0.454 tINS RR 1 R15C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n810_s2/F
7.057 0.000 tNET RR 1 R15C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.746 1.573 tNET RR 1 R15C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0/CLK
7.695 -0.051 tSu 1 R15C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.480%; route: 4.498, 81.946%; tC2Q: 0.306, 5.575%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.573, 100.000%

Path38

Path Summary:

Slack 0.638
Data Arrival Time 7.027
Data Required Time 7.666
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_20_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.573 2.432 tNET RR 1 R12C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n824_s2/I3
7.027 0.454 tINS RR 1 R12C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n824_s2/F
7.027 0.000 tNET RR 1 R12C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R12C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_20_s0/CLK
7.666 -0.051 tSu 1 R12C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_20_s0

Path Statistics:

Clock Skew -0.025
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.548%; route: 4.468, 81.846%; tC2Q: 0.306, 5.605%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path39

Path Summary:

Slack 0.641
Data Arrival Time 7.025
Data Required Time 7.666
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_0_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/I1
4.143 0.233 tINS RR 64 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/F
6.794 2.650 tNET RR 1 R12C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s3/I3
7.025 0.231 tINS RR 1 R12C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s3/F
7.025 0.000 tNET RR 1 R12C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R12C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_0_s0/CLK
7.666 -0.051 tSu 1 R12C111[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_0_s0

Path Statistics:

Clock Skew -0.025
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.464, 8.504%; route: 4.686, 85.888%; tC2Q: 0.306, 5.608%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path40

Path Summary:

Slack 0.643
Data Arrival Time 7.027
Data Required Time 7.670
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_16_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.573 2.432 tNET RR 1 R13C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n828_s2/I3
7.027 0.454 tINS RR 1 R13C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n828_s2/F
7.027 0.000 tNET RR 1 R13C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.721 1.548 tNET RR 1 R13C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_16_s0/CLK
7.670 -0.051 tSu 1 R13C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_16_s0

Path Statistics:

Clock Skew -0.020
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.548%; route: 4.468, 81.846%; tC2Q: 0.306, 5.605%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.548, 100.000%

Path41

Path Summary:

Slack 0.643
Data Arrival Time 7.080
Data Required Time 7.723
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_15_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK
1.874 0.306 tC2Q RR 122 R17C116[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q
4.068 2.193 tNET RR 1 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/I2
4.432 0.365 tINS RR 2 R9C112[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s4/F
5.036 0.604 tNET RR 1 R12C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s3/I0
5.496 0.459 tINS RR 8 R12C112[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n987_s3/F
6.674 1.178 tNET RR 1 R22C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n435_s2/I1
7.080 0.406 tINS RR 1 R22C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n435_s2/F
7.080 0.000 tNET RR 1 R22C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.774 1.601 tNET RR 1 R22C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_15_s0/CLK
7.723 -0.051 tSu 1 R22C109[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_15_s0

Path Statistics:

Clock Skew 0.033
Setup Relationship 6.173
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 1.230, 22.319%; route: 3.975, 72.128%; tC2Q: 0.306, 5.553%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.601, 100.000%

Path42

Path Summary:

Slack 0.645
Data Arrival Time 7.035
Data Required Time 7.680
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.576 2.434 tNET RR 1 R15C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n812_s2/I3
7.035 0.459 tINS RR 1 R15C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n812_s2/F
7.035 0.000 tNET RR 1 R15C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.731 1.558 tNET RR 1 R15C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0/CLK
7.680 -0.051 tSu 1 R15C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.690, 12.623%; route: 4.470, 81.778%; tC2Q: 0.306, 5.598%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.558, 100.000%

Path43

Path Summary:

Slack 0.648
Data Arrival Time 7.023
Data Required Time 7.671
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/I1
4.143 0.233 tINS RR 64 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/F
6.768 2.625 tNET RR 1 R12C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n627_s2/I3
7.023 0.255 tINS RF 1 R12C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n627_s2/F
7.023 0.000 tNET FF 1 R12C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.717 1.544 tNET RR 1 R12C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0/CLK
7.671 -0.046 tSu 1 R12C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0

Path Statistics:

Clock Skew -0.025
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.488, 8.947%; route: 4.661, 85.443%; tC2Q: 0.306, 5.610%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.544, 100.000%

Path44

Path Summary:

Slack 0.650
Data Arrival Time 7.030
Data Required Time 7.680
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_30_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/I1
4.141 0.231 tINS RR 64 R21C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n844_s2/F
6.576 2.434 tNET RR 1 R15C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n814_s2/I3
7.030 0.454 tINS RR 1 R15C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n814_s2/F
7.030 0.000 tNET RR 1 R15C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_30_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.731 1.558 tNET RR 1 R15C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_30_s0/CLK
7.680 -0.051 tSu 1 R15C107[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_30_s0

Path Statistics:

Clock Skew -0.010
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.685, 12.543%; route: 4.470, 81.853%; tC2Q: 0.306, 5.603%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.558, 100.000%

Path45

Path Summary:

Slack 0.653
Data Arrival Time 7.025
Data Required Time 7.678
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_40_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/I1
4.143 0.233 tINS RR 64 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/F
6.794 2.650 tNET RR 1 R13C110[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n607_s2/I3
7.025 0.231 tINS RR 1 R13C110[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n607_s2/F
7.025 0.000 tNET RR 1 R13C110[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_40_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.729 1.556 tNET RR 1 R13C110[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_40_s0/CLK
7.678 -0.051 tSu 1 R13C110[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_40_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.464, 8.504%; route: 4.686, 85.888%; tC2Q: 0.306, 5.608%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.556, 100.000%

Path46

Path Summary:

Slack 0.664
Data Arrival Time 7.023
Data Required Time 7.687
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_22_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/I1
4.143 0.233 tINS RR 64 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/F
6.768 2.625 tNET RR 1 R16C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n625_s2/I3
7.023 0.255 tINS RF 1 R16C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n625_s2/F
7.023 0.000 tNET FF 1 R16C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.733 1.560 tNET RR 1 R16C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_22_s0/CLK
7.687 -0.046 tSu 1 R16C107[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_22_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.488, 8.947%; route: 4.661, 85.443%; tC2Q: 0.306, 5.610%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.560, 100.000%

Path47

Path Summary:

Slack 0.674
Data Arrival Time 6.999
Data Required Time 7.673
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/I1
4.143 0.233 tINS RR 64 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/F
6.768 2.625 tNET RR 1 R12C108[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n623_s2/I3
6.999 0.231 tINS RR 1 R12C108[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n623_s2/F
6.999 0.000 tNET RR 1 R12C108[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.724 1.551 tNET RR 1 R12C108[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0/CLK
7.673 -0.051 tSu 1 R12C108[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0

Path Statistics:

Clock Skew -0.017
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.464, 8.544%; route: 4.661, 85.821%; tC2Q: 0.306, 5.635%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.551, 100.000%

Path48

Path Summary:

Slack 0.674
Data Arrival Time 6.999
Data Required Time 7.673
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/I1
4.143 0.233 tINS RR 64 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/F
6.768 2.625 tNET RR 1 R12C108[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n619_s2/I3
6.999 0.231 tINS RR 1 R12C108[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n619_s2/F
6.999 0.000 tNET RR 1 R12C108[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.724 1.551 tNET RR 1 R12C108[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0/CLK
7.673 -0.051 tSu 1 R12C108[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0

Path Statistics:

Clock Skew -0.017
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.464, 8.544%; route: 4.661, 85.821%; tC2Q: 0.306, 5.635%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.551, 100.000%

Path49

Path Summary:

Slack 0.676
Data Arrival Time 6.995
Data Required Time 7.670
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_12_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/I1
4.143 0.233 tINS RR 64 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/F
6.764 2.620 tNET RR 1 R13C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n635_s2/I3
6.995 0.231 tINS RR 1 R13C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n635_s2/F
6.995 0.000 tNET RR 1 R13C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.721 1.548 tNET RR 1 R13C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_12_s0/CLK
7.670 -0.051 tSu 1 R13C107[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_12_s0

Path Statistics:

Clock Skew -0.020
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.464, 8.551%; route: 4.656, 85.810%; tC2Q: 0.306, 5.639%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.548, 100.000%

Path50

Path Summary:

Slack 0.682
Data Arrival Time 7.003
Data Required Time 7.685
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_6_s0
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.568 1.568 tNET RR 1 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/CLK
1.874 0.306 tC2Q RR 68 R9C115[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_5_s0/Q
3.911 2.036 tNET RR 1 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/I1
4.143 0.233 tINS RR 64 R21C115[3][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n647_s2/F
6.597 2.454 tNET RR 1 R13C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n641_s2/I3
7.003 0.406 tINS RR 1 R13C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n641_s2/F
7.003 0.000 tNET RR 1 R13C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 serdes_tx_clk
6.173 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
7.736 1.564 tNET RR 1 R13C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_6_s0/CLK
7.685 -0.051 tSu 1 R13C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_6_s0

Path Statistics:

Clock Skew -0.005
Setup Relationship 6.173
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%
Arrival Data Path Delay cell: 0.639, 11.758%; route: 4.490, 82.611%; tC2Q: 0.306, 5.631%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Setup Analysis Report[3]:

Report Command:report_timing -setup -from_clock [get_clocks {xgmii_clk}] -to_clock [get_clocks {xgmii_clk}] -max_paths 50 -max_common_paths 1

Path1

Path Summary:

Slack -0.573
Data Arrival Time 9.646
Data Required Time 9.073
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_10_s3
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_1_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.735 2.735 tNET RR 1 R20C121[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_10_s3/CLK
3.041 0.306 tC2Q RR 15 R20C121[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_10_s3/Q
4.413 1.372 tNET RR 1 R15C129[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9304_s9/I0
4.819 0.406 tINS RR 11 R15C129[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9304_s9/F
5.825 1.006 tNET RR 1 R21C126[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9221_s8/I1
6.056 0.231 tINS RR 3 R21C126[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9221_s8/F
6.925 0.869 tNET RR 1 R16C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9224_s3/I1
7.156 0.231 tINS RR 1 R16C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9224_s3/F
7.461 0.305 tNET RR 1 R14C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9224_s1/I1
7.915 0.454 tINS RR 2 R14C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9224_s1/F
9.646 1.731 tNET RR 1 R4C120[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.123 2.724 tNET RR 1 R4C120[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_1_s0/CLK
9.073 -0.051 tSu 1 R4C120[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_1_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay cell: 1.322, 19.129%; route: 5.283, 76.443%; tC2Q: 0.306, 4.428%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.724, 100.000%

Path2

Path Summary:

Slack -0.571
Data Arrival Time 9.612
Data Required Time 9.041
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_58_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/CLK
2.997 0.306 tC2Q RR 82 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q
4.584 1.587 tNET RR 1 R2C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s10/I2
4.990 0.406 tINS RR 10 R2C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s10/F
6.254 1.264 tNET RR 1 R12C130[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24455_s5/I3
6.619 0.365 tINS RR 8 R12C130[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24455_s5/F
7.683 1.064 tNET RR 1 R7C132[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24455_s3/I0
8.142 0.459 tINS RR 1 R7C132[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24455_s3/F
8.144 0.002 tNET RR 1 R7C132[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24455_s1/I0
8.607 0.463 tINS RR 2 R7C132[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24455_s1/F
9.357 0.750 tNET RR 1 R11C135[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24423_s2/I0
9.612 0.255 tINS RF 1 R11C135[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24423_s2/F
9.612 0.000 tNET FF 1 R11C135[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_58_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.087 2.687 tNET RR 1 R11C135[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_58_s0/CLK
9.041 -0.046 tSu 1 R11C135[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_58_s0

Path Statistics:

Clock Skew -0.004
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 1.948, 28.146%; route: 4.667, 67.432%; tC2Q: 0.306, 4.421%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.687, 100.000%

Path3

Path Summary:

Slack -0.569
Data Arrival Time 9.628
Data Required Time 9.059
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_10_s3
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_23_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.735 2.735 tNET RR 1 R20C121[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_10_s3/CLK
3.041 0.306 tC2Q RR 15 R20C121[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_10_s3/Q
4.413 1.372 tNET RR 1 R15C129[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9304_s9/I0
4.819 0.406 tINS RR 11 R15C129[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9304_s9/F
6.311 1.492 tNET RR 1 R5C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9357_s2/I3
6.566 0.255 tINS RF 2 R5C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9357_s2/F
7.371 0.805 tNET FF 1 R15C125[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9202_s5/I0
7.602 0.231 tINS FR 1 R15C125[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9202_s5/F
7.740 0.138 tNET RR 1 R15C126[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9202_s1/I3
7.971 0.231 tINS RR 2 R15C126[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9202_s1/F
9.628 1.657 tNET RR 1 R7C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.110 2.710 tNET RR 1 R7C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_23_s0/CLK
9.059 -0.051 tSu 1 R7C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_23_s0

Path Statistics:

Clock Skew -0.025
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay cell: 1.123, 16.292%; route: 5.464, 79.269%; tC2Q: 0.306, 4.439%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.710, 100.000%

Path4

Path Summary:

Slack -0.568
Data Arrival Time 9.604
Data Required Time 9.036
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.679 2.679 tNET RR 1 R13C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/CLK
2.985 0.306 tC2Q RR 105 R13C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/Q
5.428 2.443 tNET RR 1 R9C119[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s21/I2
5.891 0.463 tINS RR 1 R9C119[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s21/F
6.029 0.138 tNET RR 1 R8C119[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s14/I2
6.483 0.454 tINS RR 1 R8C119[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s14/F
6.641 0.158 tNET RR 1 R8C119[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s6/I1
7.100 0.459 tINS RR 7 R8C119[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s6/F
8.694 1.595 tNET RR 1 R11C131[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s3/I2
9.149 0.454 tINS RR 1 R11C131[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s3/F
9.151 0.002 tNET RR 1 R11C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s0/I3
9.604 0.454 tINS RR 1 R11C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s0/F
9.604 0.000 tNET RR 1 R11C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.087 2.687 tNET RR 1 R11C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0/CLK
9.036 -0.051 tSu 1 R11C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0

Path Statistics:

Clock Skew 0.008
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.679, 100.000%
Arrival Data Path Delay cell: 2.284, 32.977%; route: 4.336, 62.605%; tC2Q: 0.306, 4.418%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.687, 100.000%

Path5

Path Summary:

Slack -0.566
Data Arrival Time 9.609
Data Required Time 9.044
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.679 2.679 tNET RR 1 R13C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/CLK
2.985 0.306 tC2Q RR 105 R13C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/Q
5.428 2.443 tNET RR 1 R9C119[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s21/I2
5.891 0.463 tINS RR 1 R9C119[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s21/F
6.029 0.138 tNET RR 1 R8C119[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s14/I2
6.483 0.454 tINS RR 1 R8C119[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s14/F
6.641 0.158 tNET RR 1 R8C119[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s6/I1
7.100 0.459 tINS RR 7 R8C119[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s6/F
8.694 1.595 tNET RR 1 R11C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24475_s1/I0
9.149 0.454 tINS RR 1 R11C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24475_s1/F
9.151 0.002 tNET RR 1 R11C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24475_s0/I0
9.609 0.459 tINS RR 1 R11C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24475_s0/F
9.609 0.000 tNET RR 1 R11C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.095 2.695 tNET RR 1 R11C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0/CLK
9.044 -0.051 tSu 1 R11C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.679, 100.000%
Arrival Data Path Delay cell: 2.289, 33.026%; route: 4.336, 62.560%; tC2Q: 0.306, 4.415%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.695, 100.000%

Path6

Path Summary:

Slack -0.564
Data Arrival Time 9.600
Data Required Time 9.035
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_22_s3
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_5_s3
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.728 2.728 tNET RR 1 R20C134[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_22_s3/CLK
3.022 0.294 tC2Q RF 33 R20C134[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_22_s3/Q
4.791 1.769 tNET FF 1 R14C118[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9287_s6/I1
5.250 0.459 tINS FR 5 R14C118[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9287_s6/F
6.039 0.789 tNET RR 1 R16C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9199_s3/I2
6.445 0.406 tINS RR 1 R16C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9199_s3/F
8.110 1.665 tNET RR 1 R15C127[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9199_s1/I1
8.564 0.454 tINS RR 2 R15C127[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9199_s1/F
9.141 0.577 tNET RR 1 R13C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n8900_s3/I3
9.600 0.459 tINS RR 1 R13C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n8900_s3/F
9.600 0.000 tNET RR 1 R13C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_5_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.086 2.686 tNET RR 1 R13C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_5_s3/CLK
9.035 -0.051 tSu 1 R13C132[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_5_s3

Path Statistics:

Clock Skew -0.042
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.728, 100.000%
Arrival Data Path Delay cell: 1.778, 25.873%; route: 4.800, 69.849%; tC2Q: 0.294, 4.278%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.686, 100.000%

Path7

Path Summary:

Slack -0.564
Data Arrival Time 9.609
Data Required Time 9.045
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_17_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_1_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.716 2.716 tNET RR 1 R22C127[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_17_s1/CLK
3.022 0.306 tC2Q RR 43 R22C127[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_17_s1/Q
4.859 1.837 tNET RR 1 R38C136[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5607_s1/I1
5.092 0.233 tINS RR 6 R38C136[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5607_s1/F
6.844 1.752 tNET RR 1 R25C132[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5777_s2/I2
7.298 0.454 tINS RR 1 R25C132[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5777_s2/F
9.155 1.857 tNET RR 1 R33C132[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5777_s0/I3
9.609 0.454 tINS RR 1 R33C132[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5777_s0/F
9.609 0.000 tNET RR 1 R33C132[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.095 2.696 tNET RR 1 R33C132[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_1_s0/CLK
9.045 -0.051 tSu 1 R33C132[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_1_s0

Path Statistics:

Clock Skew -0.020
Setup Relationship 6.400
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.716, 100.000%
Arrival Data Path Delay cell: 1.141, 16.553%; route: 5.446, 79.008%; tC2Q: 0.306, 4.439%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.696, 100.000%

Path8

Path Summary:

Slack -0.560
Data Arrival Time 9.633
Data Required Time 9.073
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_13_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_11_s1
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.724 2.724 tNET RR 1 R22C126[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_13_s1/CLK
3.017 0.294 tC2Q RF 34 R22C126[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_13_s1/Q
4.972 1.955 tNET FF 1 R38C139[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n8233_s10/I1
5.203 0.231 tINS FR 4 R38C139[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n8233_s10/F
6.741 1.538 tNET RR 1 R27C129[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2791_s12/I3
7.180 0.438 tINS RR 1 R27C129[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2791_s12/F
7.318 0.138 tNET RR 1 R26C129[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2791_s4/I3
7.724 0.406 tINS RR 1 R26C129[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2791_s4/F
7.862 0.138 tNET RR 1 R25C129[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2791_s0/I3
8.316 0.454 tINS RR 2 R25C129[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2791_s0/F
9.227 0.911 tNET RR 1 R22C124[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3645_s2/I2
9.633 0.406 tINS RR 1 R22C124[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3645_s2/F
9.633 0.000 tNET RR 1 R22C124[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.123 2.724 tNET RR 1 R22C124[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_11_s1/CLK
9.073 -0.051 tSu 1 R22C124[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.724, 100.000%
Arrival Data Path Delay cell: 1.935, 28.007%; route: 4.680, 67.738%; tC2Q: 0.294, 4.255%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.724, 100.000%

Path9

Path Summary:

Slack -0.559
Data Arrival Time 9.608
Data Required Time 9.049
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/store_data_crc_12_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_error_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.720 2.720 tNET RR 1 R38C131[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/store_data_crc_12_s1/CLK
3.026 0.306 tC2Q RR 8 R38C131[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/store_data_crc_12_s1/Q
5.004 1.978 tNET RR 1 R24C122[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s171/I0
5.458 0.454 tINS RR 1 R24C122[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s171/F
5.460 0.002 tNET RR 1 R24C122[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s79/I2
5.825 0.365 tINS RR 1 R24C122[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s79/F
6.130 0.305 tNET RR 1 R25C124[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s21/I2
6.568 0.438 tINS RR 1 R25C124[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s21/F
7.705 1.137 tNET RR 1 R31C128[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s6/I3
7.936 0.231 tINS RR 1 R31C128[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s6/F
8.241 0.305 tNET RR 1 R34C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s2/I1
8.704 0.463 tINS RR 1 R34C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s2/F
9.377 0.673 tNET RR 1 R36C130[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s1/I0
9.608 0.231 tINS RR 1 R36C130[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n11962_s1/F
9.608 0.000 tNET RR 1 R36C130[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_error_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.100 2.700 tNET RR 1 R36C130[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_error_s0/CLK
9.049 -0.051 tSu 1 R36C130[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_error_s0

Path Statistics:

Clock Skew -0.020
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%
Arrival Data Path Delay cell: 2.182, 31.678%; route: 4.400, 63.879%; tC2Q: 0.306, 4.443%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.700, 100.000%

Path10

Path Summary:

Slack -0.558
Data Arrival Time 9.615
Data Required Time 9.057
From byte_cnt_9_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_2_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.725 2.725 tNET RR 1 R25C117[1][B] byte_cnt_9_s1/CLK
3.031 0.306 tC2Q RR 3 R25C117[1][B] byte_cnt_9_s1/Q
3.156 0.125 tNET RR 1 R25C117[0][A] n702_s5/I1
3.619 0.463 tINS RR 1 R25C117[0][A] n702_s5/F
3.621 0.002 tNET RR 1 R25C117[3][A] n702_s3/I3
3.876 0.255 tINS RF 3 R25C117[3][A] n702_s3/F
4.009 0.133 tNET FF 1 R25C118[2][A] n702_s6/I1
4.240 0.231 tINS FR 3 R25C118[2][A] n702_s6/F
4.380 0.140 tNET RR 1 R24C118[2][B] tx_mac_byte_7_s2/I3
4.786 0.406 tINS RR 5 R24C118[2][B] tx_mac_byte_7_s2/F
5.706 0.920 tNET RR 1 R12C117[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s8/I3
5.939 0.233 tINS RR 2 R12C117[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s8/F
6.512 0.573 tNET RR 1 R9C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1116_s5/I2
6.950 0.438 tINS RR 2 R9C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1116_s5/F
6.954 0.004 tNET RR 1 R9C117[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1116_s4/I0
7.417 0.463 tINS RR 2 R9C117[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1116_s4/F
8.157 0.740 tNET RR 1 R13C117[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1183_s4/I0
8.611 0.454 tINS RR 8 R13C117[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1183_s4/F
9.156 0.545 tNET RR 1 R18C117[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1181_s3/I1
9.615 0.459 tINS RR 1 R18C117[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1181_s3/F
9.615 0.000 tNET RR 1 R18C117[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.108 2.707 tNET RR 1 R18C117[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_2_s0/CLK
9.057 -0.051 tSu 1 R18C117[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_2_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.400
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.725, 100.000%
Arrival Data Path Delay cell: 3.402, 49.376%; route: 3.182, 46.183%; tC2Q: 0.306, 4.441%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.707, 100.000%

Path11

Path Summary:

Slack -0.556
Data Arrival Time 9.623
Data Required Time 9.067
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_29_s3
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_10_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.699 2.699 tNET RR 1 R17C118[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_29_s3/CLK
3.005 0.306 tC2Q RR 36 R17C118[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_29_s3/Q
4.380 1.375 tNET RR 1 R4C120[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9305_s7/I0
4.613 0.233 tINS RR 5 R4C120[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9305_s7/F
6.189 1.576 tNET RR 1 R18C126[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9215_s12/I3
6.420 0.231 tINS RR 1 R18C126[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9215_s12/F
6.725 0.305 tNET RR 1 R18C123[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9215_s11/I2
6.956 0.231 tINS RR 1 R18C123[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9215_s11/F
7.645 0.689 tNET RR 1 R20C122[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9215_s5/I3
7.876 0.231 tINS RR 1 R20C122[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9215_s5/F
8.014 0.138 tNET RR 1 R20C123[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9215_s1/I3
8.245 0.231 tINS RR 2 R20C123[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9215_s1/F
9.623 1.379 tNET RR 1 R3C123[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.118 2.718 tNET RR 1 R3C123[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_10_s0/CLK
9.067 -0.051 tSu 1 R3C123[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_10_s0

Path Statistics:

Clock Skew 0.020
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.699, 100.000%
Arrival Data Path Delay cell: 1.157, 16.708%; route: 5.462, 78.874%; tC2Q: 0.306, 4.419%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.718, 100.000%

Path12

Path Summary:

Slack -0.556
Data Arrival Time 9.632
Data Required Time 9.076
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_51_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/CLK
2.997 0.306 tC2Q RR 82 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q
4.584 1.587 tNET RR 1 R2C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s10/I2
4.990 0.406 tINS RR 10 R2C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s10/F
6.078 1.088 tNET RR 1 R20C119[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s9/I3
6.309 0.231 tINS RR 5 R20C119[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s9/F
7.836 1.527 tNET RR 1 R5C131[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24462_s11/I0
8.091 0.255 tINS RF 1 R5C131[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24462_s11/F
8.095 0.004 tNET FF 1 R5C131[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24430_s5/I0
8.558 0.463 tINS FR 1 R5C131[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24430_s5/F
8.696 0.138 tNET RR 1 R4C131[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24430_s4/I0
8.929 0.233 tINS RR 1 R4C131[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24430_s4/F
9.401 0.472 tNET RR 1 R6C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24430_s2/I2
9.632 0.231 tINS RR 1 R6C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24430_s2/F
9.632 0.000 tNET RR 1 R6C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_51_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.127 2.727 tNET RR 1 R6C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_51_s0/CLK
9.076 -0.051 tSu 1 R6C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_51_s0

Path Statistics:

Clock Skew 0.036
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 1.819, 26.207%; route: 4.816, 69.385%; tC2Q: 0.306, 4.409%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.727, 100.000%

Path13

Path Summary:

Slack -0.555
Data Arrival Time 9.622
Data Required Time 9.067
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_31_s5
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result4_13_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.699 2.699 tNET RR 1 R17C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_31_s5/CLK
3.005 0.306 tC2Q RR 31 R17C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_31_s5/Q
4.316 1.311 tNET RR 1 R3C120[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9256_s2/I1
4.779 0.463 tINS RR 6 R3C120[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9256_s2/F
6.217 1.438 tNET RR 1 R18C125[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9221_s14/I3
6.448 0.231 tINS RR 2 R18C125[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9221_s14/F
7.170 0.722 tNET RR 1 R20C127[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9221_s13/I2
7.633 0.463 tINS RR 2 R20C127[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9221_s13/F
9.159 1.526 tNET RR 1 R7C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9340_s1/I1
9.622 0.463 tINS RR 1 R7C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9340_s1/F
9.622 0.000 tNET RR 1 R7C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result4_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.118 2.718 tNET RR 1 R7C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result4_13_s0/CLK
9.067 -0.051 tSu 1 R7C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result4_13_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.699, 100.000%
Arrival Data Path Delay cell: 1.620, 23.400%; route: 4.997, 72.180%; tC2Q: 0.306, 4.420%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.718, 100.000%

Path14

Path Summary:

Slack -0.554
Data Arrival Time 9.407
Data Required Time 8.853
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_19_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.407 3.269 tNET RR 1 R29C129[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_19_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.102 2.702 tNET RR 1 R29C129[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_19_s0/CLK
8.853 -0.249 tSu 1 R29C129[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_19_s0

Path Statistics:

Clock Skew -0.031
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.740%; route: 5.451, 81.675%; tC2Q: 0.306, 4.585%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.702, 100.000%

Path15

Path Summary:

Slack -0.553
Data Arrival Time 9.614
Data Required Time 9.061
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_63_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.679 2.679 tNET RR 1 R13C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/CLK
2.985 0.306 tC2Q RR 105 R13C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/Q
5.715 2.731 tNET RR 1 R2C122[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24450_s13/I0
6.121 0.406 tINS RR 1 R2C122[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24450_s13/F
6.242 0.121 tNET RR 1 R2C122[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24450_s6/I2
6.705 0.463 tINS RR 1 R2C122[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24450_s6/F
6.707 0.002 tNET RR 1 R2C122[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24450_s2/I1
6.938 0.231 tINS RR 8 R2C122[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24450_s2/F
7.994 1.056 tNET RR 1 R6C136[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24450_s9/I0
8.453 0.459 tINS RR 2 R6C136[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24450_s9/F
8.457 0.004 tNET RR 1 R6C136[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24418_s3/I1
8.920 0.463 tINS RR 1 R6C136[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24418_s3/F
9.208 0.288 tNET RR 1 R8C136[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24418_s2/I0
9.614 0.406 tINS RR 1 R8C136[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24418_s2/F
9.614 0.000 tNET RR 1 R8C136[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_63_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.112 2.712 tNET RR 1 R8C136[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_63_s0/CLK
9.061 -0.051 tSu 1 R8C136[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_63_s0

Path Statistics:

Clock Skew 0.033
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.679, 100.000%
Arrival Data Path Delay cell: 2.428, 35.008%; route: 4.202, 60.580%; tC2Q: 0.306, 4.412%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.712, 100.000%

Path16

Path Summary:

Slack -0.553
Data Arrival Time 9.594
Data Required Time 9.042
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_1_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_25_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.681 2.681 tNET RR 1 R30C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_1_s1/CLK
2.987 0.306 tC2Q RR 31 R30C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_1_s1/Q
5.494 2.507 tNET RR 1 R29C134[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5197_s1/I1
5.900 0.406 tINS RR 2 R29C134[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5197_s1/F
7.677 1.777 tNET RR 1 R32C133[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9090_s4/I1
8.115 0.438 tINS RR 1 R32C133[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9090_s4/F
8.253 0.138 tNET RR 1 R32C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9090_s2/I3
8.659 0.406 tINS RR 1 R32C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9090_s2/F
9.131 0.472 tNET RR 1 R36C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9090_s0/I2
9.594 0.463 tINS RR 1 R36C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9090_s0/F
9.594 0.000 tNET RR 1 R36C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.093 2.693 tNET RR 1 R36C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_25_s0/CLK
9.042 -0.051 tSu 1 R36C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_25_s0

Path Statistics:

Clock Skew 0.011
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.681, 100.000%
Arrival Data Path Delay cell: 1.713, 24.779%; route: 4.894, 70.794%; tC2Q: 0.306, 4.426%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.693, 100.000%

Path17

Path Summary:

Slack -0.546
Data Arrival Time 9.591
Data Required Time 9.045
From byte_cnt_9_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_31_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.725 2.725 tNET RR 1 R25C117[1][B] byte_cnt_9_s1/CLK
3.031 0.306 tC2Q RR 3 R25C117[1][B] byte_cnt_9_s1/Q
3.156 0.125 tNET RR 1 R25C117[0][A] n702_s5/I1
3.619 0.463 tINS RR 1 R25C117[0][A] n702_s5/F
3.621 0.002 tNET RR 1 R25C117[3][A] n702_s3/I3
3.876 0.255 tINS RF 3 R25C117[3][A] n702_s3/F
4.009 0.133 tNET FF 1 R25C118[2][A] n702_s6/I1
4.240 0.231 tINS FR 3 R25C118[2][A] n702_s6/F
4.380 0.140 tNET RR 1 R24C118[2][B] tx_mac_byte_7_s2/I3
4.786 0.406 tINS RR 5 R24C118[2][B] tx_mac_byte_7_s2/F
5.842 1.056 tNET RR 1 R12C117[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s7/I0
6.073 0.231 tINS RR 1 R12C117[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s7/F
6.194 0.121 tNET RR 1 R12C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s4/I1
6.425 0.231 tINS RR 4 R12C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s4/F
6.998 0.573 tNET RR 1 R9C117[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1159_s4/I0
7.229 0.231 tINS RR 2 R9C117[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1159_s4/F
7.400 0.171 tNET RR 1 R8C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1159_s3/I0
7.765 0.365 tINS RR 8 R8C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1159_s3/F
9.360 1.595 tNET RR 1 R15C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1152_s2/I1
9.591 0.231 tINS RR 1 R15C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1152_s2/F
9.591 0.000 tNET RR 1 R15C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_31_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.095 2.696 tNET RR 1 R15C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_31_s0/CLK
9.045 -0.051 tSu 1 R15C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_31_s0

Path Statistics:

Clock Skew -0.030
Setup Relationship 6.400
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.725, 100.000%
Arrival Data Path Delay cell: 2.644, 38.509%; route: 3.916, 57.035%; tC2Q: 0.306, 4.457%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.696, 100.000%

Path18

Path Summary:

Slack -0.545
Data Arrival Time 9.589
Data Required Time 9.044
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_54_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_22_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.735 2.735 tNET RR 1 R38C129[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_54_s0/CLK
3.041 0.306 tC2Q RR 20 R38C129[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_54_s0/Q
4.864 1.823 tNET RR 1 R25C136[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2837_s16/I0
5.327 0.463 tINS RR 3 R25C136[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2837_s16/F
6.089 0.762 tNET RR 1 R25C133[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3226_s8/I0
6.320 0.231 tINS RR 1 R25C133[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3226_s8/F
7.212 0.892 tNET RR 1 R25C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3226_s3/I3
7.443 0.231 tINS RR 1 R25C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3226_s3/F
7.748 0.305 tNET RR 1 R26C126[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3226_s0/I2
8.211 0.463 tINS RR 2 R26C126[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3226_s0/F
9.589 1.378 tNET RR 1 R29C124[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.095 2.695 tNET RR 1 R29C124[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_22_s0/CLK
9.044 -0.051 tSu 1 R29C124[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_22_s0

Path Statistics:

Clock Skew -0.040
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay cell: 1.388, 20.251%; route: 5.160, 75.285%; tC2Q: 0.306, 4.465%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.695, 100.000%

Path19

Path Summary:

Slack -0.542
Data Arrival Time 9.622
Data Required Time 9.080
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_32_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_12_s1
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.722 2.722 tNET RR 1 R41C122[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_32_s0/CLK
3.028 0.306 tC2Q RR 33 R41C122[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_32_s0/Q
4.606 1.578 tNET RR 1 R38C138[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n10020_s1/I1
4.970 0.365 tINS RR 7 R38C138[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n10020_s1/F
6.486 1.516 tNET RR 1 R25C132[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2837_s13/I2
6.851 0.365 tINS RR 1 R25C132[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2837_s13/F
7.467 0.616 tNET RR 1 R25C136[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2837_s4/I2
7.698 0.231 tINS RR 1 R25C136[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2837_s4/F
8.023 0.325 tNET RR 1 R26C138[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2837_s0/I3
8.388 0.365 tINS RR 2 R26C138[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2837_s0/F
9.159 0.771 tNET RR 1 R22C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3644_s2/I2
9.622 0.463 tINS RR 1 R22C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3644_s2/F
9.622 0.000 tNET RR 1 R22C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_12_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.131 2.731 tNET RR 1 R22C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_12_s1/CLK
9.080 -0.051 tSu 1 R22C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_12_s1

Path Statistics:

Clock Skew 0.010
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.722, 100.000%
Arrival Data Path Delay cell: 1.789, 25.924%; route: 4.806, 69.642%; tC2Q: 0.306, 4.434%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.731, 100.000%

Path20

Path Summary:

Slack -0.539
Data Arrival Time 9.610
Data Required Time 9.071
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_35_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/remote_fault_pipe1_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.735 2.735 tNET RR 1 R38C121[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_35_s0/CLK
3.041 0.306 tC2Q RR 4 R38C121[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_35_s0/Q
4.633 1.592 tNET RR 1 R39C126[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1540_s15/I1
5.071 0.438 tINS RR 1 R39C126[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1540_s15/F
5.209 0.138 tNET RR 1 R38C126[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1540_s12/I2
5.647 0.438 tINS RR 1 R38C126[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1540_s12/F
5.785 0.138 tNET RR 1 R38C125[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1540_s8/I3
6.018 0.233 tINS RR 1 R38C125[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1540_s8/F
6.619 0.601 tNET RR 1 R35C125[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1540_s16/I3
7.057 0.438 tINS RR 2 R35C125[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1540_s16/F
8.214 1.157 tNET RR 1 R27C130[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1611_s2/I2
8.677 0.463 tINS RR 3 R27C130[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1611_s2/F
9.151 0.474 tNET RR 1 R23C130[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1611_s3/I3
9.610 0.459 tINS RR 1 R23C130[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n1611_s3/F
9.610 0.000 tNET RR 1 R23C130[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/remote_fault_pipe1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.122 2.722 tNET RR 1 R23C130[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/remote_fault_pipe1_s0/CLK
9.071 -0.051 tSu 1 R23C130[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/remote_fault_pipe1_s0

Path Statistics:

Clock Skew -0.013
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay cell: 2.469, 35.913%; route: 4.100, 59.636%; tC2Q: 0.306, 4.451%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.722, 100.000%

Path21

Path Summary:

Slack -0.534
Data Arrival Time 9.607
Data Required Time 9.073
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_25_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/CLK
2.997 0.306 tC2Q RR 110 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q
4.451 1.454 tNET RR 1 R2C120[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24463_s4/I1
4.857 0.406 tINS RR 3 R2C120[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24463_s4/F
5.974 1.117 tNET RR 1 R14C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s7/I1
6.205 0.231 tINS RR 1 R14C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s7/F
6.707 0.502 tNET RR 1 R11C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s5/I0
6.940 0.233 tINS RR 8 R11C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s5/F
7.950 1.010 tNET RR 1 R7C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s3/I0
8.181 0.231 tINS RR 1 R7C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s3/F
8.183 0.002 tNET RR 1 R7C131[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s1/I0
8.642 0.459 tINS RR 2 R7C131[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s1/F
9.376 0.734 tNET RR 1 R4C136[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s0/I0
9.607 0.231 tINS RR 1 R4C136[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s0/F
9.607 0.000 tNET RR 1 R4C136[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.123 2.724 tNET RR 1 R4C136[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_25_s0/CLK
9.073 -0.051 tSu 1 R4C136[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_25_s0

Path Statistics:

Clock Skew 0.033
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 1.791, 25.896%; route: 4.819, 69.679%; tC2Q: 0.306, 4.425%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.724, 100.000%

Path22

Path Summary:

Slack -0.534
Data Arrival Time 9.607
Data Required Time 9.073
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_57_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/CLK
2.997 0.306 tC2Q RR 110 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q
4.451 1.454 tNET RR 1 R2C120[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24463_s4/I1
4.857 0.406 tINS RR 3 R2C120[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24463_s4/F
5.974 1.117 tNET RR 1 R14C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s7/I1
6.205 0.231 tINS RR 1 R14C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s7/F
6.707 0.502 tNET RR 1 R11C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s5/I0
6.940 0.233 tINS RR 8 R11C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s5/F
7.950 1.010 tNET RR 1 R7C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s3/I0
8.181 0.231 tINS RR 1 R7C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s3/F
8.183 0.002 tNET RR 1 R7C131[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s1/I0
8.642 0.459 tINS RR 2 R7C131[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24456_s1/F
9.376 0.734 tNET RR 1 R4C136[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24424_s2/I0
9.607 0.231 tINS RR 1 R4C136[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24424_s2/F
9.607 0.000 tNET RR 1 R4C136[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_57_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.123 2.724 tNET RR 1 R4C136[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_57_s0/CLK
9.073 -0.051 tSu 1 R4C136[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_57_s0

Path Statistics:

Clock Skew 0.033
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 1.791, 25.896%; route: 4.819, 69.679%; tC2Q: 0.306, 4.425%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.724, 100.000%

Path23

Path Summary:

Slack -0.534
Data Arrival Time 9.596
Data Required Time 9.063
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/last_valid_num_pipe3_0_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.681 2.681 tNET RR 1 R12C138[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/last_valid_num_pipe3_0_s0/CLK
2.975 0.294 tC2Q RF 73 R12C138[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/last_valid_num_pipe3_0_s0/Q
4.550 1.575 tNET FF 1 R2C135[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24004_s4/I0
4.757 0.207 tINS FF 13 R2C135[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24004_s4/F
5.223 0.466 tNET FF 1 R6C133[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s2/I0
5.686 0.463 tINS FR 9 R6C133[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s2/F
6.241 0.555 tNET RR 1 R4C131[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24411_s4/I3
6.695 0.454 tINS RR 5 R4C131[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24411_s4/F
7.669 0.974 tNET RR 1 R11C135[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s22/I0
8.132 0.463 tINS RR 1 R11C135[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s22/F
8.733 0.601 tNET RR 1 R9C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s3/I3
9.196 0.463 tINS RR 1 R9C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s3/F
9.365 0.169 tNET RR 1 R9C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s0/I2
9.596 0.231 tINS RR 1 R9C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s0/F
9.596 0.000 tNET RR 1 R9C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.114 2.714 tNET RR 1 R9C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0/CLK
9.063 -0.051 tSu 1 R9C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0

Path Statistics:

Clock Skew 0.032
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.681, 100.000%
Arrival Data Path Delay cell: 2.281, 32.986%; route: 4.340, 62.762%; tC2Q: 0.294, 4.252%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.714, 100.000%

Path24

Path Summary:

Slack -0.534
Data Arrival Time 9.597
Data Required Time 9.063
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_62_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/CLK
2.985 0.294 tC2Q RF 110 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q
4.824 1.839 tNET FF 1 R12C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s19/I2
5.278 0.454 tINS FR 1 R12C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s19/F
5.416 0.138 tNET RR 1 R11C118[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s11/I0
5.822 0.406 tINS RR 1 R11C118[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s11/F
5.943 0.121 tNET RR 1 R11C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s5/I1
6.406 0.463 tINS RR 6 R11C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s5/F
7.683 1.277 tNET RR 1 R8C133[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s14/I0
8.137 0.454 tINS RR 3 R8C133[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s14/F
8.613 0.476 tNET RR 1 R5C134[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s1/I1
9.051 0.438 tINS RR 2 R5C134[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s1/F
9.191 0.140 tNET RR 1 R5C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24419_s2/I0
9.597 0.406 tINS RR 1 R5C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24419_s2/F
9.597 0.000 tNET RR 1 R5C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_62_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.114 2.714 tNET RR 1 R5C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_62_s0/CLK
9.063 -0.051 tSu 1 R5C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_62_s0

Path Statistics:

Clock Skew 0.023
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 2.621, 37.953%; route: 3.991, 57.790%; tC2Q: 0.294, 4.257%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.714, 100.000%

Path25

Path Summary:

Slack -0.533
Data Arrival Time 9.584
Data Required Time 9.051
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_54_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.679 2.679 tNET RR 1 R13C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/CLK
2.985 0.306 tC2Q RR 105 R13C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_0_s0/Q
5.428 2.443 tNET RR 1 R9C119[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s21/I2
5.891 0.463 tINS RR 1 R9C119[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s21/F
6.029 0.138 tNET RR 1 R8C119[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s14/I2
6.483 0.454 tINS RR 1 R8C119[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s14/F
6.641 0.158 tNET RR 1 R8C119[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s6/I1
7.100 0.459 tINS RR 7 R8C119[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s6/F
8.644 1.545 tNET RR 1 R11C133[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24427_s4/I0
9.009 0.365 tINS RR 1 R11C133[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24427_s4/F
9.130 0.121 tNET RR 1 R11C133[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24427_s2/I1
9.584 0.454 tINS RR 1 R11C133[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24427_s2/F
9.584 0.000 tNET RR 1 R11C133[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_54_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.102 2.702 tNET RR 1 R11C133[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_54_s0/CLK
9.051 -0.051 tSu 1 R11C133[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_54_s0

Path Statistics:

Clock Skew 0.023
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.679, 100.000%
Arrival Data Path Delay cell: 2.195, 31.784%; route: 4.405, 63.785%; tC2Q: 0.306, 4.431%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.702, 100.000%

Path26

Path Summary:

Slack -0.533
Data Arrival Time 9.379
Data Required Time 8.846
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_23_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.379 3.241 tNET RR 1 R29C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_23_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.095 2.695 tNET RR 1 R29C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_23_s0/CLK
8.846 -0.249 tSu 1 R29C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_23_s0

Path Statistics:

Clock Skew -0.038
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.798%; route: 5.423, 81.598%; tC2Q: 0.306, 4.604%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.695, 100.000%

Path27

Path Summary:

Slack -0.532
Data Arrival Time 9.606
Data Required Time 9.075
From c_tx_state_0_s5
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_6_s1
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.720 2.720 tNET RR 1 R24C118[0][B] c_tx_state_0_s5/CLK
3.026 0.306 tC2Q RR 22 R24C118[0][B] c_tx_state_0_s5/Q
3.370 0.344 tNET RR 1 R26C119[3][B] tx_mac_last_s21/I0
3.735 0.365 tINS RR 11 R26C119[3][B] tx_mac_last_s21/F
5.432 1.697 tNET RR 1 R4C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/I3
5.663 0.231 tINS RR 1 R4C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/F
5.784 0.121 tNET RR 1 R4C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/I0
6.039 0.255 tINS RF 4 R4C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/F
6.833 0.794 tNET FF 2 R2C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/I1
7.331 0.498 tINS FR 4 R2C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/SUM
7.839 0.508 tNET RR 1 R2C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/I1
8.302 0.463 tINS RR 4 R2C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/F
8.446 0.144 tNET RR 1 R2C126[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s8/I3
8.677 0.231 tINS RR 2 R2C126[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s8/F
8.800 0.123 tNET RR 1 R2C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n103_s2/I1
9.238 0.438 tINS RR 1 R2C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n103_s2/F
9.375 0.138 tNET RR 1 R3C126[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n103_s0/I1
9.606 0.231 tINS RR 1 R3C126[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n103_s0/F
9.606 0.000 tNET RR 1 R3C126[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.125 2.726 tNET RR 1 R3C126[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_6_s1/CLK
9.075 -0.051 tSu 1 R3C126[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_6_s1

Path Statistics:

Clock Skew 0.006
Setup Relationship 6.400
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%
Arrival Data Path Delay cell: 2.712, 39.379%; route: 3.869, 56.178%; tC2Q: 0.306, 4.443%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.726, 100.000%

Path28

Path Summary:

Slack -0.530
Data Arrival Time 9.591
Data Required Time 9.061
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_35_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/CLK
2.997 0.306 tC2Q RR 82 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q
5.645 2.648 tNET RR 1 R8C121[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24462_s4/I3
6.051 0.406 tINS RR 1 R8C121[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24462_s4/F
6.715 0.664 tNET RR 1 R3C121[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24462_s1/I0
7.169 0.454 tINS RR 8 R3C121[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24462_s1/F
8.161 0.992 tNET RR 1 R7C133[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24446_s5/I0
8.599 0.438 tINS RR 1 R7C133[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24446_s5/F
8.904 0.305 tNET RR 1 R8C132[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24446_s3/I1
9.135 0.231 tINS RR 1 R8C132[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24446_s3/F
9.137 0.002 tNET RR 1 R8C132[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24446_s2/I0
9.591 0.454 tINS RR 1 R8C132[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24446_s2/F
9.591 0.000 tNET RR 1 R8C132[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_35_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.112 2.712 tNET RR 1 R8C132[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_35_s0/CLK
9.061 -0.051 tSu 1 R8C132[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_35_s0

Path Statistics:

Clock Skew 0.021
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 1.983, 28.739%; route: 4.611, 66.826%; tC2Q: 0.306, 4.435%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.712, 100.000%

Path29

Path Summary:

Slack -0.529
Data Arrival Time 9.613
Data Required Time 9.084
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_pipe2_25_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_23_s3
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.697 2.697 tNET RR 1 R16C132[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_pipe2_25_s1/CLK
3.003 0.306 tC2Q RR 24 R16C132[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_pipe2_25_s1/Q
5.144 2.141 tNET RR 1 R7C118[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9384_s8/I0
5.375 0.231 tINS RR 3 R7C118[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9384_s8/F
6.111 0.736 tNET RR 1 R8C124[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9340_s2/I2
6.574 0.463 tINS RR 2 R8C124[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9340_s2/F
7.917 1.343 tNET RR 1 R20C127[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9217_s5/I0
8.282 0.365 tINS RR 1 R20C127[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9217_s5/F
8.284 0.002 tNET RR 1 R20C127[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9217_s1/I3
8.747 0.463 tINS RR 2 R20C127[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9217_s1/F
9.159 0.412 tNET RR 1 R20C121[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n8882_s3/I3
9.613 0.454 tINS RR 1 R20C121[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n8882_s3/F
9.613 0.000 tNET RR 1 R20C121[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_23_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.135 2.735 tNET RR 1 R20C121[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_23_s3/CLK
9.084 -0.051 tSu 1 R20C121[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_23_s3

Path Statistics:

Clock Skew 0.038
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.697, 100.000%
Arrival Data Path Delay cell: 1.976, 28.571%; route: 4.634, 67.004%; tC2Q: 0.306, 4.425%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.735, 100.000%

Path30

Path Summary:

Slack -0.528
Data Arrival Time 9.589
Data Required Time 9.061
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_30_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/CLK
2.985 0.294 tC2Q RF 110 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q
4.824 1.839 tNET FF 1 R12C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s19/I2
5.278 0.454 tINS FR 1 R12C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s19/F
5.416 0.138 tNET RR 1 R11C118[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s11/I0
5.822 0.406 tINS RR 1 R11C118[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s11/F
5.943 0.121 tNET RR 1 R11C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s5/I1
6.406 0.463 tINS RR 6 R11C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24459_s5/F
7.683 1.277 tNET RR 1 R8C133[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s14/I0
8.137 0.454 tINS RR 3 R8C133[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s14/F
8.613 0.476 tNET RR 1 R5C134[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s1/I1
9.051 0.438 tINS RR 2 R5C134[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s1/F
9.358 0.307 tNET RR 1 R6C135[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s0/I0
9.589 0.231 tINS RR 1 R6C135[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s0/F
9.589 0.000 tNET RR 1 R6C135[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_30_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.112 2.712 tNET RR 1 R6C135[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_30_s0/CLK
9.061 -0.051 tSu 1 R6C135[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_30_s0

Path Statistics:

Clock Skew 0.021
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 2.446, 35.460%; route: 4.158, 60.278%; tC2Q: 0.294, 4.262%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.712, 100.000%

Path31

Path Summary:

Slack -0.526
Data Arrival Time 9.379
Data Required Time 8.853
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_8_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.379 3.241 tNET RR 1 R29C125[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.102 2.702 tNET RR 1 R29C125[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_8_s0/CLK
8.853 -0.249 tSu 1 R29C125[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out3_8_s0

Path Statistics:

Clock Skew -0.031
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.798%; route: 5.423, 81.598%; tC2Q: 0.306, 4.604%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.702, 100.000%

Path32

Path Summary:

Slack -0.526
Data Arrival Time 9.379
Data Required Time 8.853
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_24_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.379 3.241 tNET RR 1 R29C125[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_24_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.102 2.702 tNET RR 1 R29C125[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_24_s0/CLK
8.853 -0.249 tSu 1 R29C125[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_24_s0

Path Statistics:

Clock Skew -0.031
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.798%; route: 5.423, 81.598%; tC2Q: 0.306, 4.604%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.702, 100.000%

Path33

Path Summary:

Slack -0.525
Data Arrival Time 9.363
Data Required Time 8.838
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_26_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.363 3.225 tNET RR 1 R29C131[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_26_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.087 2.687 tNET RR 1 R29C131[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_26_s0/CLK
8.838 -0.249 tSu 1 R29C131[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out6_26_s0

Path Statistics:

Clock Skew -0.046
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.831%; route: 5.407, 81.554%; tC2Q: 0.306, 4.615%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.687, 100.000%

Path34

Path Summary:

Slack -0.525
Data Arrival Time 9.552
Data Required Time 9.028
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_24_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_20_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.699 2.699 tNET RR 1 R35C128[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_24_s0/CLK
2.993 0.294 tC2Q RF 24 R35C128[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_24_s0/Q
4.865 1.872 tNET FF 1 R38C138[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3142_s14/I0
5.319 0.454 tINS FR 4 R38C138[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3142_s14/F
7.122 1.804 tNET RR 1 R25C132[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3142_s4/I2
7.353 0.231 tINS RR 1 R25C132[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3142_s4/F
7.491 0.138 tNET RR 1 R24C132[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3142_s0/I3
7.945 0.454 tINS RR 2 R24C132[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3142_s0/F
9.552 1.607 tNET RR 1 R31C123[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.079 2.679 tNET RR 1 R31C123[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_20_s0/CLK
9.028 -0.051 tSu 1 R31C123[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out0_20_s0

Path Statistics:

Clock Skew -0.020
Setup Relationship 6.400
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.699, 100.000%
Arrival Data Path Delay cell: 1.139, 16.618%; route: 5.421, 79.092%; tC2Q: 0.294, 4.289%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.679, 100.000%

Path35

Path Summary:

Slack -0.524
Data Arrival Time 9.570
Data Required Time 9.046
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_pipe2_0_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_14_s3
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.698 2.698 tNET RR 1 R14C133[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_pipe2_0_s1/CLK
3.004 0.306 tC2Q RR 30 R14C133[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_pipe2_0_s1/Q
3.834 0.830 tNET RR 1 R18C128[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9194_s14/I2
4.288 0.454 tINS RR 8 R18C128[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9194_s14/F
5.311 1.023 tNET RR 1 R8C128[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9372_s7/I1
5.774 0.463 tINS RR 3 R8C128[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9372_s7/F
6.114 0.340 tNET RR 1 R9C130[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9208_s16/I2
6.552 0.438 tINS RR 3 R9C130[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9208_s16/F
7.787 1.235 tNET RR 1 R16C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9208_s1/I0
8.246 0.459 tINS RR 2 R16C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n9208_s1/F
9.339 1.093 tNET RR 1 R16C122[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n8891_s3/I3
9.570 0.231 tINS RR 1 R16C122[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n8891_s3/F
9.570 0.000 tNET RR 1 R16C122[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_14_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.097 2.697 tNET RR 1 R16C122[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_14_s3/CLK
9.046 -0.051 tSu 1 R16C122[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_tmp_14_s3

Path Statistics:

Clock Skew -0.001
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.698, 100.000%
Arrival Data Path Delay cell: 2.045, 29.758%; route: 4.521, 65.789%; tC2Q: 0.306, 4.453%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.697, 100.000%

Path36

Path Summary:

Slack -0.521
Data Arrival Time 9.392
Data Required Time 8.871
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_25_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.392 3.254 tNET RR 1 R38C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_25_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.120 2.720 tNET RR 1 R38C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_25_s0/CLK
8.871 -0.249 tSu 1 R38C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_25_s0

Path Statistics:

Clock Skew -0.013
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.771%; route: 5.436, 81.634%; tC2Q: 0.306, 4.595%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%

Path37

Path Summary:

Slack -0.520
Data Arrival Time 9.581
Data Required Time 9.061
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_23_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_15_s1
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.695 2.695 tNET RR 1 R29C126[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_23_s1/CLK
3.001 0.306 tC2Q RR 46 R29C126[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_23_s1/Q
4.455 1.454 tNET RR 1 R36C130[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5707_s4/I0
4.686 0.231 tINS RR 3 R36C130[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n5707_s4/F
6.187 1.501 tNET RR 1 R32C130[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2503_s12/I3
6.649 0.463 tINS RR 2 R32C130[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2503_s12/F
7.711 1.062 tNET RR 1 R29C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2972_s3/I0
8.165 0.454 tINS RR 2 R29C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n2972_s3/F
9.127 0.962 tNET RR 1 R24C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3641_s2/I3
9.581 0.454 tINS RR 1 R24C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n3641_s2/F
9.581 0.000 tNET RR 1 R24C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.112 2.712 tNET RR 1 R24C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_15_s1/CLK
9.061 -0.051 tSu 1 R24C131[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_64bit_crc_tmp_15_s1

Path Statistics:

Clock Skew 0.017
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.695, 100.000%
Arrival Data Path Delay cell: 1.602, 23.261%; route: 4.979, 72.296%; tC2Q: 0.306, 4.443%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.712, 100.000%

Path38

Path Summary:

Slack -0.520
Data Arrival Time 9.583
Data Required Time 9.063
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_42_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/CLK
2.997 0.306 tC2Q RR 110 R14C134[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_1_s0/Q
4.741 1.744 tNET RR 1 R12C119[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24479_s11/I1
5.195 0.454 tINS RR 1 R12C119[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24479_s11/F
6.349 1.154 tNET RR 1 R12C120[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24479_s4/I2
6.803 0.454 tINS RR 6 R12C120[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24479_s4/F
8.187 1.384 tNET RR 1 R7C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24439_s5/I1
8.641 0.454 tINS RR 1 R7C133[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24439_s5/F
8.810 0.169 tNET RR 1 R9C133[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24439_s4/I2
9.175 0.365 tINS RR 1 R9C133[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24439_s4/F
9.177 0.002 tNET RR 1 R9C133[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24439_s2/I2
9.583 0.406 tINS RR 1 R9C133[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24439_s2/F
9.583 0.000 tNET RR 1 R9C133[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_42_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.114 2.714 tNET RR 1 R9C133[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_42_s0/CLK
9.063 -0.051 tSu 1 R9C133[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_42_s0

Path Statistics:

Clock Skew 0.023
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 2.133, 30.949%; route: 4.453, 64.611%; tC2Q: 0.306, 4.440%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.714, 100.000%

Path39

Path Summary:

Slack -0.519
Data Arrival Time 9.599
Data Required Time 9.080
From c_tx_state_0_s5
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_7_s1
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.720 2.720 tNET RR 1 R24C118[0][B] c_tx_state_0_s5/CLK
3.026 0.306 tC2Q RR 22 R24C118[0][B] c_tx_state_0_s5/Q
3.370 0.344 tNET RR 1 R26C119[3][B] tx_mac_last_s21/I0
3.735 0.365 tINS RR 11 R26C119[3][B] tx_mac_last_s21/F
5.432 1.697 tNET RR 1 R4C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/I3
5.663 0.231 tINS RR 1 R4C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/F
5.784 0.121 tNET RR 1 R4C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/I0
6.039 0.255 tINS RF 4 R4C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/F
6.833 0.794 tNET FF 2 R2C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/I1
7.331 0.498 tINS FR 4 R2C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/SUM
7.839 0.508 tNET RR 1 R2C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/I1
8.302 0.463 tINS RR 4 R2C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/F
8.446 0.144 tNET RR 1 R2C126[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s8/I3
8.677 0.231 tINS RR 2 R2C126[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s8/F
8.800 0.123 tNET RR 1 R2C126[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s2/I1
9.206 0.406 tINS RR 1 R2C126[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s2/F
9.344 0.138 tNET RR 1 R3C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s0/I1
9.599 0.255 tINS RF 1 R3C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n102_s0/F
9.599 0.000 tNET FF 1 R3C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.125 2.726 tNET RR 1 R3C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_7_s1/CLK
9.080 -0.046 tSu 1 R3C126[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_7_s1

Path Statistics:

Clock Skew 0.006
Setup Relationship 6.400
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%
Arrival Data Path Delay cell: 2.704, 39.308%; route: 3.869, 56.244%; tC2Q: 0.306, 4.448%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.726, 100.000%

Path40

Path Summary:

Slack -0.511
Data Arrival Time 9.572
Data Required Time 9.061
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_61_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/CLK
2.985 0.294 tC2Q RF 82 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q
3.685 0.700 tNET FF 1 R6C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24476_s12/I0
4.148 0.463 tINS FR 2 R6C132[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24476_s12/F
5.762 1.614 tNET RR 1 R18C118[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s9/I2
6.127 0.365 tINS RR 1 R18C118[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s9/F
6.129 0.002 tNET RR 1 R18C118[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s5/I1
6.494 0.365 tINS RR 7 R18C118[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24460_s5/F
8.076 1.582 tNET RR 1 R6C136[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24452_s4/I0
8.530 0.454 tINS RR 1 R6C136[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24452_s4/F
8.532 0.002 tNET RR 1 R6C136[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24452_s1/I1
8.938 0.406 tINS RR 2 R6C136[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24452_s1/F
9.109 0.171 tNET RR 1 R8C136[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24420_s2/I0
9.572 0.463 tINS RR 1 R8C136[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24420_s2/F
9.572 0.000 tNET RR 1 R8C136[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_61_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.112 2.712 tNET RR 1 R8C136[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_61_s0/CLK
9.061 -0.051 tSu 1 R8C136[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_61_s0

Path Statistics:

Clock Skew 0.021
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 2.516, 36.564%; route: 4.071, 59.163%; tC2Q: 0.294, 4.273%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.712, 100.000%

Path41

Path Summary:

Slack -0.507
Data Arrival Time 9.552
Data Required Time 9.045
From byte_cnt_9_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_30_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.725 2.725 tNET RR 1 R25C117[1][B] byte_cnt_9_s1/CLK
3.031 0.306 tC2Q RR 3 R25C117[1][B] byte_cnt_9_s1/Q
3.156 0.125 tNET RR 1 R25C117[0][A] n702_s5/I1
3.619 0.463 tINS RR 1 R25C117[0][A] n702_s5/F
3.621 0.002 tNET RR 1 R25C117[3][A] n702_s3/I3
3.876 0.255 tINS RF 3 R25C117[3][A] n702_s3/F
4.009 0.133 tNET FF 1 R25C118[2][A] n702_s6/I1
4.240 0.231 tINS FR 3 R25C118[2][A] n702_s6/F
4.380 0.140 tNET RR 1 R24C118[2][B] tx_mac_byte_7_s2/I3
4.786 0.406 tINS RR 5 R24C118[2][B] tx_mac_byte_7_s2/F
5.842 1.056 tNET RR 1 R12C117[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s7/I0
6.073 0.231 tINS RR 1 R12C117[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s7/F
6.194 0.121 tNET RR 1 R12C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s4/I1
6.425 0.231 tINS RR 4 R12C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1175_s4/F
6.998 0.573 tNET RR 1 R9C117[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1159_s4/I0
7.229 0.231 tINS RR 2 R9C117[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1159_s4/F
7.400 0.171 tNET RR 1 R8C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1159_s3/I0
7.765 0.365 tINS RR 8 R8C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1159_s3/F
9.297 1.532 tNET RR 1 R14C138[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1153_s2/I1
9.552 0.255 tINS RF 1 R14C138[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/n1153_s2/F
9.552 0.000 tNET FF 1 R14C138[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_30_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.091 2.691 tNET RR 1 R14C138[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_30_s0/CLK
9.045 -0.046 tSu 1 R14C138[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/send_data_30_s0

Path Statistics:

Clock Skew -0.034
Setup Relationship 6.400
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.725, 100.000%
Arrival Data Path Delay cell: 2.668, 39.080%; route: 3.853, 56.438%; tC2Q: 0.306, 4.482%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%

Path42

Path Summary:

Slack -0.505
Data Arrival Time 9.582
Data Required Time 9.077
From c_tx_state_0_s5
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_4_s1
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.720 2.720 tNET RR 1 R24C118[0][B] c_tx_state_0_s5/CLK
3.026 0.306 tC2Q RR 22 R24C118[0][B] c_tx_state_0_s5/Q
3.370 0.344 tNET RR 1 R26C119[3][B] tx_mac_last_s21/I0
3.735 0.365 tINS RR 11 R26C119[3][B] tx_mac_last_s21/F
5.432 1.697 tNET RR 1 R4C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/I3
5.663 0.231 tINS RR 1 R4C117[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s3/F
5.784 0.121 tNET RR 1 R4C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/I0
6.039 0.255 tINS RF 4 R4C117[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_controller/tx_data_columns_Z_s/F
6.833 0.794 tNET FF 2 R2C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/I1
7.331 0.498 tINS FR 4 R2C128[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n54_s/SUM
7.839 0.508 tNET RR 1 R2C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/I1
8.302 0.463 tINS RR 4 R2C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n106_s5/F
8.446 0.144 tNET RR 1 R2C126[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s4/I1
8.677 0.231 tINS RR 1 R2C126[2][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s4/F
8.679 0.002 tNET RR 1 R2C126[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s1/I2
9.116 0.438 tINS RR 1 R2C126[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s1/F
9.118 0.002 tNET RR 1 R2C126[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s0/I0
9.582 0.463 tINS RR 1 R2C126[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/n105_s0/F
9.582 0.000 tNET RR 1 R2C126[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.128 2.728 tNET RR 1 R2C126[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_4_s1/CLK
9.077 -0.051 tSu 1 R2C126[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_user_if/ifg_columns_cnt_4_s1

Path Statistics:

Clock Skew 0.008
Setup Relationship 6.400
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%
Arrival Data Path Delay cell: 2.944, 42.903%; route: 3.612, 52.638%; tC2Q: 0.306, 4.459%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.728, 100.000%

Path43

Path Summary:

Slack -0.501
Data Arrival Time 9.578
Data Required Time 9.077
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_43_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/CLK
2.997 0.306 tC2Q RR 82 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q
4.584 1.587 tNET RR 1 R2C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s10/I2
4.990 0.406 tINS RR 10 R2C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s10/F
6.078 1.088 tNET RR 1 R20C119[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s9/I3
6.309 0.231 tINS RR 5 R20C119[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s9/F
8.193 1.884 tNET RR 1 R5C133[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24438_s7/I1
8.652 0.459 tINS RR 1 R5C133[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24438_s7/F
9.124 0.472 tNET RR 1 R2C134[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24438_s2/I1
9.578 0.454 tINS RR 1 R2C134[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24438_s2/F
9.578 0.000 tNET RR 1 R2C134[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_43_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.128 2.728 tNET RR 1 R2C134[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_43_s0/CLK
9.077 -0.051 tSu 1 R2C134[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_43_s0

Path Statistics:

Clock Skew 0.037
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 1.550, 22.506%; route: 5.031, 73.051%; tC2Q: 0.306, 4.443%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.728, 100.000%

Path44

Path Summary:

Slack -0.495
Data Arrival Time 9.334
Data Required Time 8.839
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_10_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.334 3.196 tNET RR 1 R33C127[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.088 2.688 tNET RR 1 R33C127[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_10_s0/CLK
8.839 -0.249 tSu 1 R33C127[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_10_s0

Path Statistics:

Clock Skew -0.045
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.892%; route: 5.378, 81.473%; tC2Q: 0.306, 4.636%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.688, 100.000%

Path45

Path Summary:

Slack -0.495
Data Arrival Time 9.334
Data Required Time 8.839
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_17_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.334 3.196 tNET RR 1 R33C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_17_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.088 2.688 tNET RR 1 R33C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_17_s0/CLK
8.839 -0.249 tSu 1 R33C127[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out2_17_s0

Path Statistics:

Clock Skew -0.045
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.892%; route: 5.378, 81.473%; tC2Q: 0.306, 4.636%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.688, 100.000%

Path46

Path Summary:

Slack -0.495
Data Arrival Time 9.334
Data Required Time 8.839
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_6_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.334 3.196 tNET RR 1 R33C127[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.088 2.688 tNET RR 1 R33C127[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_6_s0/CLK
8.839 -0.249 tSu 1 R33C127[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_6_s0

Path Statistics:

Clock Skew -0.045
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.892%; route: 5.378, 81.473%; tC2Q: 0.306, 4.636%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.688, 100.000%

Path47

Path Summary:

Slack -0.495
Data Arrival Time 9.334
Data Required Time 8.839
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_28_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.733 2.733 tNET RR 1 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/CLK
3.039 0.306 tC2Q RR 6 R39C125[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/ch_terminate_hit_pipe1_s0/Q
3.919 0.880 tNET RR 1 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/I1
4.382 0.463 tINS RR 5 R32C124[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/crc_be_2_s2/F
5.684 1.302 tNET RR 1 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/I0
6.138 0.454 tINS RR 258 R30C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out_en_s0/F
9.334 3.196 tNET RR 1 R33C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_28_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.088 2.688 tNET RR 1 R33C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_28_s0/CLK
8.839 -0.249 tSu 1 R33C127[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out1_28_s0

Path Statistics:

Clock Skew -0.045
Setup Relationship 6.400
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.733, 100.000%
Arrival Data Path Delay cell: 0.917, 13.892%; route: 5.378, 81.473%; tC2Q: 0.306, 4.636%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.688, 100.000%

Path48

Path Summary:

Slack -0.495
Data Arrival Time 9.554
Data Required Time 9.059
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_59_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.691 2.691 tNET RR 1 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/CLK
2.997 0.306 tC2Q RR 82 R14C134[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_cal_be_latch_2_s0/Q
4.584 1.587 tNET RR 1 R2C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s10/I2
4.990 0.406 tINS RR 10 R2C119[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24451_s10/F
6.459 1.469 tNET RR 1 R13C124[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s10/I3
6.714 0.255 tINS RF 5 R13C124[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s10/F
7.788 1.074 tNET FF 1 R7C133[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s5/I1
8.247 0.459 tINS FR 4 R7C133[3][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s5/F
8.422 0.175 tNET RR 1 R7C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s1/I1
8.885 0.463 tINS RR 2 R7C135[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24454_s1/F
8.889 0.004 tNET RR 1 R7C135[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24422_s3/I1
9.144 0.255 tINS RF 1 R7C135[3][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24422_s3/F
9.148 0.004 tNET FF 1 R7C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24422_s2/I2
9.554 0.406 tINS FR 1 R7C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n24422_s2/F
9.554 0.000 tNET RR 1 R7C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_59_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.110 2.710 tNET RR 1 R7C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_59_s0/CLK
9.059 -0.051 tSu 1 R7C135[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_59_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.691, 100.000%
Arrival Data Path Delay cell: 2.244, 32.697%; route: 4.313, 62.844%; tC2Q: 0.306, 4.459%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.710, 100.000%

Path49

Path Summary:

Slack -0.493
Data Arrival Time 9.372
Data Required Time 8.879
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe2_s1
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_8_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.686 2.686 tNET RR 1 R13C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe2_s1/CLK
2.980 0.294 tC2Q RF 39 R13C118[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe2_s1/Q
4.666 1.686 tNET FF 1 R13C134[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_31_s2/I1
4.897 0.231 tINS FR 256 R13C134[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_31_s2/F
9.372 4.475 tNET RR 1 R20C118[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.128 2.728 tNET RR 1 R20C118[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_8_s0/CLK
8.879 -0.249 tSu 1 R20C118[1][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_result0_8_s0

Path Statistics:

Clock Skew 0.042
Setup Relationship 6.400
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.686, 100.000%
Arrival Data Path Delay cell: 0.231, 3.455%; route: 6.161, 92.148%; tC2Q: 0.294, 4.397%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.728, 100.000%

Path50

Path Summary:

Slack -0.493
Data Arrival Time 9.554
Data Required Time 9.061
From u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_31_s0
To u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_16_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.686 2.686 tNET RR 1 R31C120[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_31_s0/CLK
2.992 0.306 tC2Q RR 33 R31C120[1][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_pipe2_31_s0/Q
5.075 2.083 tNET RR 1 R34C135[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n8038_s5/I0
5.481 0.406 tINS RR 3 R34C135[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n8038_s5/F
7.474 1.993 tNET RR 1 R29C136[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9987_s5/I3
7.705 0.231 tINS RR 1 R29C136[0][B] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9987_s5/F
8.111 0.406 tNET RR 1 R29C137[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9987_s6/I3
8.342 0.231 tINS RR 1 R29C137[2][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9987_s6/F
9.091 0.749 tNET RR 1 R26C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9987_s0/I1
9.554 0.463 tINS RR 1 R26C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n9987_s0/F
9.554 0.000 tNET RR 1 R26C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.112 2.712 tNET RR 1 R26C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_16_s0/CLK
9.061 -0.051 tSu 1 R26C138[0][A] u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/cal_crc_out7_16_s0

Path Statistics:

Clock Skew 0.026
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.686, 100.000%
Arrival Data Path Delay cell: 1.331, 19.380%; route: 5.231, 76.165%; tC2Q: 0.306, 4.455%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.712, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.023
Data Arrival Time 0.934
Data Required Time 0.911
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_20_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.697 0.697 tNET RR 1 R45C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_20_s0/CLK
0.841 0.144 tC2Q RR 1 R45C114[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_20_s0/Q
0.934 0.093 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[20]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.696 0.696 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKA
0.911 0.215 tHld 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path2

Path Summary:

Slack 0.023
Data Arrival Time 0.934
Data Required Time 0.911
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_19_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.697 0.697 tNET RR 1 R45C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_19_s0/CLK
0.841 0.144 tC2Q RR 1 R45C114[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_19_s0/Q
0.934 0.093 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[19]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.696 0.696 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKA
0.911 0.215 tHld 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path3

Path Summary:

Slack 0.051
Data Arrival Time 1.645
Data Required Time 1.594
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.400 1.400 tNET RR 1 R42C121[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/CLK
1.544 0.144 tC2Q RR 1 R42C121[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q
1.645 0.101 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.379 1.379 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.594 0.215 tHld 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.400, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.379, 100.000%

Path4

Path Summary:

Slack 0.113
Data Arrival Time 1.024
Data Required Time 0.911
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_34_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.706 0.706 tNET RR 1 R44C115[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_34_s0/CLK
0.850 0.144 tC2Q RR 1 R44C115[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_34_s0/Q
1.024 0.174 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[34]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.696 0.696 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKA
0.911 0.215 tHld 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.706, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path5

Path Summary:

Slack 0.113
Data Arrival Time 1.024
Data Required Time 0.911
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.706 0.706 tNET RR 1 R44C113[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_2_s0/CLK
0.850 0.144 tC2Q RR 1 R44C113[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_2_s0/Q
1.024 0.174 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.696 0.696 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKA
0.911 0.215 tHld 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.706, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path6

Path Summary:

Slack 0.119
Data Arrival Time 1.030
Data Required Time 0.911
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_22_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.697 0.697 tNET RR 1 R45C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_22_s0/CLK
0.841 0.144 tC2Q RR 1 R45C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_22_s0/Q
1.030 0.189 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[22]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.696 0.696 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKA
0.911 0.215 tHld 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path7

Path Summary:

Slack 0.119
Data Arrival Time 1.034
Data Required Time 0.915
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_54_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.701 0.701 tNET RR 1 R45C115[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_54_s0/CLK
0.845 0.144 tC2Q RR 1 R45C115[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_54_s0/Q
1.034 0.189 tNET RR 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/DI[18]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.700 0.700 tNET RR 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKA
0.915 0.215 tHld 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.700, 100.000%

Path8

Path Summary:

Slack 0.119
Data Arrival Time 1.034
Data Required Time 0.915
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_52_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.701 0.701 tNET RR 1 R45C115[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_52_s0/CLK
0.845 0.144 tC2Q RR 1 R45C115[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_52_s0/Q
1.034 0.189 tNET RR 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/DI[16]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.700 0.700 tNET RR 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKA
0.915 0.215 tHld 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.700, 100.000%

Path9

Path Summary:

Slack 0.122
Data Arrival Time 1.720
Data Required Time 1.598
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_61_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.400 1.400 tNET RR 1 R42C125[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_61_s0/CLK
1.544 0.144 tC2Q RR 1 R42C125[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_61_s0/Q
1.720 0.176 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[29]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.383 1.383 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.598 0.215 tHld 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.400, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.176, 55.000%; tC2Q: 0.144, 45.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.383, 100.000%

Path10

Path Summary:

Slack 0.123
Data Arrival Time 1.717
Data Required Time 1.594
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.384 1.384 tNET RR 1 R45C120[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/CLK
1.528 0.144 tC2Q RR 1 R45C120[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/Q
1.717 0.189 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.379 1.379 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.594 0.215 tHld 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.384, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.379, 100.000%

Path11

Path Summary:

Slack 0.123
Data Arrival Time 1.038
Data Required Time 0.915
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_4_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.705 0.705 tNET RR 1 R45C116[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_4_s0/CLK
0.849 0.144 tC2Q RR 1 R45C116[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_4_s0/Q
1.038 0.189 tNET RR 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/DI[32]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.700 0.700 tNET RR 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKA
0.915 0.215 tHld 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.705, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.700, 100.000%

Path12

Path Summary:

Slack 0.123
Data Arrival Time 1.034
Data Required Time 0.911
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.701 0.701 tNET RR 1 R45C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0/CLK
0.845 0.144 tC2Q RR 1 R45C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0/Q
1.034 0.189 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[35]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.696 0.696 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKA
0.911 0.215 tHld 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path13

Path Summary:

Slack 0.124
Data Arrival Time 1.039
Data Required Time 0.915
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_38_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.706 0.706 tNET RR 1 R44C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_38_s0/CLK
0.850 0.144 tC2Q RR 1 R44C115[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_38_s0/Q
1.039 0.189 tNET RR 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.700 0.700 tNET RR 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKA
0.915 0.215 tHld 1 BSRAM_R46[24] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.706, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.700, 100.000%

Path14

Path Summary:

Slack 0.127
Data Arrival Time 1.038
Data Required Time 0.911
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_25_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.705 0.705 tNET RR 1 R45C112[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_25_s0/CLK
0.849 0.144 tC2Q RR 1 R45C112[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_25_s0/Q
1.038 0.189 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[25]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.696 0.696 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKA
0.911 0.215 tHld 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.705, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path15

Path Summary:

Slack 0.129
Data Arrival Time 1.723
Data Required Time 1.594
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.390 1.390 tNET RR 1 R43C123[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK
1.534 0.144 tC2Q RR 1 R43C123[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q
1.723 0.189 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.379 1.379 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.594 0.215 tHld 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.379, 100.000%

Path16

Path Summary:

Slack 0.129
Data Arrival Time 1.723
Data Required Time 1.594
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.390 1.390 tNET RR 1 R43C123[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/CLK
1.534 0.144 tC2Q RR 1 R43C123[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q
1.723 0.189 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.379 1.379 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.594 0.215 tHld 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.011
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.379, 100.000%

Path17

Path Summary:

Slack 0.130
Data Arrival Time 1.041
Data Required Time 0.911
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.702 0.702 tNET RR 1 R44C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0/CLK
0.846 0.144 tC2Q RR 1 R44C114[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0/Q
1.041 0.195 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.696 0.696 tNET RR 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKA
0.911 0.215 tHld 1 BSRAM_R46[23][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.702, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path18

Path Summary:

Slack 0.135
Data Arrival Time 1.732
Data Required Time 1.598
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.397 1.397 tNET RR 1 R41C124[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/CLK
1.541 0.144 tC2Q RR 1 R41C124[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q
1.732 0.191 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.383 1.383 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.598 0.215 tHld 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.397, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.383, 100.000%

Path19

Path Summary:

Slack 0.135
Data Arrival Time 1.732
Data Required Time 1.598
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.397 1.397 tNET RR 1 R41C126[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/CLK
1.541 0.144 tC2Q RR 1 R41C126[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/Q
1.732 0.191 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.383 1.383 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.598 0.215 tHld 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.397, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.383, 100.000%

Path20

Path Summary:

Slack 0.135
Data Arrival Time 1.733
Data Required Time 1.598
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.398 1.398 tNET RR 1 R43C125[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/CLK
1.542 0.144 tC2Q RR 1 R43C125[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q
1.733 0.191 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[21]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.383 1.383 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.598 0.215 tHld 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.398, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.383, 100.000%

Path21

Path Summary:

Slack 0.135
Data Arrival Time 1.733
Data Required Time 1.598
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.398 1.398 tNET RR 1 R43C125[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/CLK
1.542 0.144 tC2Q RR 1 R43C125[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q
1.733 0.191 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[20]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.383 1.383 tNET RR 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.598 0.215 tHld 1 BSRAM_R46[26] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.398, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.383, 100.000%

Path22

Path Summary:

Slack 0.135
Data Arrival Time 1.729
Data Required Time 1.594
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.394 1.394 tNET RR 1 R43C122[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/CLK
1.538 0.144 tC2Q RR 1 R43C122[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q
1.729 0.191 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.379 1.379 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.594 0.215 tHld 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.015
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.394, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.379, 100.000%

Path23

Path Summary:

Slack 0.137
Data Arrival Time 1.731
Data Required Time 1.594
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.396 1.396 tNET RR 1 R42C122[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK
1.540 0.144 tC2Q RR 1 R42C122[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q
1.731 0.191 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[19]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.379 1.379 tNET RR 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.594 0.215 tHld 1 BSRAM_R46[25][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.396, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.379, 100.000%

Path24

Path Summary:

Slack 0.139
Data Arrival Time 1.732
Data Required Time 1.594
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.397 1.397 tNET RR 1 R41C128[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/CLK
1.541 0.144 tC2Q RR 1 R41C128[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/Q
1.732 0.191 tNET RR 1 BSRAM_R46[27][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.379 1.379 tNET RR 1 BSRAM_R46[27][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.594 0.215 tHld 1 BSRAM_R46[27][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew -0.018
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.397, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.379, 100.000%

Path25

Path Summary:

Slack 0.142
Data Arrival Time 1.736
Data Required Time 1.594
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_25_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.388 1.388 tNET RR 1 R9C109[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_25_s0/CLK
1.532 0.144 tC2Q RR 1 R9C109[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_25_s0/Q
1.736 0.204 tNET RR 1 BSRAM_R10[24][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[25]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.379 1.379 tNET RR 1 BSRAM_R10[24][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA
1.594 0.215 tHld 1 BSRAM_R10[24][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s

Path Statistics:

Clock Skew -0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.388, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.379, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -0.147
Data Arrival Time 8.989
Data Required Time 8.842
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.989 2.979 tNET FF 1 R42C130[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.120 2.720 tNET RR 1 R42C130[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
8.842 -0.278 tSu 1 R42C130[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5

Path Statistics:

Clock Skew 0.264
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.979, 89.379%; tC2Q: 0.354, 10.621%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%

Path2

Path Summary:

Slack -0.140
Data Arrival Time 8.989
Data Required Time 8.849
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.989 2.979 tNET FF 1 R42C129[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.127 2.727 tNET RR 1 R42C129[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
8.849 -0.278 tSu 1 R42C129[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew 0.271
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.979, 89.379%; tC2Q: 0.354, 10.621%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.727, 100.000%

Path3

Path Summary:

Slack -0.140
Data Arrival Time 8.989
Data Required Time 8.849
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.989 2.979 tNET FF 1 R42C129[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.127 2.727 tNET RR 1 R42C129[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
8.849 -0.278 tSu 1 R42C129[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.271
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.979, 89.379%; tC2Q: 0.354, 10.621%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.727, 100.000%

Path4

Path Summary:

Slack -0.140
Data Arrival Time 8.989
Data Required Time 8.849
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.989 2.979 tNET FF 1 R42C129[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.127 2.727 tNET RR 1 R42C129[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
8.849 -0.278 tSu 1 R42C129[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew 0.271
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.979, 89.379%; tC2Q: 0.354, 10.621%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.727, 100.000%

Path5

Path Summary:

Slack -0.140
Data Arrival Time 8.989
Data Required Time 8.849
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.989 2.979 tNET FF 1 R42C129[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.127 2.727 tNET RR 1 R42C129[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
8.849 -0.278 tSu 1 R42C129[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.271
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.979, 89.379%; tC2Q: 0.354, 10.621%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.727, 100.000%

Path6

Path Summary:

Slack -0.140
Data Arrival Time 8.989
Data Required Time 8.849
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.989 2.979 tNET FF 1 R42C129[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.127 2.727 tNET RR 1 R42C129[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
8.849 -0.278 tSu 1 R42C129[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew 0.271
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.979, 89.379%; tC2Q: 0.354, 10.621%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.727, 100.000%

Path7

Path Summary:

Slack -0.134
Data Arrival Time 8.968
Data Required Time 8.834
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.968 2.958 tNET FF 1 R44C128[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.112 2.712 tNET RR 1 R44C128[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK
8.834 -0.278 tSu 1 R44C128[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0

Path Statistics:

Clock Skew 0.256
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.958, 89.312%; tC2Q: 0.354, 10.688%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.712, 100.000%

Path8

Path Summary:

Slack 0.027
Data Arrival Time 8.807
Data Required Time 8.834
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.807 2.797 tNET FF 1 R42C127[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.112 2.712 tNET RR 1 R42C127[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
8.834 -0.278 tSu 1 R42C127[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.256
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.797, 88.765%; tC2Q: 0.354, 11.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.712, 100.000%

Path9

Path Summary:

Slack 0.027
Data Arrival Time 8.807
Data Required Time 8.834
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.807 2.797 tNET FF 1 R42C127[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.112 2.712 tNET RR 1 R42C127[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
8.834 -0.278 tSu 1 R42C127[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew 0.256
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.797, 88.765%; tC2Q: 0.354, 11.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.712, 100.000%

Path10

Path Summary:

Slack 0.034
Data Arrival Time 8.787
Data Required Time 8.821
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.787 2.777 tNET FF 1 R45C127[3][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.099 2.699 tNET RR 1 R45C127[3][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
8.821 -0.278 tSu 1 R45C127[3][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew 0.243
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.777, 88.694%; tC2Q: 0.354, 11.306%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.699, 100.000%

Path11

Path Summary:

Slack 0.034
Data Arrival Time 8.787
Data Required Time 8.821
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.787 2.777 tNET FF 1 R45C127[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.099 2.699 tNET RR 1 R45C127[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
8.821 -0.278 tSu 1 R45C127[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew 0.243
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.777, 88.694%; tC2Q: 0.354, 11.306%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.699, 100.000%

Path12

Path Summary:

Slack 0.035
Data Arrival Time 8.807
Data Required Time 8.842
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.807 2.797 tNET FF 1 R42C128[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.120 2.720 tNET RR 1 R42C128[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
8.842 -0.278 tSu 1 R42C128[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.264
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.797, 88.765%; tC2Q: 0.354, 11.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%

Path13

Path Summary:

Slack 0.035
Data Arrival Time 8.807
Data Required Time 8.842
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.807 2.797 tNET FF 1 R42C128[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.120 2.720 tNET RR 1 R42C128[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
8.842 -0.278 tSu 1 R42C128[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.264
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.797, 88.765%; tC2Q: 0.354, 11.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%

Path14

Path Summary:

Slack 0.035
Data Arrival Time 8.807
Data Required Time 8.842
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.807 2.797 tNET FF 1 R42C128[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.120 2.720 tNET RR 1 R42C128[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
8.842 -0.278 tSu 1 R42C128[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew 0.264
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.797, 88.765%; tC2Q: 0.354, 11.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%

Path15

Path Summary:

Slack 0.040
Data Arrival Time 8.787
Data Required Time 8.826
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/gt_flag_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.787 2.777 tNET FF 1 R44C127[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/gt_flag_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.104 2.704 tNET RR 1 R44C127[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/gt_flag_s0/CLK
8.826 -0.278 tSu 1 R44C127[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/gt_flag_s0

Path Statistics:

Clock Skew 0.249
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.777, 88.694%; tC2Q: 0.354, 11.306%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.704, 100.000%

Path16

Path Summary:

Slack 0.040
Data Arrival Time 8.787
Data Required Time 8.826
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/lt_flag_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.787 2.777 tNET FF 1 R44C127[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/lt_flag_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.104 2.704 tNET RR 1 R44C127[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/lt_flag_s0/CLK
8.826 -0.278 tSu 1 R44C127[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/lt_flag_s0

Path Statistics:

Clock Skew 0.249
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.777, 88.694%; tC2Q: 0.354, 11.306%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.704, 100.000%

Path17

Path Summary:

Slack 0.040
Data Arrival Time 8.787
Data Required Time 8.826
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/ge_flag_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.787 2.777 tNET FF 1 R44C127[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/ge_flag_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.104 2.704 tNET RR 1 R44C127[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/ge_flag_s0/CLK
8.826 -0.278 tSu 1 R44C127[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/ge_flag_s0

Path Statistics:

Clock Skew 0.249
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.777, 88.694%; tC2Q: 0.354, 11.306%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.704, 100.000%

Path18

Path Summary:

Slack 0.040
Data Arrival Time 8.787
Data Required Time 8.826
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/le_flag_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.787 2.777 tNET FF 1 R44C127[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/le_flag_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.104 2.704 tNET RR 1 R44C127[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/le_flag_s0/CLK
8.826 -0.278 tSu 1 R44C127[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/le_flag_s0

Path Statistics:

Clock Skew 0.249
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.777, 88.694%; tC2Q: 0.354, 11.306%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.704, 100.000%

Path19

Path Summary:

Slack 0.220
Data Arrival Time 8.612
Data Required Time 8.832
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.612 2.602 tNET FF 1 R43C127[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.110 2.710 tNET RR 1 R43C127[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
8.832 -0.278 tSu 1 R43C127[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.254
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.602, 88.024%; tC2Q: 0.354, 11.976%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.710, 100.000%

Path20

Path Summary:

Slack 0.228
Data Arrival Time 8.612
Data Required Time 8.840
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.612 2.602 tNET FF 1 R43C128[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.118 2.718 tNET RR 1 R43C128[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
8.840 -0.278 tSu 1 R43C128[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew 0.262
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.602, 88.024%; tC2Q: 0.354, 11.976%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.718, 100.000%

Path21

Path Summary:

Slack 0.267
Data Arrival Time 8.575
Data Required Time 8.842
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.575 2.565 tNET FF 1 R42C126[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.120 2.720 tNET RR 1 R42C126[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
8.842 -0.278 tSu 1 R42C126[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew 0.264
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.565, 87.873%; tC2Q: 0.354, 12.127%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%

Path22

Path Summary:

Slack 0.267
Data Arrival Time 8.575
Data Required Time 8.842
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.575 2.565 tNET FF 1 R42C126[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.120 2.720 tNET RR 1 R42C126[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
8.842 -0.278 tSu 1 R42C126[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew 0.264
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.565, 87.873%; tC2Q: 0.354, 12.127%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%

Path23

Path Summary:

Slack 0.267
Data Arrival Time 8.575
Data Required Time 8.842
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.575 2.565 tNET FF 1 R42C126[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.120 2.720 tNET RR 1 R42C126[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
8.842 -0.278 tSu 1 R42C126[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew 0.264
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.565, 87.873%; tC2Q: 0.354, 12.127%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.720, 100.000%

Path24

Path Summary:

Slack 0.548
Data Arrival Time 8.292
Data Required Time 8.840
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.292 2.282 tNET FF 1 R43C136[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.118 2.718 tNET RR 1 R43C136[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
8.840 -0.278 tSu 1 R43C136[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew 0.262
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.282, 86.571%; tC2Q: 0.354, 13.429%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.718, 100.000%

Path25

Path Summary:

Slack 0.548
Data Arrival Time 8.292
Data Required Time 8.840
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk xgmii_clk:[F]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.200 3.200 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.656 2.456 tNET FF 1 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.010 0.354 tC2Q FF 52 R42C126[0][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.292 2.282 tNET FF 1 R43C136[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
9.118 2.718 tNET RR 1 R43C136[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
8.840 -0.278 tSu 1 R43C136[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew 0.262
Setup Relationship 3.200
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.282, 86.571%; tC2Q: 0.354, 13.429%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.718, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.467
Data Arrival Time 1.169
Data Required Time 0.702
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s
Launch Clk serdes_tx_clk:[R]
Latch Clk serdes_tx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
0.715 0.715 tNET RR 1 R5C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK
0.859 0.144 tC2Q RR 356 R5C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q
1.169 0.311 tNET RR 36 BSRAM_R10[24][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_tx_clk
0.000 0.000 tCL RR 643 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
0.692 0.692 tNET RR 1 BSRAM_R10[24][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKB
0.702 0.010 tHld 1 BSRAM_R10[24][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s

Path Statistics:

Clock Skew -0.022
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.311, 68.352%; tC2Q: 0.144, 31.648%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.692, 100.000%

Path2

Path Summary:

Slack 0.487
Data Arrival Time 1.034
Data Required Time 0.547
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_14_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.698 0.698 tNET RR 1 R36C105[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/CLK
0.842 0.144 tC2Q RR 458 R36C105[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q
1.034 0.192 tNET RR 1 R36C103[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.698 0.698 tNET RR 1 R36C103[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_14_s0/CLK
0.547 -0.151 tHld 1 R36C103[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.698, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.192, 57.143%; tC2Q: 0.144, 42.857%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.698, 100.000%

Path3

Path Summary:

Slack 0.489
Data Arrival Time 1.741
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_0_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C105[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C105[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_0_s0/CLK
1.252 -0.151 tHld 1 R4C105[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_0_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path4

Path Summary:

Slack 0.489
Data Arrival Time 1.741
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_0_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C105[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C105[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_0_s0/CLK
1.252 -0.151 tHld 1 R4C105[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_0_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path5

Path Summary:

Slack 0.489
Data Arrival Time 1.741
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_12_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C105[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C105[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_12_s0/CLK
1.252 -0.151 tHld 1 R4C105[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_12_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path6

Path Summary:

Slack 0.489
Data Arrival Time 1.741
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_0_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C105[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C105[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_0_s0/CLK
1.252 -0.151 tHld 1 R4C105[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_0_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path7

Path Summary:

Slack 0.489
Data Arrival Time 1.741
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_12_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C105[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C105[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_12_s0/CLK
1.252 -0.151 tHld 1 R4C105[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_12_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path8

Path Summary:

Slack 0.489
Data Arrival Time 1.741
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C105[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C105[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0/CLK
1.252 -0.151 tHld 1 R4C105[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path9

Path Summary:

Slack 0.489
Data Arrival Time 1.741
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_12_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C105[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C105[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_12_s0/CLK
1.252 -0.151 tHld 1 R4C105[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_12_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path10

Path Summary:

Slack 0.491
Data Arrival Time 1.743
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_CL_s56
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C109[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_CL_s56/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C109[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_CL_s56/CLK
1.252 -0.151 tHld 1 R4C109[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_CL_s56

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path11

Path Summary:

Slack 0.491
Data Arrival Time 1.743
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_13_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_13_s0/CLK
1.252 -0.151 tHld 1 R4C109[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_13_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path12

Path Summary:

Slack 0.491
Data Arrival Time 1.743
Data Required Time 1.252
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_46_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_46_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.403 1.403 tNET RR 1 R4C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_46_s0/CLK
1.252 -0.151 tHld 1 R4C109[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_46_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.403, 100.000%

Path13

Path Summary:

Slack 0.493
Data Arrival Time 1.036
Data Required Time 0.543
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_9_s0
Launch Clk serdes_rx_clk:[R]
Latch Clk serdes_rx_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.692 0.692 tNET RR 1 R35C94[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/CLK
0.836 0.144 tC2Q RR 1100 R35C94[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q
1.036 0.199 tNET RR 1 R36C94[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_rx_clk
0.000 0.000 tCL RR 2035 R0C38 u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
0.694 0.694 tNET RR 1 R36C94[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_9_s0/CLK
0.543 -0.151 tHld 1 R36C94[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_9_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.692, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.199, 58.017%; tC2Q: 0.144, 41.983%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.694, 100.000%

Path14

Path Summary:

Slack 0.493
Data Arrival Time 1.741
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/sync_header_tmp_0_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C106[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/sync_header_tmp_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C106[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/sync_header_tmp_0_s0/CLK
1.248 -0.151 tHld 1 R4C106[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/sync_header_tmp_0_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path15

Path Summary:

Slack 0.493
Data Arrival Time 1.741
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/idle_char_d2_5_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C106[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/idle_char_d2_5_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C106[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/idle_char_d2_5_s0/CLK
1.248 -0.151 tHld 1 R4C106[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/idle_char_d2_5_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path16

Path Summary:

Slack 0.493
Data Arrival Time 1.741
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_46_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C106[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_46_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C106[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_46_s0/CLK
1.248 -0.151 tHld 1 R4C106[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_46_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path17

Path Summary:

Slack 0.493
Data Arrival Time 1.741
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_46_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C106[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_46_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C106[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_46_s0/CLK
1.248 -0.151 tHld 1 R4C106[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_46_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path18

Path Summary:

Slack 0.493
Data Arrival Time 1.741
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_45_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.741 0.202 tNET RR 1 R4C106[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_45_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C106[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_45_s0/CLK
1.248 -0.151 tHld 1 R4C106[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_45_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path19

Path Summary:

Slack 0.495
Data Arrival Time 1.743
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_11_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C108[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C108[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_11_s0/CLK
1.248 -0.151 tHld 1 R4C108[2][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_11_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path20

Path Summary:

Slack 0.495
Data Arrival Time 1.743
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_15_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C108[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C108[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_15_s0/CLK
1.248 -0.151 tHld 1 R4C108[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_15_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path21

Path Summary:

Slack 0.495
Data Arrival Time 1.743
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_19_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C108[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_19_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C108[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_19_s0/CLK
1.248 -0.151 tHld 1 R4C108[0][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_19_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path22

Path Summary:

Slack 0.495
Data Arrival Time 1.743
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_21_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C108[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_21_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C108[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_21_s0/CLK
1.248 -0.151 tHld 1 R4C108[3][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_21_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path23

Path Summary:

Slack 0.495
Data Arrival Time 1.743
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_44_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C108[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_44_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C108[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_44_s0/CLK
1.248 -0.151 tHld 1 R4C108[2][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_44_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path24

Path Summary:

Slack 0.495
Data Arrival Time 1.743
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_52_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_52_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_52_s0/CLK
1.248 -0.151 tHld 1 R4C108[1][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_52_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Path25

Path Summary:

Slack 0.495
Data Arrival Time 1.743
Data Required Time 1.248
From u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0
To u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_62_s0
Launch Clk xgmii_clk:[R]
Latch Clk xgmii_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.395 1.395 tNET RR 1 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK
1.539 0.144 tC2Q RR 1257 R4C107[0][A] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q
1.743 0.204 tNET RR 1 R4C108[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_62_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR 3930 R0C38 u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
1.399 1.399 tNET RR 1 R4C108[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_62_s0/CLK
1.248 -0.151 tHld 1 R4C108[1][B] u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_62_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.395, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.399, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 1.277
Actual Width: 2.139
Required Width: 0.862
Type: Low Pulse Width
Clock: xgmii_clk
Objects: u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.644 2.444 tNET FF u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
7.783 1.383 tNET RR u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA

MPW2

MPW Summary:

Slack: 1.277
Actual Width: 2.139
Required Width: 0.862
Type: Low Pulse Width
Clock: xgmii_clk
Objects: u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.644 2.444 tNET FF u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
7.783 1.383 tNET RR u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKB

MPW3

MPW Summary:

Slack: 1.277
Actual Width: 2.139
Required Width: 0.862
Type: Low Pulse Width
Clock: xgmii_clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.644 2.444 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
7.783 1.383 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW4

MPW Summary:

Slack: 1.281
Actual Width: 2.143
Required Width: 0.862
Type: Low Pulse Width
Clock: xgmii_clk
Objects: u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.636 2.436 tNET FF u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
7.779 1.379 tNET RR u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKB

MPW5

MPW Summary:

Slack: 1.281
Actual Width: 2.143
Required Width: 0.862
Type: Low Pulse Width
Clock: xgmii_clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.636 2.436 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
7.779 1.379 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW6

MPW Summary:

Slack: 1.281
Actual Width: 2.143
Required Width: 0.862
Type: Low Pulse Width
Clock: xgmii_clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.636 2.436 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
7.779 1.379 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW7

MPW Summary:

Slack: 1.281
Actual Width: 2.143
Required Width: 0.862
Type: Low Pulse Width
Clock: xgmii_clk
Objects: u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
5.636 2.436 tNET FF u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 xgmii_clk
6.400 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
7.779 1.379 tNET RR u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA

MPW8

MPW Summary:

Slack: 1.290
Actual Width: 2.152
Required Width: 0.862
Type: High Pulse Width
Clock: xgmii_clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.708 2.708 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
4.860 1.660 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW9

MPW Summary:

Slack: 1.290
Actual Width: 2.152
Required Width: 0.862
Type: High Pulse Width
Clock: xgmii_clk
Objects: u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.708 2.708 tNET RR u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
4.860 1.660 tNET FF u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKB

MPW10

MPW Summary:

Slack: 1.290
Actual Width: 2.152
Required Width: 0.862
Type: High Pulse Width
Clock: xgmii_clk
Objects: u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 xgmii_clk
0.000 0.000 tCL RR u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
2.708 2.708 tNET RR u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 xgmii_clk
3.200 0.000 tCL FF u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O
4.860 1.660 tNET FF u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
3930 tx_mac_clk -0.573 2.735
2035 q1_lane1_fabric_rx_clk 0.828 1.605
1614 block_lock 0.936 3.230
643 q1_lane1_fabric_tx_clk -0.360 1.605
584 descrambler_valid_out 1.907 3.787
356 baser_tx_rstn_d2 2.933 1.578
353 control0[0] 20.522 4.567
349 vld_rd_d1 3.297 2.258
267 cnt[2] 2.515 2.936
258 cal_crc_out_en -0.554 3.320

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R16C123 90.28%
R32C129 87.50%
R16C126 87.50%
R32C132 86.11%
R33C134 86.11%
R6C122 86.11%
R6C125 86.11%
R31C133 86.11%
R30C132 86.11%
R12C121 86.11%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name serdes_tx_clk -period 6.173 -waveform {0 3.087} [get_nets {u_SerDes_Top/q1_lane1_fabric_tx_clk}]
TC_CLOCK Actived create_clock -name serdes_rx_clk -period 6.173 -waveform {0 3.087} [get_nets {u_SerDes_Top/q1_lane1_fabric_rx_clk}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_nets {tck_pad_i}]
TC_CLOCK Actived create_clock -name xgmii_clk -period 6.4 -waveform {0 3.2} [get_nets {tx_mac_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {serdes_rx_clk}] -group [get_clocks {serdes_tx_clk}] -group [get_clocks {xgmii_clk}] -group [get_clocks {tck_pad_i}]
TC_REPORT_TIMING Actived report_timing -setup -from_clock [get_clocks {serdes_rx_clk}] -to_clock [get_clocks {serdes_rx_clk}] -max_paths 50 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -setup -from_clock [get_clocks {serdes_tx_clk}] -to_clock [get_clocks {serdes_tx_clk}] -max_paths 50 -max_common_paths 1
TC_REPORT_TIMING Actived report_timing -setup -from_clock [get_clocks {xgmii_clk}] -to_clock [get_clocks {xgmii_clk}] -max_paths 50 -max_common_paths 1