Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\RefDesign\1.9.9\Gowin_10G_Serial_Ethernet_RefDesign\fpga_project\impl\gwsynthesis\fpga_project.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\RefDesign\1.9.9\Gowin_10G_Serial_Ethernet_RefDesign\fpga_project\src\fpga_project.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\RefDesign\1.9.9\Gowin_10G_Serial_Ethernet_RefDesign\fpga_project\src\fpga_project.sdc |
Tool Version | V1.9.9 (64-bit) |
Part Number | GW5AST-LV138FPG676AC2/I1 |
Device | GW5AST-138B |
Device Version | B |
Created Time | Mon Dec 4 11:27:32 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.85V -40C C2/I1 |
Hold Delay Model | Fast 0.95V 100C C2/I1 |
Numbers of Paths Analyzed | 11491 |
Numbers of Endpoints Analyzed | 16072 |
Numbers of Falling Endpoints | 10 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i | ||
xgmii_clk | Base | 6.400 | 156.250 | 0.000 | 3.200 | ref_clk | ||
serdes_rx_clk | Base | 6.173 | 161.996 | 0.000 | 3.087 | u_SerDes_Top/q1_lane1_fabric_rx_clk | ||
serdes_tx_clk | Base | 6.173 | 161.996 | 0.000 | 3.087 | u_SerDes_Top/q1_lane1_fabric_tx_clk |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | tck_pad_i | 20.000(MHz) | 96.592(MHz) | 6 | TOP |
2 | xgmii_clk | 156.250(MHz) | 183.444(MHz) | 6 | TOP |
3 | serdes_rx_clk | 161.996(MHz) | 170.387(MHz) | 6 | TOP |
4 | serdes_tx_clk | 161.996(MHz) | 163.265(MHz) | 4 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
xgmii_clk | Setup | 0.000 | 0 |
xgmii_clk | Hold | 0.000 | 0 |
serdes_rx_clk | Setup | 0.000 | 0 |
serdes_rx_clk | Hold | 0.000 | 0 |
serdes_tx_clk | Setup | 0.000 | 0 |
serdes_tx_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Setup Paths Table[1]:
Report Command:report_timing -setup -from_clock [get_clocks {serdes_rx_clk}] -to_clock [get_clocks {serdes_rx_clk}] -max_paths 50 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.304 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.030 | 5.848 |
2 | 0.304 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.030 | 5.848 |
3 | 0.479 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.030 | 5.673 |
4 | 0.576 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_56_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.024 | 5.570 |
5 | 0.691 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_40_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.040 | 5.471 |
6 | 0.691 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_c0_d5_7_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.073 | 5.358 |
7 | 0.727 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.039 | 5.356 |
8 | 0.748 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_48_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.040 | 5.414 |
9 | 0.753 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_0_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.082 | 5.452 |
10 | 0.805 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_60_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.022 | 5.339 |
11 | 0.827 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_48_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.030 | 5.325 |
12 | 0.849 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_37_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.025 | 5.298 |
13 | 0.861 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.003 | 5.264 |
14 | 0.862 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.049 | 5.309 |
15 | 0.870 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.032 | 5.284 |
16 | 0.876 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_40_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.023 | 5.268 |
17 | 0.927 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_54_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.037 | 5.232 |
18 | 0.931 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_37_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.039 | 5.152 |
19 | 0.941 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_56_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.065 | 5.246 |
20 | 0.942 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_28_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.008 | 5.188 |
21 | 0.942 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_52_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.032 | 5.212 |
22 | 0.945 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.039 | 5.216 |
23 | 0.947 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 5.138 |
24 | 0.947 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 5.138 |
25 | 0.947 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 5.138 |
26 | 0.955 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.029 | 5.138 |
27 | 0.971 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.041 | 5.110 |
28 | 0.988 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 5.097 |
29 | 1.008 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_36_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.032 | 5.146 |
30 | 1.039 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_49_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.005 | 5.078 |
31 | 1.040 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_53_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.012 | 5.071 |
32 | 1.040 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_58_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.012 | 5.071 |
33 | 1.042 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_44_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.030 | 5.110 |
34 | 1.069 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 4.818 |
35 | 1.069 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_10_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 4.818 |
36 | 1.069 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 4.818 |
37 | 1.069 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 4.818 |
38 | 1.069 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 4.818 |
39 | 1.069 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 4.818 |
40 | 1.069 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.037 | 4.818 |
41 | 1.077 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.029 | 4.818 |
42 | 1.077 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.029 | 4.818 |
43 | 1.079 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_0_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.075 | 5.118 |
44 | 1.088 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_38_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.034 | 5.068 |
45 | 1.090 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.047 | 5.079 |
46 | 1.090 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_61_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.010 | 5.042 |
47 | 1.091 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_49_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.038 | 5.069 |
48 | 1.094 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_46_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.037 | 5.065 |
49 | 1.112 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_53_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.038 | 5.048 |
50 | 1.116 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.065 | 5.071 |
Setup Paths Table[2]:
Report Command:report_timing -setup -from_clock [get_clocks {serdes_tx_clk}] -to_clock [get_clocks {serdes_tx_clk}] -max_paths 50 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.048 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.013 | 6.087 |
2 | 0.058 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.006 | 6.070 |
3 | 0.454 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_42_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.002 | 5.666 |
4 | 0.622 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 5.500 |
5 | 0.690 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.011 | 5.420 |
6 | 0.698 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_28_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.004 | 5.420 |
7 | 0.918 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_31_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.013 | 5.191 |
8 | 0.923 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_38_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.003 | 5.196 |
9 | 0.956 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_55_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.023 | 5.143 |
10 | 0.959 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 5.163 |
11 | 1.002 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.008 | 5.112 |
12 | 1.013 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_18_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 5.109 |
13 | 1.017 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_47_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.016 | 5.089 |
14 | 1.023 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_39_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.010 | 5.089 |
15 | 1.130 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_16_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.006 | 4.986 |
16 | 1.141 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_18_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.008 | 4.988 |
17 | 1.162 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.009 | 4.951 |
18 | 1.187 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_45_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.015 | 4.920 |
19 | 1.207 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_52_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.003 | 4.918 |
20 | 1.210 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0/CE | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.002 | 4.716 |
21 | 1.293 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_26_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.007 | 4.821 |
22 | 1.293 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_26_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.007 | 4.821 |
23 | 1.303 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_48_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.016 | 4.803 |
24 | 1.357 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_10_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.010 | 4.755 |
25 | 1.367 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_44_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.004 | 4.751 |
26 | 1.380 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.004 | 4.738 |
27 | 1.381 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_14_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.006 | 4.735 |
28 | 1.414 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_34_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 4.708 |
29 | 1.419 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_44_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.004 | 4.699 |
30 | 1.419 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.008 | 4.695 |
31 | 1.432 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.007 | 4.683 |
32 | 1.443 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.006 | 4.673 |
33 | 1.459 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.004 | 4.659 |
34 | 1.462 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 4.660 |
35 | 1.465 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_29_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.008 | 4.665 |
36 | 1.469 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.016 | 4.637 |
37 | 1.482 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_13_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.008 | 4.648 |
38 | 1.498 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.002 | 4.625 |
39 | 1.503 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_23_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.008 | 4.611 |
40 | 1.511 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_32_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.008 | 4.603 |
41 | 1.519 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.002 | 4.601 |
42 | 1.521 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_13_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 4.601 |
43 | 1.534 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 4.588 |
44 | 1.542 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_21_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.010 | 4.570 |
45 | 1.561 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_5_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.007 | 4.553 |
46 | 1.564 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.003 | 4.561 |
47 | 1.580 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_56_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.029 | 4.513 |
48 | 1.584 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_61_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.015 | 4.522 |
49 | 1.588 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.021 | 4.513 |
50 | 1.601 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_14_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.013 | 4.534 |
Setup Paths Table[3]:
Report Command:report_timing -setup -from_clock [get_clocks {xgmii_clk}] -to_clock [get_clocks {xgmii_clk}] -max_paths 50 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.949 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_44_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.062 | 5.338 |
2 | 0.949 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_47_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.062 | 5.338 |
3 | 1.018 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_46_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.065 | 5.266 |
4 | 1.043 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_45_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.070 | 5.236 |
5 | 1.258 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_2_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.003 | 5.094 |
6 | 1.258 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_d3_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.003 | 5.094 |
7 | 1.296 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.007 | 4.848 |
8 | 1.308 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CE | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.011 | 4.854 |
9 | 1.308 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CE | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.011 | 4.854 |
10 | 1.308 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CE | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.011 | 4.854 |
11 | 1.357 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_49_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.005 | 4.997 |
12 | 1.367 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.002 | 4.984 |
13 | 1.394 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_50_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.049 | 4.906 |
14 | 1.442 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CE | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.007 | 4.716 |
15 | 1.442 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CE | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.007 | 4.716 |
16 | 1.503 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_0_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.012 | 4.834 |
17 | 1.506 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.002 | 4.845 |
18 | 1.506 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.002 | 4.845 |
19 | 1.587 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.003 | 4.759 |
20 | 1.599 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_48_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.062 | 4.688 |
21 | 1.632 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_ODDD_d3_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.002 | 4.719 |
22 | 1.660 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_30_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.063 | 4.752 |
23 | 1.662 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_55_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.050 | 4.637 |
24 | 1.675 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.000 | 4.674 |
25 | 1.675 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.000 | 4.674 |
26 | 1.734 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_54_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.060 | 4.555 |
27 | 1.744 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_31_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.054 | 4.551 |
28 | 1.751 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_CCCC_d3_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.068 | 4.531 |
29 | 1.838 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_42_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.070 | 4.441 |
30 | 1.854 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_32_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.057 | 4.438 |
31 | 1.877 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.007 | 4.464 |
32 | 1.877 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.007 | 4.464 |
33 | 1.877 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.007 | 4.464 |
34 | 1.904 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.000 | 4.445 |
35 | 1.957 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.007 | 4.385 |
36 | 2.030 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_33_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.057 | 4.262 |
37 | 2.037 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_52_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.013 | 4.325 |
38 | 2.045 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_1_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.012 | 4.292 |
39 | 2.087 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_location_d3_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.000 | 4.262 |
40 | 2.100 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_ODDD_d3_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.003 | 4.252 |
41 | 2.128 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_d3_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.000 | 4.221 |
42 | 2.139 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_11_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.014 | 4.196 |
43 | 2.173 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_20_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.047 | 4.223 |
44 | 2.202 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DO[4] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.025 | 4.172 |
45 | 2.227 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_CCCC_d3_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.068 | 4.055 |
46 | 2.245 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/data_pattern_select_d1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/seed_init_51_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.010 | 4.154 |
47 | 2.249 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_5_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.016 | 4.084 |
48 | 2.249 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_7_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.016 | 4.084 |
49 | 2.249 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_9_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.016 | 4.084 |
50 | 2.250 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DO[7] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_7_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.025 | 4.124 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.027 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_28_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[28] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.005 | 0.237 |
2 | 0.031 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_21_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[21] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.009 | 0.237 |
3 | 0.031 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_15_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[15] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.009 | 0.237 |
4 | 0.051 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_59_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[23] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.021 | 0.245 |
5 | 0.051 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_51_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[15] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.021 | 0.245 |
6 | 0.051 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_39_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[3] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.021 | 0.245 |
7 | 0.051 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_38_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[2] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.021 | 0.245 |
8 | 0.055 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_65_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[29] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.025 | 0.245 |
9 | 0.117 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_49_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[13] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.014 | 0.318 |
10 | 0.130 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_10_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[10] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.006 | 0.339 |
11 | 0.135 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_54_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[18] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.015 | 0.335 |
12 | 0.135 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_46_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[10] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.015 | 0.335 |
13 | 0.137 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_58_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[22] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.019 | 0.333 |
14 | 0.137 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_57_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[21] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.019 | 0.333 |
15 | 0.137 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_25_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[25] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.019 | 0.333 |
16 | 0.139 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_6_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[6] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.019 | 0.335 |
17 | 0.141 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_55_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[19] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.021 | 0.335 |
18 | 0.141 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_26_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[26] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.017 | 0.339 |
19 | 0.141 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_62_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[26] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.023 | 0.333 |
20 | 0.145 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_47_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[11] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.021 | 0.339 |
21 | 0.147 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_23_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[23] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.021 | 0.341 |
22 | 0.148 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_30_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[30] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.005 | 0.358 |
23 | 0.148 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_29_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[29] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.005 | 0.358 |
24 | 0.152 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_22_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[22] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.009 | 0.358 |
25 | 0.163 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_13_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[13] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.005 | 0.373 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.113 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/RESET | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.025 | 5.657 |
2 | 0.382 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C2_I_E_sel_d4_5_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.018 | 5.722 |
3 | 0.382 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_2_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.018 | 5.722 |
4 | 0.382 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_5_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.018 | 5.722 |
5 | 0.382 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_7_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.018 | 5.722 |
6 | 0.547 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C6_I_E_sel_d4_5_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.021 | 5.554 |
7 | 0.547 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_7_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.021 | 5.554 |
8 | 0.547 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/terminate_char_d2_4_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.021 | 5.554 |
9 | 0.624 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/RESET | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.018 | 5.154 |
10 | 0.716 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_43_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.032 | 5.374 |
11 | 0.716 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.032 | 5.374 |
12 | 0.716 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/start_char_d2_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.032 | 5.374 |
13 | 0.716 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.032 | 5.374 |
14 | 0.721 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.027 | 5.374 |
15 | 0.722 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved5_char_d2_4_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.021 | 5.379 |
16 | 0.722 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved4_char_d2_4_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.021 | 5.379 |
17 | 0.748 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_4_s0/CLEAR | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.007 | 5.154 |
18 | 0.748 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_4_s0/CLEAR | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.007 | 5.154 |
19 | 0.749 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_3_s0/CLEAR | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.006 | 5.140 |
20 | 0.749 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_3_s0/CLEAR | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.006 | 5.140 |
21 | 0.749 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_2_s0/CLEAR | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.006 | 5.140 |
22 | 0.749 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_3_s0/CLEAR | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.006 | 5.140 |
23 | 0.879 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved3_char_d2_2_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.044 | 5.199 |
24 | 0.879 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved2_char_d2_2_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.044 | 5.199 |
25 | 0.879 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_2_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.044 | 5.199 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.483 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d4_7_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.336 |
2 | 0.483 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d3_7_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.336 |
3 | 0.483 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d2_7_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.336 |
4 | 0.491 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198/CLEAR | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 0.000 | -0.006 | 0.346 |
5 | 0.491 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_49_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.002 | 0.342 |
6 | 0.492 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_9_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.005 | 0.346 |
7 | 0.492 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_10_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.005 | 0.346 |
8 | 0.492 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_62_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.005 | 0.346 |
9 | 0.493 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_46_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.003 | 0.338 |
10 | 0.493 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_58_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.003 | 0.338 |
11 | 0.493 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_3_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.012 | 0.354 |
12 | 0.493 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_33_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.012 | 0.354 |
13 | 0.493 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_35_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.012 | 0.354 |
14 | 0.493 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_3_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.012 | 0.354 |
15 | 0.493 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_35_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.012 | 0.354 |
16 | 0.495 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d5_35_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.010 | 0.354 |
17 | 0.495 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_35_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.010 | 0.354 |
18 | 0.495 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_35_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.010 | 0.354 |
19 | 0.495 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_35_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.010 | 0.354 |
20 | 0.495 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_rd_d2_7_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.010 | 0.354 |
21 | 0.499 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_30_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.004 | 0.352 |
22 | 0.499 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_30_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.004 | 0.352 |
23 | 0.499 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_30_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.004 | 0.352 |
24 | 0.499 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_30_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.004 | 0.352 |
25 | 0.499 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_27_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.004 | 0.352 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 0.347 | 1.209 | 0.862 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
2 | 0.347 | 1.209 | 0.862 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
3 | 0.347 | 1.209 | 0.862 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s |
4 | 0.351 | 1.213 | 0.862 | Low Pulse Width | xgmii_clk | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
5 | 0.351 | 1.213 | 0.862 | Low Pulse Width | xgmii_clk | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s |
6 | 0.351 | 1.213 | 0.862 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
7 | 0.351 | 1.213 | 0.862 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
8 | 0.351 | 1.213 | 0.862 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
9 | 0.351 | 1.213 | 0.862 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
10 | 0.354 | 1.216 | 0.862 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Timing Report By Analysis Type:
Setup Analysis Report
Setup Analysis Report[1]:
Report Command:report_timing -setup -from_clock [get_clocks {serdes_rx_clk}] -to_clock [get_clocks {serdes_rx_clk}] -max_paths 50 -max_common_paths 1
Path1
Path Summary:
Slack | 0.304 |
Data Arrival Time | 8.099 |
Data Required Time | 8.403 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
5.390 | 1.048 | tNET | RR | 1 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/I2 |
5.852 | 0.463 | tINS | RR | 4 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/F |
5.859 | 0.006 | tNET | RR | 1 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/I3 |
6.318 | 0.459 | tINS | RR | 16 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/F |
7.693 | 1.375 | tNET | RR | 1 | R75C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3123_s10/I0 |
8.099 | 0.406 | tINS | RR | 1 | R75C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3123_s10/F |
8.099 | 0.000 | tNET | RR | 1 | R75C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.453 | 2.281 | tNET | RR | 1 | R75C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0/CLK |
8.403 | -0.051 | tSu | 1 | R75C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_51_s0 |
Path Statistics:
Clock Skew | 0.030 |
Setup Relationship | 6.173 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 2.250, 38.475%; route: 3.292, 56.293%; tC2Q: 0.306, 5.233% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.281, 100.000% |
Path2
Path Summary:
Slack | 0.304 |
Data Arrival Time | 8.099 |
Data Required Time | 8.403 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
5.390 | 1.048 | tNET | RR | 1 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/I2 |
5.852 | 0.463 | tINS | RR | 4 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/F |
5.859 | 0.006 | tNET | RR | 1 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/I3 |
6.318 | 0.459 | tINS | RR | 16 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/F |
7.693 | 1.375 | tNET | RR | 1 | R75C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s10/I0 |
8.099 | 0.406 | tINS | RR | 1 | R75C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s10/F |
8.099 | 0.000 | tNET | RR | 1 | R75C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.453 | 2.281 | tNET | RR | 1 | R75C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0/CLK |
8.403 | -0.051 | tSu | 1 | R75C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_55_s0 |
Path Statistics:
Clock Skew | 0.030 |
Setup Relationship | 6.173 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 2.250, 38.475%; route: 3.292, 56.293%; tC2Q: 0.306, 5.233% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.281, 100.000% |
Path3
Path Summary:
Slack | 0.479 |
Data Arrival Time | 7.924 |
Data Required Time | 8.403 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
5.390 | 1.048 | tNET | RR | 1 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/I2 |
5.852 | 0.463 | tINS | RR | 4 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/F |
5.859 | 0.006 | tNET | RR | 1 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/I3 |
6.318 | 0.459 | tINS | RR | 16 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/F |
7.693 | 1.375 | tNET | RR | 1 | R75C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3129_s10/I0 |
7.924 | 0.231 | tINS | RR | 1 | R75C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3129_s10/F |
7.924 | 0.000 | tNET | RR | 1 | R75C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.453 | 2.281 | tNET | RR | 1 | R75C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0/CLK |
8.403 | -0.051 | tSu | 1 | R75C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0 |
Path Statistics:
Clock Skew | 0.030 |
Setup Relationship | 6.173 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 2.075, 36.577%; route: 3.292, 58.029%; tC2Q: 0.306, 5.394% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.281, 100.000% |
Path4
Path Summary:
Slack | 0.576 |
Data Arrival Time | 7.869 |
Data Required Time | 8.445 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_56_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1139_s3/I2 |
6.028 | 0.463 | tINS | FR | 4 | R65C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1139_s3/F |
7.406 | 1.378 | tNET | RR | 1 | R59C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n919_s2/I1 |
7.869 | 0.463 | tINS | RR | 1 | R59C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n919_s2/F |
7.869 | 0.000 | tNET | RR | 1 | R59C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_56_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.496 | 2.323 | tNET | RR | 1 | R59C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_56_s0/CLK |
8.445 | -0.051 | tSu | 1 | R59C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_56_s0 |
Path Statistics:
Clock Skew | 0.024 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.926, 16.624%; route: 4.350, 78.098%; tC2Q: 0.294, 5.278% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.323, 100.000% |
Path5
Path Summary:
Slack | 0.691 |
Data Arrival Time | 7.721 |
Data Required Time | 8.412 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_40_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
6.851 | 2.509 | tNET | RR | 1 | R74C148[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3134_s12/I0 |
7.257 | 0.406 | tINS | RR | 1 | R74C148[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3134_s12/F |
7.259 | 0.002 | tNET | RR | 1 | R74C148[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3134_s10/I1 |
7.721 | 0.463 | tINS | RR | 1 | R74C148[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3134_s10/F |
7.721 | 0.000 | tNET | RR | 1 | R74C148[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_40_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.463 | 2.290 | tNET | RR | 1 | R74C148[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_40_s0/CLK |
8.412 | -0.051 | tSu | 1 | R74C148[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_40_s0 |
Path Statistics:
Clock Skew | 0.040 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 1.791, 32.736%; route: 3.374, 61.671%; tC2Q: 0.306, 5.593% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.290, 100.000% |
Path6
Path Summary:
Slack | 0.691 |
Data Arrival Time | 7.677 |
Data Required Time | 8.368 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_c0_d5_7_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.319 | 2.319 | tNET | RR | 1 | R61C142[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_c0_d5_7_s0/CLK |
2.625 | 0.306 | tC2Q | RR | 3 | R61C142[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_c0_d5_7_s0/Q |
3.511 | 0.886 | tNET | RR | 1 | R67C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s16/I0 |
3.970 | 0.459 | tINS | RR | 2 | R67C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s16/F |
4.277 | 0.307 | tNET | RR | 1 | R67C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s12/I1 |
4.731 | 0.454 | tINS | RR | 3 | R67C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s12/F |
5.617 | 0.886 | tNET | RR | 1 | R62C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s13/I3 |
6.071 | 0.454 | tINS | RR | 2 | R62C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s13/F |
6.639 | 0.568 | tNET | RR | 1 | R71C146[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s14/I2 |
7.102 | 0.463 | tINS | RR | 1 | R71C146[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s14/F |
7.223 | 0.121 | tNET | RR | 1 | R71C146[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s13/I1 |
7.677 | 0.454 | tINS | RR | 1 | R71C146[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s13/F |
7.677 | 0.000 | tNET | RR | 1 | R71C146[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.419 | 2.246 | tNET | RR | 1 | R71C146[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0/CLK |
8.368 | -0.051 | tSu | 1 | R71C146[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0 |
Path Statistics:
Clock Skew | -0.073 |
Setup Relationship | 6.173 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.319, 100.000% |
Arrival Data Path Delay | cell: 2.284, 42.628%; route: 2.768, 51.661%; tC2Q: 0.306, 5.711% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.246, 100.000% |
Path7
Path Summary:
Slack | 0.727 |
Data Arrival Time | 7.692 |
Data Required Time | 8.419 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/I2 |
5.348 | 0.406 | tINS | RR | 36 | R71C134[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1591_s3/F |
7.239 | 1.891 | tNET | RR | 1 | R69C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1653_s1/I2 |
7.693 | 0.454 | tINS | RR | 1 | R69C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1653_s1/F |
7.693 | 0.000 | tNET | RR | 1 | R69C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.470 | 2.297 | tNET | RR | 1 | R69C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0/CLK |
8.419 | -0.051 | tSu | 1 | R69C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_5_s0 |
Path Statistics:
Clock Skew | -0.039 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.688, 31.516%; route: 3.362, 62.771%; tC2Q: 0.306, 5.713% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.297, 100.000% |
Path8
Path Summary:
Slack | 0.748 |
Data Arrival Time | 7.665 |
Data Required Time | 8.412 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_48_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
6.851 | 2.509 | tNET | RR | 1 | R74C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s11/I1 |
7.257 | 0.406 | tINS | RR | 1 | R74C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s11/F |
7.259 | 0.002 | tNET | RR | 1 | R74C148[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s10/I0 |
7.665 | 0.406 | tINS | RR | 1 | R74C148[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3126_s10/F |
7.665 | 0.000 | tNET | RR | 1 | R74C148[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_48_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.463 | 2.290 | tNET | RR | 1 | R74C148[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_48_s0/CLK |
8.412 | -0.051 | tSu | 1 | R74C148[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_48_s0 |
Path Statistics:
Clock Skew | 0.040 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 1.734, 32.028%; route: 3.374, 62.320%; tC2Q: 0.306, 5.652% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.290, 100.000% |
Path9
Path Summary:
Slack | 0.753 |
Data Arrival Time | 7.712 |
Data Required Time | 8.464 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_0_s1 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.260 | 2.260 | tNET | RR | 1 | R70C148[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_0_s1/CLK |
2.566 | 0.306 | tC2Q | RR | 55 | R70C148[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_0_s1/Q |
4.464 | 1.898 | tNET | RR | 1 | R76C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s14/I1 |
4.918 | 0.454 | tINS | RR | 6 | R76C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s14/F |
5.538 | 0.620 | tNET | RR | 1 | R70C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/I1 |
5.769 | 0.231 | tINS | RR | 16 | R70C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/F |
7.258 | 1.489 | tNET | RR | 1 | R75C144[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3152_s10/I0 |
7.712 | 0.454 | tINS | RR | 1 | R75C144[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3152_s10/F |
7.712 | 0.000 | tNET | RR | 1 | R75C144[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.515 | 2.342 | tNET | RR | 1 | R75C144[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0/CLK |
8.464 | -0.051 | tSu | 1 | R75C144[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_22_s0 |
Path Statistics:
Clock Skew | 0.082 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.260, 100.000% |
Arrival Data Path Delay | cell: 1.139, 20.891%; route: 4.007, 73.496%; tC2Q: 0.306, 5.613% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.342, 100.000% |
Path10
Path Summary:
Slack | 0.805 |
Data Arrival Time | 7.638 |
Data Required Time | 8.443 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_60_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/I2 |
6.024 | 0.459 | tINS | FR | 4 | R65C122[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/F |
7.232 | 1.208 | tNET | RR | 1 | R62C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n915_s2/I0 |
7.638 | 0.406 | tINS | RR | 1 | R62C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n915_s2/F |
7.638 | 0.000 | tNET | RR | 1 | R62C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_60_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.494 | 2.321 | tNET | RR | 1 | R62C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_60_s0/CLK |
8.443 | -0.051 | tSu | 1 | R62C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_60_s0 |
Path Statistics:
Clock Skew | 0.022 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.865, 16.201%; route: 4.180, 78.293%; tC2Q: 0.294, 5.506% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.321, 100.000% |
Path11
Path Summary:
Slack | 0.827 |
Data Arrival Time | 7.624 |
Data Required Time | 8.451 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_48_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1139_s3/I2 |
6.028 | 0.463 | tINS | FR | 4 | R65C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1139_s3/F |
7.161 | 1.133 | tNET | RR | 1 | R60C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1131_s3/I0 |
7.624 | 0.463 | tINS | RR | 1 | R60C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1131_s3/F |
7.624 | 0.000 | tNET | RR | 1 | R60C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_48_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.502 | 2.329 | tNET | RR | 1 | R60C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_48_s0/CLK |
8.451 | -0.051 | tSu | 1 | R60C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_48_s0 |
Path Statistics:
Clock Skew | 0.030 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.926, 17.389%; route: 4.105, 77.090%; tC2Q: 0.294, 5.521% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.329, 100.000% |
Path12
Path Summary:
Slack | 0.849 |
Data Arrival Time | 7.549 |
Data Required Time | 8.397 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_37_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
6.682 | 2.340 | tNET | RR | 1 | R74C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s11/I3 |
7.088 | 0.406 | tINS | RR | 1 | R74C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s11/F |
7.090 | 0.002 | tNET | RR | 1 | R74C146[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s10/I0 |
7.549 | 0.459 | tINS | RR | 1 | R74C146[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s10/F |
7.549 | 0.000 | tNET | RR | 1 | R74C146[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_37_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.448 | 2.275 | tNET | RR | 1 | R74C146[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_37_s0/CLK |
8.397 | -0.051 | tSu | 1 | R74C146[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_37_s0 |
Path Statistics:
Clock Skew | 0.025 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 1.787, 33.730%; route: 3.205, 60.495%; tC2Q: 0.306, 5.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.275, 100.000% |
Path13
Path Summary:
Slack | 0.861 |
Data Arrival Time | 7.515 |
Data Required Time | 8.376 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
5.390 | 1.048 | tNET | RR | 1 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/I2 |
5.852 | 0.463 | tINS | RR | 4 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/F |
5.859 | 0.006 | tNET | RR | 1 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/I3 |
6.318 | 0.459 | tINS | RR | 16 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/F |
7.061 | 0.743 | tNET | RR | 1 | R71C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3121_s10/I0 |
7.515 | 0.454 | tINS | RR | 1 | R71C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3121_s10/F |
7.515 | 0.000 | tNET | RR | 1 | R71C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.427 | 2.254 | tNET | RR | 1 | R71C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0/CLK |
8.376 | -0.051 | tSu | 1 | R71C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 6.173 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 2.298, 43.655%; route: 2.660, 50.532%; tC2Q: 0.306, 5.813% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.254, 100.000% |
Path14
Path Summary:
Slack | 0.862 |
Data Arrival Time | 7.596 |
Data Required Time | 8.459 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.288 | 2.288 | tNET | RR | 1 | R67C142[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0/CLK |
2.594 | 0.306 | tC2Q | RR | 7 | R67C142[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0/Q |
3.106 | 0.512 | tNET | RR | 1 | R66C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3164_s16/I2 |
3.560 | 0.454 | tINS | RR | 9 | R66C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3164_s16/F |
4.145 | 0.585 | tNET | RR | 1 | R70C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/I1 |
4.551 | 0.406 | tINS | RR | 4 | R70C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/F |
5.059 | 0.508 | tNET | RR | 1 | R69C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s12/I0 |
5.522 | 0.463 | tINS | RR | 5 | R69C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s12/F |
7.142 | 1.621 | tNET | RR | 1 | R74C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3153_s10/I3 |
7.596 | 0.454 | tINS | RR | 1 | R74C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3153_s10/F |
7.596 | 0.000 | tNET | RR | 1 | R74C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.510 | 2.337 | tNET | RR | 1 | R74C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0/CLK |
8.459 | -0.051 | tSu | 1 | R74C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_21_s0 |
Path Statistics:
Clock Skew | 0.049 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.288, 100.000% |
Arrival Data Path Delay | cell: 1.777, 33.471%; route: 3.226, 60.765%; tC2Q: 0.306, 5.764% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Path15
Path Summary:
Slack | 0.870 |
Data Arrival Time | 7.535 |
Data Required Time | 8.405 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
6.682 | 2.340 | tNET | RR | 1 | R74C146[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3117_s10/I1 |
6.913 | 0.231 | tINS | RR | 1 | R74C146[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3117_s10/F |
7.081 | 0.168 | tNET | RR | 1 | R74C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3117_s9/I2 |
7.535 | 0.454 | tINS | RR | 1 | R74C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3117_s9/F |
7.535 | 0.000 | tNET | RR | 1 | R74C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.455 | 2.283 | tNET | RR | 1 | R74C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0/CLK |
8.405 | -0.051 | tSu | 1 | R74C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_57_s0 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 1.607, 30.413%; route: 3.371, 63.796%; tC2Q: 0.306, 5.791% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.283, 100.000% |
Path16
Path Summary:
Slack | 0.876 |
Data Arrival Time | 7.567 |
Data Required Time | 8.443 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_40_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1139_s3/I2 |
6.028 | 0.463 | tINS | FR | 4 | R65C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1139_s3/F |
7.161 | 1.133 | tNET | RR | 1 | R60C126[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1139_s4/I1 |
7.567 | 0.406 | tINS | RR | 1 | R60C126[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1139_s4/F |
7.567 | 0.000 | tNET | RR | 1 | R60C126[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_40_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.494 | 2.321 | tNET | RR | 1 | R60C126[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_40_s0/CLK |
8.443 | -0.051 | tSu | 1 | R60C126[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_40_s0 |
Path Statistics:
Clock Skew | 0.023 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.869, 16.495%; route: 4.105, 77.924%; tC2Q: 0.294, 5.581% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.321, 100.000% |
Path17
Path Summary:
Slack | 0.927 |
Data Arrival Time | 7.531 |
Data Required Time | 8.458 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_54_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1141_s3/I2 |
6.019 | 0.454 | tINS | FR | 4 | R65C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1141_s3/F |
7.077 | 1.058 | tNET | RR | 1 | R60C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n921_s2/I1 |
7.531 | 0.454 | tINS | RR | 1 | R60C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n921_s2/F |
7.531 | 0.000 | tNET | RR | 1 | R60C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_54_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.509 | 2.336 | tNET | RR | 1 | R60C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_54_s0/CLK |
8.458 | -0.051 | tSu | 1 | R60C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_54_s0 |
Path Statistics:
Clock Skew | 0.037 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.908, 17.354%; route: 4.030, 77.027%; tC2Q: 0.294, 5.619% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.336, 100.000% |
Path18
Path Summary:
Slack | 0.931 |
Data Arrival Time | 7.488 |
Data Required Time | 8.419 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_37_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1 |
5.307 | 0.365 | tINS | RR | 36 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F |
7.026 | 1.719 | tNET | RR | 1 | R69C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1621_s1/I2 |
7.489 | 0.463 | tINS | RR | 1 | R69C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1621_s1/F |
7.489 | 0.000 | tNET | RR | 1 | R69C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_37_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.470 | 2.297 | tNET | RR | 1 | R69C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_37_s0/CLK |
8.419 | -0.051 | tSu | 1 | R69C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_37_s0 |
Path Statistics:
Clock Skew | -0.039 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.656, 32.143%; route: 3.190, 61.918%; tC2Q: 0.306, 5.939% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.297, 100.000% |
Path19
Path Summary:
Slack | 0.941 |
Data Arrival Time | 7.497 |
Data Required Time | 8.437 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_56_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
5.390 | 1.048 | tNET | RR | 1 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/I2 |
5.852 | 0.463 | tINS | RR | 4 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/F |
5.859 | 0.006 | tNET | RR | 1 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/I3 |
6.318 | 0.459 | tINS | RR | 16 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/F |
7.090 | 0.773 | tNET | RR | 1 | R71C144[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3118_s10/I0 |
7.497 | 0.406 | tINS | RR | 1 | R71C144[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3118_s10/F |
7.497 | 0.000 | tNET | RR | 1 | R71C144[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_56_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.488 | 2.315 | tNET | RR | 1 | R71C144[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_56_s0/CLK |
8.437 | -0.051 | tSu | 1 | R71C144[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_56_s0 |
Path Statistics:
Clock Skew | 0.065 |
Setup Relationship | 6.173 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 2.250, 42.890%; route: 2.690, 51.277%; tC2Q: 0.306, 5.833% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.315, 100.000% |
Path20
Path Summary:
Slack | 0.942 |
Data Arrival Time | 7.476 |
Data Required Time | 8.417 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_28_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.288 | 2.288 | tNET | RR | 1 | R67C142[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0/CLK |
2.594 | 0.306 | tC2Q | RR | 7 | R67C142[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0/Q |
3.106 | 0.512 | tNET | RR | 1 | R66C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3164_s16/I2 |
3.560 | 0.454 | tINS | RR | 9 | R66C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3164_s16/F |
4.145 | 0.585 | tNET | RR | 1 | R70C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/I1 |
4.551 | 0.406 | tINS | RR | 4 | R70C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/F |
5.059 | 0.508 | tNET | RR | 1 | R69C145[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s13/I0 |
5.522 | 0.463 | tINS | RR | 5 | R69C145[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s13/F |
7.022 | 1.500 | tNET | RR | 1 | R67C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3146_s10/I3 |
7.476 | 0.454 | tINS | RR | 1 | R67C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3146_s10/F |
7.476 | 0.000 | tNET | RR | 1 | R67C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_28_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.468 | 2.295 | tNET | RR | 1 | R67C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_28_s0/CLK |
8.417 | -0.051 | tSu | 1 | R67C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_28_s0 |
Path Statistics:
Clock Skew | 0.008 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.288, 100.000% |
Arrival Data Path Delay | cell: 1.777, 34.252%; route: 3.105, 59.850%; tC2Q: 0.306, 5.898% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.295, 100.000% |
Path21
Path Summary:
Slack | 0.942 |
Data Arrival Time | 7.511 |
Data Required Time | 8.453 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_52_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/I2 |
6.024 | 0.459 | tINS | FR | 4 | R65C122[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/F |
7.280 | 1.256 | tNET | RR | 1 | R59C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n923_s2/I1 |
7.511 | 0.231 | tINS | RR | 1 | R59C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n923_s2/F |
7.511 | 0.000 | tNET | RR | 1 | R59C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_52_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.503 | 2.331 | tNET | RR | 1 | R59C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_52_s0/CLK |
8.453 | -0.051 | tSu | 1 | R59C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_52_s0 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.690, 13.238%; route: 4.228, 81.121%; tC2Q: 0.294, 5.641% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.331, 100.000% |
Path22
Path Summary:
Slack | 0.945 |
Data Arrival Time | 7.515 |
Data Required Time | 8.460 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/I2 |
6.024 | 0.459 | tINS | FR | 4 | R65C122[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/F |
7.061 | 1.037 | tNET | RR | 1 | R59C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s5/I1 |
7.515 | 0.454 | tINS | RR | 1 | R59C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s5/F |
7.515 | 0.000 | tNET | RR | 1 | R59C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.511 | 2.338 | tNET | RR | 1 | R59C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0/CLK |
8.460 | -0.051 | tSu | 1 | R59C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0 |
Path Statistics:
Clock Skew | 0.039 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.913, 17.503%; route: 4.009, 76.861%; tC2Q: 0.294, 5.636% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.338, 100.000% |
Path23
Path Summary:
Slack | 0.947 |
Data Arrival Time | 7.474 |
Data Required Time | 8.422 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1 |
5.279 | 0.337 | tINS | RF | 36 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F |
7.069 | 1.790 | tNET | FF | 1 | R68C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1625_s1/I2 |
7.475 | 0.406 | tINS | FR | 1 | R68C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1625_s1/F |
7.475 | 0.000 | tNET | RR | 1 | R68C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0/CLK |
8.422 | -0.051 | tSu | 1 | R68C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.571, 30.576%; route: 3.261, 63.468%; tC2Q: 0.306, 5.956% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path24
Path Summary:
Slack | 0.947 |
Data Arrival Time | 7.474 |
Data Required Time | 8.422 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1 |
5.279 | 0.337 | tINS | RF | 36 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F |
7.069 | 1.790 | tNET | FF | 1 | R68C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1618_s1/I2 |
7.475 | 0.406 | tINS | FR | 1 | R68C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1618_s1/F |
7.475 | 0.000 | tNET | RR | 1 | R68C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0/CLK |
8.422 | -0.051 | tSu | 1 | R68C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.571, 30.576%; route: 3.261, 63.468%; tC2Q: 0.306, 5.956% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path25
Path Summary:
Slack | 0.947 |
Data Arrival Time | 7.474 |
Data Required Time | 8.422 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1 |
5.279 | 0.337 | tINS | RF | 36 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F |
7.069 | 1.790 | tNET | FF | 1 | R68C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1616_s1/I2 |
7.475 | 0.406 | tINS | FR | 1 | R68C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1616_s1/F |
7.475 | 0.000 | tNET | RR | 1 | R68C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0/CLK |
8.422 | -0.051 | tSu | 1 | R68C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.571, 30.576%; route: 3.261, 63.468%; tC2Q: 0.306, 5.956% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path26
Path Summary:
Slack | 0.955 |
Data Arrival Time | 7.474 |
Data Required Time | 8.429 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1 |
5.279 | 0.337 | tINS | RF | 36 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F |
7.069 | 1.790 | tNET | FF | 1 | R68C136[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1623_s1/I2 |
7.475 | 0.406 | tINS | FR | 1 | R68C136[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1623_s1/F |
7.475 | 0.000 | tNET | RR | 1 | R68C136[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.480 | 2.307 | tNET | RR | 1 | R68C136[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0/CLK |
8.429 | -0.051 | tSu | 1 | R68C136[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0 |
Path Statistics:
Clock Skew | -0.029 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.571, 30.576%; route: 3.261, 63.468%; tC2Q: 0.306, 5.956% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.307, 100.000% |
Path27
Path Summary:
Slack | 0.971 |
Data Arrival Time | 7.446 |
Data Required Time | 8.417 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1 |
5.307 | 0.365 | tINS | RR | 36 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F |
7.216 | 1.909 | tNET | RR | 1 | R67C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1622_s1/I2 |
7.447 | 0.231 | tINS | RR | 1 | R67C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1622_s1/F |
7.447 | 0.000 | tNET | RR | 1 | R67C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.468 | 2.295 | tNET | RR | 1 | R67C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0/CLK |
8.417 | -0.051 | tSu | 1 | R67C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_36_s0 |
Path Statistics:
Clock Skew | -0.041 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.424, 27.867%; route: 3.380, 66.145%; tC2Q: 0.306, 5.988% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.295, 100.000% |
Path28
Path Summary:
Slack | 0.988 |
Data Arrival Time | 7.433 |
Data Required Time | 8.422 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1 |
5.279 | 0.337 | tINS | RF | 36 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F |
7.069 | 1.790 | tNET | FF | 1 | R68C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1589_s1/I2 |
7.434 | 0.365 | tINS | FR | 1 | R68C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1589_s1/F |
7.434 | 0.000 | tNET | RR | 1 | R68C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0/CLK |
8.422 | -0.051 | tSu | 1 | R68C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.530, 30.018%; route: 3.261, 63.979%; tC2Q: 0.306, 6.004% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path29
Path Summary:
Slack | 1.008 |
Data Arrival Time | 7.445 |
Data Required Time | 8.453 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_36_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.605 | 0.306 | tC2Q | RR | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.081 | 2.476 | tNET | RR | 1 | R63C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1159_s3/I2 |
5.544 | 0.463 | tINS | RR | 6 | R63C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1159_s3/F |
7.080 | 1.536 | tNET | RR | 1 | R59C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n939_s2/I1 |
7.445 | 0.365 | tINS | RR | 1 | R59C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n939_s2/F |
7.445 | 0.000 | tNET | RR | 1 | R59C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_36_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.503 | 2.331 | tNET | RR | 1 | R59C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_36_s0/CLK |
8.453 | -0.051 | tSu | 1 | R59C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_36_s0 |
Path Statistics:
Clock Skew | 0.032 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.828, 16.089%; route: 4.012, 77.965%; tC2Q: 0.306, 5.946% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.331, 100.000% |
Path30
Path Summary:
Slack | 1.039 |
Data Arrival Time | 7.328 |
Data Required Time | 8.368 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_49_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
6.425 | 2.084 | tNET | RR | 1 | R68C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3125_s10/I0 |
6.864 | 0.438 | tINS | RR | 1 | R68C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3125_s10/F |
6.865 | 0.002 | tNET | RR | 1 | R68C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3125_s9/I3 |
7.328 | 0.463 | tINS | RR | 1 | R68C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3125_s9/F |
7.328 | 0.000 | tNET | RR | 1 | R68C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_49_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.419 | 2.246 | tNET | RR | 1 | R68C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_49_s0/CLK |
8.368 | -0.051 | tSu | 1 | R68C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_49_s0 |
Path Statistics:
Clock Skew | -0.005 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 1.823, 35.900%; route: 2.949, 58.074%; tC2Q: 0.306, 6.026% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.246, 100.000% |
Path31
Path Summary:
Slack | 1.040 |
Data Arrival Time | 7.407 |
Data Required Time | 8.447 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_53_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1 |
5.307 | 0.365 | tINS | RR | 36 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F |
7.002 | 1.695 | tNET | RR | 1 | R76C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1605_s1/I2 |
7.408 | 0.406 | tINS | RR | 1 | R76C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1605_s1/F |
7.408 | 0.000 | tNET | RR | 1 | R76C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_53_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.498 | 2.325 | tNET | RR | 1 | R76C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_53_s0/CLK |
8.447 | -0.051 | tSu | 1 | R76C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_53_s0 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.599, 31.532%; route: 3.166, 62.433%; tC2Q: 0.306, 6.034% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.325, 100.000% |
Path32
Path Summary:
Slack | 1.040 |
Data Arrival Time | 7.407 |
Data Required Time | 8.447 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_58_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/I1 |
5.307 | 0.365 | tINS | RR | 36 | R71C134[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1587_s2/F |
7.002 | 1.695 | tNET | RR | 1 | R76C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1600_s1/I2 |
7.408 | 0.406 | tINS | RR | 1 | R76C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/n1600_s1/F |
7.408 | 0.000 | tNET | RR | 1 | R76C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_58_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.498 | 2.325 | tNET | RR | 1 | R76C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_58_s0/CLK |
8.447 | -0.051 | tSu | 1 | R76C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_58_s0 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.599, 31.532%; route: 3.166, 62.433%; tC2Q: 0.306, 6.034% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.325, 100.000% |
Path33
Path Summary:
Slack | 1.042 |
Data Arrival Time | 7.409 |
Data Required Time | 8.451 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_44_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/I2 |
6.024 | 0.459 | tINS | FR | 4 | R65C122[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/F |
6.946 | 0.922 | tNET | RR | 1 | R60C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1135_s3/I0 |
7.409 | 0.463 | tINS | RR | 1 | R60C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1135_s3/F |
7.409 | 0.000 | tNET | RR | 1 | R60C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_44_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.502 | 2.329 | tNET | RR | 1 | R60C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_44_s0/CLK |
8.451 | -0.051 | tSu | 1 | R60C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_44_s0 |
Path Statistics:
Clock Skew | 0.030 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.922, 18.042%; route: 3.894, 76.205%; tC2Q: 0.294, 5.753% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.329, 100.000% |
Path34
Path Summary:
Slack | 1.069 |
Data Arrival Time | 7.155 |
Data Required Time | 8.224 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2 |
5.348 | 0.406 | tINS | RR | 73 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F |
7.155 | 1.807 | tNET | RR | 1 | R68C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0/CLK |
8.224 | -0.249 | tSu | 1 | R68C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_7_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.234, 25.612%; route: 3.278, 68.037%; tC2Q: 0.306, 6.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path35
Path Summary:
Slack | 1.069 |
Data Arrival Time | 7.155 |
Data Required Time | 8.224 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_10_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2 |
5.348 | 0.406 | tINS | RR | 73 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F |
7.155 | 1.807 | tNET | RR | 1 | R68C135[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_10_s0/CLK |
8.224 | -0.249 | tSu | 1 | R68C135[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_10_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.234, 25.612%; route: 3.278, 68.037%; tC2Q: 0.306, 6.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path36
Path Summary:
Slack | 1.069 |
Data Arrival Time | 7.155 |
Data Required Time | 8.224 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2 |
5.348 | 0.406 | tINS | RR | 73 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F |
7.155 | 1.807 | tNET | RR | 1 | R68C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0/CLK |
8.224 | -0.249 | tSu | 1 | R68C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_33_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.234, 25.612%; route: 3.278, 68.037%; tC2Q: 0.306, 6.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path37
Path Summary:
Slack | 1.069 |
Data Arrival Time | 7.155 |
Data Required Time | 8.224 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2 |
5.348 | 0.406 | tINS | RR | 73 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F |
7.155 | 1.807 | tNET | RR | 1 | R68C135[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0/CLK |
8.224 | -0.249 | tSu | 1 | R68C135[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_39_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.234, 25.612%; route: 3.278, 68.037%; tC2Q: 0.306, 6.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path38
Path Summary:
Slack | 1.069 |
Data Arrival Time | 7.155 |
Data Required Time | 8.224 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2 |
5.348 | 0.406 | tINS | RR | 73 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F |
7.155 | 1.807 | tNET | RR | 1 | R68C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0/CLK |
8.224 | -0.249 | tSu | 1 | R68C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_40_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.234, 25.612%; route: 3.278, 68.037%; tC2Q: 0.306, 6.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path39
Path Summary:
Slack | 1.069 |
Data Arrival Time | 7.155 |
Data Required Time | 8.224 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2 |
5.348 | 0.406 | tINS | RR | 73 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F |
7.155 | 1.807 | tNET | RR | 1 | R68C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0/CLK |
8.224 | -0.249 | tSu | 1 | R68C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_42_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.234, 25.612%; route: 3.278, 68.037%; tC2Q: 0.306, 6.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path40
Path Summary:
Slack | 1.069 |
Data Arrival Time | 7.155 |
Data Required Time | 8.224 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2 |
5.348 | 0.406 | tINS | RR | 73 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F |
7.155 | 1.807 | tNET | RR | 1 | R68C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.473 | 2.300 | tNET | RR | 1 | R68C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0/CLK |
8.224 | -0.249 | tSu | 1 | R68C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_5_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.234, 25.612%; route: 3.278, 68.037%; tC2Q: 0.306, 6.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.300, 100.000% |
Path41
Path Summary:
Slack | 1.077 |
Data Arrival Time | 7.155 |
Data Required Time | 8.231 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2 |
5.348 | 0.406 | tINS | RR | 73 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F |
7.155 | 1.807 | tNET | RR | 1 | R68C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.480 | 2.307 | tNET | RR | 1 | R68C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/CLK |
8.231 | -0.249 | tSu | 1 | R68C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0 |
Path Statistics:
Clock Skew | -0.029 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.234, 25.612%; route: 3.278, 68.037%; tC2Q: 0.306, 6.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.307, 100.000% |
Path42
Path Summary:
Slack | 1.077 |
Data Arrival Time | 7.155 |
Data Required Time | 8.231 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.337 | 2.337 | tNET | RR | 1 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/CLK |
2.643 | 0.306 | tC2Q | RR | 3 | R74C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_lo_idle_d4_s0/Q |
3.585 | 0.942 | tNET | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/I1 |
4.048 | 0.463 | tINS | RR | 1 | R72C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s5/F |
4.049 | 0.002 | tNET | RR | 1 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/I2 |
4.415 | 0.365 | tINS | RR | 45 | R72C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s4/F |
4.942 | 0.527 | tNET | RR | 1 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/I2 |
5.348 | 0.406 | tINS | RR | 73 | R71C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxc_7_s2/F |
7.155 | 1.807 | tNET | RR | 1 | R68C136[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.480 | 2.307 | tNET | RR | 1 | R68C136[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0/CLK |
8.231 | -0.249 | tSu | 1 | R68C136[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_35_s0 |
Path Statistics:
Clock Skew | -0.029 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Arrival Data Path Delay | cell: 1.234, 25.612%; route: 3.278, 68.037%; tC2Q: 0.306, 6.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.307, 100.000% |
Path43
Path Summary:
Slack | 1.079 |
Data Arrival Time | 7.377 |
Data Required Time | 8.457 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_0_s1 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.260 | 2.260 | tNET | RR | 1 | R70C148[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_0_s1/CLK |
2.566 | 0.306 | tC2Q | RR | 55 | R70C148[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_0_s1/Q |
4.464 | 1.898 | tNET | RR | 1 | R76C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s14/I1 |
4.918 | 0.454 | tINS | RR | 6 | R76C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s14/F |
5.538 | 0.620 | tNET | RR | 1 | R70C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/I1 |
5.769 | 0.231 | tINS | RR | 16 | R70C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s11/F |
6.924 | 1.155 | tNET | RR | 1 | R75C143[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3155_s10/I0 |
7.378 | 0.454 | tINS | RR | 1 | R75C143[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3155_s10/F |
7.378 | 0.000 | tNET | RR | 1 | R75C143[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.507 | 2.335 | tNET | RR | 1 | R75C143[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0/CLK |
8.457 | -0.051 | tSu | 1 | R75C143[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_19_s0 |
Path Statistics:
Clock Skew | 0.075 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.260, 100.000% |
Arrival Data Path Delay | cell: 1.139, 22.255%; route: 3.673, 71.766%; tC2Q: 0.306, 5.979% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.335, 100.000% |
Path44
Path Summary:
Slack | 1.088 |
Data Arrival Time | 7.367 |
Data Required Time | 8.455 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_38_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1141_s3/I2 |
6.019 | 0.454 | tINS | FR | 4 | R65C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1141_s3/F |
6.908 | 0.889 | tNET | RR | 1 | R58C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1141_s5/I1 |
7.367 | 0.459 | tINS | RR | 1 | R58C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1141_s5/F |
7.367 | 0.000 | tNET | RR | 1 | R58C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_38_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.505 | 2.333 | tNET | RR | 1 | R58C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_38_s0/CLK |
8.455 | -0.051 | tSu | 1 | R58C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_38_s0 |
Path Statistics:
Clock Skew | 0.034 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.913, 18.014%; route: 3.861, 76.185%; tC2Q: 0.294, 5.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.333, 100.000% |
Path45
Path Summary:
Slack | 1.090 |
Data Arrival Time | 7.366 |
Data Required Time | 8.457 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.288 | 2.288 | tNET | RR | 1 | R67C142[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0/CLK |
2.594 | 0.306 | tC2Q | RR | 7 | R67C142[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_location_d5_s0/Q |
3.106 | 0.512 | tNET | RR | 1 | R66C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3164_s16/I2 |
3.560 | 0.454 | tINS | RR | 9 | R66C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3164_s16/F |
4.145 | 0.585 | tNET | RR | 1 | R70C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/I1 |
4.551 | 0.406 | tINS | RR | 4 | R70C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/F |
5.059 | 0.508 | tNET | RR | 1 | R69C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s12/I0 |
5.522 | 0.463 | tINS | RR | 5 | R69C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3151_s12/F |
6.913 | 1.391 | tNET | RR | 1 | R75C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3154_s10/I3 |
7.367 | 0.454 | tINS | RR | 1 | R75C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3154_s10/F |
7.367 | 0.000 | tNET | RR | 1 | R75C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.507 | 2.335 | tNET | RR | 1 | R75C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0/CLK |
8.457 | -0.051 | tSu | 1 | R75C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_20_s0 |
Path Statistics:
Clock Skew | 0.047 |
Setup Relationship | 6.173 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.288, 100.000% |
Arrival Data Path Delay | cell: 1.777, 34.987%; route: 2.996, 58.988%; tC2Q: 0.306, 6.025% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.335, 100.000% |
Path46
Path Summary:
Slack | 1.090 |
Data Arrival Time | 7.341 |
Data Required Time | 8.431 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_61_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.383 | 2.790 | tNET | FF | 1 | R67C122[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1150_s3/I2 |
5.846 | 0.463 | tINS | FR | 5 | R67C122[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1150_s3/F |
7.110 | 1.264 | tNET | RR | 1 | R72C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n711_s2/I1 |
7.341 | 0.231 | tINS | RR | 1 | R72C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n711_s2/F |
7.341 | 0.000 | tNET | RR | 1 | R72C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_61_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.482 | 2.309 | tNET | RR | 1 | R72C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_61_s0/CLK |
8.431 | -0.051 | tSu | 1 | R72C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_61_s0 |
Path Statistics:
Clock Skew | 0.010 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.694, 13.764%; route: 4.054, 80.406%; tC2Q: 0.294, 5.831% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.309, 100.000% |
Path47
Path Summary:
Slack | 1.091 |
Data Arrival Time | 7.368 |
Data Required Time | 8.459 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_49_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.383 | 2.790 | tNET | FF | 1 | R67C121[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1146_s3/I2 |
5.846 | 0.463 | tINS | FR | 5 | R67C121[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1146_s3/F |
6.914 | 1.068 | tNET | RR | 1 | R74C119[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n926_s2/I1 |
7.368 | 0.454 | tINS | RR | 1 | R74C119[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n926_s2/F |
7.368 | 0.000 | tNET | RR | 1 | R74C119[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_49_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.510 | 2.337 | tNET | RR | 1 | R74C119[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_49_s0/CLK |
8.459 | -0.051 | tSu | 1 | R74C119[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_49_s0 |
Path Statistics:
Clock Skew | 0.038 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.917, 18.089%; route: 3.858, 76.111%; tC2Q: 0.294, 5.800% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Path48
Path Summary:
Slack | 1.094 |
Data Arrival Time | 7.364 |
Data Required Time | 8.458 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_46_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.565 | 2.972 | tNET | FF | 1 | R65C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1141_s3/I2 |
6.019 | 0.454 | tINS | FR | 4 | R65C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1141_s3/F |
6.910 | 0.891 | tNET | RR | 1 | R60C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1133_s3/I0 |
7.364 | 0.454 | tINS | RR | 1 | R60C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1133_s3/F |
7.364 | 0.000 | tNET | RR | 1 | R60C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_46_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.509 | 2.336 | tNET | RR | 1 | R60C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_46_s0/CLK |
8.458 | -0.051 | tSu | 1 | R60C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_46_s0 |
Path Statistics:
Clock Skew | 0.037 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.908, 17.926%; route: 3.863, 76.270%; tC2Q: 0.294, 5.804% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.336, 100.000% |
Path49
Path Summary:
Slack | 1.112 |
Data Arrival Time | 7.347 |
Data Required Time | 8.459 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_53_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.299 | 2.299 | tNET | RR | 1 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/CLK |
2.593 | 0.294 | tC2Q | RF | 127 | R70C118[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_0_s2/Q |
5.383 | 2.790 | tNET | FF | 1 | R67C122[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1150_s3/I2 |
5.846 | 0.463 | tINS | FR | 5 | R67C122[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1150_s3/F |
6.893 | 1.047 | tNET | RR | 1 | R74C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n922_s2/I0 |
7.347 | 0.454 | tINS | RR | 1 | R74C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n922_s2/F |
7.347 | 0.000 | tNET | RR | 1 | R74C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_53_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.510 | 2.337 | tNET | RR | 1 | R74C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_53_s0/CLK |
8.459 | -0.051 | tSu | 1 | R74C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_53_s0 |
Path Statistics:
Clock Skew | 0.038 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.299, 100.000% |
Arrival Data Path Delay | cell: 0.917, 18.165%; route: 3.837, 76.011%; tC2Q: 0.294, 5.824% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.337, 100.000% |
Path50
Path Summary:
Slack | 1.116 |
Data Arrival Time | 7.321 |
Data Required Time | 8.437 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
2.250 | 2.250 | tNET | RR | 1 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
2.556 | 0.306 | tC2Q | RR | 16 | R69C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
3.238 | 0.681 | tNET | RR | 1 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/I0 |
3.697 | 0.459 | tINS | RR | 11 | R67C144[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s12/F |
3.879 | 0.182 | tNET | RR | 1 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/I2 |
4.342 | 0.463 | tINS | RR | 14 | R65C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3103_s11/F |
5.390 | 1.048 | tNET | RR | 1 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/I2 |
5.852 | 0.463 | tINS | RR | 4 | R76C146[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3138_s17/F |
5.859 | 0.006 | tNET | RR | 1 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/I3 |
6.318 | 0.459 | tINS | RR | 16 | R76C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s11/F |
7.090 | 0.773 | tNET | RR | 1 | R71C144[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3113_s10/I0 |
7.321 | 0.231 | tINS | RR | 1 | R71C144[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3113_s10/F |
7.321 | 0.000 | tNET | RR | 1 | R71C144[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_rx_clk | ||||
6.173 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
8.488 | 2.315 | tNET | RR | 1 | R71C144[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0/CLK |
8.437 | -0.051 | tSu | 1 | R71C144[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0 |
Path Statistics:
Clock Skew | 0.065 |
Setup Relationship | 6.173 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.250, 100.000% |
Arrival Data Path Delay | cell: 2.075, 40.919%; route: 2.690, 53.047%; tC2Q: 0.306, 6.034% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.315, 100.000% |
Setup Analysis Report[2]:
Report Command:report_timing -setup -from_clock [get_clocks {serdes_tx_clk}] -to_clock [get_clocks {serdes_tx_clk}] -max_paths 50 -max_common_paths 1
Path1
Path Summary:
Slack | 0.048 |
Data Arrival Time | 7.675 |
Data Required Time | 7.723 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
6.385 | 4.503 | tNET | FF | 1 | R40C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s3/I0 |
6.839 | 0.454 | tINS | FR | 1 | R40C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s3/F |
6.841 | 0.002 | tNET | RR | 1 | R40C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s9/I1 |
7.304 | 0.463 | tINS | RR | 2 | R40C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s9/F |
7.444 | 0.140 | tNET | RR | 1 | R40C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s10/I2 |
7.675 | 0.231 | tINS | RR | 1 | R40C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s10/F |
7.675 | 0.000 | tNET | RR | 1 | R40C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.774 | 1.601 | tNET | RR | 1 | R40C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198/CLK |
7.723 | -0.051 | tSu | 1 | R40C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198 |
Path Statistics:
Clock Skew | 0.013 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 1.148, 18.860%; route: 4.645, 76.310%; tC2Q: 0.294, 4.830% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.601, 100.000% |
Path2
Path Summary:
Slack | 0.058 |
Data Arrival Time | 7.658 |
Data Required Time | 7.715 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
6.385 | 4.503 | tNET | FF | 1 | R40C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s3/I0 |
6.839 | 0.454 | tINS | FR | 1 | R40C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s3/F |
6.841 | 0.002 | tNET | RR | 1 | R40C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s9/I1 |
7.304 | 0.463 | tINS | RR | 2 | R40C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s9/F |
7.658 | 0.354 | tNET | RR | 1 | R40C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.766 | 1.594 | tNET | RR | 1 | R40C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s/CLK |
7.715 | -0.051 | tSu | 1 | R40C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 0.917, 15.107%; route: 4.859, 80.049%; tC2Q: 0.294, 4.843% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.594, 100.000% |
Path3
Path Summary:
Slack | 0.454 |
Data Arrival Time | 7.264 |
Data Required Time | 7.717 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_42_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.430 | 2.526 | tNET | RR | 1 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/I2 |
4.836 | 0.406 | tINS | RR | 7 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/F |
6.810 | 1.974 | tNET | RR | 1 | R39C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s5/I0 |
7.264 | 0.454 | tINS | RR | 1 | R39C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s5/F |
7.264 | 0.000 | tNET | RR | 1 | R39C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_42_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.768 | 1.596 | tNET | RR | 1 | R39C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_42_s0/CLK |
7.717 | -0.051 | tSu | 1 | R39C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_42_s0 |
Path Statistics:
Clock Skew | -0.002 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.860, 15.178%; route: 4.500, 79.421%; tC2Q: 0.306, 5.401% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.596, 100.000% |
Path4
Path Summary:
Slack | 0.622 |
Data Arrival Time | 7.098 |
Data Required Time | 7.719 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.263 | 2.359 | tNET | RR | 1 | R43C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/I2 |
4.669 | 0.406 | tINS | RR | 5 | R43C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/F |
6.635 | 1.966 | tNET | RR | 1 | R38C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n416_s2/I1 |
7.098 | 0.463 | tINS | RR | 1 | R38C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n416_s2/F |
7.098 | 0.000 | tNET | RR | 1 | R38C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.770 | 1.597 | tNET | RR | 1 | R38C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0/CLK |
7.719 | -0.051 | tSu | 1 | R38C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.869, 15.800%; route: 4.325, 78.636%; tC2Q: 0.306, 5.564% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Path5
Path Summary:
Slack | 0.690 |
Data Arrival Time | 7.017 |
Data Required Time | 7.708 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/I2 |
4.900 | 0.463 | tINS | RR | 5 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/F |
6.555 | 1.654 | tNET | RR | 1 | R40C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n414_s2/I1 |
7.017 | 0.463 | tINS | RR | 1 | R40C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n414_s2/F |
7.017 | 0.000 | tNET | RR | 1 | R40C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.759 | 1.586 | tNET | RR | 1 | R40C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0/CLK |
7.708 | -0.051 | tSu | 1 | R40C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.926, 17.085%; route: 4.188, 77.269%; tC2Q: 0.306, 5.646% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.586, 100.000% |
Path6
Path Summary:
Slack | 0.698 |
Data Arrival Time | 7.017 |
Data Required Time | 7.715 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_28_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/I2 |
4.900 | 0.463 | tINS | RR | 5 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/F |
6.555 | 1.654 | tNET | RR | 1 | R40C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n422_s2/I0 |
7.017 | 0.463 | tINS | RR | 1 | R40C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n422_s2/F |
7.017 | 0.000 | tNET | RR | 1 | R40C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_28_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.766 | 1.594 | tNET | RR | 1 | R40C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_28_s0/CLK |
7.715 | -0.051 | tSu | 1 | R40C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_28_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.926, 17.085%; route: 4.188, 77.269%; tC2Q: 0.306, 5.646% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.594, 100.000% |
Path7
Path Summary:
Slack | 0.918 |
Data Arrival Time | 6.788 |
Data Required Time | 7.706 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_31_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n781_s3/I2 |
4.900 | 0.463 | tINS | RR | 5 | R43C131[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n781_s3/F |
6.557 | 1.657 | tNET | RR | 1 | R41C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n419_s2/I0 |
6.788 | 0.231 | tINS | RR | 1 | R41C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n419_s2/F |
6.788 | 0.000 | tNET | RR | 1 | R41C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_31_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.757 | 1.584 | tNET | RR | 1 | R41C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_31_s0/CLK |
7.706 | -0.051 | tSu | 1 | R41C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_31_s0 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.694, 13.369%; route: 4.191, 80.736%; tC2Q: 0.306, 5.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.584, 100.000% |
Path8
Path Summary:
Slack | 0.923 |
Data Arrival Time | 6.793 |
Data Required Time | 7.717 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_38_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.222 | 2.319 | tNET | RR | 1 | R44C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1004_s3/I2 |
4.628 | 0.406 | tINS | RR | 6 | R44C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1004_s3/F |
6.339 | 1.711 | tNET | RR | 1 | R43C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1004_s5/I0 |
6.793 | 0.454 | tINS | RR | 1 | R43C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1004_s5/F |
6.793 | 0.000 | tNET | RR | 1 | R43C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_38_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.768 | 1.595 | tNET | RR | 1 | R43C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_38_s0/CLK |
7.717 | -0.051 | tSu | 1 | R43C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_38_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.860, 16.551%; route: 4.030, 77.560%; tC2Q: 0.306, 5.889% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.595, 100.000% |
Path9
Path Summary:
Slack | 0.956 |
Data Arrival Time | 6.740 |
Data Required Time | 7.696 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_55_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n781_s3/I2 |
4.900 | 0.463 | tINS | RR | 5 | R43C131[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n781_s3/F |
6.509 | 1.609 | tNET | RR | 1 | R44C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n592_s4/I1 |
6.740 | 0.231 | tINS | RR | 1 | R44C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n592_s4/F |
6.740 | 0.000 | tNET | RR | 1 | R44C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_55_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.747 | 1.574 | tNET | RR | 1 | R44C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_55_s0/CLK |
7.696 | -0.051 | tSu | 1 | R44C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_55_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.694, 13.494%; route: 4.143, 80.556%; tC2Q: 0.306, 5.950% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.574, 100.000% |
Path10
Path Summary:
Slack | 0.959 |
Data Arrival Time | 6.761 |
Data Required Time | 7.719 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.430 | 2.526 | tNET | RR | 1 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/I2 |
4.836 | 0.406 | tINS | RR | 7 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/F |
6.355 | 1.519 | tNET | RR | 1 | R38C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n810_s2/I1 |
6.761 | 0.406 | tINS | RR | 1 | R38C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n810_s2/F |
6.761 | 0.000 | tNET | RR | 1 | R38C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.770 | 1.597 | tNET | RR | 1 | R38C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0/CLK |
7.719 | -0.051 | tSu | 1 | R38C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.812, 15.727%; route: 4.045, 78.346%; tC2Q: 0.306, 5.927% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Path11
Path Summary:
Slack | 1.002 |
Data Arrival Time | 6.709 |
Data Required Time | 7.711 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.234 | 2.331 | tNET | RR | 1 | R43C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n596_s3/I2 |
4.641 | 0.406 | tINS | RR | 4 | R43C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n596_s3/F |
6.247 | 1.606 | tNET | RR | 1 | R42C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n407_s2/I1 |
6.709 | 0.463 | tINS | RR | 1 | R42C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n407_s2/F |
6.709 | 0.000 | tNET | RR | 1 | R42C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.762 | 1.590 | tNET | RR | 1 | R42C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0/CLK |
7.711 | -0.051 | tSu | 1 | R42C121[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0 |
Path Statistics:
Clock Skew | -0.008 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.869, 16.999%; route: 3.937, 77.015%; tC2Q: 0.306, 5.986% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Path12
Path Summary:
Slack | 1.013 |
Data Arrival Time | 6.707 |
Data Required Time | 7.719 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_18_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.430 | 2.526 | tNET | RR | 1 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/I2 |
4.836 | 0.406 | tINS | RR | 7 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/F |
6.476 | 1.640 | tNET | RR | 1 | R38C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n629_s2/I1 |
6.707 | 0.231 | tINS | RR | 1 | R38C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n629_s2/F |
6.707 | 0.000 | tNET | RR | 1 | R38C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.770 | 1.597 | tNET | RR | 1 | R38C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_18_s0/CLK |
7.719 | -0.051 | tSu | 1 | R38C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.637, 12.468%; route: 4.166, 81.542%; tC2Q: 0.306, 5.989% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Path13
Path Summary:
Slack | 1.017 |
Data Arrival Time | 6.686 |
Data Required Time | 7.704 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_47_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n781_s3/I2 |
4.900 | 0.463 | tINS | RR | 5 | R43C131[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n781_s3/F |
6.223 | 1.323 | tNET | RR | 1 | R44C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n600_s2/I0 |
6.686 | 0.463 | tINS | RR | 1 | R44C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n600_s2/F |
6.686 | 0.000 | tNET | RR | 1 | R44C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_47_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.755 | 1.582 | tNET | RR | 1 | R44C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_47_s0/CLK |
7.704 | -0.051 | tSu | 1 | R44C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_47_s0 |
Path Statistics:
Clock Skew | -0.016 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.926, 18.196%; route: 3.857, 75.791%; tC2Q: 0.306, 6.013% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.582, 100.000% |
Path14
Path Summary:
Slack | 1.023 |
Data Arrival Time | 6.686 |
Data Required Time | 7.709 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_39_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n781_s3/I2 |
4.900 | 0.463 | tINS | RR | 5 | R43C131[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n781_s3/F |
6.223 | 1.323 | tNET | RR | 1 | R43C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n411_s2/I1 |
6.686 | 0.463 | tINS | RR | 1 | R43C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n411_s2/F |
6.686 | 0.000 | tNET | RR | 1 | R43C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_39_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.760 | 1.587 | tNET | RR | 1 | R43C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_39_s0/CLK |
7.709 | -0.051 | tSu | 1 | R43C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_39_s0 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.926, 18.196%; route: 3.857, 75.791%; tC2Q: 0.306, 6.013% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.587, 100.000% |
Path15
Path Summary:
Slack | 1.130 |
Data Arrival Time | 6.583 |
Data Required Time | 7.713 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_16_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s3/I2 |
4.900 | 0.463 | tINS | RR | 8 | R43C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s3/F |
6.124 | 1.224 | tNET | RR | 1 | R41C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n631_s2/I0 |
6.583 | 0.459 | tINS | RR | 1 | R41C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n631_s2/F |
6.583 | 0.000 | tNET | RR | 1 | R41C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.764 | 1.591 | tNET | RR | 1 | R41C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_16_s0/CLK |
7.713 | -0.051 | tSu | 1 | R41C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_16_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.922, 18.492%; route: 3.758, 75.371%; tC2Q: 0.306, 6.137% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.591, 100.000% |
Path16
Path Summary:
Slack | 1.141 |
Data Arrival Time | 6.585 |
Data Required Time | 7.727 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_18_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/I2 |
4.900 | 0.463 | tINS | RR | 7 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/F |
6.354 | 1.454 | tNET | RR | 1 | R38C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n432_s2/I1 |
6.585 | 0.231 | tINS | RR | 1 | R38C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n432_s2/F |
6.585 | 0.000 | tNET | RR | 1 | R38C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.778 | 1.605 | tNET | RR | 1 | R38C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_18_s0/CLK |
7.727 | -0.051 | tSu | 1 | R38C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_18_s0 |
Path Statistics:
Clock Skew | 0.008 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.694, 13.913%; route: 3.988, 79.952%; tC2Q: 0.306, 6.135% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.605, 100.000% |
Path17
Path Summary:
Slack | 1.162 |
Data Arrival Time | 6.540 |
Data Required Time | 7.702 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.589 | 1.589 | tNET | RR | 1 | R44C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/CLK |
1.895 | 0.306 | tC2Q | RR | 3 | R44C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/Q |
2.742 | 0.847 | tNET | RR | 1 | R44C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/I1 |
3.205 | 0.463 | tINS | RR | 2 | R44C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/F |
3.846 | 0.641 | tNET | RR | 1 | R44C132[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/I1 |
4.309 | 0.463 | tINS | RR | 7 | R44C132[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/F |
6.077 | 1.768 | tNET | RR | 1 | R43C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n610_s2/I1 |
6.540 | 0.463 | tINS | RR | 1 | R43C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n610_s2/F |
6.540 | 0.000 | tNET | RR | 1 | R43C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.753 | 1.580 | tNET | RR | 1 | R43C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0/CLK |
7.702 | -0.051 | tSu | 1 | R43C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_37_s0 |
Path Statistics:
Clock Skew | -0.009 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 1.389, 28.055%; route: 3.256, 65.764%; tC2Q: 0.306, 6.181% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.580, 100.000% |
Path18
Path Summary:
Slack | 1.187 |
Data Arrival Time | 6.509 |
Data Required Time | 7.696 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_45_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.589 | 1.589 | tNET | RR | 1 | R44C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/CLK |
1.895 | 0.306 | tC2Q | RR | 3 | R44C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/Q |
2.742 | 0.847 | tNET | RR | 1 | R44C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/I1 |
3.205 | 0.463 | tINS | RR | 2 | R44C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/F |
3.846 | 0.641 | tNET | RR | 1 | R44C132[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/I1 |
4.309 | 0.463 | tINS | RR | 7 | R44C132[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/F |
6.046 | 1.737 | tNET | RR | 1 | R44C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n799_s2/I0 |
6.509 | 0.463 | tINS | RR | 1 | R44C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n799_s2/F |
6.509 | 0.000 | tNET | RR | 1 | R44C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_45_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.747 | 1.574 | tNET | RR | 1 | R44C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_45_s0/CLK |
7.696 | -0.051 | tSu | 1 | R44C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_45_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 1.389, 28.232%; route: 3.225, 65.549%; tC2Q: 0.306, 6.220% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.574, 100.000% |
Path19
Path Summary:
Slack | 1.207 |
Data Arrival Time | 6.515 |
Data Required Time | 7.723 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_52_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/I2 |
4.900 | 0.463 | tINS | RR | 5 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/F |
6.284 | 1.384 | tNET | RR | 1 | R40C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s5/I1 |
6.515 | 0.231 | tINS | RR | 1 | R40C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s5/F |
6.515 | 0.000 | tNET | RR | 1 | R40C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_52_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.774 | 1.601 | tNET | RR | 1 | R40C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_52_s0/CLK |
7.723 | -0.051 | tSu | 1 | R40C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_52_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.694, 14.111%; route: 3.918, 79.667%; tC2Q: 0.306, 6.222% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.601, 100.000% |
Path20
Path Summary:
Slack | 1.210 |
Data Arrival Time | 6.305 |
Data Required Time | 7.515 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.590 | 1.590 | tNET | RR | 1 | R42C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CLK |
1.896 | 0.306 | tC2Q | RR | 5 | R42C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q |
2.357 | 0.461 | tNET | RR | 1 | R41C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/I0 |
2.820 | 0.463 | tINS | RR | 4 | R41C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/F |
3.131 | 0.311 | tNET | RR | 1 | R41C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/I1 |
3.496 | 0.365 | tINS | RR | 2 | R41C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/F |
3.970 | 0.474 | tNET | RR | 2 | R44C142[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/I1 |
4.406 | 0.436 | tINS | RR | 1 | R44C142[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/COUT |
4.406 | 0.000 | tNET | RR | 2 | R44C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/CIN |
4.446 | 0.040 | tINS | RR | 1 | R44C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/COUT |
4.446 | 0.000 | tNET | RR | 2 | R44C142[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/CIN |
4.641 | 0.195 | tINS | RR | 1 | R44C142[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/SUM |
4.762 | 0.121 | tNET | RR | 1 | R44C142[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/I2 |
5.200 | 0.438 | tINS | RR | 2 | R44C142[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/F |
5.340 | 0.140 | tNET | RR | 1 | R43C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s2/I0 |
5.571 | 0.231 | tINS | RR | 1 | R43C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s2/F |
6.306 | 0.735 | tNET | RR | 1 | R41C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.764 | 1.591 | tNET | RR | 1 | R41C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0/CLK |
7.515 | -0.249 | tSu | 1 | R41C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0 |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 6.173 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Arrival Data Path Delay | cell: 2.168, 45.971%; route: 2.242, 47.540%; tC2Q: 0.306, 6.489% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.591, 100.000% |
Path21
Path Summary:
Slack | 1.293 |
Data Arrival Time | 6.418 |
Data Required Time | 7.712 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_26_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.430 | 2.526 | tNET | RR | 1 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/I2 |
4.836 | 0.406 | tINS | RR | 7 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/F |
6.188 | 1.352 | tNET | RR | 1 | R38C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n818_s2/I0 |
6.418 | 0.231 | tINS | RR | 1 | R38C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n818_s2/F |
6.418 | 0.000 | tNET | RR | 1 | R38C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_26_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.763 | 1.590 | tNET | RR | 1 | R38C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_26_s0/CLK |
7.712 | -0.051 | tSu | 1 | R38C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_26_s0 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.637, 13.213%; route: 3.878, 80.440%; tC2Q: 0.306, 6.347% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Path22
Path Summary:
Slack | 1.293 |
Data Arrival Time | 6.418 |
Data Required Time | 7.712 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_26_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/I2 |
4.900 | 0.463 | tINS | RR | 7 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/F |
6.188 | 1.287 | tNET | RR | 1 | R38C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n621_s2/I0 |
6.418 | 0.231 | tINS | RR | 1 | R38C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n621_s2/F |
6.418 | 0.000 | tNET | RR | 1 | R38C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_26_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.763 | 1.590 | tNET | RR | 1 | R38C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_26_s0/CLK |
7.712 | -0.051 | tSu | 1 | R38C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_26_s0 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.694, 14.395%; route: 3.821, 79.257%; tC2Q: 0.306, 6.347% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Path23
Path Summary:
Slack | 1.303 |
Data Arrival Time | 6.400 |
Data Required Time | 7.704 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_48_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s3/I2 |
4.900 | 0.463 | tINS | RR | 8 | R43C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s3/F |
5.938 | 1.037 | tNET | RR | 1 | R44C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s5/I0 |
6.400 | 0.463 | tINS | RR | 1 | R44C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s5/F |
6.400 | 0.000 | tNET | RR | 1 | R44C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_48_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.755 | 1.582 | tNET | RR | 1 | R44C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_48_s0/CLK |
7.704 | -0.051 | tSu | 1 | R44C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_48_s0 |
Path Statistics:
Clock Skew | -0.016 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.926, 19.280%; route: 3.571, 74.349%; tC2Q: 0.306, 6.371% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.582, 100.000% |
Path24
Path Summary:
Slack | 1.357 |
Data Arrival Time | 6.352 |
Data Required Time | 7.710 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_10_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.430 | 2.526 | tNET | RR | 1 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/I2 |
4.836 | 0.406 | tINS | RR | 7 | R44C128[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s3/F |
5.946 | 1.111 | tNET | RR | 1 | R39C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n637_s2/I0 |
6.352 | 0.406 | tINS | RR | 1 | R39C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n637_s2/F |
6.352 | 0.000 | tNET | RR | 1 | R39C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.761 | 1.588 | tNET | RR | 1 | R39C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_10_s0/CLK |
7.710 | -0.051 | tSu | 1 | R39C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_10_s0 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.812, 17.077%; route: 3.637, 76.488%; tC2Q: 0.306, 6.435% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Path25
Path Summary:
Slack | 1.367 |
Data Arrival Time | 6.348 |
Data Required Time | 7.715 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_44_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/I2 |
4.900 | 0.463 | tINS | RR | 5 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/F |
6.117 | 1.217 | tNET | RR | 1 | R40C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n603_s2/I0 |
6.348 | 0.231 | tINS | RR | 1 | R40C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n603_s2/F |
6.348 | 0.000 | tNET | RR | 1 | R40C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_44_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.766 | 1.594 | tNET | RR | 1 | R40C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_44_s0/CLK |
7.715 | -0.051 | tSu | 1 | R40C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_44_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.694, 14.607%; route: 3.751, 78.952%; tC2Q: 0.306, 6.441% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.594, 100.000% |
Path26
Path Summary:
Slack | 1.380 |
Data Arrival Time | 6.335 |
Data Required Time | 7.715 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/I2 |
4.900 | 0.463 | tINS | RR | 5 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/F |
5.872 | 0.972 | tNET | RR | 1 | R40C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s5/I0 |
6.335 | 0.463 | tINS | RR | 1 | R40C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s5/F |
6.335 | 0.000 | tNET | RR | 1 | R40C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.766 | 1.594 | tNET | RR | 1 | R40C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0/CLK |
7.715 | -0.051 | tSu | 1 | R40C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_60_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.926, 19.544%; route: 3.506, 73.997%; tC2Q: 0.306, 6.458% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.594, 100.000% |
Path27
Path Summary:
Slack | 1.381 |
Data Arrival Time | 6.332 |
Data Required Time | 7.713 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_14_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.222 | 2.319 | tNET | RR | 1 | R44C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1004_s3/I2 |
4.628 | 0.406 | tINS | RR | 6 | R44C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1004_s3/F |
5.878 | 1.250 | tNET | RR | 1 | R41C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n633_s2/I1 |
6.332 | 0.454 | tINS | RR | 1 | R41C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n633_s2/F |
6.332 | 0.000 | tNET | RR | 1 | R41C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.764 | 1.591 | tNET | RR | 1 | R41C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_14_s0/CLK |
7.713 | -0.051 | tSu | 1 | R41C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_14_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.860, 18.163%; route: 3.569, 75.375%; tC2Q: 0.306, 6.463% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.591, 100.000% |
Path28
Path Summary:
Slack | 1.414 |
Data Arrival Time | 6.306 |
Data Required Time | 7.719 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_34_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/I2 |
4.900 | 0.463 | tINS | RR | 7 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/F |
5.899 | 0.999 | tNET | RR | 1 | R38C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n613_s2/I1 |
6.306 | 0.406 | tINS | RR | 1 | R38C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n613_s2/F |
6.306 | 0.000 | tNET | RR | 1 | R38C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_34_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.770 | 1.597 | tNET | RR | 1 | R38C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_34_s0/CLK |
7.719 | -0.051 | tSu | 1 | R38C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_34_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.869, 18.458%; route: 3.533, 75.042%; tC2Q: 0.306, 6.500% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Path29
Path Summary:
Slack | 1.419 |
Data Arrival Time | 6.297 |
Data Required Time | 7.715 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_44_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.430 | 2.526 | tNET | RR | 1 | R44C128[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/I2 |
4.836 | 0.406 | tINS | RR | 7 | R44C128[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/F |
5.834 | 0.998 | tNET | RR | 1 | R40C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s5/I0 |
6.297 | 0.463 | tINS | RR | 1 | R40C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s5/F |
6.297 | 0.000 | tNET | RR | 1 | R40C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_44_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.766 | 1.594 | tNET | RR | 1 | R40C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_44_s0/CLK |
7.715 | -0.051 | tSu | 1 | R40C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_44_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.869, 18.493%; route: 3.524, 74.995%; tC2Q: 0.306, 6.512% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.594, 100.000% |
Path30
Path Summary:
Slack | 1.419 |
Data Arrival Time | 6.293 |
Data Required Time | 7.711 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s3/I2 |
4.900 | 0.463 | tINS | RR | 8 | R43C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s3/F |
5.839 | 0.938 | tNET | RR | 1 | R42C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n623_s2/I1 |
6.293 | 0.454 | tINS | RR | 1 | R42C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n623_s2/F |
6.293 | 0.000 | tNET | RR | 1 | R42C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.762 | 1.590 | tNET | RR | 1 | R42C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0/CLK |
7.711 | -0.051 | tSu | 1 | R42C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_24_s0 |
Path Statistics:
Clock Skew | -0.008 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.917, 19.531%; route: 3.472, 73.951%; tC2Q: 0.306, 6.518% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Path31
Path Summary:
Slack | 1.432 |
Data Arrival Time | 6.280 |
Data Required Time | 7.712 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.263 | 2.359 | tNET | RR | 1 | R43C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/I2 |
4.669 | 0.406 | tINS | RR | 5 | R43C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/F |
5.818 | 1.149 | tNET | RR | 1 | R38C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n424_s2/I0 |
6.280 | 0.463 | tINS | RR | 1 | R38C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n424_s2/F |
6.280 | 0.000 | tNET | RR | 1 | R38C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.763 | 1.590 | tNET | RR | 1 | R38C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0/CLK |
7.712 | -0.051 | tSu | 1 | R38C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.869, 18.556%; route: 3.508, 74.909%; tC2Q: 0.306, 6.534% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Path32
Path Summary:
Slack | 1.443 |
Data Arrival Time | 6.270 |
Data Required Time | 7.713 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s3/I2 |
4.900 | 0.463 | tINS | RR | 8 | R43C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s3/F |
5.816 | 0.916 | tNET | RR | 1 | R41C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n812_s2/I0 |
6.270 | 0.454 | tINS | RR | 1 | R41C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n812_s2/F |
6.270 | 0.000 | tNET | RR | 1 | R41C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.764 | 1.591 | tNET | RR | 1 | R41C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0/CLK |
7.713 | -0.051 | tSu | 1 | R41C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_32_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.917, 19.623%; route: 3.450, 73.828%; tC2Q: 0.306, 6.548% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.591, 100.000% |
Path33
Path Summary:
Slack | 1.459 |
Data Arrival Time | 6.257 |
Data Required Time | 7.715 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.430 | 2.526 | tNET | RR | 1 | R44C128[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/I2 |
4.836 | 0.406 | tINS | RR | 7 | R44C128[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/F |
5.803 | 0.967 | tNET | RR | 1 | R40C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n627_s2/I1 |
6.257 | 0.454 | tINS | RR | 1 | R40C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n627_s2/F |
6.257 | 0.000 | tNET | RR | 1 | R40C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.766 | 1.594 | tNET | RR | 1 | R40C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0/CLK |
7.715 | -0.051 | tSu | 1 | R40C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.860, 18.459%; route: 3.493, 74.973%; tC2Q: 0.306, 6.568% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.594, 100.000% |
Path34
Path Summary:
Slack | 1.462 |
Data Arrival Time | 6.257 |
Data Required Time | 7.719 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/I2 |
4.900 | 0.463 | tINS | RR | 7 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/F |
5.851 | 0.951 | tNET | RR | 1 | R42C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n794_s5/I1 |
6.257 | 0.406 | tINS | RR | 1 | R42C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n794_s5/F |
6.257 | 0.000 | tNET | RR | 1 | R42C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.770 | 1.597 | tNET | RR | 1 | R42C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0/CLK |
7.719 | -0.051 | tSu | 1 | R42C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_50_s0 |
Path Statistics:
Clock Skew | -0.000 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.869, 18.648%; route: 3.485, 74.785%; tC2Q: 0.306, 6.567% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Path35
Path Summary:
Slack | 1.465 |
Data Arrival Time | 6.254 |
Data Required Time | 7.719 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_29_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.589 | 1.589 | tNET | RR | 1 | R44C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/CLK |
1.895 | 0.306 | tC2Q | RR | 3 | R44C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/Q |
2.742 | 0.847 | tNET | RR | 1 | R44C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/I1 |
3.205 | 0.463 | tINS | RR | 2 | R44C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/F |
3.846 | 0.641 | tNET | RR | 1 | R44C132[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/I1 |
4.309 | 0.463 | tINS | RR | 7 | R44C132[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/F |
5.800 | 1.491 | tNET | RR | 1 | R38C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n618_s2/I0 |
6.254 | 0.454 | tINS | RR | 1 | R38C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n618_s2/F |
6.254 | 0.000 | tNET | RR | 1 | R38C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_29_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.770 | 1.597 | tNET | RR | 1 | R38C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_29_s0/CLK |
7.719 | -0.051 | tSu | 1 | R38C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_29_s0 |
Path Statistics:
Clock Skew | 0.008 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 1.380, 29.582%; route: 2.979, 63.859%; tC2Q: 0.306, 6.559% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Path36
Path Summary:
Slack | 1.469 |
Data Arrival Time | 6.234 |
Data Required Time | 7.704 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s3/I2 |
4.900 | 0.463 | tINS | RR | 7 | R43C131[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s3/F |
5.772 | 0.871 | tNET | RR | 1 | R44C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n796_s5/I1 |
6.234 | 0.463 | tINS | RR | 1 | R44C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n796_s5/F |
6.234 | 0.000 | tNET | RR | 1 | R44C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.755 | 1.582 | tNET | RR | 1 | R44C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0/CLK |
7.704 | -0.051 | tSu | 1 | R44C125[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_48_s0 |
Path Statistics:
Clock Skew | -0.016 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.926, 19.970%; route: 3.405, 73.431%; tC2Q: 0.306, 6.599% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.582, 100.000% |
Path37
Path Summary:
Slack | 1.482 |
Data Arrival Time | 6.237 |
Data Required Time | 7.719 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_13_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.589 | 1.589 | tNET | RR | 1 | R44C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/CLK |
1.895 | 0.306 | tC2Q | RR | 3 | R44C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_7_s0/Q |
2.742 | 0.847 | tNET | RR | 1 | R44C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/I1 |
3.205 | 0.463 | tINS | RR | 2 | R44C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n983_s4/F |
3.846 | 0.641 | tNET | RR | 1 | R44C132[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/I1 |
4.309 | 0.463 | tINS | RR | 7 | R44C132[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n981_s3/F |
5.831 | 1.522 | tNET | RR | 1 | R38C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n437_s2/I0 |
6.237 | 0.406 | tINS | RR | 1 | R38C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n437_s2/F |
6.237 | 0.000 | tNET | RR | 1 | R38C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.770 | 1.597 | tNET | RR | 1 | R38C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_13_s0/CLK |
7.719 | -0.051 | tSu | 1 | R38C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_13_s0 |
Path Statistics:
Clock Skew | 0.008 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.589, 100.000% |
Arrival Data Path Delay | cell: 1.332, 28.657%; route: 3.010, 64.759%; tC2Q: 0.306, 6.583% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Path38
Path Summary:
Slack | 1.498 |
Data Arrival Time | 6.222 |
Data Required Time | 7.721 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.222 | 2.319 | tNET | RR | 1 | R44C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1004_s3/I2 |
4.628 | 0.406 | tINS | RR | 6 | R44C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1004_s3/F |
5.760 | 1.131 | tNET | RR | 1 | R41C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n822_s2/I0 |
6.222 | 0.463 | tINS | RR | 1 | R41C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n822_s2/F |
6.222 | 0.000 | tNET | RR | 1 | R41C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.772 | 1.599 | tNET | RR | 1 | R41C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0/CLK |
7.721 | -0.051 | tSu | 1 | R41C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_22_s0 |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.869, 18.789%; route: 3.450, 74.595%; tC2Q: 0.306, 6.616% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.599, 100.000% |
Path39
Path Summary:
Slack | 1.503 |
Data Arrival Time | 6.209 |
Data Required Time | 7.711 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_23_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.602 | 2.699 | tNET | RR | 1 | R41C128[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1019_s3/I2 |
5.009 | 0.406 | tINS | RR | 4 | R41C128[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1019_s3/F |
5.803 | 0.794 | tNET | RR | 1 | R42C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1019_s5/I0 |
6.209 | 0.406 | tINS | RR | 1 | R42C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1019_s5/F |
6.209 | 0.000 | tNET | RR | 1 | R42C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_23_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.762 | 1.590 | tNET | RR | 1 | R42C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_23_s0/CLK |
7.711 | -0.051 | tSu | 1 | R42C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_23_s0 |
Path Statistics:
Clock Skew | -0.008 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.812, 17.610%; route: 3.493, 75.754%; tC2Q: 0.306, 6.636% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Path40
Path Summary:
Slack | 1.511 |
Data Arrival Time | 6.201 |
Data Required Time | 7.711 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_32_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.263 | 2.359 | tNET | RR | 1 | R43C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s3/I2 |
4.669 | 0.406 | tINS | RR | 5 | R43C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s3/F |
5.795 | 1.126 | tNET | RR | 1 | R42C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n418_s2/I1 |
6.201 | 0.406 | tINS | RR | 1 | R42C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n418_s2/F |
6.201 | 0.000 | tNET | RR | 1 | R42C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_32_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.762 | 1.590 | tNET | RR | 1 | R42C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_32_s0/CLK |
7.711 | -0.051 | tSu | 1 | R42C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_32_s0 |
Path Statistics:
Clock Skew | -0.008 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.812, 17.641%; route: 3.485, 75.712%; tC2Q: 0.306, 6.648% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Path41
Path Summary:
Slack | 1.519 |
Data Arrival Time | 6.198 |
Data Required Time | 7.717 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/I2 |
4.900 | 0.463 | tINS | RR | 7 | R43C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n984_s3/F |
5.744 | 0.844 | tNET | RR | 1 | R39C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n802_s2/I0 |
6.198 | 0.454 | tINS | RR | 1 | R39C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n802_s2/F |
6.198 | 0.000 | tNET | RR | 1 | R39C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.768 | 1.596 | tNET | RR | 1 | R39C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0/CLK |
7.717 | -0.051 | tSu | 1 | R39C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0 |
Path Statistics:
Clock Skew | -0.002 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.917, 19.930%; route: 3.378, 73.419%; tC2Q: 0.306, 6.651% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.596, 100.000% |
Path42
Path Summary:
Slack | 1.521 |
Data Arrival Time | 6.199 |
Data Required Time | 7.719 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_13_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.263 | 2.359 | tNET | RR | 1 | R43C128[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1005_s3/I2 |
4.628 | 0.365 | tINS | RR | 6 | R43C128[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1005_s3/F |
5.793 | 1.165 | tNET | RR | 1 | R38C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n634_s2/I1 |
6.199 | 0.406 | tINS | RR | 1 | R38C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n634_s2/F |
6.199 | 0.000 | tNET | RR | 1 | R38C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.770 | 1.597 | tNET | RR | 1 | R38C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_13_s0/CLK |
7.719 | -0.051 | tSu | 1 | R38C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.771, 16.757%; route: 3.524, 76.592%; tC2Q: 0.306, 6.651% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Path43
Path Summary:
Slack | 1.534 |
Data Arrival Time | 6.186 |
Data Required Time | 7.719 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.263 | 2.359 | tNET | RR | 1 | R43C128[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1005_s3/I2 |
4.628 | 0.365 | tINS | RR | 6 | R43C128[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1005_s3/F |
5.732 | 1.104 | tNET | RR | 1 | R38C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n815_s2/I1 |
6.186 | 0.454 | tINS | RR | 1 | R38C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n815_s2/F |
6.186 | 0.000 | tNET | RR | 1 | R38C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.770 | 1.597 | tNET | RR | 1 | R38C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0/CLK |
7.719 | -0.051 | tSu | 1 | R38C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_29_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.819, 17.851%; route: 3.463, 75.480%; tC2Q: 0.306, 6.670% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Path44
Path Summary:
Slack | 1.542 |
Data Arrival Time | 6.168 |
Data Required Time | 7.710 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_21_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.263 | 2.359 | tNET | RR | 1 | R43C129[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n997_s3/I2 |
4.628 | 0.365 | tINS | RR | 7 | R43C129[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n997_s3/F |
5.762 | 1.134 | tNET | RR | 1 | R39C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n626_s2/I1 |
6.168 | 0.406 | tINS | RR | 1 | R39C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n626_s2/F |
6.168 | 0.000 | tNET | RR | 1 | R39C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_21_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.761 | 1.588 | tNET | RR | 1 | R39C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_21_s0/CLK |
7.710 | -0.051 | tSu | 1 | R39C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_21_s0 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.771, 16.871%; route: 3.493, 76.433%; tC2Q: 0.306, 6.696% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Path45
Path Summary:
Slack | 1.561 |
Data Arrival Time | 6.151 |
Data Required Time | 7.712 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_5_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.263 | 2.359 | tNET | RR | 1 | R43C128[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1005_s3/I2 |
4.628 | 0.365 | tINS | RR | 6 | R43C128[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1005_s3/F |
5.745 | 1.117 | tNET | RR | 1 | R38C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n642_s2/I0 |
6.151 | 0.406 | tINS | RR | 1 | R38C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n642_s2/F |
6.151 | 0.000 | tNET | RR | 1 | R38C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.763 | 1.590 | tNET | RR | 1 | R38C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_5_s0/CLK |
7.712 | -0.051 | tSu | 1 | R38C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_5_s0 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.771, 16.934%; route: 3.476, 76.345%; tC2Q: 0.306, 6.721% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Path46
Path Summary:
Slack | 1.564 |
Data Arrival Time | 6.159 |
Data Required Time | 7.723 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.430 | 2.526 | tNET | RR | 1 | R44C128[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/I2 |
4.836 | 0.406 | tINS | RR | 7 | R44C128[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/F |
5.696 | 0.860 | tNET | RR | 1 | R40C122[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n990_s5/I1 |
6.159 | 0.463 | tINS | RR | 1 | R40C122[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n990_s5/F |
6.159 | 0.000 | tNET | RR | 1 | R40C122[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.774 | 1.601 | tNET | RR | 1 | R40C122[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0/CLK |
7.723 | -0.051 | tSu | 1 | R40C122[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.869, 19.053%; route: 3.386, 74.238%; tC2Q: 0.306, 6.709% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.601, 100.000% |
Path47
Path Summary:
Slack | 1.580 |
Data Arrival Time | 6.110 |
Data Required Time | 7.690 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_56_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s3/I2 |
4.900 | 0.463 | tINS | RR | 7 | R43C131[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s3/F |
5.648 | 0.747 | tNET | RR | 1 | R45C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s5/I0 |
6.110 | 0.463 | tINS | RR | 1 | R45C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s5/F |
6.110 | 0.000 | tNET | RR | 1 | R45C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_56_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.741 | 1.568 | tNET | RR | 1 | R45C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_56_s0/CLK |
7.690 | -0.051 | tSu | 1 | R45C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_56_s0 |
Path Statistics:
Clock Skew | -0.029 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.926, 20.518%; route: 3.281, 72.701%; tC2Q: 0.306, 6.780% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.568, 100.000% |
Path48
Path Summary:
Slack | 1.584 |
Data Arrival Time | 6.120 |
Data Required Time | 7.704 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_61_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.430 | 2.526 | tNET | RR | 1 | R44C129[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n397_s2/I2 |
4.836 | 0.406 | tINS | RR | 2 | R44C129[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n397_s2/F |
5.657 | 0.821 | tNET | RR | 1 | R42C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n389_s1/I1 |
6.120 | 0.463 | tINS | RR | 1 | R42C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n389_s1/F |
6.120 | 0.000 | tNET | RR | 1 | R42C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_61_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.755 | 1.582 | tNET | RR | 1 | R42C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_61_s0/CLK |
7.704 | -0.051 | tSu | 1 | R42C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_61_s0 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.869, 19.217%; route: 3.347, 74.016%; tC2Q: 0.306, 6.767% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.582, 100.000% |
Path49
Path Summary:
Slack | 1.588 |
Data Arrival Time | 6.110 |
Data Required Time | 7.698 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.597 | 1.597 | tNET | RR | 1 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/CLK |
1.903 | 0.306 | tC2Q | RR | 120 | R38C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_0_s0/Q |
4.438 | 2.534 | tNET | RR | 1 | R43C131[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s3/I2 |
4.900 | 0.463 | tINS | RR | 7 | R43C131[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s3/F |
5.648 | 0.747 | tNET | RR | 1 | R45C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n804_s2/I0 |
6.110 | 0.463 | tINS | RR | 1 | R45C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n804_s2/F |
6.110 | 0.000 | tNET | RR | 1 | R45C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.749 | 1.576 | tNET | RR | 1 | R45C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0/CLK |
7.698 | -0.051 | tSu | 1 | R45C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_40_s0 |
Path Statistics:
Clock Skew | -0.021 |
Setup Relationship | 6.173 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.597, 100.000% |
Arrival Data Path Delay | cell: 0.926, 20.518%; route: 3.281, 72.701%; tC2Q: 0.306, 6.780% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.576, 100.000% |
Path50
Path Summary:
Slack | 1.601 |
Data Arrival Time | 6.110 |
Data Required Time | 7.711 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_14_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.576 | 1.576 | tNET | RR | 1 | R45C139[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_14_s0/CLK |
1.882 | 0.306 | tC2Q | RR | 3 | R45C139[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_14_s0/Q |
3.043 | 1.161 | tNET | RR | 1 | R44C134[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n980_s4/I0 |
3.408 | 0.365 | tINS | RR | 2 | R44C134[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n980_s4/F |
4.001 | 0.593 | tNET | RR | 1 | R44C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n796_s3/I1 |
4.464 | 0.463 | tINS | RR | 6 | R44C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n796_s3/F |
5.672 | 1.208 | tNET | RR | 1 | R42C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n434_s2/I0 |
6.110 | 0.438 | tINS | RR | 1 | R42C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n434_s2/F |
6.110 | 0.000 | tNET | RR | 1 | R42C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.762 | 1.590 | tNET | RR | 1 | R42C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0/CLK |
7.711 | -0.051 | tSu | 1 | R42C119[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0 |
Path Statistics:
Clock Skew | 0.013 |
Setup Relationship | 6.173 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.576, 100.000% |
Arrival Data Path Delay | cell: 1.266, 27.922%; route: 2.962, 65.329%; tC2Q: 0.306, 6.749% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.590, 100.000% |
Setup Analysis Report[3]:
Report Command:report_timing -setup -from_clock [get_clocks {xgmii_clk}] -to_clock [get_clocks {xgmii_clk}] -max_paths 50 -max_common_paths 1
Path1
Path Summary:
Slack | 0.949 |
Data Arrival Time | 9.844 |
Data Required Time | 10.793 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_44_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
8.106 | 0.311 | tNET | RR | 1 | R51C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s18/I0 |
8.569 | 0.463 | tINS | RR | 5 | R51C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s18/F |
8.573 | 0.004 | tNET | RR | 1 | R51C148[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s17/I0 |
8.938 | 0.365 | tINS | RR | 4 | R51C148[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s17/F |
9.613 | 0.676 | tNET | RR | 1 | R48C148[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4590_s10/I0 |
9.844 | 0.231 | tINS | RR | 1 | R48C148[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4590_s10/F |
9.844 | 0.000 | tNET | RR | 1 | R48C148[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_44_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.844 | 4.444 | tNET | RR | 1 | R48C148[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_44_s0/CLK |
10.793 | -0.051 | tSu | 1 | R48C148[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_44_s0 |
Path Statistics:
Clock Skew | -0.062 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.887, 35.350%; route: 3.157, 59.142%; tC2Q: 0.294, 5.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.444, 100.000% |
Path2
Path Summary:
Slack | 0.949 |
Data Arrival Time | 9.844 |
Data Required Time | 10.793 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_47_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
8.106 | 0.311 | tNET | RR | 1 | R51C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s18/I0 |
8.569 | 0.463 | tINS | RR | 5 | R51C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s18/F |
8.573 | 0.004 | tNET | RR | 1 | R51C148[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s17/I0 |
8.938 | 0.365 | tINS | RR | 4 | R51C148[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s17/F |
9.613 | 0.676 | tNET | RR | 1 | R48C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s10/I0 |
9.844 | 0.231 | tINS | RR | 1 | R48C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s10/F |
9.844 | 0.000 | tNET | RR | 1 | R48C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_47_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.844 | 4.444 | tNET | RR | 1 | R48C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_47_s0/CLK |
10.793 | -0.051 | tSu | 1 | R48C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_47_s0 |
Path Statistics:
Clock Skew | -0.062 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.887, 35.350%; route: 3.157, 59.142%; tC2Q: 0.294, 5.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.444, 100.000% |
Path3
Path Summary:
Slack | 1.018 |
Data Arrival Time | 9.773 |
Data Required Time | 10.791 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_46_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
8.106 | 0.311 | tNET | RR | 1 | R51C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s18/I0 |
8.569 | 0.463 | tINS | RR | 5 | R51C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s18/F |
8.911 | 0.342 | tNET | RR | 1 | R49C147[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4588_s11/I3 |
9.317 | 0.406 | tINS | RR | 1 | R49C147[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4588_s11/F |
9.319 | 0.002 | tNET | RR | 1 | R49C147[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4588_s10/I2 |
9.773 | 0.454 | tINS | RR | 1 | R49C147[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4588_s10/F |
9.773 | 0.000 | tNET | RR | 1 | R49C147[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_46_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.842 | 4.442 | tNET | RR | 1 | R49C147[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_46_s0/CLK |
10.791 | -0.051 | tSu | 1 | R49C147[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_46_s0 |
Path Statistics:
Clock Skew | -0.065 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 2.151, 40.847%; route: 2.821, 53.570%; tC2Q: 0.294, 5.583% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.442, 100.000% |
Path4
Path Summary:
Slack | 1.043 |
Data Arrival Time | 9.742 |
Data Required Time | 10.786 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_45_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
8.106 | 0.311 | tNET | RR | 1 | R51C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s18/I0 |
8.569 | 0.463 | tINS | RR | 5 | R51C148[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s18/F |
9.078 | 0.509 | tNET | RR | 1 | R48C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4589_s11/I3 |
9.333 | 0.255 | tINS | RF | 1 | R48C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4589_s11/F |
9.337 | 0.004 | tNET | FF | 1 | R48C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4589_s10/I2 |
9.743 | 0.406 | tINS | FR | 1 | R48C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4589_s10/F |
9.743 | 0.000 | tNET | RR | 1 | R48C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_45_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.837 | 4.437 | tNET | RR | 1 | R48C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_45_s0/CLK |
10.786 | -0.051 | tSu | 1 | R48C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_45_s0 |
Path Statistics:
Clock Skew | -0.070 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.952, 37.280%; route: 2.990, 57.105%; tC2Q: 0.294, 5.615% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.437, 100.000% |
Path5
Path Summary:
Slack | 1.258 |
Data Arrival Time | 9.614 |
Data Required Time | 10.872 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_2_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.772 | 0.292 | tNET | RR | 1 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/I2 |
7.226 | 0.454 | tINS | RR | 2 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/F |
7.366 | 0.140 | tNET | RR | 1 | R51C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s4/I2 |
7.829 | 0.463 | tINS | RR | 2 | R51C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s4/F |
8.406 | 0.577 | tNET | RR | 1 | R53C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s4/I1 |
8.812 | 0.406 | tINS | RR | 3 | R53C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s4/F |
9.151 | 0.339 | tNET | RR | 1 | R53C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3307_s3/I0 |
9.614 | 0.463 | tINS | RR | 1 | R53C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3307_s3/F |
9.614 | 0.000 | tNET | RR | 1 | R53C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.923 | 4.523 | tNET | RR | 1 | R53C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_2_s0/CLK |
10.872 | -0.051 | tSu | 1 | R53C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_2_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 2.249, 44.150%; route: 2.539, 49.843%; tC2Q: 0.306, 6.007% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Path6
Path Summary:
Slack | 1.258 |
Data Arrival Time | 9.614 |
Data Required Time | 10.872 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_d3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.772 | 0.292 | tNET | RR | 1 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/I2 |
7.226 | 0.454 | tINS | RR | 2 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/F |
7.366 | 0.140 | tNET | RR | 1 | R51C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s4/I2 |
7.829 | 0.463 | tINS | RR | 2 | R51C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s4/F |
8.406 | 0.577 | tNET | RR | 1 | R53C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s4/I1 |
8.812 | 0.406 | tINS | RR | 3 | R53C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s4/F |
9.151 | 0.339 | tNET | RR | 1 | R53C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3306_s2/I0 |
9.614 | 0.463 | tINS | RR | 1 | R53C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3306_s2/F |
9.614 | 0.000 | tNET | RR | 1 | R53C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_d3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.923 | 4.523 | tNET | RR | 1 | R53C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_d3_s0/CLK |
10.872 | -0.051 | tSu | 1 | R53C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_d3_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 2.249, 44.150%; route: 2.539, 49.843%; tC2Q: 0.306, 6.007% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Path7
Path Summary:
Slack | 1.296 |
Data Arrival Time | 9.371 |
Data Required Time | 10.667 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
8.743 | 0.177 | tNET | RR | 1 | R35C137[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
9.202 | 0.459 | tINS | RR | 1 | R35C137[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
9.371 | 0.169 | tNET | RR | 1 | R35C138[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.916 | 4.516 | tNET | RR | 1 | R35C138[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
10.667 | -0.249 | tSu | 1 | R35C138[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.616, 33.333%; route: 2.926, 60.355%; tC2Q: 0.306, 6.312% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.516, 100.000% |
Path8
Path Summary:
Slack | 1.308 |
Data Arrival Time | 9.389 |
Data Required Time | 10.697 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/CLK |
4.841 | 0.306 | tC2Q | RR | 2 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q |
5.148 | 0.307 | tNET | RR | 1 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I1 |
5.611 | 0.463 | tINS | RR | 2 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
6.347 | 0.736 | tNET | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
6.785 | 0.438 | tINS | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
7.209 | 0.424 | tNET | RR | 2 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
7.645 | 0.436 | tINS | RR | 1 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
7.645 | 0.000 | tNET | RR | 2 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
7.685 | 0.040 | tINS | RR | 1 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
7.685 | 0.000 | tNET | RR | 2 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
7.725 | 0.040 | tINS | RR | 1 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/COUT |
7.725 | 0.000 | tNET | RR | 2 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/CIN |
7.962 | 0.237 | tINS | RR | 1 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/SUM |
8.083 | 0.121 | tNET | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I2 |
8.521 | 0.438 | tINS | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
8.523 | 0.002 | tNET | RR | 1 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
8.961 | 0.438 | tINS | RR | 5 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
9.389 | 0.428 | tNET | RR | 1 | R41C141[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.946 | 4.546 | tNET | RR | 1 | R41C141[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CLK |
10.697 | -0.249 | tSu | 1 | R41C141[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
Path Statistics:
Clock Skew | 0.011 |
Setup Relationship | 6.400 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 2.530, 52.122%; route: 2.018, 41.574%; tC2Q: 0.306, 6.304% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.546, 100.000% |
Path9
Path Summary:
Slack | 1.308 |
Data Arrival Time | 9.389 |
Data Required Time | 10.697 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/CLK |
4.841 | 0.306 | tC2Q | RR | 2 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q |
5.148 | 0.307 | tNET | RR | 1 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I1 |
5.611 | 0.463 | tINS | RR | 2 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
6.347 | 0.736 | tNET | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
6.785 | 0.438 | tINS | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
7.209 | 0.424 | tNET | RR | 2 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
7.645 | 0.436 | tINS | RR | 1 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
7.645 | 0.000 | tNET | RR | 2 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
7.685 | 0.040 | tINS | RR | 1 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
7.685 | 0.000 | tNET | RR | 2 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
7.725 | 0.040 | tINS | RR | 1 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/COUT |
7.725 | 0.000 | tNET | RR | 2 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/CIN |
7.962 | 0.237 | tINS | RR | 1 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/SUM |
8.083 | 0.121 | tNET | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I2 |
8.521 | 0.438 | tINS | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
8.523 | 0.002 | tNET | RR | 1 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
8.961 | 0.438 | tINS | RR | 5 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
9.389 | 0.428 | tNET | RR | 1 | R41C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.946 | 4.546 | tNET | RR | 1 | R41C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CLK |
10.697 | -0.249 | tSu | 1 | R41C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
Path Statistics:
Clock Skew | 0.011 |
Setup Relationship | 6.400 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 2.530, 52.122%; route: 2.018, 41.574%; tC2Q: 0.306, 6.304% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.546, 100.000% |
Path10
Path Summary:
Slack | 1.308 |
Data Arrival Time | 9.389 |
Data Required Time | 10.697 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/CLK |
4.841 | 0.306 | tC2Q | RR | 2 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q |
5.148 | 0.307 | tNET | RR | 1 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I1 |
5.611 | 0.463 | tINS | RR | 2 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
6.347 | 0.736 | tNET | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
6.785 | 0.438 | tINS | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
7.209 | 0.424 | tNET | RR | 2 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
7.645 | 0.436 | tINS | RR | 1 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
7.645 | 0.000 | tNET | RR | 2 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
7.685 | 0.040 | tINS | RR | 1 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
7.685 | 0.000 | tNET | RR | 2 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
7.725 | 0.040 | tINS | RR | 1 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/COUT |
7.725 | 0.000 | tNET | RR | 2 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/CIN |
7.962 | 0.237 | tINS | RR | 1 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/SUM |
8.083 | 0.121 | tNET | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I2 |
8.521 | 0.438 | tINS | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
8.523 | 0.002 | tNET | RR | 1 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
8.961 | 0.438 | tINS | RR | 5 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
9.389 | 0.428 | tNET | RR | 1 | R41C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.946 | 4.546 | tNET | RR | 1 | R41C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CLK |
10.697 | -0.249 | tSu | 1 | R41C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
Path Statistics:
Clock Skew | 0.011 |
Setup Relationship | 6.400 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 2.530, 52.122%; route: 2.018, 41.574%; tC2Q: 0.306, 6.304% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.546, 100.000% |
Path11
Path Summary:
Slack | 1.357 |
Data Arrival Time | 9.503 |
Data Required Time | 10.861 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_49_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
7.939 | 0.144 | tNET | RR | 1 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/I0 |
8.398 | 0.459 | tINS | RR | 6 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/F |
9.097 | 0.700 | tNET | RR | 1 | R47C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4585_s11/I3 |
9.503 | 0.406 | tINS | RR | 1 | R47C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4585_s11/F |
9.503 | 0.000 | tNET | RR | 1 | R47C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_49_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.911 | 4.511 | tNET | RR | 1 | R47C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_49_s0/CLK |
10.861 | -0.051 | tSu | 1 | R47C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_49_s0 |
Path Statistics:
Clock Skew | 0.005 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.693, 33.880%; route: 3.010, 60.236%; tC2Q: 0.294, 5.884% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.511, 100.000% |
Path12
Path Summary:
Slack | 1.367 |
Data Arrival Time | 9.507 |
Data Required Time | 10.874 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
9.101 | 0.535 | tNET | RR | 1 | R36C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n870_s1/I3 |
9.507 | 0.406 | tINS | RR | 1 | R36C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n870_s1/F |
9.507 | 0.000 | tNET | RR | 1 | R36C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.925 | 4.525 | tNET | RR | 1 | R36C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
10.874 | -0.051 | tSu | 1 | R36C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.563, 31.360%; route: 3.115, 62.500%; tC2Q: 0.306, 6.140% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.525, 100.000% |
Path13
Path Summary:
Slack | 1.394 |
Data Arrival Time | 9.412 |
Data Required Time | 10.807 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_50_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
7.939 | 0.144 | tNET | RR | 1 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/I0 |
8.398 | 0.459 | tINS | RR | 6 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/F |
8.958 | 0.561 | tNET | RR | 1 | R47C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4584_s11/I3 |
9.413 | 0.454 | tINS | RR | 1 | R47C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4584_s11/F |
9.413 | 0.000 | tNET | RR | 1 | R47C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_50_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.858 | 4.457 | tNET | RR | 1 | R47C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_50_s0/CLK |
10.807 | -0.051 | tSu | 1 | R47C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_50_s0 |
Path Statistics:
Clock Skew | -0.049 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.741, 35.487%; route: 2.871, 58.520%; tC2Q: 0.294, 5.993% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.457, 100.000% |
Path14
Path Summary:
Slack | 1.442 |
Data Arrival Time | 9.251 |
Data Required Time | 10.693 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/CLK |
4.841 | 0.306 | tC2Q | RR | 2 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q |
5.148 | 0.307 | tNET | RR | 1 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I1 |
5.611 | 0.463 | tINS | RR | 2 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
6.347 | 0.736 | tNET | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
6.785 | 0.438 | tINS | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
7.209 | 0.424 | tNET | RR | 2 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
7.645 | 0.436 | tINS | RR | 1 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
7.645 | 0.000 | tNET | RR | 2 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
7.685 | 0.040 | tINS | RR | 1 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
7.685 | 0.000 | tNET | RR | 2 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
7.725 | 0.040 | tINS | RR | 1 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/COUT |
7.725 | 0.000 | tNET | RR | 2 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/CIN |
7.962 | 0.237 | tINS | RR | 1 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/SUM |
8.083 | 0.121 | tNET | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I2 |
8.521 | 0.438 | tINS | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
8.523 | 0.002 | tNET | RR | 1 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
8.961 | 0.438 | tINS | RR | 5 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
9.251 | 0.290 | tNET | RR | 1 | R43C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.942 | 4.542 | tNET | RR | 1 | R43C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CLK |
10.693 | -0.249 | tSu | 1 | R43C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
Path Statistics:
Clock Skew | 0.007 |
Setup Relationship | 6.400 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 2.530, 53.647%; route: 1.880, 39.864%; tC2Q: 0.306, 6.489% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.542, 100.000% |
Path15
Path Summary:
Slack | 1.442 |
Data Arrival Time | 9.251 |
Data Required Time | 10.693 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/CLK |
4.841 | 0.306 | tC2Q | RR | 2 | R39C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_2_s0/Q |
5.148 | 0.307 | tNET | RR | 1 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I1 |
5.611 | 0.463 | tINS | RR | 2 | R40C142[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
6.347 | 0.736 | tNET | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
6.785 | 0.438 | tINS | RR | 1 | R41C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
7.209 | 0.424 | tNET | RR | 2 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
7.645 | 0.436 | tINS | RR | 1 | R44C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
7.645 | 0.000 | tNET | RR | 2 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
7.685 | 0.040 | tINS | RR | 1 | R44C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
7.685 | 0.000 | tNET | RR | 2 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
7.725 | 0.040 | tINS | RR | 1 | R44C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/COUT |
7.725 | 0.000 | tNET | RR | 2 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/CIN |
7.962 | 0.237 | tINS | RR | 1 | R44C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/SUM |
8.083 | 0.121 | tNET | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I2 |
8.521 | 0.438 | tINS | RR | 1 | R44C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
8.523 | 0.002 | tNET | RR | 1 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
8.961 | 0.438 | tINS | RR | 5 | R44C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
9.251 | 0.290 | tNET | RR | 1 | R43C141[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.942 | 4.542 | tNET | RR | 1 | R43C141[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CLK |
10.693 | -0.249 | tSu | 1 | R43C141[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0 |
Path Statistics:
Clock Skew | 0.007 |
Setup Relationship | 6.400 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 2.530, 53.647%; route: 1.880, 39.864%; tC2Q: 0.306, 6.489% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.542, 100.000% |
Path16
Path Summary:
Slack | 1.503 |
Data Arrival Time | 9.354 |
Data Required Time | 10.857 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_0_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.772 | 0.292 | tNET | RR | 1 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/I2 |
7.226 | 0.454 | tINS | RR | 2 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/F |
7.366 | 0.140 | tNET | RR | 1 | R51C139[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s8/I2 |
7.731 | 0.365 | tINS | RR | 2 | R51C139[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s8/F |
8.038 | 0.307 | tNET | RR | 1 | R52C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s2/I3 |
8.444 | 0.406 | tINS | RR | 1 | R52C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s2/F |
8.916 | 0.472 | tNET | RR | 1 | R53C143[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s1/I0 |
9.354 | 0.438 | tINS | RR | 1 | R53C143[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s1/F |
9.354 | 0.000 | tNET | RR | 1 | R53C143[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.908 | 4.508 | tNET | RR | 1 | R53C143[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_0_s0/CLK |
10.857 | -0.051 | tSu | 1 | R53C143[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 2.126, 43.980%; route: 2.402, 49.690%; tC2Q: 0.306, 6.330% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.508, 100.000% |
Path17
Path Summary:
Slack | 1.506 |
Data Arrival Time | 9.368 |
Data Required Time | 10.874 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
8.914 | 0.348 | tNET | RR | 1 | R36C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n871_s1/I3 |
9.368 | 0.454 | tINS | RR | 1 | R36C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n871_s1/F |
9.368 | 0.000 | tNET | RR | 1 | R36C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.925 | 4.525 | tNET | RR | 1 | R36C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
10.874 | -0.051 | tSu | 1 | R36C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.611, 33.251%; route: 2.928, 60.433%; tC2Q: 0.306, 6.316% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.525, 100.000% |
Path18
Path Summary:
Slack | 1.506 |
Data Arrival Time | 9.368 |
Data Required Time | 10.874 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
8.914 | 0.348 | tNET | RR | 1 | R36C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s2/I2 |
9.368 | 0.454 | tINS | RR | 1 | R36C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s2/F |
9.368 | 0.000 | tNET | RR | 1 | R36C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.925 | 4.525 | tNET | RR | 1 | R36C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
10.874 | -0.051 | tSu | 1 | R36C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.611, 33.251%; route: 2.928, 60.433%; tC2Q: 0.306, 6.316% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.525, 100.000% |
Path19
Path Summary:
Slack | 1.587 |
Data Arrival Time | 9.265 |
Data Required Time | 10.852 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
7.939 | 0.144 | tNET | RR | 1 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/I0 |
8.398 | 0.459 | tINS | RR | 6 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/F |
8.811 | 0.414 | tNET | RR | 1 | R49C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4591_s11/I3 |
9.265 | 0.454 | tINS | RR | 1 | R49C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4591_s11/F |
9.265 | 0.000 | tNET | RR | 1 | R49C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.903 | 4.503 | tNET | RR | 1 | R49C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0/CLK |
10.852 | -0.051 | tSu | 1 | R49C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.741, 36.583%; route: 2.724, 57.239%; tC2Q: 0.294, 6.178% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.503, 100.000% |
Path20
Path Summary:
Slack | 1.599 |
Data Arrival Time | 9.194 |
Data Required Time | 10.793 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_48_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
7.939 | 0.144 | tNET | RR | 1 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/I0 |
8.398 | 0.459 | tINS | RR | 6 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/F |
8.741 | 0.343 | tNET | RR | 1 | R48C146[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4586_s11/I3 |
9.194 | 0.454 | tINS | RR | 1 | R48C146[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4586_s11/F |
9.194 | 0.000 | tNET | RR | 1 | R48C146[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_48_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.844 | 4.444 | tNET | RR | 1 | R48C146[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_48_s0/CLK |
10.793 | -0.051 | tSu | 1 | R48C146[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_48_s0 |
Path Statistics:
Clock Skew | -0.062 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.741, 37.137%; route: 2.653, 56.591%; tC2Q: 0.294, 6.271% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.444, 100.000% |
Path21
Path Summary:
Slack | 1.632 |
Data Arrival Time | 9.239 |
Data Required Time | 10.871 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_ODDD_d3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.486 | 0.006 | tNET | RR | 1 | R50C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s31/I3 |
6.924 | 0.438 | tINS | RR | 1 | R50C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s31/F |
7.229 | 0.305 | tNET | RR | 1 | R51C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s9/I3 |
7.667 | 0.438 | tINS | RR | 4 | R51C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s9/F |
7.809 | 0.142 | tNET | RR | 1 | R51C140[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2938_s3/I0 |
8.042 | 0.233 | tINS | RR | 2 | R51C140[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2938_s3/F |
8.785 | 0.743 | tNET | RR | 1 | R52C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2939_s1/I1 |
9.239 | 0.454 | tINS | RR | 1 | R52C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2939_s1/F |
9.239 | 0.000 | tNET | RR | 1 | R52C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_ODDD_d3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.922 | 4.522 | tNET | RR | 1 | R52C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_ODDD_d3_s0/CLK |
10.871 | -0.051 | tSu | 1 | R52C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_ODDD_d3_s0 |
Path Statistics:
Clock Skew | 0.002 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 2.026, 42.933%; route: 2.387, 50.583%; tC2Q: 0.306, 6.484% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.522, 100.000% |
Path22
Path Summary:
Slack | 1.660 |
Data Arrival Time | 9.212 |
Data Required Time | 10.872 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_30_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.460 | 4.460 | tNET | RR | 1 | R52C150[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/CLK |
4.754 | 0.294 | tC2Q | RF | 36 | R52C150[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/Q |
5.406 | 0.652 | tNET | FF | 1 | R51C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s16/I2 |
5.771 | 0.365 | tINS | FR | 26 | R51C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s16/F |
8.073 | 2.302 | tNET | RR | 1 | R53C148[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4603_s13/I3 |
8.438 | 0.365 | tINS | RR | 2 | R53C148[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4603_s13/F |
8.806 | 0.368 | tNET | RR | 1 | R53C145[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4604_s10/I3 |
9.212 | 0.406 | tINS | RR | 1 | R53C145[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4604_s10/F |
9.212 | 0.000 | tNET | RR | 1 | R53C145[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_30_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.923 | 4.523 | tNET | RR | 1 | R53C145[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_30_s0/CLK |
10.872 | -0.051 | tSu | 1 | R53C145[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_30_s0 |
Path Statistics:
Clock Skew | 0.063 |
Setup Relationship | 6.400 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.460, 100.000% |
Arrival Data Path Delay | cell: 1.136, 23.906%; route: 3.322, 69.907%; tC2Q: 0.294, 6.187% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Path23
Path Summary:
Slack | 1.662 |
Data Arrival Time | 9.143 |
Data Required Time | 10.806 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_55_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
7.939 | 0.144 | tNET | RR | 1 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/I0 |
8.398 | 0.459 | tINS | RR | 6 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/F |
8.689 | 0.292 | tNET | RR | 1 | R49C149[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4579_s11/I3 |
9.143 | 0.454 | tINS | RR | 1 | R49C149[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4579_s11/F |
9.143 | 0.000 | tNET | RR | 1 | R49C149[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_55_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.857 | 4.457 | tNET | RR | 1 | R49C149[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_55_s0/CLK |
10.806 | -0.051 | tSu | 1 | R49C149[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_55_s0 |
Path Statistics:
Clock Skew | -0.050 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.741, 37.546%; route: 2.602, 56.114%; tC2Q: 0.294, 6.340% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.457, 100.000% |
Path24
Path Summary:
Slack | 1.675 |
Data Arrival Time | 9.197 |
Data Required Time | 10.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
8.743 | 0.177 | tNET | RR | 1 | R35C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n874_s1/I2 |
9.197 | 0.454 | tINS | RR | 1 | R35C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n874_s1/F |
9.197 | 0.000 | tNET | RR | 1 | R35C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.923 | 4.523 | tNET | RR | 1 | R35C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
10.872 | -0.051 | tSu | 1 | R35C137[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.611, 34.467%; route: 2.757, 58.986%; tC2Q: 0.306, 6.547% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Path25
Path Summary:
Slack | 1.675 |
Data Arrival Time | 9.197 |
Data Required Time | 10.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
8.743 | 0.177 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n873_s3/I3 |
9.197 | 0.454 | tINS | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n873_s3/F |
9.197 | 0.000 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.923 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
10.872 | -0.051 | tSu | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.611, 34.467%; route: 2.757, 58.986%; tC2Q: 0.306, 6.547% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Path26
Path Summary:
Slack | 1.734 |
Data Arrival Time | 9.062 |
Data Required Time | 10.795 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_54_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.624 | 0.811 | tNET | RR | 1 | R50C147[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s15/I0 |
8.030 | 0.406 | tINS | RR | 1 | R50C147[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s15/F |
8.032 | 0.002 | tNET | RR | 1 | R50C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s11/I2 |
8.486 | 0.454 | tINS | RR | 1 | R50C147[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s11/F |
8.608 | 0.121 | tNET | RR | 1 | R50C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s10/I0 |
9.062 | 0.454 | tINS | RR | 1 | R50C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s10/F |
9.062 | 0.000 | tNET | RR | 1 | R50C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_54_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.846 | 4.446 | tNET | RR | 1 | R50C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_54_s0/CLK |
10.795 | -0.051 | tSu | 1 | R50C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_54_s0 |
Path Statistics:
Clock Skew | -0.060 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.777, 39.012%; route: 2.484, 54.533%; tC2Q: 0.294, 6.454% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.446, 100.000% |
Path27
Path Summary:
Slack | 1.744 |
Data Arrival Time | 9.074 |
Data Required Time | 10.818 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_31_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R53C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0/CLK |
4.817 | 0.294 | tC2Q | RF | 22 | R53C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0/Q |
5.965 | 1.148 | tNET | FF | 1 | R50C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4600_s13/I2 |
6.371 | 0.406 | tINS | FR | 6 | R50C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4600_s13/F |
7.151 | 0.780 | tNET | RR | 1 | R53C148[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s15/I1 |
7.557 | 0.406 | tINS | RR | 2 | R53C148[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s15/F |
7.847 | 0.290 | tNET | RR | 1 | R53C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4603_s10/I0 |
8.306 | 0.459 | tINS | RR | 2 | R53C146[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4603_s10/F |
8.611 | 0.305 | tNET | RR | 1 | R53C149[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4603_s9/I0 |
9.074 | 0.463 | tINS | RR | 1 | R53C149[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4603_s9/F |
9.074 | 0.000 | tNET | RR | 1 | R53C149[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_31_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.869 | 4.469 | tNET | RR | 1 | R53C149[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_31_s0/CLK |
10.818 | -0.051 | tSu | 1 | R53C149[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_31_s0 |
Path Statistics:
Clock Skew | -0.054 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.734, 38.102%; route: 2.523, 55.438%; tC2Q: 0.294, 6.460% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.469, 100.000% |
Path28
Path Summary:
Slack | 1.751 |
Data Arrival Time | 9.051 |
Data Required Time | 10.802 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_CCCC_d3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.486 | 0.006 | tNET | RR | 1 | R50C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s31/I3 |
6.924 | 0.438 | tINS | RR | 1 | R50C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s31/F |
7.229 | 0.305 | tNET | RR | 1 | R51C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s9/I3 |
7.667 | 0.438 | tINS | RR | 4 | R51C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s9/F |
7.809 | 0.142 | tNET | RR | 1 | R51C140[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2938_s3/I0 |
8.042 | 0.233 | tINS | RR | 2 | R51C140[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2938_s3/F |
8.588 | 0.546 | tNET | RR | 1 | R52C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2938_s1/I1 |
9.051 | 0.463 | tINS | RR | 1 | R52C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2938_s1/F |
9.051 | 0.000 | tNET | RR | 1 | R52C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_CCCC_d3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.852 | 4.452 | tNET | RR | 1 | R52C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_CCCC_d3_s0/CLK |
10.802 | -0.051 | tSu | 1 | R52C147[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/ODDD_CCCC_d3_s0 |
Path Statistics:
Clock Skew | -0.068 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 2.035, 44.913%; route: 2.190, 48.334%; tC2Q: 0.306, 6.753% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.452, 100.000% |
Path29
Path Summary:
Slack | 1.838 |
Data Arrival Time | 8.948 |
Data Required Time | 10.786 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_42_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.430 | 0.616 | tNET | RR | 1 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/I1 |
7.795 | 0.365 | tINS | RR | 6 | R50C147[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4587_s16/F |
7.939 | 0.144 | tNET | RR | 1 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/I0 |
8.398 | 0.459 | tINS | RR | 6 | R49C147[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s13/F |
8.542 | 0.144 | tNET | RR | 1 | R48C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s11/I3 |
8.948 | 0.406 | tINS | RR | 1 | R48C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4592_s11/F |
8.948 | 0.000 | tNET | RR | 1 | R48C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_42_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.837 | 4.437 | tNET | RR | 1 | R48C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_42_s0/CLK |
10.786 | -0.051 | tSu | 1 | R48C147[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_42_s0 |
Path Statistics:
Clock Skew | -0.070 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.693, 38.122%; route: 2.454, 55.258%; tC2Q: 0.294, 6.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.437, 100.000% |
Path30
Path Summary:
Slack | 1.854 |
Data Arrival Time | 8.961 |
Data Required Time | 10.815 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_32_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R53C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0/CLK |
4.817 | 0.294 | tC2Q | RF | 22 | R53C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0/Q |
5.965 | 1.148 | tNET | FF | 1 | R50C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4600_s13/I2 |
6.371 | 0.406 | tINS | FR | 6 | R50C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4600_s13/F |
7.151 | 0.780 | tNET | RR | 1 | R53C148[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s15/I1 |
7.557 | 0.406 | tINS | RR | 2 | R53C148[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s15/F |
7.561 | 0.004 | tNET | RR | 1 | R53C148[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s19/I0 |
8.024 | 0.463 | tINS | RR | 2 | R53C148[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s19/F |
8.498 | 0.474 | tNET | RR | 1 | R51C149[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4602_s10/I1 |
8.961 | 0.463 | tINS | RR | 1 | R51C149[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4602_s10/F |
8.961 | 0.000 | tNET | RR | 1 | R51C149[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_32_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.866 | 4.466 | tNET | RR | 1 | R51C149[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_32_s0/CLK |
10.815 | -0.051 | tSu | 1 | R51C149[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_32_s0 |
Path Statistics:
Clock Skew | -0.057 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.738, 39.162%; route: 2.406, 54.214%; tC2Q: 0.294, 6.625% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.466, 100.000% |
Path31
Path Summary:
Slack | 1.877 |
Data Arrival Time | 8.987 |
Data Required Time | 10.865 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
8.581 | 0.015 | tNET | RR | 1 | R35C136[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n877_s1/I2 |
8.987 | 0.406 | tINS | RR | 1 | R35C136[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n877_s1/F |
8.987 | 0.000 | tNET | RR | 1 | R35C136[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.916 | 4.516 | tNET | RR | 1 | R35C136[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
10.865 | -0.051 | tSu | 1 | R35C136[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.563, 35.013%; route: 2.595, 58.132%; tC2Q: 0.306, 6.855% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.516, 100.000% |
Path32
Path Summary:
Slack | 1.877 |
Data Arrival Time | 8.987 |
Data Required Time | 10.865 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
8.581 | 0.015 | tNET | RR | 1 | R35C136[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n876_s1/I3 |
8.987 | 0.406 | tINS | RR | 1 | R35C136[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n876_s1/F |
8.987 | 0.000 | tNET | RR | 1 | R35C136[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.916 | 4.516 | tNET | RR | 1 | R35C136[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
10.865 | -0.051 | tSu | 1 | R35C136[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.563, 35.013%; route: 2.595, 58.132%; tC2Q: 0.306, 6.855% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.516, 100.000% |
Path33
Path Summary:
Slack | 1.877 |
Data Arrival Time | 8.987 |
Data Required Time | 10.865 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
8.581 | 0.015 | tNET | RR | 1 | R35C136[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n875_s1/I2 |
8.987 | 0.406 | tINS | RR | 1 | R35C136[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n875_s1/F |
8.987 | 0.000 | tNET | RR | 1 | R35C136[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.916 | 4.516 | tNET | RR | 1 | R35C136[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
10.865 | -0.051 | tSu | 1 | R35C136[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.563, 35.013%; route: 2.595, 58.132%; tC2Q: 0.306, 6.855% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.516, 100.000% |
Path34
Path Summary:
Slack | 1.904 |
Data Arrival Time | 8.968 |
Data Required Time | 10.872 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.335 | 0.598 | tNET | RR | 1 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/I1 |
8.566 | 0.231 | tINS | RR | 10 | R35C136[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s5/F |
8.737 | 0.171 | tNET | RR | 1 | R35C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n872_s1/I3 |
8.968 | 0.231 | tINS | RR | 1 | R35C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n872_s1/F |
8.968 | 0.000 | tNET | RR | 1 | R35C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.923 | 4.523 | tNET | RR | 1 | R35C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
10.872 | -0.051 | tSu | 1 | R35C137[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.388, 31.226%; route: 2.751, 61.890%; tC2Q: 0.306, 6.884% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Path35
Path Summary:
Slack | 1.957 |
Data Arrival Time | 8.908 |
Data Required Time | 10.865 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
4.829 | 0.306 | tC2Q | RR | 13 | R35C137[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
6.523 | 1.694 | tNET | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/I2 |
6.986 | 0.463 | tINS | RR | 1 | R34C128[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s14/F |
7.274 | 0.288 | tNET | RR | 1 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/I3 |
7.737 | 0.463 | tINS | RR | 2 | R34C130[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s8/F |
8.454 | 0.717 | tNET | RR | 1 | R35C136[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n878_s2/I2 |
8.908 | 0.454 | tINS | RR | 1 | R35C136[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n878_s2/F |
8.908 | 0.000 | tNET | RR | 1 | R35C136[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.916 | 4.516 | tNET | RR | 1 | R35C136[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
10.865 | -0.051 | tSu | 1 | R35C136[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 6.400 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.380, 31.471%; route: 2.699, 61.551%; tC2Q: 0.306, 6.978% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.516, 100.000% |
Path36
Path Summary:
Slack | 2.030 |
Data Arrival Time | 8.785 |
Data Required Time | 10.815 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_33_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.523 | 4.523 | tNET | RR | 1 | R53C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0/CLK |
4.817 | 0.294 | tC2Q | RF | 22 | R53C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_2_s0/Q |
5.965 | 1.148 | tNET | FF | 1 | R50C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4600_s13/I2 |
6.371 | 0.406 | tINS | FR | 6 | R50C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4600_s13/F |
7.151 | 0.780 | tNET | RR | 1 | R53C148[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s15/I1 |
7.557 | 0.406 | tINS | RR | 2 | R53C148[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s15/F |
7.561 | 0.004 | tNET | RR | 1 | R53C148[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s19/I0 |
8.024 | 0.463 | tINS | RR | 2 | R53C148[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s19/F |
8.331 | 0.307 | tNET | RR | 1 | R51C149[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s10/I1 |
8.785 | 0.454 | tINS | RR | 1 | R51C149[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4601_s10/F |
8.785 | 0.000 | tNET | RR | 1 | R51C149[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_33_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.866 | 4.466 | tNET | RR | 1 | R51C149[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_33_s0/CLK |
10.815 | -0.051 | tSu | 1 | R51C149[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_33_s0 |
Path Statistics:
Clock Skew | -0.057 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Arrival Data Path Delay | cell: 1.729, 40.568%; route: 2.239, 52.534%; tC2Q: 0.294, 6.898% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.466, 100.000% |
Path37
Path Summary:
Slack | 2.037 |
Data Arrival Time | 8.832 |
Data Required Time | 10.868 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_52_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.506 | 4.506 | tNET | RR | 1 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/CLK |
4.800 | 0.294 | tC2Q | RF | 16 | R52C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d4_1_s0/Q |
6.351 | 1.550 | tNET | FF | 1 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/I1 |
6.813 | 0.463 | tINS | FR | 5 | R48C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4580_s14/F |
7.312 | 0.498 | tNET | RR | 1 | R48C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4582_s13/I0 |
7.774 | 0.463 | tINS | RR | 1 | R48C145[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4582_s13/F |
7.912 | 0.138 | tNET | RR | 1 | R47C145[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4582_s11/I2 |
8.366 | 0.454 | tINS | RR | 1 | R47C145[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4582_s11/F |
8.368 | 0.002 | tNET | RR | 1 | R47C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4582_s10/I0 |
8.832 | 0.463 | tINS | RR | 1 | R47C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4582_s10/F |
8.832 | 0.000 | tNET | RR | 1 | R47C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_52_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.919 | 4.519 | tNET | RR | 1 | R47C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_52_s0/CLK |
10.868 | -0.051 | tSu | 1 | R47C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_52_s0 |
Path Statistics:
Clock Skew | 0.013 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Arrival Data Path Delay | cell: 1.843, 42.613%; route: 2.188, 50.590%; tC2Q: 0.294, 6.798% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.519, 100.000% |
Path38
Path Summary:
Slack | 2.045 |
Data Arrival Time | 8.812 |
Data Required Time | 10.857 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_1_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.772 | 0.292 | tNET | RR | 1 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/I2 |
7.226 | 0.454 | tINS | RR | 2 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/F |
7.366 | 0.140 | tNET | RR | 1 | R51C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s4/I2 |
7.829 | 0.463 | tINS | RR | 2 | R51C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s4/F |
8.406 | 0.577 | tNET | RR | 1 | R53C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s1/I2 |
8.812 | 0.406 | tINS | RR | 1 | R53C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s1/F |
8.812 | 0.000 | tNET | RR | 1 | R53C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.908 | 4.508 | tNET | RR | 1 | R53C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_1_s0/CLK |
10.857 | -0.051 | tSu | 1 | R53C143[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/T_location_d3_1_s0 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 1.786, 41.612%; route: 2.200, 51.258%; tC2Q: 0.306, 7.130% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.508, 100.000% |
Path39
Path Summary:
Slack | 2.087 |
Data Arrival Time | 8.782 |
Data Required Time | 10.869 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_location_d3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.772 | 0.292 | tNET | RR | 1 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/I2 |
7.226 | 0.454 | tINS | RR | 2 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/F |
7.366 | 0.140 | tNET | RR | 1 | R51C139[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s8/I2 |
7.731 | 0.365 | tINS | RR | 2 | R51C139[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s8/F |
7.871 | 0.140 | tNET | RR | 1 | R51C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3000_s3/I0 |
8.236 | 0.365 | tINS | RR | 2 | R51C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3000_s3/F |
8.376 | 0.140 | tNET | RR | 1 | R51C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3000_s1/I2 |
8.782 | 0.406 | tINS | RR | 1 | R51C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3000_s1/F |
8.782 | 0.000 | tNET | RR | 1 | R51C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_location_d3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.920 | 4.520 | tNET | RR | 1 | R51C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_location_d3_s0/CLK |
10.869 | -0.051 | tSu | 1 | R51C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_location_d3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 2.053, 48.170%; route: 1.903, 44.650%; tC2Q: 0.306, 7.180% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Path40
Path Summary:
Slack | 2.100 |
Data Arrival Time | 8.772 |
Data Required Time | 10.872 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_ODDD_d3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.486 | 0.006 | tNET | RR | 1 | R50C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s31/I3 |
6.924 | 0.438 | tINS | RR | 1 | R50C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s31/F |
7.229 | 0.305 | tNET | RR | 1 | R51C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s9/I3 |
7.667 | 0.438 | tINS | RR | 4 | R51C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s9/F |
8.309 | 0.642 | tNET | RR | 1 | R53C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2937_s1/I0 |
8.772 | 0.463 | tINS | RR | 1 | R53C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2937_s1/F |
8.772 | 0.000 | tNET | RR | 1 | R53C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_ODDD_d3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.923 | 4.523 | tNET | RR | 1 | R53C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_ODDD_d3_s0/CLK |
10.872 | -0.051 | tSu | 1 | R53C145[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_ODDD_d3_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 1.802, 42.380%; route: 2.144, 50.423%; tC2Q: 0.306, 7.197% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.523, 100.000% |
Path41
Path Summary:
Slack | 2.128 |
Data Arrival Time | 8.741 |
Data Required Time | 10.869 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_d3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.772 | 0.292 | tNET | RR | 1 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/I2 |
7.226 | 0.454 | tINS | RR | 2 | R50C139[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3308_s8/F |
7.366 | 0.140 | tNET | RR | 1 | R51C139[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s8/I2 |
7.731 | 0.365 | tINS | RR | 2 | R51C139[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3309_s8/F |
7.871 | 0.140 | tNET | RR | 1 | R51C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3000_s3/I0 |
8.236 | 0.365 | tINS | RR | 2 | R51C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n3000_s3/F |
8.376 | 0.140 | tNET | RR | 1 | R51C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2999_s1/I1 |
8.741 | 0.365 | tINS | RR | 1 | R51C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2999_s1/F |
8.741 | 0.000 | tNET | RR | 1 | R51C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_d3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.920 | 4.520 | tNET | RR | 1 | R51C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_d3_s0/CLK |
10.869 | -0.051 | tSu | 1 | R51C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/S_d3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 6.400 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 2.012, 47.666%; route: 1.903, 45.084%; tC2Q: 0.306, 7.249% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Path42
Path Summary:
Slack | 2.139 |
Data Arrival Time | 8.655 |
Data Required Time | 10.793 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_11_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.459 | 4.459 | tNET | RR | 1 | R51C150[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_0_s0/CLK |
4.765 | 0.306 | tC2Q | RR | 60 | R51C150[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_0_s0/Q |
4.933 | 0.168 | tNET | RR | 1 | R52C150[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n_state_1_s13/I0 |
5.387 | 0.454 | tINS | RR | 8 | R52C150[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n_state_1_s13/F |
5.984 | 0.597 | tNET | RR | 1 | R51C147[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4611_s15/I3 |
6.447 | 0.463 | tINS | RR | 17 | R51C147[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4611_s15/F |
7.746 | 1.299 | tNET | RR | 1 | R49C146[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4623_s11/I0 |
8.111 | 0.365 | tINS | RR | 1 | R49C146[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4623_s11/F |
8.249 | 0.138 | tNET | RR | 1 | R48C146[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4623_s10/I0 |
8.655 | 0.406 | tINS | RR | 1 | R48C146[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4623_s10/F |
8.655 | 0.000 | tNET | RR | 1 | R48C146[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.844 | 4.444 | tNET | RR | 1 | R48C146[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_11_s0/CLK |
10.793 | -0.051 | tSu | 1 | R48C146[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_11_s0 |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.459, 100.000% |
Arrival Data Path Delay | cell: 1.688, 40.229%; route: 2.202, 52.479%; tC2Q: 0.306, 7.293% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.444, 100.000% |
Path43
Path Summary:
Slack | 2.173 |
Data Arrival Time | 8.682 |
Data Required Time | 10.855 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_0_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_20_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.459 | 4.459 | tNET | RR | 1 | R51C150[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_0_s0/CLK |
4.753 | 0.294 | tC2Q | RF | 60 | R51C150[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_0_s0/Q |
5.134 | 0.381 | tNET | FF | 1 | R51C147[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s18/I0 |
5.597 | 0.463 | tINS | FR | 17 | R51C147[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s18/F |
6.626 | 1.029 | tNET | RR | 1 | R52C144[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4614_s13/I0 |
7.089 | 0.463 | tINS | RR | 3 | R52C144[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4614_s13/F |
7.591 | 0.502 | tNET | RR | 1 | R50C145[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4614_s11/I3 |
8.050 | 0.459 | tINS | RR | 1 | R50C145[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4614_s11/F |
8.219 | 0.169 | tNET | RR | 1 | R48C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4614_s10/I1 |
8.682 | 0.463 | tINS | RR | 1 | R48C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4614_s10/F |
8.682 | 0.000 | tNET | RR | 1 | R48C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_20_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.906 | 4.506 | tNET | RR | 1 | R48C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_20_s0/CLK |
10.855 | -0.051 | tSu | 1 | R48C145[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_20_s0 |
Path Statistics:
Clock Skew | 0.047 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.459, 100.000% |
Arrival Data Path Delay | cell: 1.848, 43.760%; route: 2.081, 49.278%; tC2Q: 0.294, 6.962% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.506, 100.000% |
Path44
Path Summary:
Slack | 2.202 |
Data Arrival Time | 8.682 |
Data Required Time | 10.884 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.510 | 4.510 | tNET | RR | 36 | BSRAM_R64[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKB |
6.458 | 1.948 | tC2Q | RR | 2 | BSRAM_R64[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DO[4] |
7.248 | 0.790 | tNET | RR | 1 | R65C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d1_4_s4/I1 |
7.711 | 0.463 | tINS | RR | 2 | R65C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d1_4_s4/F |
8.682 | 0.971 | tNET | RR | 1 | R61C134[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.935 | 4.535 | tNET | RR | 1 | R61C134[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0/CLK |
10.884 | -0.051 | tSu | 1 | R61C134[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0 |
Path Statistics:
Clock Skew | 0.025 |
Setup Relationship | 6.400 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.510, 100.000% |
Arrival Data Path Delay | cell: 0.463, 11.097%; route: 1.761, 42.209%; tC2Q: 1.948, 46.694% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Path45
Path Summary:
Slack | 2.227 |
Data Arrival Time | 8.575 |
Data Required Time | 10.802 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_CCCC_d3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.520 | 4.520 | tNET | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/CLK |
4.826 | 0.306 | tC2Q | RR | 1 | R51C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_3_s0/Q |
6.017 | 1.191 | tNET | RR | 1 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/I2 |
6.480 | 0.463 | tINS | RR | 3 | R50C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s23/F |
6.486 | 0.006 | tNET | RR | 1 | R50C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s31/I3 |
6.924 | 0.438 | tINS | RR | 1 | R50C137[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s31/F |
7.229 | 0.305 | tNET | RR | 1 | R51C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s9/I3 |
7.667 | 0.438 | tINS | RR | 4 | R51C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s9/F |
8.112 | 0.445 | tNET | RR | 1 | R52C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s8/I0 |
8.575 | 0.463 | tINS | RR | 1 | R52C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n2840_s8/F |
8.575 | 0.000 | tNET | RR | 1 | R52C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_CCCC_d3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.852 | 4.452 | tNET | RR | 1 | R52C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_CCCC_d3_s0/CLK |
10.802 | -0.051 | tSu | 1 | R52C147[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/CCCC_CCCC_d3_s0 |
Path Statistics:
Clock Skew | -0.068 |
Setup Relationship | 6.400 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.520, 100.000% |
Arrival Data Path Delay | cell: 1.802, 44.439%; route: 1.947, 48.015%; tC2Q: 0.306, 7.546% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.452, 100.000% |
Path46
Path Summary:
Slack | 2.245 |
Data Arrival Time | 8.675 |
Data Required Time | 10.920 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/data_pattern_select_d1_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/seed_init_51_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.522 | 4.522 | tNET | RR | 1 | R52C129[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/data_pattern_select_d1_s0/CLK |
4.828 | 0.306 | tC2Q | RR | 59 | R52C129[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/data_pattern_select_d1_s0/Q |
8.471 | 3.644 | tNET | RR | 1 | R47C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/n876_s0/S0 |
8.673 | 0.202 | tINS | RR | 1 | R47C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/n876_s0/O |
8.675 | 0.002 | tNET | RR | 1 | R47C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/seed_init_51_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.911 | 4.511 | tNET | RR | 1 | R47C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/seed_init_51_s0/CLK |
10.920 | 0.008 | tSu | 1 | R47C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/seed_init_51_s0 |
Path Statistics:
Clock Skew | -0.010 |
Setup Relationship | 6.400 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.522, 100.000% |
Arrival Data Path Delay | cell: 0.202, 4.863%; route: 3.646, 87.769%; tC2Q: 0.306, 7.367% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.511, 100.000% |
Path47
Path Summary:
Slack | 2.249 |
Data Arrival Time | 8.544 |
Data Required Time | 10.793 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_5_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.460 | 4.460 | tNET | RR | 1 | R52C150[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/CLK |
4.754 | 0.294 | tC2Q | RF | 36 | R52C150[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/Q |
5.406 | 0.652 | tNET | FF | 1 | R51C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s16/I2 |
5.771 | 0.365 | tINS | FR | 26 | R51C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s16/F |
8.081 | 2.310 | tNET | RR | 1 | R48C150[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4629_s10/I3 |
8.544 | 0.463 | tINS | RR | 1 | R48C150[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4629_s10/F |
8.544 | 0.000 | tNET | RR | 1 | R48C150[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.844 | 4.444 | tNET | RR | 1 | R48C150[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_5_s0/CLK |
10.793 | -0.051 | tSu | 1 | R48C150[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_5_s0 |
Path Statistics:
Clock Skew | -0.016 |
Setup Relationship | 6.400 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.460, 100.000% |
Arrival Data Path Delay | cell: 0.828, 20.274%; route: 2.962, 72.527%; tC2Q: 0.294, 7.199% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.444, 100.000% |
Path48
Path Summary:
Slack | 2.249 |
Data Arrival Time | 8.544 |
Data Required Time | 10.793 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_7_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.460 | 4.460 | tNET | RR | 1 | R52C150[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/CLK |
4.754 | 0.294 | tC2Q | RF | 36 | R52C150[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/Q |
5.406 | 0.652 | tNET | FF | 1 | R51C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s16/I2 |
5.771 | 0.365 | tINS | FR | 26 | R51C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s16/F |
8.081 | 2.310 | tNET | RR | 1 | R48C150[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4627_s11/I3 |
8.544 | 0.463 | tINS | RR | 1 | R48C150[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4627_s11/F |
8.544 | 0.000 | tNET | RR | 1 | R48C150[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.844 | 4.444 | tNET | RR | 1 | R48C150[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_7_s0/CLK |
10.793 | -0.051 | tSu | 1 | R48C150[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_7_s0 |
Path Statistics:
Clock Skew | -0.016 |
Setup Relationship | 6.400 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.460, 100.000% |
Arrival Data Path Delay | cell: 0.828, 20.274%; route: 2.962, 72.527%; tC2Q: 0.294, 7.199% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.444, 100.000% |
Path49
Path Summary:
Slack | 2.249 |
Data Arrival Time | 8.544 |
Data Required Time | 10.793 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_9_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.460 | 4.460 | tNET | RR | 1 | R52C150[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/CLK |
4.754 | 0.294 | tC2Q | RF | 36 | R52C150[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/c_state_2_s0/Q |
5.406 | 0.652 | tNET | FF | 1 | R51C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s16/I2 |
5.771 | 0.365 | tINS | FR | 26 | R51C141[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4571_s16/F |
8.081 | 2.310 | tNET | RR | 1 | R48C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4625_s10/I2 |
8.544 | 0.463 | tINS | RR | 1 | R48C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/n4625_s10/F |
8.544 | 0.000 | tNET | RR | 1 | R48C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.844 | 4.444 | tNET | RR | 1 | R48C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_9_s0/CLK |
10.793 | -0.051 | tSu | 1 | R48C146[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_9_s0 |
Path Statistics:
Clock Skew | -0.016 |
Setup Relationship | 6.400 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.460, 100.000% |
Arrival Data Path Delay | cell: 0.828, 20.274%; route: 2.962, 72.527%; tC2Q: 0.294, 7.199% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.444, 100.000% |
Path50
Path Summary:
Slack | 2.250 |
Data Arrival Time | 8.634 |
Data Required Time | 10.884 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_7_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.510 | 4.510 | tNET | RR | 36 | BSRAM_R64[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKB |
6.458 | 1.948 | tC2Q | RR | 1 | BSRAM_R64[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/DO[7] |
7.080 | 0.622 | tNET | RR | 1 | R66C136[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d1_7_s4/I1 |
7.518 | 0.438 | tINS | RR | 3 | R66C136[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d1_7_s4/F |
8.634 | 1.116 | tNET | RR | 1 | R61C134[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.935 | 4.535 | tNET | RR | 1 | R61C134[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_7_s0/CLK |
10.884 | -0.051 | tSu | 1 | R61C134[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_7_s0 |
Path Statistics:
Clock Skew | 0.025 |
Setup Relationship | 6.400 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.510, 100.000% |
Arrival Data Path Delay | cell: 0.438, 10.620%; route: 1.738, 42.142%; tC2Q: 1.948, 47.237% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.027 |
Data Arrival Time | 2.498 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_28_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R45C142[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_28_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 1 | R45C142[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_28_s0/Q |
2.498 | 0.093 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[28] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path2
Path Summary:
Slack | 0.031 |
Data Arrival Time | 2.502 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_21_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.265 | 2.265 | tNET | RR | 1 | R45C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_21_s0/CLK |
2.409 | 0.144 | tC2Q | RR | 1 | R45C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_21_s0/Q |
2.502 | 0.093 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[21] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.265, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path3
Path Summary:
Slack | 0.031 |
Data Arrival Time | 2.502 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_15_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.265 | 2.265 | tNET | RR | 1 | R45C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_15_s0/CLK |
2.409 | 0.144 | tC2Q | RR | 1 | R45C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_15_s0/Q |
2.502 | 0.093 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[15] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.265, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path4
Path Summary:
Slack | 0.051 |
Data Arrival Time | 2.518 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_59_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R42C144[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_59_s0/CLK |
2.417 | 0.144 | tC2Q | RR | 1 | R42C144[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_59_s0/Q |
2.518 | 0.101 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[23] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path5
Path Summary:
Slack | 0.051 |
Data Arrival Time | 2.518 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_51_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R42C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_51_s0/CLK |
2.417 | 0.144 | tC2Q | RR | 1 | R42C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_51_s0/Q |
2.518 | 0.101 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[15] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path6
Path Summary:
Slack | 0.051 |
Data Arrival Time | 2.518 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_39_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R42C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_39_s0/CLK |
2.417 | 0.144 | tC2Q | RR | 1 | R42C144[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_39_s0/Q |
2.518 | 0.101 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path7
Path Summary:
Slack | 0.051 |
Data Arrival Time | 2.518 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_38_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R42C144[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_38_s0/CLK |
2.417 | 0.144 | tC2Q | RR | 1 | R42C144[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_38_s0/Q |
2.518 | 0.101 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path8
Path Summary:
Slack | 0.055 |
Data Arrival Time | 2.522 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_65_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.277 | 2.277 | tNET | RR | 1 | R42C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_65_s0/CLK |
2.421 | 0.144 | tC2Q | RR | 1 | R42C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_65_s0/Q |
2.522 | 0.101 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[29] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.025 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.277, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path9
Path Summary:
Slack | 0.117 |
Data Arrival Time | 2.584 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_49_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.266 | 2.266 | tNET | RR | 1 | R44C144[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_49_s0/CLK |
2.410 | 0.144 | tC2Q | RR | 1 | R44C144[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_49_s0/Q |
2.584 | 0.174 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.014 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.266, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path10
Path Summary:
Slack | 0.130 |
Data Arrival Time | 2.601 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_10_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.262 | 2.262 | tNET | RR | 1 | R44C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_10_s0/CLK |
2.406 | 0.144 | tC2Q | RR | 1 | R44C143[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_10_s0/Q |
2.601 | 0.195 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.262, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path11
Path Summary:
Slack | 0.135 |
Data Arrival Time | 2.602 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_54_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.267 | 2.267 | tNET | RR | 1 | R43C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_54_s0/CLK |
2.411 | 0.144 | tC2Q | RR | 1 | R43C143[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_54_s0/Q |
2.602 | 0.191 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[18] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.267, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path12
Path Summary:
Slack | 0.135 |
Data Arrival Time | 2.602 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_46_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.267 | 2.267 | tNET | RR | 1 | R43C143[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_46_s0/CLK |
2.411 | 0.144 | tC2Q | RR | 1 | R43C143[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_46_s0/Q |
2.602 | 0.191 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.267, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path13
Path Summary:
Slack | 0.137 |
Data Arrival Time | 2.604 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_58_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.271 | 2.271 | tNET | RR | 1 | R43C144[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_58_s0/CLK |
2.415 | 0.144 | tC2Q | RR | 1 | R43C144[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_58_s0/Q |
2.604 | 0.189 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[22] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.019 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path14
Path Summary:
Slack | 0.137 |
Data Arrival Time | 2.604 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_57_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.271 | 2.271 | tNET | RR | 1 | R43C144[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_57_s0/CLK |
2.415 | 0.144 | tC2Q | RR | 1 | R43C144[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_57_s0/Q |
2.604 | 0.189 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[21] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.019 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path15
Path Summary:
Slack | 0.137 |
Data Arrival Time | 2.608 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_25_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.275 | 2.275 | tNET | RR | 1 | R43C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_25_s0/CLK |
2.419 | 0.144 | tC2Q | RR | 1 | R43C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_25_s0/Q |
2.608 | 0.189 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[25] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.019 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.275, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path16
Path Summary:
Slack | 0.139 |
Data Arrival Time | 2.610 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_6_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.275 | 2.275 | tNET | RR | 1 | R43C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_6_s0/CLK |
2.419 | 0.144 | tC2Q | RR | 1 | R43C141[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_6_s0/Q |
2.610 | 0.191 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.019 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.275, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path17
Path Summary:
Slack | 0.141 |
Data Arrival Time | 2.608 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_55_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R42C142[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_55_s0/CLK |
2.417 | 0.144 | tC2Q | RR | 1 | R42C142[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_55_s0/Q |
2.608 | 0.191 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[19] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path18
Path Summary:
Slack | 0.141 |
Data Arrival Time | 2.612 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_26_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R42C142[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_26_s0/CLK |
2.417 | 0.144 | tC2Q | RR | 1 | R42C142[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_26_s0/Q |
2.612 | 0.195 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[26] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.017 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path19
Path Summary:
Slack | 0.141 |
Data Arrival Time | 2.608 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_62_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.275 | 2.275 | tNET | RR | 1 | R43C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_62_s0/CLK |
2.419 | 0.144 | tC2Q | RR | 1 | R43C145[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_62_s0/Q |
2.608 | 0.189 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[26] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.023 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.275, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path20
Path Summary:
Slack | 0.145 |
Data Arrival Time | 2.612 |
Data Required Time | 2.467 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_47_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R42C144[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_47_s0/CLK |
2.417 | 0.144 | tC2Q | RR | 1 | R42C144[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_47_s0/Q |
2.612 | 0.195 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.252 | 2.252 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
2.467 | 0.215 | tHld | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.252, 100.000% |
Path21
Path Summary:
Slack | 0.147 |
Data Arrival Time | 2.618 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_23_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.277 | 2.277 | tNET | RR | 1 | R42C145[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_23_s0/CLK |
2.421 | 0.144 | tC2Q | RR | 1 | R42C145[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_23_s0/Q |
2.618 | 0.197 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[23] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.021 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.277, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.197, 57.771%; tC2Q: 0.144, 42.229% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path22
Path Summary:
Slack | 0.148 |
Data Arrival Time | 2.619 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_30_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R45C142[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_30_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 1 | R45C142[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_30_s0/Q |
2.619 | 0.214 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[30] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.214, 59.777%; tC2Q: 0.144, 40.223% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path23
Path Summary:
Slack | 0.148 |
Data Arrival Time | 2.619 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_29_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R45C142[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_29_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 1 | R45C142[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_29_s0/Q |
2.619 | 0.214 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[29] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.214, 59.777%; tC2Q: 0.144, 40.223% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path24
Path Summary:
Slack | 0.152 |
Data Arrival Time | 2.623 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_22_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.265 | 2.265 | tNET | RR | 1 | R45C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_22_s0/CLK |
2.409 | 0.144 | tC2Q | RR | 1 | R45C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_22_s0/Q |
2.623 | 0.214 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[22] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.265, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.214, 59.777%; tC2Q: 0.144, 40.223% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Path25
Path Summary:
Slack | 0.163 |
Data Arrival Time | 2.634 |
Data Required Time | 2.471 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_13_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R45C142[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_13_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 1 | R45C142[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_13_s0/Q |
2.634 | 0.229 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.256 | 2.256 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
2.471 | 0.215 | tHld | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.229, 61.394%; tC2Q: 0.144, 38.606% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.256, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.113 |
Data Arrival Time | 7.245 |
Data Required Time | 7.358 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
7.245 | 5.363 | tNET | FF | 36 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.736 | 1.563 | tNET | RR | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKB |
7.358 | -0.378 | tSu | 1 | BSRAM_R46[30] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Path Statistics:
Clock Skew | -0.025 |
Setup Relationship | 6.173 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.363, 94.803%; tC2Q: 0.294, 5.197% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.563, 100.000% |
Path2
Path Summary:
Slack | 0.382 |
Data Arrival Time | 10.257 |
Data Required Time | 10.639 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C2_I_E_sel_d4_5_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
10.257 | 5.428 | tNET | FF | 1 | R54C140[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C2_I_E_sel_d4_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.917 | 4.517 | tNET | RR | 1 | R54C140[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C2_I_E_sel_d4_5_s0/CLK |
10.639 | -0.278 | tSu | 1 | R54C140[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C2_I_E_sel_d4_5_s0 |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.428, 94.862%; tC2Q: 0.294, 5.138% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.517, 100.000% |
Path3
Path Summary:
Slack | 0.382 |
Data Arrival Time | 10.257 |
Data Required Time | 10.639 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_2_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
10.257 | 5.428 | tNET | FF | 1 | R54C140[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.917 | 4.517 | tNET | RR | 1 | R54C140[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_2_s0/CLK |
10.639 | -0.278 | tSu | 1 | R54C140[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_2_s0 |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.428, 94.862%; tC2Q: 0.294, 5.138% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.517, 100.000% |
Path4
Path Summary:
Slack | 0.382 |
Data Arrival Time | 10.257 |
Data Required Time | 10.639 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_5_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
10.257 | 5.428 | tNET | FF | 1 | R54C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.917 | 4.517 | tNET | RR | 1 | R54C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_5_s0/CLK |
10.639 | -0.278 | tSu | 1 | R54C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_5_s0 |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.428, 94.862%; tC2Q: 0.294, 5.138% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.517, 100.000% |
Path5
Path Summary:
Slack | 0.382 |
Data Arrival Time | 10.257 |
Data Required Time | 10.639 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_7_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
10.257 | 5.428 | tNET | FF | 1 | R54C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.917 | 4.517 | tNET | RR | 1 | R54C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_7_s0/CLK |
10.639 | -0.278 | tSu | 1 | R54C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_7_s0 |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.428, 94.862%; tC2Q: 0.294, 5.138% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.517, 100.000% |
Path6
Path Summary:
Slack | 0.547 |
Data Arrival Time | 10.089 |
Data Required Time | 10.636 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C6_I_E_sel_d4_5_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
10.089 | 5.260 | tNET | FF | 1 | R52C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C6_I_E_sel_d4_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.914 | 4.514 | tNET | RR | 1 | R52C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C6_I_E_sel_d4_5_s0/CLK |
10.636 | -0.278 | tSu | 1 | R52C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/C6_I_E_sel_d4_5_s0 |
Path Statistics:
Clock Skew | -0.021 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.260, 94.706%; tC2Q: 0.294, 5.294% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.514, 100.000% |
Path7
Path Summary:
Slack | 0.547 |
Data Arrival Time | 10.089 |
Data Required Time | 10.636 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_7_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
10.089 | 5.260 | tNET | FF | 1 | R52C140[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.914 | 4.514 | tNET | RR | 1 | R52C140[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_7_s0/CLK |
10.636 | -0.278 | tSu | 1 | R52C140[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/error_char_d3_7_s0 |
Path Statistics:
Clock Skew | -0.021 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.260, 94.706%; tC2Q: 0.294, 5.294% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.514, 100.000% |
Path8
Path Summary:
Slack | 0.547 |
Data Arrival Time | 10.089 |
Data Required Time | 10.636 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/terminate_char_d2_4_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
10.089 | 5.260 | tNET | FF | 1 | R52C140[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/terminate_char_d2_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.914 | 4.514 | tNET | RR | 1 | R52C140[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/terminate_char_d2_4_s0/CLK |
10.636 | -0.278 | tSu | 1 | R52C140[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/terminate_char_d2_4_s0 |
Path Statistics:
Clock Skew | -0.021 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.260, 94.706%; tC2Q: 0.294, 5.294% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.514, 100.000% |
Path9
Path Summary:
Slack | 0.624 |
Data Arrival Time | 6.742 |
Data Required Time | 7.366 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
6.742 | 4.860 | tNET | FF | 36 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.743 | 1.570 | tNET | RR | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKB |
7.366 | -0.378 | tSu | 1 | BSRAM_R46[29][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
Clock Skew | -0.018 |
Setup Relationship | 6.173 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.860, 94.296%; tC2Q: 0.294, 5.704% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.570, 100.000% |
Path10
Path Summary:
Slack | 0.716 |
Data Arrival Time | 9.909 |
Data Required Time | 10.625 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_43_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.909 | 5.080 | tNET | FF | 1 | R49C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_43_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.903 | 4.503 | tNET | RR | 1 | R49C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_43_s0/CLK |
10.625 | -0.278 | tSu | 1 | R49C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_43_s0 |
Path Statistics:
Clock Skew | -0.032 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.080, 94.529%; tC2Q: 0.294, 5.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.503, 100.000% |
Path11
Path Summary:
Slack | 0.716 |
Data Arrival Time | 9.909 |
Data Required Time | 10.625 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.909 | 5.080 | tNET | FF | 1 | R49C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.903 | 4.503 | tNET | RR | 1 | R49C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0/CLK |
10.625 | -0.278 | tSu | 1 | R49C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/block_payload_tmp_43_s0 |
Path Statistics:
Clock Skew | -0.032 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.080, 94.529%; tC2Q: 0.294, 5.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.503, 100.000% |
Path12
Path Summary:
Slack | 0.716 |
Data Arrival Time | 9.909 |
Data Required Time | 10.625 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/start_char_d2_0_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.909 | 5.080 | tNET | FF | 1 | R49C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/start_char_d2_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.903 | 4.503 | tNET | RR | 1 | R49C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/start_char_d2_0_s0/CLK |
10.625 | -0.278 | tSu | 1 | R49C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/start_char_d2_0_s0 |
Path Statistics:
Clock Skew | -0.032 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.080, 94.529%; tC2Q: 0.294, 5.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.503, 100.000% |
Path13
Path Summary:
Slack | 0.716 |
Data Arrival Time | 9.909 |
Data Required Time | 10.625 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.909 | 5.080 | tNET | FF | 1 | R49C140[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.903 | 4.503 | tNET | RR | 1 | R49C140[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0/CLK |
10.625 | -0.278 | tSu | 1 | R49C140[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d1_10_s0 |
Path Statistics:
Clock Skew | -0.032 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.080, 94.529%; tC2Q: 0.294, 5.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.503, 100.000% |
Path14
Path Summary:
Slack | 0.721 |
Data Arrival Time | 9.909 |
Data Required Time | 10.630 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_0_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.909 | 5.080 | tNET | FF | 1 | R50C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.908 | 4.508 | tNET | RR | 1 | R50C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_0_s0/CLK |
10.630 | -0.278 | tSu | 1 | R50C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/data_char_d2_0_s0 |
Path Statistics:
Clock Skew | -0.027 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.080, 94.529%; tC2Q: 0.294, 5.471% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.508, 100.000% |
Path15
Path Summary:
Slack | 0.722 |
Data Arrival Time | 9.914 |
Data Required Time | 10.636 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved5_char_d2_4_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.914 | 5.085 | tNET | FF | 1 | R52C138[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved5_char_d2_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.914 | 4.514 | tNET | RR | 1 | R52C138[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved5_char_d2_4_s0/CLK |
10.636 | -0.278 | tSu | 1 | R52C138[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved5_char_d2_4_s0 |
Path Statistics:
Clock Skew | -0.021 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.085, 94.534%; tC2Q: 0.294, 5.466% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.514, 100.000% |
Path16
Path Summary:
Slack | 0.722 |
Data Arrival Time | 9.914 |
Data Required Time | 10.636 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved4_char_d2_4_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.914 | 5.085 | tNET | FF | 1 | R52C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved4_char_d2_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.914 | 4.514 | tNET | RR | 1 | R52C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved4_char_d2_4_s0/CLK |
10.636 | -0.278 | tSu | 1 | R52C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved4_char_d2_4_s0 |
Path Statistics:
Clock Skew | -0.021 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 5.085, 94.534%; tC2Q: 0.294, 5.466% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.514, 100.000% |
Path17
Path Summary:
Slack | 0.748 |
Data Arrival Time | 6.742 |
Data Required Time | 7.490 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_4_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
6.742 | 4.860 | tNET | FF | 1 | R43C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.768 | 1.595 | tNET | RR | 1 | R43C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_4_s0/CLK |
7.490 | -0.278 | tSu | 1 | R43C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_4_s0 |
Path Statistics:
Clock Skew | 0.007 |
Setup Relationship | 6.173 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.860, 94.296%; tC2Q: 0.294, 5.704% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.595, 100.000% |
Path18
Path Summary:
Slack | 0.748 |
Data Arrival Time | 6.742 |
Data Required Time | 7.490 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_4_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
6.742 | 4.860 | tNET | FF | 1 | R43C142[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.768 | 1.595 | tNET | RR | 1 | R43C142[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_4_s0/CLK |
7.490 | -0.278 | tSu | 1 | R43C142[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_4_s0 |
Path Statistics:
Clock Skew | 0.007 |
Setup Relationship | 6.173 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.860, 94.296%; tC2Q: 0.294, 5.704% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.595, 100.000% |
Path19
Path Summary:
Slack | 0.749 |
Data Arrival Time | 6.728 |
Data Required Time | 7.477 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_3_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
6.728 | 4.846 | tNET | FF | 1 | R42C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.755 | 1.582 | tNET | RR | 1 | R42C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_3_s0/CLK |
7.477 | -0.278 | tSu | 1 | R42C140[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe1_3_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 6.173 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.846, 94.280%; tC2Q: 0.294, 5.720% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.582, 100.000% |
Path20
Path Summary:
Slack | 0.749 |
Data Arrival Time | 6.728 |
Data Required Time | 7.477 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_3_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
6.728 | 4.846 | tNET | FF | 1 | R42C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.755 | 1.582 | tNET | RR | 1 | R42C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_3_s0/CLK |
7.477 | -0.278 | tSu | 1 | R42C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/PROC_WR_GRAY_ADD1.u_wr2rdaddr_gray/pipe0_3_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 6.173 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.846, 94.280%; tC2Q: 0.294, 5.720% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.582, 100.000% |
Path21
Path Summary:
Slack | 0.749 |
Data Arrival Time | 6.728 |
Data Required Time | 7.477 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_2_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
6.728 | 4.846 | tNET | FF | 1 | R42C140[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.755 | 1.582 | tNET | RR | 1 | R42C140[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_2_s0/CLK |
7.477 | -0.278 | tSu | 1 | R42C140[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_2_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 6.173 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.846, 94.280%; tC2Q: 0.294, 5.720% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.582, 100.000% |
Path22
Path Summary:
Slack | 0.749 |
Data Arrival Time | 6.728 |
Data Required Time | 7.477 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_3_s0 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
1.588 | 1.588 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
1.882 | 0.294 | tC2Q | RF | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
6.728 | 4.846 | tNET | FF | 1 | R42C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.173 | 6.173 | active clock edge time | ||||
6.173 | 0.000 | serdes_tx_clk | ||||
6.173 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
7.755 | 1.582 | tNET | RR | 1 | R42C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_3_s0/CLK |
7.477 | -0.278 | tSu | 1 | R42C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr2ram_3_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 6.173 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.588, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.846, 94.280%; tC2Q: 0.294, 5.720% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.582, 100.000% |
Path23
Path Summary:
Slack | 0.879 |
Data Arrival Time | 9.734 |
Data Required Time | 10.613 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved3_char_d2_2_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.734 | 4.905 | tNET | FF | 1 | R48C139[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved3_char_d2_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.891 | 4.491 | tNET | RR | 1 | R48C139[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved3_char_d2_2_s0/CLK |
10.613 | -0.278 | tSu | 1 | R48C139[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved3_char_d2_2_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.905, 94.345%; tC2Q: 0.294, 5.655% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.491, 100.000% |
Path24
Path Summary:
Slack | 0.879 |
Data Arrival Time | 9.734 |
Data Required Time | 10.613 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved2_char_d2_2_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.734 | 4.905 | tNET | FF | 1 | R48C139[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved2_char_d2_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.891 | 4.491 | tNET | RR | 1 | R48C139[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved2_char_d2_2_s0/CLK |
10.613 | -0.278 | tSu | 1 | R48C139[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved2_char_d2_2_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.905, 94.345%; tC2Q: 0.294, 5.655% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.491, 100.000% |
Path25
Path Summary:
Slack | 0.879 |
Data Arrival Time | 9.734 |
Data Required Time | 10.613 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_2_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
4.535 | 4.535 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
4.829 | 0.294 | tC2Q | RF | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
9.734 | 4.905 | tNET | FF | 1 | R48C139[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
6.400 | 6.400 | active clock edge time | ||||
6.400 | 0.000 | xgmii_clk | ||||
6.400 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
10.891 | 4.491 | tNET | RR | 1 | R48C139[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_2_s0/CLK |
10.613 | -0.278 | tSu | 1 | R48C139[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/reserved1_char_d2_2_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 6.400 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.535, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 4.905, 94.345%; tC2Q: 0.294, 5.655% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.491, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.483 |
Data Arrival Time | 1.345 |
Data Required Time | 0.862 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d4_7_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
1.009 | 1.009 | tNET | RR | 1 | R66C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/CLK |
1.153 | 0.144 | tC2Q | RR | 458 | R66C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q |
1.345 | 0.192 | tNET | RR | 1 | R68C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d4_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
1.013 | 1.013 | tNET | RR | 1 | R68C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d4_7_s0/CLK |
0.862 | -0.151 | tHld | 1 | R68C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d4_7_s0 |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.009, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.192, 57.143%; tC2Q: 0.144, 42.857% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.013, 100.000% |
Path2
Path Summary:
Slack | 0.483 |
Data Arrival Time | 1.345 |
Data Required Time | 0.862 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d3_7_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
1.009 | 1.009 | tNET | RR | 1 | R66C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/CLK |
1.153 | 0.144 | tC2Q | RR | 458 | R66C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q |
1.345 | 0.192 | tNET | RR | 1 | R68C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d3_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
1.013 | 1.013 | tNET | RR | 1 | R68C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d3_7_s0/CLK |
0.862 | -0.151 | tHld | 1 | R68C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d3_7_s0 |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.009, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.192, 57.143%; tC2Q: 0.144, 42.857% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.013, 100.000% |
Path3
Path Summary:
Slack | 0.483 |
Data Arrival Time | 1.345 |
Data Required Time | 0.862 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d2_7_s0 |
Launch Clk | serdes_rx_clk:[R] |
Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
1.009 | 1.009 | tNET | RR | 1 | R66C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/CLK |
1.153 | 0.144 | tC2Q | RR | 458 | R66C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q |
1.345 | 0.192 | tNET | RR | 1 | R68C130[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d2_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_rx_clk | ||||
0.000 | 0.000 | tCL | RR | 2035 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
1.013 | 1.013 | tNET | RR | 1 | R68C130[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d2_7_s0/CLK |
0.862 | -0.151 | tHld | 1 | R68C130[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_wr_d2_7_s0 |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.009, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.192, 57.143%; tC2Q: 0.144, 42.857% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.013, 100.000% |
Path4
Path Summary:
Slack | 0.491 |
Data Arrival Time | 1.060 |
Data Required Time | 0.569 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198 |
Launch Clk | serdes_tx_clk:[R] |
Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
0.714 | 0.714 | tNET | RR | 1 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
0.858 | 0.144 | tC2Q | RR | 356 | R39C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
1.060 | 0.202 | tNET | RR | 1 | R40C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | serdes_tx_clk | ||||
0.000 | 0.000 | tCL | RR | 643 | - | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
0.720 | 0.720 | tNET | RR | 1 | R40C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198/CLK |
0.569 | -0.151 | tHld | 1 | R40C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198 |
Path Statistics:
Clock Skew | 0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.714, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.720, 100.000% |
Path5
Path Summary:
Slack | 0.491 |
Data Arrival Time | 2.616 |
Data Required Time | 2.125 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_49_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.274 | 2.274 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
2.418 | 0.144 | tC2Q | RR | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
2.616 | 0.198 | tNET | RR | 1 | R40C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_49_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.276 | 2.276 | tNET | RR | 1 | R40C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_49_s0/CLK |
2.125 | -0.151 | tHld | 1 | R40C136[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_49_s0 |
Path Statistics:
Clock Skew | 0.002 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.198, 57.895%; tC2Q: 0.144, 42.105% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.276, 100.000% |
Path6
Path Summary:
Slack | 0.492 |
Data Arrival Time | 2.607 |
Data Required Time | 2.115 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_9_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.607 | 0.202 | tNET | RR | 1 | R62C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.266 | 2.266 | tNET | RR | 1 | R62C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_9_s0/CLK |
2.115 | -0.151 | tHld | 1 | R62C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_9_s0 |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.266, 100.000% |
Path7
Path Summary:
Slack | 0.492 |
Data Arrival Time | 2.607 |
Data Required Time | 2.115 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_10_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.607 | 0.202 | tNET | RR | 1 | R62C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_10_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.266 | 2.266 | tNET | RR | 1 | R62C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_10_s0/CLK |
2.115 | -0.151 | tHld | 1 | R62C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_10_s0 |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.266, 100.000% |
Path8
Path Summary:
Slack | 0.492 |
Data Arrival Time | 2.607 |
Data Required Time | 2.115 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_62_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.607 | 0.202 | tNET | RR | 1 | R62C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_62_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.266 | 2.266 | tNET | RR | 1 | R62C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_62_s0/CLK |
2.115 | -0.151 | tHld | 1 | R62C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_62_s0 |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.266, 100.000% |
Path9
Path Summary:
Slack | 0.493 |
Data Arrival Time | 2.612 |
Data Required Time | 2.119 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_46_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.274 | 2.274 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
2.418 | 0.144 | tC2Q | RR | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
2.612 | 0.194 | tNET | RR | 1 | R41C135[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_46_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.270 | 2.270 | tNET | RR | 1 | R41C135[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_46_s0/CLK |
2.119 | -0.151 | tHld | 1 | R41C135[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_46_s0 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.194, 57.396%; tC2Q: 0.144, 42.604% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.270, 100.000% |
Path10
Path Summary:
Slack | 0.493 |
Data Arrival Time | 2.612 |
Data Required Time | 2.119 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_58_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.274 | 2.274 | tNET | RR | 1 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
2.418 | 0.144 | tC2Q | RR | 1118 | R39C135[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
2.612 | 0.194 | tNET | RR | 1 | R41C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_58_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.270 | 2.270 | tNET | RR | 1 | R41C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_58_s0/CLK |
2.119 | -0.151 | tHld | 1 | R41C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_58_s0 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.274, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.194, 57.396%; tC2Q: 0.144, 42.604% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.270, 100.000% |
Path11
Path Summary:
Slack | 0.493 |
Data Arrival Time | 2.615 |
Data Required Time | 2.122 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R60C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_3_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R60C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_3_s0/CLK |
2.122 | -0.151 | tHld | 1 | R60C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_3_s0 |
Path Statistics:
Clock Skew | 0.012 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Path12
Path Summary:
Slack | 0.493 |
Data Arrival Time | 2.615 |
Data Required Time | 2.122 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_33_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R60C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_33_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R60C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_33_s0/CLK |
2.122 | -0.151 | tHld | 1 | R60C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_33_s0 |
Path Statistics:
Clock Skew | 0.012 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Path13
Path Summary:
Slack | 0.493 |
Data Arrival Time | 2.615 |
Data Required Time | 2.122 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_35_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R60C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_35_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R60C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_35_s0/CLK |
2.122 | -0.151 | tHld | 1 | R60C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_35_s0 |
Path Statistics:
Clock Skew | 0.012 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Path14
Path Summary:
Slack | 0.493 |
Data Arrival Time | 2.615 |
Data Required Time | 2.122 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_3_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R60C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_3_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R60C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_3_s0/CLK |
2.122 | -0.151 | tHld | 1 | R60C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_3_s0 |
Path Statistics:
Clock Skew | 0.012 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Path15
Path Summary:
Slack | 0.493 |
Data Arrival Time | 2.615 |
Data Required Time | 2.122 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_35_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R60C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_35_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.273 | 2.273 | tNET | RR | 1 | R60C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_35_s0/CLK |
2.122 | -0.151 | tHld | 1 | R60C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_35_s0 |
Path Statistics:
Clock Skew | 0.012 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.273, 100.000% |
Path16
Path Summary:
Slack | 0.495 |
Data Arrival Time | 2.615 |
Data Required Time | 2.120 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d5_35_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R61C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d5_35_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.271 | 2.271 | tNET | RR | 1 | R61C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d5_35_s0/CLK |
2.120 | -0.151 | tHld | 1 | R61C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d5_35_s0 |
Path Statistics:
Clock Skew | 0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path17
Path Summary:
Slack | 0.495 |
Data Arrival Time | 2.615 |
Data Required Time | 2.120 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_35_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R61C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_35_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.271 | 2.271 | tNET | RR | 1 | R61C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_35_s0/CLK |
2.120 | -0.151 | tHld | 1 | R61C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_35_s0 |
Path Statistics:
Clock Skew | 0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path18
Path Summary:
Slack | 0.495 |
Data Arrival Time | 2.615 |
Data Required Time | 2.120 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_35_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R61C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_35_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.271 | 2.271 | tNET | RR | 1 | R61C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_35_s0/CLK |
2.120 | -0.151 | tHld | 1 | R61C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_35_s0 |
Path Statistics:
Clock Skew | 0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path19
Path Summary:
Slack | 0.495 |
Data Arrival Time | 2.615 |
Data Required Time | 2.120 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_35_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R61C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_35_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.271 | 2.271 | tNET | RR | 1 | R61C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_35_s0/CLK |
2.120 | -0.151 | tHld | 1 | R61C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_35_s0 |
Path Statistics:
Clock Skew | 0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path20
Path Summary:
Slack | 0.495 |
Data Arrival Time | 2.615 |
Data Required Time | 2.120 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_rd_d2_7_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.615 | 0.210 | tNET | RR | 1 | R61C130[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_rd_d2_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.271 | 2.271 | tNET | RR | 1 | R61C130[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_rd_d2_7_s0/CLK |
2.120 | -0.151 | tHld | 1 | R61C130[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxc_rd_d2_7_s0 |
Path Statistics:
Clock Skew | 0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.210, 59.322%; tC2Q: 0.144, 40.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path21
Path Summary:
Slack | 0.499 |
Data Arrival Time | 2.613 |
Data Required Time | 2.114 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_30_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.613 | 0.208 | tNET | RR | 1 | R63C133[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_30_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.265 | 2.265 | tNET | RR | 1 | R63C133[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_30_s0/CLK |
2.114 | -0.151 | tHld | 1 | R63C133[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_30_s0 |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.265, 100.000% |
Path22
Path Summary:
Slack | 0.499 |
Data Arrival Time | 2.613 |
Data Required Time | 2.114 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_30_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.613 | 0.208 | tNET | RR | 1 | R63C133[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_30_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.265 | 2.265 | tNET | RR | 1 | R63C133[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_30_s0/CLK |
2.114 | -0.151 | tHld | 1 | R63C133[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_30_s0 |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.265, 100.000% |
Path23
Path Summary:
Slack | 0.499 |
Data Arrival Time | 2.613 |
Data Required Time | 2.114 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_30_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.613 | 0.208 | tNET | RR | 1 | R63C133[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_30_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.265 | 2.265 | tNET | RR | 1 | R63C133[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_30_s0/CLK |
2.114 | -0.151 | tHld | 1 | R63C133[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_30_s0 |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.265, 100.000% |
Path24
Path Summary:
Slack | 0.499 |
Data Arrival Time | 2.613 |
Data Required Time | 2.114 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_30_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.613 | 0.208 | tNET | RR | 1 | R63C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_30_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.265 | 2.265 | tNET | RR | 1 | R63C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_30_s0/CLK |
2.114 | -0.151 | tHld | 1 | R63C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_30_s0 |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.265, 100.000% |
Path25
Path Summary:
Slack | 0.499 |
Data Arrival Time | 2.613 |
Data Required Time | 2.114 |
From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_27_s0 |
Launch Clk | xgmii_clk:[R] |
Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.261 | 2.261 | tNET | RR | 1 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
2.405 | 0.144 | tC2Q | RR | 450 | R63C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
2.613 | 0.208 | tNET | RR | 1 | R63C133[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_27_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | xgmii_clk | ||||
0.000 | 0.000 | tCL | RR | 1965 | - | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
2.265 | 2.265 | tNET | RR | 1 | R63C133[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_27_s0/CLK |
2.114 | -0.151 | tHld | 1 | R63C133[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_27_s0 |
Path Statistics:
Clock Skew | 0.004 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.261, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.265, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 0.347 |
Actual Width: | 1.209 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.451 | 4.251 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.660 | 2.260 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW2
MPW Summary:
Slack: | 0.347 |
Actual Width: | 1.209 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.451 | 4.251 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.660 | 2.260 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
MPW3
MPW Summary:
Slack: | 0.347 |
Actual Width: | 1.209 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.451 | 4.251 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.660 | 2.260 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA |
MPW4
MPW Summary:
Slack: | 0.351 |
Actual Width: | 1.213 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.443 | 4.243 | tNET | FF | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.656 | 2.256 | tNET | RR | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
MPW5
MPW Summary:
Slack: | 0.351 |
Actual Width: | 1.213 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.443 | 4.243 | tNET | FF | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.656 | 2.256 | tNET | RR | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKB |
MPW6
MPW Summary:
Slack: | 0.351 |
Actual Width: | 1.213 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.443 | 4.243 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.656 | 2.256 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
MPW7
MPW Summary:
Slack: | 0.351 |
Actual Width: | 1.213 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.443 | 4.243 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.656 | 2.256 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
MPW8
MPW Summary:
Slack: | 0.351 |
Actual Width: | 1.213 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.443 | 4.243 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.656 | 2.256 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA |
MPW9
MPW Summary:
Slack: | 0.351 |
Actual Width: | 1.213 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.443 | 4.243 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.656 | 2.256 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
MPW10
MPW Summary:
Slack: | 0.354 |
Actual Width: | 1.216 |
Required Width: | 0.862 |
Type: | Low Pulse Width |
Clock: | xgmii_clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
3.200 | 0.000 | active clock edge time | ||
3.200 | 0.000 | xgmii_clk | ||
3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
7.436 | 4.236 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
6.400 | 0.000 | active clock edge time | ||
6.400 | 0.000 | xgmii_clk | ||
6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_CMU_CK_REF_O |
8.652 | 2.252 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
2035 | q1_lane1_fabric_rx_clk | 0.304 | 2.344 |
1965 | ref_clk | 0.382 | 4.552 |
643 | q1_lane1_fabric_tx_clk | 0.048 | 1.605 |
584 | descrambler_valid_out | 2.024 | 3.533 |
473 | control0[0] | 19.824 | 4.560 |
356 | baser_tx_rstn_d2 | 0.048 | 4.503 |
349 | vld_rd_d1 | 3.088 | 2.568 |
267 | cnt[2] | 2.557 | 2.832 |
256 | rd_en_cnt_d2[2] | 2.197 | 3.229 |
251 | vld_wr_d1 | 2.598 | 2.139 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R42C141 | 66.67% |
R43C125 | 66.67% |
R67C124 | 65.28% |
R39C128 | 63.89% |
R43C134 | 63.89% |
R51C149 | 62.50% |
R67C147 | 62.50% |
R44C130 | 62.50% |
R65C136 | 62.50% |
R65C137 | 62.50% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_nets {tck_pad_i}] |
TC_CLOCK | Actived | create_clock -name xgmii_clk -period 6.4 -waveform {0 3.2} [get_nets {ref_clk}] |
TC_CLOCK | Actived | create_clock -name serdes_rx_clk -period 6.173 -waveform {0 3.087} [get_nets {u_SerDes_Top/q1_lane1_fabric_rx_clk}] |
TC_CLOCK | Actived | create_clock -name serdes_tx_clk -period 6.173 -waveform {0 3.087} [get_nets {u_SerDes_Top/q1_lane1_fabric_tx_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {serdes_rx_clk}] -group [get_clocks {serdes_tx_clk}] -group [get_clocks {xgmii_clk}] -group [get_clocks {tck_pad_i}] |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {serdes_rx_clk}] -to_clock [get_clocks {serdes_rx_clk}] -max_paths 50 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {serdes_tx_clk}] -to_clock [get_clocks {serdes_tx_clk}] -max_paths 50 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {xgmii_clk}] -to_clock [get_clocks {xgmii_clk}] -max_paths 50 -max_common_paths 1 |