Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\SERDES_IP\IPlib\10GSERETH\data\xg_baser_wrapper.v D:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\SERDES_IP\IPlib\10GSERETH\data\xg_baser.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9 (64-bit) |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Mon Dec 4 10:26:43 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Ten_Giga_Serial_Ethernet_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 86.492MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 86.492MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 86.492MB Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.156s, Peak memory usage = 86.492MB Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 86.492MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 86.492MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 86.492MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 86.492MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 86.492MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 86.492MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 86.492MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 86.492MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.354s, Peak memory usage = 93.250MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 93.250MB Generate output files: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.486s, Peak memory usage = 109.980MB |
Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 109.980MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 380 |
I/O Buf | 347 |
    IBUF | 152 |
    OBUF | 195 |
Register | 4475 |
    DFFSE | 64 |
    DFFRE | 232 |
    DFFPE | 618 |
    DFFCE | 3561 |
LUT | 3483 |
    LUT2 | 405 |
    LUT3 | 1515 |
    LUT4 | 1563 |
ALU | 34 |
    ALU | 34 |
INV | 164 |
    INV | 164 |
BSRAM | 4 |
    SDPX9B | 4 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 3681(3647 LUT, 34 ALU) / 138240 | 3% |
Register | 4475 / 139140 | 4% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 4475 / 139140 | 4% |
BSRAM | 4 / 340 | 2% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
xgmii_tx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | xgmii_tx_clk_i_ibuf/I | ||
serdes_pcs_tx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | serdes_pcs_tx_clk_i_ibuf/I | ||
serdes_pcs_rx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | serdes_pcs_rx_clk_i_ibuf/I | ||
xgmii_rx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | xgmii_rx_clk_i_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | xgmii_tx_clk_i | 100.0(MHz) | 195.4(MHz) | 7 | TOP |
2 | serdes_pcs_tx_clk_i | 100.0(MHz) | 197.3(MHz) | 7 | TOP |
3 | serdes_pcs_rx_clk_i | 100.0(MHz) | 220.1(MHz) | 6 | TOP |
4 | xgmii_rx_clk_i | 100.0(MHz) | 293.6(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.882 |
Data Arrival Time | 5.695 |
Data Required Time | 10.578 |
From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
Launch Clk | xgmii_tx_clk_i[R] |
Latch Clk | xgmii_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | xgmii_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
2.056 | 0.579 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
2.263 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
2.830 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
3.036 | 0.206 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
3.636 | 0.600 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
3.636 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
3.686 | 0.050 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
3.686 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
3.930 | 0.244 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
4.136 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
4.704 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
4.910 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
5.489 | 0.579 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
5.695 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | xgmii_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CLK |
10.578 | -0.311 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.186, 66.294%; route: 1.237, 25.748%; tC2Q: 0.382, 7.958% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 2
Path Summary:Slack | 4.882 |
Data Arrival Time | 5.695 |
Data Required Time | 10.578 |
From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
Launch Clk | xgmii_tx_clk_i[R] |
Latch Clk | xgmii_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | xgmii_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
2.056 | 0.579 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
2.263 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
2.830 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
3.036 | 0.206 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
3.636 | 0.600 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
3.636 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
3.686 | 0.050 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
3.686 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
3.930 | 0.244 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
4.136 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
4.704 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
4.910 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
5.489 | 0.579 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
5.695 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | xgmii_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CLK |
10.578 | -0.311 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.186, 66.294%; route: 1.237, 25.748%; tC2Q: 0.382, 7.958% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 3
Path Summary:Slack | 4.882 |
Data Arrival Time | 5.695 |
Data Required Time | 10.578 |
From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
Launch Clk | xgmii_tx_clk_i[R] |
Latch Clk | xgmii_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | xgmii_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
2.056 | 0.579 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
2.263 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
2.830 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
3.036 | 0.206 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
3.636 | 0.600 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
3.636 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
3.686 | 0.050 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
3.686 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
3.930 | 0.244 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
4.136 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
4.704 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
4.910 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
5.489 | 0.579 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
5.695 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | xgmii_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CLK |
10.578 | -0.311 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.186, 66.294%; route: 1.237, 25.748%; tC2Q: 0.382, 7.958% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 4
Path Summary:Slack | 4.882 |
Data Arrival Time | 5.695 |
Data Required Time | 10.578 |
From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
Launch Clk | xgmii_tx_clk_i[R] |
Latch Clk | xgmii_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | xgmii_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
2.056 | 0.579 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
2.263 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
2.830 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
3.036 | 0.206 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
3.636 | 0.600 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
3.636 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
3.686 | 0.050 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
3.686 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
3.930 | 0.244 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
4.136 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
4.704 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
4.910 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
5.489 | 0.579 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
5.695 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | xgmii_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CLK |
10.578 | -0.311 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.186, 66.294%; route: 1.237, 25.748%; tC2Q: 0.382, 7.958% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Path 5
Path Summary:Slack | 4.882 |
Data Arrival Time | 5.695 |
Data Required Time | 10.578 |
From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0 |
Launch Clk | xgmii_tx_clk_i[R] |
Latch Clk | xgmii_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | xgmii_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
0.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
1.271 | 0.382 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
1.477 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
2.056 | 0.579 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
2.263 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
2.830 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
3.036 | 0.206 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
3.636 | 0.600 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
3.636 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
3.686 | 0.050 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
3.686 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
3.930 | 0.244 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
4.136 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
4.704 | 0.567 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
4.910 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
5.489 | 0.579 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
5.695 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | xgmii_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
10.889 | 0.206 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CLK |
10.578 | -0.311 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |
Arrival Data Path Delay: | cell: 3.186, 66.294%; route: 1.237, 25.748%; tC2Q: 0.382, 7.958% |
Required Clock Path Delay: | cell: 0.683, 76.793%; route: 0.206, 23.207% |