Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\button.v
E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\giga_serial_ethernet_lvds\giga_serial_ethernet_lvds.v
E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\mac_rx_model.v
E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\mac_tx_model.v
E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\pll_hclk\pll_hclk.v
E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\pll_uart\pll_uart.v
E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\sysreg.v
E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\top.v
E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\uart_to_bus\uart_to_bus.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.02
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Wed Mar 20 15:16:20 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 271.336MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.298s, Peak memory usage = 271.336MB
    Optimizing Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.274s, Peak memory usage = 271.336MB
    Optimizing Phase 2: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.542s, Peak memory usage = 271.336MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.174s, Peak memory usage = 271.336MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 271.336MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 271.336MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 271.336MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 0.887s, Peak memory usage = 271.336MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 271.336MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 271.336MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 336.414MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.411s, Peak memory usage = 336.414MB
Generate output files:
    CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.695s, Peak memory usage = 336.414MB
Total Time and Memory Usage CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 336.414MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 12
I/O Buf 10
    IBUF 3
    OBUF 5
    TLVDS_IBUF 1
    TLVDS_OBUF 1
Register 5199
    DFFRE 910
    DFFPE 176
    DFFCE 4113
LUT 4902
    LUT2 563
    LUT3 1604
    LUT4 2735
ALU 390
    ALU 390
INV 48
    INV 48
IOLOGIC 2
    OSER8 1
    OSIDES32 1
BSRAM 1
    SDPB 1
CLOCK 7
    CLKDIV 1
    DHCE 4
    PLLA 2

Resource Utilization Summary

Resource Usage Utilization
Logic 5340(4950 LUT, 390 ALU) / 23040 24%
Register 5199 / 23685 22%
  --Register as Latch 0 / 23685 0%
  --Register as FF 5199 / 23685 22%
BSRAM 1 / 56 2%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
board_clk Base 20.000 50.0 0.000 10.000 board_clk_ibuf/I
u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk Generated 1.600 625.0 0.000 0.800 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT0
u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk Generated 1.600 625.0 0.000 0.800 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT1
u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk Generated 1.600 625.0 0.000 0.800 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT2
u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk Generated 1.600 625.0 0.000 0.800 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT3
u_pll_hclk/PLLA_inst/CLKOUT4.default_gen_clk Generated 8.000 125.0 0.000 4.000 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT4
u_pll_uart/PLLA_inst/CLKOUT0.default_gen_clk Generated 100.000 10.0 0.000 50.000 board_clk_ibuf/I board_clk u_pll_uart/PLLA_inst/CLKOUT0
u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk Generated 6.400 156.3 0.000 3.200 u_pll_hclk/PLLA_inst/CLKOUT0 u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 board_clk 50.000(MHz) 478.240(MHz) 3 TOP
2 u_pll_hclk/PLLA_inst/CLKOUT4.default_gen_clk 125.000(MHz) 212.947(MHz) 7 TOP
3 u_pll_uart/PLLA_inst/CLKOUT0.default_gen_clk 10.000(MHz) 156.030(MHz) 9 TOP
4 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk 156.250(MHz) 185.839(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -2.098
Data Arrival Time 503.140
Data Required Time 501.042
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/mr_lp_adv_ability_11_s1
To u_sysreg/uart_rdata_1_s0
Launch Clk u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_pll_uart/PLLA_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
499.200 0.000 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk
499.454 0.254 tCL RR 770 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
499.754 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/mr_lp_adv_ability_11_s1/CLK
500.060 0.306 tC2Q RR 2 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/mr_lp_adv_ability_11_s1/Q
500.360 0.300 tNET RR 1 u_sysreg/n1791_s54/I0
500.781 0.421 tINS RR 1 u_sysreg/n1791_s54/F
501.081 0.300 tNET RR 1 u_sysreg/n1791_s42/I2
501.450 0.369 tINS RR 1 u_sysreg/n1791_s42/F
501.750 0.300 tNET RR 1 u_sysreg/n1791_s36/I2
502.119 0.369 tINS RR 1 u_sysreg/n1791_s36/F
502.419 0.300 tNET RR 1 u_sysreg/n1791_s35/I0
502.840 0.421 tINS RR 1 u_sysreg/n1791_s35/F
503.140 0.300 tNET RR 1 u_sysreg/uart_rdata_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
500.000 0.000 u_pll_uart/PLLA_inst/CLKOUT0.default_gen_clk
500.828 0.828 tCL RR 2004 u_pll_uart/PLLA_inst/CLKOUT0
501.128 0.300 tNET RR 1 u_sysreg/uart_rdata_1_s0/CLK
501.093 -0.035 tUnc u_sysreg/uart_rdata_1_s0
501.042 -0.051 tSu 1 u_sysreg/uart_rdata_1_s0
Path Statistics:
Clock Skew: 0.574
Setup Relationship: 0.800
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.580, 46.663%; route: 1.500, 44.300%; tC2Q: 0.306, 9.037%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack -1.923
Data Arrival Time 502.965
Data Required Time 501.042
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/mr_lp_adv_ability_12_s1
To u_sysreg/uart_rdata_2_s0
Launch Clk u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_pll_uart/PLLA_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
499.200 0.000 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk
499.454 0.254 tCL RR 770 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
499.754 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/mr_lp_adv_ability_12_s1/CLK
500.060 0.306 tC2Q RR 2 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/mr_lp_adv_ability_12_s1/Q
500.360 0.300 tNET RR 1 u_sysreg/n1790_s54/I1
500.773 0.413 tINS RR 1 u_sysreg/n1790_s54/F
501.073 0.300 tNET RR 1 u_sysreg/n1790_s47/I1
501.486 0.413 tINS RR 1 u_sysreg/n1790_s47/F
501.786 0.300 tNET RR 1 u_sysreg/n1790_s39/I2
502.155 0.369 tINS RR 1 u_sysreg/n1790_s39/F
502.455 0.300 tNET RR 1 u_sysreg/n1790_s35/I3
502.665 0.210 tINS RR 1 u_sysreg/n1790_s35/F
502.965 0.300 tNET RR 1 u_sysreg/uart_rdata_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
500.000 0.000 u_pll_uart/PLLA_inst/CLKOUT0.default_gen_clk
500.828 0.828 tCL RR 2004 u_pll_uart/PLLA_inst/CLKOUT0
501.128 0.300 tNET RR 1 u_sysreg/uart_rdata_2_s0/CLK
501.093 -0.035 tUnc u_sysreg/uart_rdata_2_s0
501.042 -0.051 tSu 1 u_sysreg/uart_rdata_2_s0
Path Statistics:
Clock Skew: 0.574
Setup Relationship: 0.800
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.405, 43.756%; route: 1.500, 46.714%; tC2Q: 0.306, 9.530%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack -1.856
Data Arrival Time 303.124
Data Required Time 301.268
From u_sysreg/reg0x0020_1_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/tx_config_14_s1
Launch Clk u_pll_uart/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
300.000 0.000 u_pll_uart/PLLA_inst/CLKOUT0.default_gen_clk
300.828 0.828 tCL RR 2004 u_pll_uart/PLLA_inst/CLKOUT0
301.128 0.300 tNET RR 1 u_sysreg/reg0x0020_1_s0/CLK
301.434 0.306 tC2Q RR 9 u_sysreg/reg0x0020_1_s0/Q
301.734 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n238_s5/I2
302.103 0.369 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n238_s5/F
302.403 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n238_s6/I0
302.824 0.421 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n238_s6/F
303.124 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/tx_config_14_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
300.800 0.000 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk
301.054 0.254 tCL RR 770 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
301.354 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/tx_config_14_s1/CLK
301.319 -0.035 tUnc u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/tx_config_14_s1
301.268 -0.051 tSu 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/tx_config_14_s1
Path Statistics:
Clock Skew: -0.574
Setup Relationship: 0.800
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.790, 39.579%; route: 0.900, 45.090%; tC2Q: 0.306, 15.331%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack -1.534
Data Arrival Time 27.602
Data Required Time 26.068
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/regstore[2]_0_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_0_s0
Launch Clk u_pll_hclk/PLLA_inst/CLKOUT4.default_gen_clk[R]
Latch Clk u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
24.000 0.000 u_pll_hclk/PLLA_inst/CLKOUT4.default_gen_clk
24.828 0.828 tCL RR 2398 u_pll_hclk/PLLA_inst/CLKOUT4
25.128 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/regstore[2]_0_s0/CLK
25.434 0.306 tC2Q RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/regstore[2]_0_s0/Q
25.734 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_0_s7/I0
26.155 0.421 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_0_s7/F
26.455 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_0_s2/I1
26.564 0.109 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_0_s2/O
26.864 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_0_s0/I0
26.933 0.069 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_0_s0/O
27.233 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_0_s/I0
27.302 0.069 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_0_s/O
27.602 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
25.600 0.000 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk
25.854 0.254 tCL RR 770 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
26.154 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_0_s0/CLK
26.119 -0.035 tUnc u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_0_s0
26.068 -0.051 tSu 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_0_s0
Path Statistics:
Clock Skew: -0.574
Setup Relationship: 1.600
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.668, 27.001%; route: 1.500, 60.630%; tC2Q: 0.306, 12.369%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack -1.534
Data Arrival Time 27.602
Data Required Time 26.068
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/regstore[2]_1_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_1_s0
Launch Clk u_pll_hclk/PLLA_inst/CLKOUT4.default_gen_clk[R]
Latch Clk u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
24.000 0.000 u_pll_hclk/PLLA_inst/CLKOUT4.default_gen_clk
24.828 0.828 tCL RR 2398 u_pll_hclk/PLLA_inst/CLKOUT4
25.128 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/regstore[2]_1_s0/CLK
25.434 0.306 tC2Q RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/regstore[2]_1_s0/Q
25.734 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_1_s7/I0
26.155 0.421 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_1_s7/F
26.455 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_1_s2/I1
26.564 0.109 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_1_s2/O
26.864 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_1_s0/I0
26.933 0.069 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_1_s0/O
27.233 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_1_s/I0
27.302 0.069 tINS RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_regram/rddata2ram_Z_1_s/O
27.602 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
25.600 0.000 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk
25.854 0.254 tCL RR 770 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
26.154 0.300 tNET RR 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_1_s0/CLK
26.119 -0.035 tUnc u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_1_s0
26.068 -0.051 tSu 1 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/rddata_1_s0
Path Statistics:
Clock Skew: -0.574
Setup Relationship: 1.600
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.668, 27.001%; route: 1.500, 60.630%; tC2Q: 0.306, 12.369%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%