Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Aug 30 08:40:42 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Uart_to_Bus_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.812s, Peak memory usage = 48.586MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 48.586MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 48.586MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 48.586MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 48.586MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 48.586MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 48.586MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 48.586MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 48.586MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 48.586MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 48.586MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 48.586MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 61.090MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.154s, Peak memory usage = 61.090MB
Generate output files:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.399s, Peak memory usage = 61.090MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 61.090MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 90
I/O Buf 90
    IBUF 37
    OBUF 53
Register 1437
    DFFRE 838
    DFFPE 9
    DFFCE 590
LUT 933
    LUT2 131
    LUT3 549
    LUT4 253
ALU 39
    ALU 39
INV 12
    INV 12

Resource Utilization Summary

Resource Usage Utilization
Logic 984(945 LUT, 39 ALU) / 23040 5%
Register 1437 / 23685 7%
  --Register as Latch 0 / 23685 0%
  --Register as FF 1437 / 23685 7%
BSRAM 0 / 56 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 10.000 100.0 0.000 5.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 100.0(MHz) 191.5(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.779
Data Arrival Time 6.023
Data Required Time 10.801
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1437 clk_i_ibuf/O
0.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/CLK
1.230 0.367 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/Q
1.410 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/I0
1.915 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/F
2.095 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/I1
2.226 0.131 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/O
2.406 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/I1
2.489 0.083 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/O
2.669 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/I2
3.111 0.443 tINS RR 3 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/F
3.291 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s46/I0
3.797 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s46/F
3.977 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s42/I0
4.482 0.505 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s42/F
4.662 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s40/I1
5.157 0.496 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s40/F
5.337 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s39/I0
5.843 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s39/F
6.023 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1437 clk_i_ibuf/O
10.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0/CLK
10.801 -0.061 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.173, 61.489%; route: 1.620, 31.395%; tC2Q: 0.367, 7.116%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.851
Data Arrival Time 5.951
Data Required Time 10.801
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1437 clk_i_ibuf/O
0.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK
1.230 0.367 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q
1.410 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0
1.915 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F
2.095 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1
2.226 0.131 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O
2.406 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1
2.489 0.083 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O
2.669 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s46/I1
3.164 0.496 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s46/F
3.344 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/I2
3.787 0.443 tINS RR 8 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/F
3.967 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/I0
4.472 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s43/F
4.652 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/I2
5.095 0.443 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/F
5.275 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/I1
5.771 0.496 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/F
5.951 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1437 clk_i_ibuf/O
10.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/CLK
10.801 -0.061 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.101, 60.943%; route: 1.620, 31.840%; tC2Q: 0.367, 7.217%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.042
Data Arrival Time 5.760
Data Required Time 10.801
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1437 clk_i_ibuf/O
0.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/CLK
1.230 0.367 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/Q
1.410 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/I0
1.915 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/F
2.095 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/I1
2.226 0.131 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/O
2.406 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/I1
2.489 0.083 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/O
2.669 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/I2
3.111 0.443 tINS RR 3 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/F
3.291 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/I1
3.787 0.496 tINS RR 8 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/F
3.967 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s43/I3
4.219 0.252 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s43/F
4.399 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/I0
4.904 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s40/F
5.084 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/I1
5.580 0.496 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/F
5.760 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1437 clk_i_ibuf/O
10.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLK
10.801 -0.061 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.910, 59.422%; route: 1.620, 33.080%; tC2Q: 0.367, 7.498%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.094
Data Arrival Time 5.707
Data Required Time 10.801
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1437 clk_i_ibuf/O
0.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/CLK
1.230 0.367 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/Q
1.410 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/I0
1.915 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/F
2.095 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/I1
2.226 0.131 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/O
2.406 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/I1
2.489 0.083 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/O
2.669 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/I2
3.111 0.443 tINS RR 3 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s45/F
3.291 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/I1
3.787 0.496 tINS RR 8 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s41/F
3.967 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s44/I3
4.219 0.252 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s44/F
4.399 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s42/I0
4.904 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s42/F
5.084 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s40/I2
5.527 0.443 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s40/F
5.707 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1437 clk_i_ibuf/O
10.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/CLK
10.801 -0.061 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.857, 58.979%; route: 1.620, 33.441%; tC2Q: 0.367, 7.580%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.114
Data Arrival Time 5.688
Data Required Time 10.801
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_32_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1437 clk_i_ibuf/O
0.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_32_s0/CLK
1.230 0.367 tC2Q RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_32_s0/Q
1.410 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n177_s1/I0
1.915 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n177_s1/F
2.095 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n177_s0/I0
2.226 0.131 tINS RR 2 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n177_s0/O
2.406 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/I0
2.911 0.505 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/F
3.091 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s46/I2
3.534 0.443 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s46/F
3.714 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s43/I2
4.157 0.443 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s43/F
4.337 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s41/I1
4.832 0.496 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s41/F
5.012 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s40/I1
5.508 0.496 tINS RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s40/F
5.688 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1437 clk_i_ibuf/O
10.863 0.180 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0/CLK
10.801 -0.061 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.018, 62.547%; route: 1.440, 29.843%; tC2Q: 0.367, 7.610%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%