Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\1GSEO_LVDS\data\giga_serial_ethernet_wrap.v D:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\1GSEO_LVDS\data\giga_serial_ethernet.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.02 |
Part Number | GW5A-LV25UG324C2/I1 |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Mar 20 15:15:44 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Giga_Serial_Ethernet_LVDS_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.596s, Peak memory usage = 97.367MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 97.367MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.164s, Peak memory usage = 97.367MB Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.123s, Peak memory usage = 97.367MB Optimizing Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.223s, Peak memory usage = 97.367MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 97.367MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 97.367MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 97.367MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 97.367MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.264s, Peak memory usage = 97.367MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 97.367MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 97.367MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 120.406MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.238s, Peak memory usage = 120.406MB Generate output files: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.278s, Peak memory usage = 120.406MB |
Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 120.406MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 321 |
I/O Buf | 319 |
    IBUF | 165 |
    OBUF | 152 |
    TLVDS_IBUF | 1 |
    TLVDS_OBUF | 1 |
Register | 2242 |
    DFFRE | 56 |
    DFFPE | 113 |
    DFFCE | 2073 |
LUT | 2423 |
    LUT2 | 320 |
    LUT3 | 623 |
    LUT4 | 1480 |
ALU | 78 |
    ALU | 78 |
INV | 26 |
    INV | 26 |
IOLOGIC | 2 |
    OSER8 | 1 |
    OSIDES32 | 1 |
BSRAM | 1 |
    SDPB | 1 |
CLOCK | 5 |
    CLKDIV | 1 |
    DHCE | 4 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2527(2449 LUT, 78 ALU) / 23040 | 11% |
Register | 2242 / 23685 | 10% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 2242 / 23685 | 10% |
BSRAM | 1 / 56 | 2% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
pll_clkout0_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkout0_i_ibuf/I | ||
pll_clkout1_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkout1_i_ibuf/I | ||
pll_clkout2_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkout2_i_ibuf/I | ||
pll_clkout3_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkout3_i_ibuf/I | ||
pll_clkout4_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkout4_i_ibuf/I | ||
pll_clkin_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | pll_clkin_i_ibuf/I | ||
miim_hs_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | miim_hs_clk_i_ibuf/I | ||
u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | pll_clkout0_i_ibuf/I | pll_clkout0_i | u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | pll_clkout4_i | 100.000(MHz) | 212.947(MHz) | 7 | TOP |
2 | pll_clkin_i | 100.000(MHz) | 478.240(MHz) | 3 | TOP |
3 | miim_hs_clk_i | 100.000(MHz) | 238.720(MHz) | 6 | TOP |
4 | u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk | 25.000(MHz) | 185.839(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.186 |
Data Arrival Time | 1.493 |
Data Required Time | 5.679 |
From | u_giga_serial_ethernet/u_share_logic/cen_s0 |
To | u_giga_serial_ethernet/u_share_logic/dhcen_625m_0 |
Launch Clk | pll_clkin_i[F] |
Latch Clk | pll_clkout0_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkin_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkin_i_ibuf/I |
0.587 | 0.587 | tINS | RR | 9 | pll_clkin_i_ibuf/O |
0.887 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_share_logic/cen_s0/CLK |
1.193 | 0.306 | tC2Q | RR | 4 | u_giga_serial_ethernet/u_share_logic/cen_s0/Q |
1.493 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_share_logic/dhcen_625m_0/CEN |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | pll_clkout0_i | |||
5.000 | 0.000 | tCL | FF | 1 | pll_clkout0_i_ibuf/I |
5.591 | 0.591 | tINS | FF | 1 | pll_clkout0_i_ibuf/O |
5.871 | 0.280 | tNET | FF | 3 | u_giga_serial_ethernet/u_share_logic/dhcen_625m_0/CLKIN |
5.836 | -0.035 | tUnc | u_giga_serial_ethernet/u_share_logic/dhcen_625m_0 | ||
5.679 | -0.157 | tSu | 1 | u_giga_serial_ethernet/u_share_logic/dhcen_625m_0 |
Clock Skew: | -0.016 |
Setup Relationship: | 5.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.300, 49.505%; tC2Q: 0.306, 50.495% |
Required Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Path 2
Path Summary:Slack | 5.304 |
Data Arrival Time | 5.334 |
Data Required Time | 10.638 |
From | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
To | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
Launch Clk | pll_clkout4_i[R] |
Latch Clk | pll_clkout4_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkout4_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkout4_i_ibuf/I |
0.587 | 0.587 | tINS | RR | 1346 | pll_clkout4_i_ibuf/O |
0.887 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
1.193 | 0.306 | tC2Q | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
1.493 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
1.914 | 0.421 | tINS | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
2.214 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
2.627 | 0.413 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
2.927 | 0.300 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
3.377 | 0.450 | tINS | RF | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
3.377 | 0.000 | tNET | FF | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
3.417 | 0.040 | tINS | FR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
3.417 | 0.000 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
3.457 | 0.040 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/COUT |
3.457 | 0.000 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/CIN |
3.652 | 0.195 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/SUM |
3.952 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
4.365 | 0.413 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
4.665 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s0/I2 |
5.034 | 0.369 | tINS | RR | 5 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
5.334 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pll_clkout4_i | |||
10.000 | 0.000 | tCL | RR | 1 | pll_clkout4_i_ibuf/I |
10.587 | 0.587 | tINS | RR | 1346 | pll_clkout4_i_ibuf/O |
10.887 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CLK |
10.638 | -0.249 | tSu | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Arrival Data Path Delay: | cell: 2.341, 52.642%; route: 1.800, 40.477%; tC2Q: 0.306, 6.881% |
Required Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Path 3
Path Summary:Slack | 5.304 |
Data Arrival Time | 5.334 |
Data Required Time | 10.638 |
From | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
To | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
Launch Clk | pll_clkout4_i[R] |
Latch Clk | pll_clkout4_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkout4_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkout4_i_ibuf/I |
0.587 | 0.587 | tINS | RR | 1346 | pll_clkout4_i_ibuf/O |
0.887 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
1.193 | 0.306 | tC2Q | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
1.493 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
1.914 | 0.421 | tINS | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
2.214 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
2.627 | 0.413 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
2.927 | 0.300 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
3.377 | 0.450 | tINS | RF | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
3.377 | 0.000 | tNET | FF | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
3.417 | 0.040 | tINS | FR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
3.417 | 0.000 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
3.457 | 0.040 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/COUT |
3.457 | 0.000 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/CIN |
3.652 | 0.195 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/SUM |
3.952 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
4.365 | 0.413 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
4.665 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s0/I2 |
5.034 | 0.369 | tINS | RR | 5 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
5.334 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pll_clkout4_i | |||
10.000 | 0.000 | tCL | RR | 1 | pll_clkout4_i_ibuf/I |
10.587 | 0.587 | tINS | RR | 1346 | pll_clkout4_i_ibuf/O |
10.887 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CLK |
10.638 | -0.249 | tSu | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Arrival Data Path Delay: | cell: 2.341, 52.642%; route: 1.800, 40.477%; tC2Q: 0.306, 6.881% |
Required Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Path 4
Path Summary:Slack | 5.304 |
Data Arrival Time | 5.334 |
Data Required Time | 10.638 |
From | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
To | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
Launch Clk | pll_clkout4_i[R] |
Latch Clk | pll_clkout4_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkout4_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkout4_i_ibuf/I |
0.587 | 0.587 | tINS | RR | 1346 | pll_clkout4_i_ibuf/O |
0.887 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
1.193 | 0.306 | tC2Q | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
1.493 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
1.914 | 0.421 | tINS | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
2.214 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
2.627 | 0.413 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
2.927 | 0.300 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
3.377 | 0.450 | tINS | RF | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
3.377 | 0.000 | tNET | FF | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
3.417 | 0.040 | tINS | FR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
3.417 | 0.000 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
3.457 | 0.040 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/COUT |
3.457 | 0.000 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/CIN |
3.652 | 0.195 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/SUM |
3.952 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
4.365 | 0.413 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
4.665 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s0/I2 |
5.034 | 0.369 | tINS | RR | 5 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
5.334 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pll_clkout4_i | |||
10.000 | 0.000 | tCL | RR | 1 | pll_clkout4_i_ibuf/I |
10.587 | 0.587 | tINS | RR | 1346 | pll_clkout4_i_ibuf/O |
10.887 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CLK |
10.638 | -0.249 | tSu | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Arrival Data Path Delay: | cell: 2.341, 52.642%; route: 1.800, 40.477%; tC2Q: 0.306, 6.881% |
Required Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Path 5
Path Summary:Slack | 5.304 |
Data Arrival Time | 5.334 |
Data Required Time | 10.638 |
From | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
To | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
Launch Clk | pll_clkout4_i[R] |
Latch Clk | pll_clkout4_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pll_clkout4_i | |||
0.000 | 0.000 | tCL | RR | 1 | pll_clkout4_i_ibuf/I |
0.587 | 0.587 | tINS | RR | 1346 | pll_clkout4_i_ibuf/O |
0.887 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
1.193 | 0.306 | tC2Q | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
1.493 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
1.914 | 0.421 | tINS | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
2.214 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
2.627 | 0.413 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
2.927 | 0.300 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
3.377 | 0.450 | tINS | RF | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
3.377 | 0.000 | tNET | FF | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
3.417 | 0.040 | tINS | FR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
3.417 | 0.000 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
3.457 | 0.040 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/COUT |
3.457 | 0.000 | tNET | RR | 2 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/CIN |
3.652 | 0.195 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_3_s/SUM |
3.952 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
4.365 | 0.413 | tINS | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
4.665 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s0/I2 |
5.034 | 0.369 | tINS | RR | 5 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
5.334 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pll_clkout4_i | |||
10.000 | 0.000 | tCL | RR | 1 | pll_clkout4_i_ibuf/I |
10.587 | 0.587 | tINS | RR | 1346 | pll_clkout4_i_ibuf/O |
10.887 | 0.300 | tNET | RR | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CLK |
10.638 | -0.249 | tSu | 1 | u_giga_serial_ethernet/u_os_pma_pcs_tx/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |
Arrival Data Path Delay: | cell: 2.341, 52.642%; route: 1.800, 40.477%; tC2Q: 0.306, 6.881% |
Required Clock Path Delay: | cell: 0.587, 66.176%; route: 0.300, 33.824% |