Timing Messages

Report Title Timing Analysis Report
Design File E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\fpga_project.cst
Timing Constraint File E:\IP_Release\1G_Serial_Ethernet_Over_LVDS\1.1\ref_design\25K\Gowin_1G_Serial_Ethernet_Over_LVDS_RefDesign\project\src\fpga_project.sdc
Tool Version V1.9.9.02
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Wed Mar 20 15:16:41 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C C2/I1
Hold Delay Model Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed 23968
Numbers of Endpoints Analyzed 15667
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
board_clk Base 20.000 50.000 0.000 10.000 board_clk_ibuf/I
hclk Generated 1.600 625.000 0.000 0.800 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT0
clk_mac Generated 8.000 125.000 0.000 4.000 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT4
clk_uart Generated 100.000 10.000 0.000 50.000 board_clk_ibuf/I board_clk u_pll_uart/PLLA_inst/CLKOUT0
clk_os Generated 6.400 156.250 0.000 3.200 u_pll_hclk/PLLA_inst/CLKOUT0 hclk u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk Generated 1.600 625.000 0.000 0.800 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT1
u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk Generated 1.600 625.000 0.000 0.800 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT2
u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk Generated 1.600 625.000 0.000 0.800 board_clk_ibuf/I board_clk u_pll_hclk/PLLA_inst/CLKOUT3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 board_clk 50.000(MHz) 424.268(MHz) 2 TOP
2 clk_mac 125.000(MHz) 167.357(MHz) 3 TOP
3 clk_uart 10.000(MHz) 86.516(MHz) 9 TOP
4 clk_os 156.250(MHz) 172.548(MHz) 7 TOP

No timing paths to get frequency of hclk!

No timing paths to get frequency of u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk!

No timing paths to get frequency of u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk!

No timing paths to get frequency of u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
board_clk Setup 0.000 0
board_clk Hold 0.000 0
hclk Setup 0.000 0
hclk Hold 0.000 0
clk_mac Setup 0.000 0
clk_mac Hold 0.000 0
clk_uart Setup 0.000 0
clk_uart Hold 0.000 0
clk_os Setup 0.000 0
clk_os Hold 0.000 0
u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk Setup 0.000 0
u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk Hold 0.000 0
u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk Setup 0.000 0
u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk Hold 0.000 0
u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk Setup 0.000 0
u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.604 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0/CE clk_os:[R] clk_os:[R] 6.400 0.039 5.507
2 0.604 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0/CE clk_os:[R] clk_os:[R] 6.400 0.039 5.507
3 0.604 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0/CE clk_os:[R] clk_os:[R] 6.400 0.039 5.507
4 0.604 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_16_s0/CE clk_os:[R] clk_os:[R] 6.400 0.039 5.507
5 0.604 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_17_s0/CE clk_os:[R] clk_os:[R] 6.400 0.039 5.507
6 0.609 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0/CE clk_os:[R] clk_os:[R] 6.400 0.035 5.507
7 0.609 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_10_s0/CE clk_os:[R] clk_os:[R] 6.400 0.035 5.507
8 0.609 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/CE clk_os:[R] clk_os:[R] 6.400 0.035 5.507
9 0.612 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_15_s0/CE clk_os:[R] clk_os:[R] 6.400 0.032 5.507
10 0.612 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_18_s0/CE clk_os:[R] clk_os:[R] 6.400 0.032 5.507
11 0.637 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_5_s0/CE clk_os:[R] clk_os:[R] 6.400 0.027 5.487
12 0.643 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_19_s0/CE clk_os:[R] clk_os:[R] 6.400 0.047 5.461
13 0.649 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_1_s0/CE clk_os:[R] clk_os:[R] 6.400 0.037 5.465
14 0.649 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_2_s0/CE clk_os:[R] clk_os:[R] 6.400 0.037 5.465
15 0.649 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_3_s0/CE clk_os:[R] clk_os:[R] 6.400 0.037 5.465
16 0.649 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_4_s0/CE clk_os:[R] clk_os:[R] 6.400 0.037 5.465
17 0.650 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_12_s0/CE clk_os:[R] clk_os:[R] 6.400 0.044 5.457
18 0.675 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0/D clk_os:[R] clk_os:[R] 6.400 0.039 5.634
19 0.680 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/D clk_os:[R] clk_os:[R] 6.400 0.035 5.634
20 0.731 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0/D clk_os:[R] clk_os:[R] 6.400 0.039 5.578
21 0.731 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0/D clk_os:[R] clk_os:[R] 6.400 0.039 5.578
22 0.738 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0/D clk_os:[R] clk_os:[R] 6.400 0.035 5.576
23 0.761 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s0/CE clk_os:[R] clk_os:[R] 6.400 0.037 5.353
24 0.766 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_0_s0/CE clk_os:[R] clk_os:[R] 6.400 0.052 5.333
25 0.766 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_7_s0/CE clk_os:[R] clk_os:[R] 6.400 0.052 5.333

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.187 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_5_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/DI[5] clk_os:[R] clk_os:[R] 0.000 -0.014 0.416
2 0.262 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_8_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/DI[8] clk_os:[R] clk_os:[R] 0.000 -0.014 0.491
3 0.277 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_9_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/DI[9] clk_os:[R] clk_os:[R] 0.000 -0.014 0.506
4 0.287 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_7_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/DI[7] clk_os:[R] clk_os:[R] 0.000 -0.010 0.512
5 0.299 u_mac_tx_model/tx_cnt_16_s1/Q u_mac_tx_model/tx_cnt_16_s1/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
6 0.299 u_mac_tx_model/data_increase_2_s1/Q u_mac_tx_model/data_increase_2_s1/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
7 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
8 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_4_s3/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_4_s3/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
9 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_6_s3/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_6_s3/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
10 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_3_s3/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_3_s3/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
11 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_12_s3/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_12_s3/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
12 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
13 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_28_s3/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_28_s3/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
14 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_47_s3/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_47_s3/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
15 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_12_s1/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_12_s1/D clk_os:[R] clk_os:[R] 0.000 0.000 0.300
16 0.299 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/D clk_os:[R] clk_os:[R] 0.000 0.000 0.300
17 0.299 u_mac_rx_model/rx_error_all_check_s4/Q u_mac_rx_model/rx_error_all_check_s4/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
18 0.299 u_mac_rx_model/rx_error_all_data_check_s4/Q u_mac_rx_model/rx_error_all_data_check_s4/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
19 0.299 u_mac_rx_model/rx_data_cnt_pause_11_s1/Q u_mac_rx_model/rx_data_cnt_pause_11_s1/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
20 0.299 u_mac_rx_model/pause_address_6_s1/Q u_mac_rx_model/pause_address_6_s1/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
21 0.299 u_mac_rx_model/pause_address_7_s1/Q u_mac_rx_model/pause_address_7_s1/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
22 0.299 u_mac_rx_model/pause_address_12_s1/Q u_mac_rx_model/pause_address_12_s1/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
23 0.299 u_mac_rx_model/pause_value_2_s1/Q u_mac_rx_model/pause_value_2_s1/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
24 0.299 u_mac_rx_model/pause_value_8_s1/Q u_mac_rx_model/pause_value_8_s1/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300
25 0.299 u_mac_rx_model/rx_data_cnt_4_s1/Q u_mac_rx_model/rx_data_cnt_4_s1/D clk_mac:[R] clk_mac:[R] 0.000 0.000 0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 3.758 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_1_s0/PRESET clk_os:[R] clk_os:[R] 6.400 0.042 2.322
2 3.758 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_2_s0/PRESET clk_os:[R] clk_os:[R] 6.400 0.042 2.322
3 3.758 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_3_s0/PRESET clk_os:[R] clk_os:[R] 6.400 0.042 2.322
4 3.758 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_4_s0/PRESET clk_os:[R] clk_os:[R] 6.400 0.042 2.322
5 3.758 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_5_s0/PRESET clk_os:[R] clk_os:[R] 6.400 0.042 2.322
6 3.758 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_6_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.042 2.322
7 3.773 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_en_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.040 2.308
8 4.012 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/gmii_align_flag_s2/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_pre_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 -0.027 2.137
9 4.012 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/gmii_align_flag_s2/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 -0.027 2.137
10 4.079 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_0_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.036 2.007
11 4.079 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_1_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.036 2.007
12 4.378 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_2_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.037 1.706
13 4.378 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_6_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.037 1.706
14 4.383 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_0_s0/PRESET clk_os:[R] clk_os:[R] 6.400 0.059 1.680
15 4.383 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_5_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.059 1.680
16 4.383 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_8_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.059 1.680
17 4.383 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_9_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.059 1.680
18 4.542 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_4_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.054 1.526
19 4.542 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_7_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.054 1.526
20 4.673 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_3_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.044 1.405
21 4.673 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_0_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.044 1.405
22 4.673 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_1_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.044 1.405
23 4.673 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_2_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.044 1.405
24 4.673 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_3_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.044 1.405
25 4.673 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_4_s0/CLEAR clk_os:[R] clk_os:[R] 6.400 0.044 1.405

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.468 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/reset_o_s0/PRESET board_clk:[R] board_clk:[R] 0.000 -0.004 0.321
2 0.468 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/resetn_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 -0.004 0.321
3 0.486 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_5_s0/CLEAR clk_mac:[R] clk_mac:[R] 0.000 -0.004 0.339
4 0.486 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_9_s0/CLEAR clk_mac:[R] clk_mac:[R] 0.000 -0.004 0.339
5 0.496 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_0_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.002 0.343
6 0.496 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_1_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.002 0.343
7 0.500 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_4_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.004 0.345
8 0.502 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_6_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.006 0.345
9 0.503 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_0_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.007 0.345
10 0.503 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_2_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.007 0.345
11 0.504 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_4_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.010 0.343
12 0.504 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_2_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.008 0.345
13 0.504 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_6_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.008 0.345
14 0.521 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_wr_addr_gray_tmp_4_s0/CLEAR clk_mac:[R] clk_mac:[R] 0.000 -0.009 0.379
15 0.535 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_0_s0/CLEAR clk_os:[R] clk_os:[R] 0.000 0.002 0.382
16 0.569 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_0_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.002 0.416
17 0.569 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_1_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.002 0.416
18 0.569 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_2_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.002 0.416
19 0.569 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_3_s0/CLEAR board_clk:[R] board_clk:[R] 0.000 0.002 0.416
20 0.580 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_3_s0/CLEAR clk_mac:[R] clk_mac:[R] 0.000 -0.008 0.437
21 0.580 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_4_s0/CLEAR clk_mac:[R] clk_mac:[R] 0.000 -0.008 0.437
22 0.580 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_8_s0/CLEAR clk_mac:[R] clk_mac:[R] 0.000 -0.008 0.437
23 0.580 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d1_0_s3/CLEAR clk_mac:[R] clk_mac:[R] 0.000 -0.012 0.441
24 0.580 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_2_s0/CLEAR clk_mac:[R] clk_mac:[R] 0.000 -0.012 0.441
25 0.580 u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_6_s0/CLEAR clk_mac:[R] clk_mac:[R] 0.000 -0.012 0.441

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 1.944 2.806 0.862 Low Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s
2 1.946 2.808 0.862 High Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s
3 2.594 2.794 0.200 Low Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_30_s0
4 2.594 2.794 0.200 Low Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_27_s0
5 2.594 2.794 0.200 Low Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_24_s0
6 2.594 2.794 0.200 Low Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d1_14_s1
7 2.594 2.794 0.200 Low Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_14_s1
8 2.594 2.794 0.200 Low Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/ability_matched_reg_6_s0
9 2.594 2.794 0.200 Low Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/acknowledge_match_s2
10 2.594 2.794 0.200 Low Pulse Width clk_os u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/IDD_30_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.604
Data Arrival Time 6.227
Data Required Time 6.832
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R31C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.081 0.681 tNET RR 1 R31C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0/CLK
6.832 -0.249 tSu 1 R31C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0

Path Statistics:

Clock Skew -0.039
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.681, 100.000%

Path2

Path Summary:

Slack 0.604
Data Arrival Time 6.227
Data Required Time 6.832
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R31C23[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.081 0.681 tNET RR 1 R31C23[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0/CLK
6.832 -0.249 tSu 1 R31C23[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0

Path Statistics:

Clock Skew -0.039
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.681, 100.000%

Path3

Path Summary:

Slack 0.604
Data Arrival Time 6.227
Data Required Time 6.832
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R31C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.081 0.681 tNET RR 1 R31C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0/CLK
6.832 -0.249 tSu 1 R31C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0

Path Statistics:

Clock Skew -0.039
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.681, 100.000%

Path4

Path Summary:

Slack 0.604
Data Arrival Time 6.227
Data Required Time 6.832
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_16_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R31C27[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_16_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.081 0.681 tNET RR 1 R31C27[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_16_s0/CLK
6.832 -0.249 tSu 1 R31C27[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_16_s0

Path Statistics:

Clock Skew -0.039
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.681, 100.000%

Path5

Path Summary:

Slack 0.604
Data Arrival Time 6.227
Data Required Time 6.832
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_17_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R31C27[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_17_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.081 0.681 tNET RR 1 R31C27[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_17_s0/CLK
6.832 -0.249 tSu 1 R31C27[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_17_s0

Path Statistics:

Clock Skew -0.039
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.681, 100.000%

Path6

Path Summary:

Slack 0.609
Data Arrival Time 6.227
Data Required Time 6.837
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R32C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R32C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0/CLK
6.837 -0.249 tSu 1 R32C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0

Path Statistics:

Clock Skew -0.035
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path7

Path Summary:

Slack 0.609
Data Arrival Time 6.227
Data Required Time 6.837
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_10_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R32C23[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R32C23[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_10_s0/CLK
6.837 -0.249 tSu 1 R32C23[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_10_s0

Path Statistics:

Clock Skew -0.035
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path8

Path Summary:

Slack 0.609
Data Arrival Time 6.227
Data Required Time 6.837
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/CLK
6.837 -0.249 tSu 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0

Path Statistics:

Clock Skew -0.035
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path9

Path Summary:

Slack 0.612
Data Arrival Time 6.227
Data Required Time 6.839
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_15_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R31C28[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_15_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.088 0.688 tNET RR 1 R31C28[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_15_s0/CLK
6.839 -0.249 tSu 1 R31C28[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_15_s0

Path Statistics:

Clock Skew -0.032
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.688, 100.000%

Path10

Path Summary:

Slack 0.612
Data Arrival Time 6.227
Data Required Time 6.839
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_18_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.227 0.452 tNET RR 1 R31C28[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_18_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.088 0.688 tNET RR 1 R31C28[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_18_s0/CLK
6.839 -0.249 tSu 1 R31C28[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_18_s0

Path Statistics:

Clock Skew -0.032
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.458%; route: 2.973, 53.986%; tC2Q: 0.306, 5.557%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.688, 100.000%

Path11

Path Summary:

Slack 0.637
Data Arrival Time 6.207
Data Required Time 6.844
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_5_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.207 0.432 tNET RR 1 R32C24[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.093 0.693 tNET RR 1 R32C24[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_5_s0/CLK
6.844 -0.249 tSu 1 R32C24[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_5_s0

Path Statistics:

Clock Skew -0.027
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.605%; route: 2.953, 53.818%; tC2Q: 0.306, 5.577%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.693, 100.000%

Path12

Path Summary:

Slack 0.643
Data Arrival Time 6.181
Data Required Time 6.824
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_19_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.181 0.406 tNET RR 1 R31C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_19_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.073 0.674 tNET RR 1 R31C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_19_s0/CLK
6.824 -0.249 tSu 1 R31C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_19_s0

Path Statistics:

Clock Skew -0.047
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.798%; route: 2.927, 53.598%; tC2Q: 0.306, 5.603%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.674, 100.000%

Path13

Path Summary:

Slack 0.649
Data Arrival Time 6.185
Data Required Time 6.835
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_1_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.185 0.410 tNET RR 1 R30C24[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R30C24[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_1_s0/CLK
6.835 -0.249 tSu 1 R30C24[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_1_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.769%; route: 2.931, 53.632%; tC2Q: 0.306, 5.599%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path14

Path Summary:

Slack 0.649
Data Arrival Time 6.185
Data Required Time 6.835
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_2_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.185 0.410 tNET RR 1 R30C24[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R30C24[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_2_s0/CLK
6.835 -0.249 tSu 1 R30C24[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_2_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.769%; route: 2.931, 53.632%; tC2Q: 0.306, 5.599%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path15

Path Summary:

Slack 0.649
Data Arrival Time 6.185
Data Required Time 6.835
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_3_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.185 0.410 tNET RR 1 R30C24[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R30C24[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_3_s0/CLK
6.835 -0.249 tSu 1 R30C24[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_3_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.769%; route: 2.931, 53.632%; tC2Q: 0.306, 5.599%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path16

Path Summary:

Slack 0.649
Data Arrival Time 6.185
Data Required Time 6.835
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_4_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.185 0.410 tNET RR 1 R30C24[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R30C24[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_4_s0/CLK
6.835 -0.249 tSu 1 R30C24[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_4_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.769%; route: 2.931, 53.632%; tC2Q: 0.306, 5.599%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path17

Path Summary:

Slack 0.650
Data Arrival Time 6.177
Data Required Time 6.827
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_12_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.177 0.402 tNET RR 1 R30C23[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_12_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.076 0.676 tNET RR 1 R30C23[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_12_s0/CLK
6.827 -0.249 tSu 1 R30C23[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_12_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 40.828%; route: 2.923, 53.564%; tC2Q: 0.306, 5.607%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path18

Path Summary:

Slack 0.675
Data Arrival Time 6.354
Data Required Time 7.030
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/I1
5.427 0.421 tINS RR 22 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/F
5.985 0.558 tNET RR 1 R31C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n332_s2/I2
6.354 0.369 tINS RR 1 R31C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n332_s2/F
6.354 0.000 tNET RR 1 R31C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.081 0.681 tNET RR 1 R31C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0/CLK
7.030 -0.051 tSu 1 R31C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_14_s0

Path Statistics:

Clock Skew -0.039
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.251, 39.954%; route: 3.077, 54.615%; tC2Q: 0.306, 5.431%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.681, 100.000%

Path19

Path Summary:

Slack 0.680
Data Arrival Time 6.354
Data Required Time 7.035
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/I1
5.427 0.421 tINS RR 22 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/F
5.985 0.558 tNET RR 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n335_s2/I2
6.354 0.369 tINS RR 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n335_s2/F
6.354 0.000 tNET RR 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/CLK
7.035 -0.051 tSu 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0

Path Statistics:

Clock Skew -0.035
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.251, 39.954%; route: 3.077, 54.615%; tC2Q: 0.306, 5.431%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path20

Path Summary:

Slack 0.731
Data Arrival Time 6.298
Data Required Time 7.030
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/I1
5.427 0.421 tINS RR 22 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/F
5.877 0.450 tNET RR 1 R31C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n338_s2/I2
6.298 0.421 tINS RR 1 R31C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n338_s2/F
6.298 0.000 tNET RR 1 R31C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.081 0.681 tNET RR 1 R31C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0/CLK
7.030 -0.051 tSu 1 R31C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_8_s0

Path Statistics:

Clock Skew -0.039
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.303, 41.287%; route: 2.969, 53.227%; tC2Q: 0.306, 5.486%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.681, 100.000%

Path21

Path Summary:

Slack 0.731
Data Arrival Time 6.298
Data Required Time 7.030
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/I1
5.427 0.421 tINS RR 22 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/F
5.877 0.450 tNET RR 1 R31C23[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n333_s2/I0
6.298 0.421 tINS RR 1 R31C23[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n333_s2/F
6.298 0.000 tNET RR 1 R31C23[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.081 0.681 tNET RR 1 R31C23[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0/CLK
7.030 -0.051 tSu 1 R31C23[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_13_s0

Path Statistics:

Clock Skew -0.039
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.303, 41.287%; route: 2.969, 53.227%; tC2Q: 0.306, 5.486%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.681, 100.000%

Path22

Path Summary:

Slack 0.738
Data Arrival Time 6.296
Data Required Time 7.035
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/I1
5.427 0.421 tINS RR 22 R30C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s2/F
5.875 0.448 tNET RR 1 R32C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n337_s2/I0
6.296 0.421 tINS RR 1 R32C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n337_s2/F
6.296 0.000 tNET RR 1 R32C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R32C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0/CLK
7.035 -0.051 tSu 1 R32C23[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_9_s0

Path Statistics:

Clock Skew -0.035
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.303, 41.302%; route: 2.967, 53.210%; tC2Q: 0.306, 5.488%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path23

Path Summary:

Slack 0.761
Data Arrival Time 6.073
Data Required Time 6.835
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.073 0.298 tNET RR 1 R30C28[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R30C28[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s0/CLK
6.835 -0.249 tSu 1 R30C28[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 41.622%; route: 2.819, 52.662%; tC2Q: 0.306, 5.716%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path24

Path Summary:

Slack 0.766
Data Arrival Time 6.053
Data Required Time 6.820
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_0_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.053 0.278 tNET RR 1 R30C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.069 0.669 tNET RR 1 R30C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_0_s0/CLK
6.820 -0.249 tSu 1 R30C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_0_s0

Path Statistics:

Clock Skew -0.052
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 41.778%; route: 2.799, 52.485%; tC2Q: 0.306, 5.738%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path25

Path Summary:

Slack 0.766
Data Arrival Time 6.053
Data Required Time 6.820
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_7_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.720 0.720 tNET RR 1 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/CLK
1.026 0.306 tC2Q RR 5 R21C19[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_5_s1/Q
1.743 0.716 tNET RR 2 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/I1
2.193 0.450 tINS RF 1 R18C18[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n703_s0/COUT
2.193 0.000 tNET FF 2 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/CIN
2.233 0.040 tINS FR 1 R18C18[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n704_s0/COUT
2.233 0.000 tNET RR 2 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/CIN
2.273 0.040 tINS RR 1 R18C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n705_s0/COUT
2.273 0.000 tNET RR 2 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/CIN
2.312 0.040 tINS RR 1 R18C18[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n706_s0/COUT
2.312 0.000 tNET RR 2 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/CIN
2.352 0.040 tINS RR 1 R18C18[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n707_s0/COUT
2.352 0.000 tNET RR 2 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/CIN
2.392 0.040 tINS RR 1 R18C18[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n708_s0/COUT
3.165 0.773 tNET RR 1 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/I2
3.578 0.413 tINS RR 2 R20C20[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/consistency_match_d_s0/F
4.604 1.026 tNET RR 1 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/I0
5.002 0.398 tINS RR 2 R30C25[3][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n415_s4/F
5.006 0.004 tNET RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/I2
5.405 0.398 tINS RR 1 R30C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s3/F
5.406 0.002 tNET RR 1 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/I2
5.775 0.369 tINS RR 21 R30C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_20_s2/F
6.053 0.278 tNET RR 1 R30C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_7_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.069 0.669 tNET RR 1 R30C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_7_s0/CLK
6.820 -0.249 tSu 1 R30C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_7_s0

Path Statistics:

Clock Skew -0.052
Setup Relationship 6.400
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 2.228, 41.778%; route: 2.799, 52.485%; tC2Q: 0.306, 5.738%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.187
Data Arrival Time 0.693
Data Required Time 0.506
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_5_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.277 0.277 tNET RR 1 R12C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_5_s0/CLK
0.421 0.144 tC2Q RR 1 R12C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_5_s0/Q
0.693 0.272 tNET RR 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.291 0.291 tNET RR 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/CLKA
0.506 0.215 tHld 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.277, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 65.385%; tC2Q: 0.144, 34.615%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.291, 100.000%

Path2

Path Summary:

Slack 0.262
Data Arrival Time 0.768
Data Required Time 0.506
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_8_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.277 0.277 tNET RR 1 R12C26[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_8_s0/CLK
0.421 0.144 tC2Q RR 1 R12C26[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_8_s0/Q
0.768 0.347 tNET RR 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.291 0.291 tNET RR 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/CLKA
0.506 0.215 tHld 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.277, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.347, 70.672%; tC2Q: 0.144, 29.328%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.291, 100.000%

Path3

Path Summary:

Slack 0.277
Data Arrival Time 0.783
Data Required Time 0.506
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_9_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.277 0.277 tNET RR 1 R12C26[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_9_s0/CLK
0.421 0.144 tC2Q RR 1 R12C26[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_9_s0/Q
0.783 0.362 tNET RR 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.291 0.291 tNET RR 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/CLKA
0.506 0.215 tHld 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.277, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.291, 100.000%

Path4

Path Summary:

Slack 0.287
Data Arrival Time 0.793
Data Required Time 0.506
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_7_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.281 0.281 tNET RR 1 R13C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_7_s0/CLK
0.425 0.144 tC2Q RR 1 R13C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_7_s0/Q
0.793 0.368 tNET RR 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.291 0.291 tNET RR 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/CLKA
0.506 0.215 tHld 1 BSRAM_R10[7] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.368, 71.875%; tC2Q: 0.144, 28.125%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.291, 100.000%

Path5

Path Summary:

Slack 0.299
Data Arrival Time 0.589
Data Required Time 0.290
From u_mac_tx_model/tx_cnt_16_s1
To u_mac_tx_model/tx_cnt_16_s1
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R33C5[1][A] u_mac_tx_model/tx_cnt_16_s1/CLK
0.430 0.141 tC2Q RF 3 R33C5[1][A] u_mac_tx_model/tx_cnt_16_s1/Q
0.436 0.006 tNET FF 1 R33C5[1][A] u_mac_tx_model/n1028_s2/I3
0.589 0.153 tINS FF 1 R33C5[1][A] u_mac_tx_model/n1028_s2/F
0.589 0.000 tNET FF 1 R33C5[1][A] u_mac_tx_model/tx_cnt_16_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R33C5[1][A] u_mac_tx_model/tx_cnt_16_s1/CLK
0.290 0.001 tHld 1 R33C5[1][A] u_mac_tx_model/tx_cnt_16_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path6

Path Summary:

Slack 0.299
Data Arrival Time 0.589
Data Required Time 0.290
From u_mac_tx_model/data_increase_2_s1
To u_mac_tx_model/data_increase_2_s1
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R33C9[1][A] u_mac_tx_model/data_increase_2_s1/CLK
0.430 0.141 tC2Q RF 4 R33C9[1][A] u_mac_tx_model/data_increase_2_s1/Q
0.436 0.006 tNET FF 1 R33C9[1][A] u_mac_tx_model/n764_s0/I2
0.589 0.153 tINS FF 1 R33C9[1][A] u_mac_tx_model/n764_s0/F
0.589 0.000 tNET FF 1 R33C9[1][A] u_mac_tx_model/data_increase_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R33C9[1][A] u_mac_tx_model/data_increase_2_s1/CLK
0.290 0.001 tHld 1 R33C9[1][A] u_mac_tx_model/data_increase_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path7

Path Summary:

Slack 0.299
Data Arrival Time 0.589
Data Required Time 0.290
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R14C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5/CLK
0.430 0.141 tC2Q RF 2 R14C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5/Q
0.436 0.006 tNET FF 1 R14C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/n134_s2/I0
0.589 0.153 tINS FF 1 R14C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/n134_s2/F
0.589 0.000 tNET FF 1 R14C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R14C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5/CLK
0.290 0.001 tHld 1 R14C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_er_int_tmp_s5

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path8

Path Summary:

Slack 0.299
Data Arrival Time 0.589
Data Required Time 0.290
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_4_s3
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_4_s3
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R32C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_4_s3/CLK
0.430 0.141 tC2Q RF 2 R32C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_4_s3/Q
0.436 0.006 tNET FF 1 R32C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n1582_s3/I2
0.589 0.153 tINS FF 1 R32C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n1582_s3/F
0.589 0.000 tNET FF 1 R32C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_4_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R32C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_4_s3/CLK
0.290 0.001 tHld 1 R32C14[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_4_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path9

Path Summary:

Slack 0.299
Data Arrival Time 0.589
Data Required Time 0.290
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_6_s3
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_6_s3
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R32C14[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_6_s3/CLK
0.430 0.141 tC2Q RF 2 R32C14[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_6_s3/Q
0.436 0.006 tNET FF 1 R32C14[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n1580_s3/I2
0.589 0.153 tINS FF 1 R32C14[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n1580_s3/F
0.589 0.000 tNET FF 1 R32C14[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_6_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R32C14[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_6_s3/CLK
0.290 0.001 tHld 1 R32C14[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/gmii_txd_6_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path10

Path Summary:

Slack 0.299
Data Arrival Time 0.617
Data Required Time 0.318
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_3_s3
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_3_s3
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.317 0.317 tNET RR 1 R21C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_3_s3/CLK
0.458 0.141 tC2Q RF 2 R21C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_3_s3/Q
0.464 0.006 tNET FF 1 R21C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n387_s4/I2
0.617 0.153 tINS FF 1 R21C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n387_s4/F
0.617 0.000 tNET FF 1 R21C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_3_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.317 0.317 tNET RR 1 R21C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_3_s3/CLK
0.318 0.001 tHld 1 R21C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_3_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.317, 100.000%

Path11

Path Summary:

Slack 0.299
Data Arrival Time 0.617
Data Required Time 0.318
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_12_s3
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_12_s3
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.317 0.317 tNET RR 1 R21C4[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_12_s3/CLK
0.458 0.141 tC2Q RF 2 R21C4[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_12_s3/Q
0.464 0.006 tNET FF 1 R21C4[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n378_s4/I2
0.617 0.153 tINS FF 1 R21C4[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n378_s4/F
0.617 0.000 tNET FF 1 R21C4[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_12_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.317 0.317 tNET RR 1 R21C4[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_12_s3/CLK
0.318 0.001 tHld 1 R21C4[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_12_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.317, 100.000%

Path12

Path Summary:

Slack 0.299
Data Arrival Time 0.617
Data Required Time 0.318
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.317 0.317 tNET RR 1 R21C4[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3/CLK
0.458 0.141 tC2Q RF 2 R21C4[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3/Q
0.464 0.006 tNET FF 1 R21C4[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n372_s4/I2
0.617 0.153 tINS FF 1 R21C4[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n372_s4/F
0.617 0.000 tNET FF 1 R21C4[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.317 0.317 tNET RR 1 R21C4[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3/CLK
0.318 0.001 tHld 1 R21C4[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_18_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.317, 100.000%

Path13

Path Summary:

Slack 0.299
Data Arrival Time 0.617
Data Required Time 0.318
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_28_s3
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_28_s3
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.317 0.317 tNET RR 1 R21C8[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_28_s3/CLK
0.458 0.141 tC2Q RF 2 R21C8[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_28_s3/Q
0.464 0.006 tNET FF 1 R21C8[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n362_s4/I2
0.617 0.153 tINS FF 1 R21C8[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n362_s4/F
0.617 0.000 tNET FF 1 R21C8[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_28_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.317 0.317 tNET RR 1 R21C8[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_28_s3/CLK
0.318 0.001 tHld 1 R21C8[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_28_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.317, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.317, 100.000%

Path14

Path Summary:

Slack 0.299
Data Arrival Time 0.589
Data Required Time 0.290
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_47_s3
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_47_s3
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R32C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_47_s3/CLK
0.430 0.141 tC2Q RF 2 R32C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_47_s3/Q
0.436 0.006 tNET FF 1 R32C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n343_s4/I2
0.589 0.153 tINS FF 1 R32C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/n343_s4/F
0.589 0.000 tNET FF 1 R32C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_47_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R32C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_47_s3/CLK
0.290 0.001 tHld 1 R32C6[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_mac_tx_ctrl/tx_pause_source_addr_latch_47_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path15

Path Summary:

Slack 0.299
Data Arrival Time 0.589
Data Required Time 0.290
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_12_s1
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_12_s1
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.289 0.289 tNET RR 1 R15C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_12_s1/CLK
0.430 0.141 tC2Q RF 3 R15C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_12_s1/Q
0.436 0.006 tNET FF 1 R15C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n487_s0/I1
0.589 0.153 tINS FF 1 R15C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/n487_s0/F
0.589 0.000 tNET FF 1 R15C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_12_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.289 0.289 tNET RR 1 R15C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_12_s1/CLK
0.290 0.001 tHld 1 R15C18[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_12_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path16

Path Summary:

Slack 0.299
Data Arrival Time 0.589
Data Required Time 0.290
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.289 0.289 tNET RR 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/CLK
0.430 0.141 tC2Q RF 3 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/Q
0.436 0.006 tNET FF 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n335_s2/I3
0.589 0.153 tINS FF 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/n335_s2/F
0.589 0.000 tNET FF 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.289 0.289 tNET RR 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0/CLK
0.290 0.001 tHld 1 R32C23[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_an/link_timer_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path17

Path Summary:

Slack 0.299
Data Arrival Time 0.610
Data Required Time 0.311
From u_mac_rx_model/rx_error_all_check_s4
To u_mac_rx_model/rx_error_all_check_s4
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.310 0.310 tNET RR 1 R25C28[1][A] u_mac_rx_model/rx_error_all_check_s4/CLK
0.451 0.141 tC2Q RF 2 R25C28[1][A] u_mac_rx_model/rx_error_all_check_s4/Q
0.457 0.006 tNET FF 1 R25C28[1][A] u_mac_tx_model/n974_s10/I1
0.610 0.153 tINS FF 1 R25C28[1][A] u_mac_tx_model/n974_s10/F
0.610 0.000 tNET FF 1 R25C28[1][A] u_mac_rx_model/rx_error_all_check_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.310 0.310 tNET RR 1 R25C28[1][A] u_mac_rx_model/rx_error_all_check_s4/CLK
0.311 0.001 tHld 1 R25C28[1][A] u_mac_rx_model/rx_error_all_check_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.310, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.310, 100.000%

Path18

Path Summary:

Slack 0.299
Data Arrival Time 0.615
Data Required Time 0.316
From u_mac_rx_model/rx_error_all_data_check_s4
To u_mac_rx_model/rx_error_all_data_check_s4
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.315 0.315 tNET RR 1 R22C30[0][A] u_mac_rx_model/rx_error_all_data_check_s4/CLK
0.456 0.141 tC2Q RF 3 R22C30[0][A] u_mac_rx_model/rx_error_all_data_check_s4/Q
0.462 0.006 tNET FF 1 R22C30[0][A] u_mac_tx_model/n974_s7/I1
0.615 0.153 tINS FF 1 R22C30[0][A] u_mac_tx_model/n974_s7/F
0.615 0.000 tNET FF 1 R22C30[0][A] u_mac_rx_model/rx_error_all_data_check_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.315 0.315 tNET RR 1 R22C30[0][A] u_mac_rx_model/rx_error_all_data_check_s4/CLK
0.316 0.001 tHld 1 R22C30[0][A] u_mac_rx_model/rx_error_all_data_check_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.315, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.315, 100.000%

Path19

Path Summary:

Slack 0.299
Data Arrival Time 0.596
Data Required Time 0.297
From u_mac_rx_model/rx_data_cnt_pause_11_s1
To u_mac_rx_model/rx_data_cnt_pause_11_s1
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.296 0.296 tNET RR 1 R9C41[0][A] u_mac_rx_model/rx_data_cnt_pause_11_s1/CLK
0.437 0.141 tC2Q RF 3 R9C41[0][A] u_mac_rx_model/rx_data_cnt_pause_11_s1/Q
0.443 0.006 tNET FF 1 R9C41[0][A] u_mac_rx_model/n2143_s1/I2
0.596 0.153 tINS FF 1 R9C41[0][A] u_mac_rx_model/n2143_s1/F
0.596 0.000 tNET FF 1 R9C41[0][A] u_mac_rx_model/rx_data_cnt_pause_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.296 0.296 tNET RR 1 R9C41[0][A] u_mac_rx_model/rx_data_cnt_pause_11_s1/CLK
0.297 0.001 tHld 1 R9C41[0][A] u_mac_rx_model/rx_data_cnt_pause_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.296, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.296, 100.000%

Path20

Path Summary:

Slack 0.299
Data Arrival Time 0.600
Data Required Time 0.301
From u_mac_rx_model/pause_address_6_s1
To u_mac_rx_model/pause_address_6_s1
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.300 0.300 tNET RR 1 R9C48[1][A] u_mac_rx_model/pause_address_6_s1/CLK
0.441 0.141 tC2Q RF 3 R9C48[1][A] u_mac_rx_model/pause_address_6_s1/Q
0.447 0.006 tNET FF 1 R9C48[1][A] u_mac_rx_model/n1451_s0/I2
0.600 0.153 tINS FF 1 R9C48[1][A] u_mac_rx_model/n1451_s0/F
0.600 0.000 tNET FF 1 R9C48[1][A] u_mac_rx_model/pause_address_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.300 0.300 tNET RR 1 R9C48[1][A] u_mac_rx_model/pause_address_6_s1/CLK
0.301 0.001 tHld 1 R9C48[1][A] u_mac_rx_model/pause_address_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.300, 100.000%

Path21

Path Summary:

Slack 0.299
Data Arrival Time 0.609
Data Required Time 0.310
From u_mac_rx_model/pause_address_7_s1
To u_mac_rx_model/pause_address_7_s1
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.309 0.309 tNET RR 1 R8C55[0][A] u_mac_rx_model/pause_address_7_s1/CLK
0.450 0.141 tC2Q RF 7 R8C55[0][A] u_mac_rx_model/pause_address_7_s1/Q
0.456 0.006 tNET FF 1 R8C55[0][A] u_mac_rx_model/n1450_s0/I2
0.609 0.153 tINS FF 1 R8C55[0][A] u_mac_rx_model/n1450_s0/F
0.609 0.000 tNET FF 1 R8C55[0][A] u_mac_rx_model/pause_address_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.309 0.309 tNET RR 1 R8C55[0][A] u_mac_rx_model/pause_address_7_s1/CLK
0.310 0.001 tHld 1 R8C55[0][A] u_mac_rx_model/pause_address_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.309, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.309, 100.000%

Path22

Path Summary:

Slack 0.299
Data Arrival Time 0.613
Data Required Time 0.314
From u_mac_rx_model/pause_address_12_s1
To u_mac_rx_model/pause_address_12_s1
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.313 0.313 tNET RR 1 R5C46[0][A] u_mac_rx_model/pause_address_12_s1/CLK
0.454 0.141 tC2Q RF 6 R5C46[0][A] u_mac_rx_model/pause_address_12_s1/Q
0.461 0.006 tNET FF 1 R5C46[0][A] u_mac_rx_model/n1445_s0/I3
0.613 0.153 tINS FF 1 R5C46[0][A] u_mac_rx_model/n1445_s0/F
0.613 0.000 tNET FF 1 R5C46[0][A] u_mac_rx_model/pause_address_12_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.313 0.313 tNET RR 1 R5C46[0][A] u_mac_rx_model/pause_address_12_s1/CLK
0.314 0.001 tHld 1 R5C46[0][A] u_mac_rx_model/pause_address_12_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.313, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.313, 100.000%

Path23

Path Summary:

Slack 0.299
Data Arrival Time 0.609
Data Required Time 0.310
From u_mac_rx_model/pause_value_2_s1
To u_mac_rx_model/pause_value_2_s1
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.309 0.309 tNET RR 1 R5C57[0][A] u_mac_rx_model/pause_value_2_s1/CLK
0.450 0.141 tC2Q RF 5 R5C57[0][A] u_mac_rx_model/pause_value_2_s1/Q
0.456 0.006 tNET FF 1 R5C57[0][A] u_mac_rx_model/n1336_s0/I3
0.609 0.153 tINS FF 1 R5C57[0][A] u_mac_rx_model/n1336_s0/F
0.609 0.000 tNET FF 1 R5C57[0][A] u_mac_rx_model/pause_value_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.309 0.309 tNET RR 1 R5C57[0][A] u_mac_rx_model/pause_value_2_s1/CLK
0.310 0.001 tHld 1 R5C57[0][A] u_mac_rx_model/pause_value_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.309, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.309, 100.000%

Path24

Path Summary:

Slack 0.299
Data Arrival Time 0.600
Data Required Time 0.301
From u_mac_rx_model/pause_value_8_s1
To u_mac_rx_model/pause_value_8_s1
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.300 0.300 tNET RR 1 R9C54[1][A] u_mac_rx_model/pause_value_8_s1/CLK
0.441 0.141 tC2Q RF 6 R9C54[1][A] u_mac_rx_model/pause_value_8_s1/Q
0.447 0.006 tNET FF 1 R9C54[1][A] u_mac_rx_model/n1330_s0/I2
0.600 0.153 tINS FF 1 R9C54[1][A] u_mac_rx_model/n1330_s0/F
0.600 0.000 tNET FF 1 R9C54[1][A] u_mac_rx_model/pause_value_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.300 0.300 tNET RR 1 R9C54[1][A] u_mac_rx_model/pause_value_8_s1/CLK
0.301 0.001 tHld 1 R9C54[1][A] u_mac_rx_model/pause_value_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.300, 100.000%

Path25

Path Summary:

Slack 0.299
Data Arrival Time 0.612
Data Required Time 0.313
From u_mac_rx_model/rx_data_cnt_4_s1
To u_mac_rx_model/rx_data_cnt_4_s1
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.312 0.312 tNET RR 1 R6C34[0][A] u_mac_rx_model/rx_data_cnt_4_s1/CLK
0.453 0.141 tC2Q RF 10 R6C34[0][A] u_mac_rx_model/rx_data_cnt_4_s1/Q
0.459 0.006 tNET FF 1 R6C34[0][A] u_mac_rx_model/n1099_s1/I0
0.612 0.153 tINS FF 1 R6C34[0][A] u_mac_rx_model/n1099_s1/F
0.612 0.000 tNET FF 1 R6C34[0][A] u_mac_rx_model/rx_data_cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.312 0.312 tNET RR 1 R6C34[0][A] u_mac_rx_model/rx_data_cnt_4_s1/CLK
0.313 0.001 tHld 1 R6C34[0][A] u_mac_rx_model/rx_data_cnt_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.312, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.312, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 3.758
Data Arrival Time 3.050
Data Required Time 6.808
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_1_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
3.050 2.028 tNET FF 1 R17C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R17C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_1_s0/CLK
6.808 -0.278 tSu 1 R17C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_1_s0

Path Statistics:

Clock Skew -0.042
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.028, 87.339%; tC2Q: 0.294, 12.661%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path2

Path Summary:

Slack 3.758
Data Arrival Time 3.050
Data Required Time 6.808
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_2_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
3.050 2.028 tNET FF 1 R17C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_2_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R17C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_2_s0/CLK
6.808 -0.278 tSu 1 R17C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_2_s0

Path Statistics:

Clock Skew -0.042
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.028, 87.339%; tC2Q: 0.294, 12.661%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path3

Path Summary:

Slack 3.758
Data Arrival Time 3.050
Data Required Time 6.808
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_3_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
3.050 2.028 tNET FF 1 R17C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_3_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R17C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_3_s0/CLK
6.808 -0.278 tSu 1 R17C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_3_s0

Path Statistics:

Clock Skew -0.042
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.028, 87.339%; tC2Q: 0.294, 12.661%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path4

Path Summary:

Slack 3.758
Data Arrival Time 3.050
Data Required Time 6.808
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_4_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
3.050 2.028 tNET FF 1 R17C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_4_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R17C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_4_s0/CLK
6.808 -0.278 tSu 1 R17C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_4_s0

Path Statistics:

Clock Skew -0.042
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.028, 87.339%; tC2Q: 0.294, 12.661%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path5

Path Summary:

Slack 3.758
Data Arrival Time 3.050
Data Required Time 6.808
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_5_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
3.050 2.028 tNET FF 1 R17C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_5_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R17C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_5_s0/CLK
6.808 -0.278 tSu 1 R17C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_5_s0

Path Statistics:

Clock Skew -0.042
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.028, 87.339%; tC2Q: 0.294, 12.661%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path6

Path Summary:

Slack 3.758
Data Arrival Time 3.050
Data Required Time 6.808
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_6_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
3.050 2.028 tNET FF 1 R17C26[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.086 0.686 tNET RR 1 R17C26[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_6_s0/CLK
6.808 -0.278 tSu 1 R17C26[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_6_s0

Path Statistics:

Clock Skew -0.042
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.028, 87.339%; tC2Q: 0.294, 12.661%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.686, 100.000%

Path7

Path Summary:

Slack 3.773
Data Arrival Time 3.036
Data Required Time 6.809
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_en_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
3.036 2.014 tNET FF 1 R18C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_en_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.087 0.688 tNET RR 1 R18C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_en_s0/CLK
6.809 -0.278 tSu 1 R18C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_en_s0

Path Statistics:

Clock Skew -0.040
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.014, 87.262%; tC2Q: 0.294, 12.738%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.688, 100.000%

Path8

Path Summary:

Slack 4.012
Data Arrival Time 2.838
Data Required Time 6.850
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/gmii_align_flag_s2
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_pre_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.701 0.701 tNET RR 1 R9C11[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/gmii_align_flag_s2/CLK
0.995 0.294 tC2Q RF 4 R9C11[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/gmii_align_flag_s2/Q
2.838 1.843 tNET FF 1 R21C28[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_pre_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.128 0.728 tNET RR 1 R21C28[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_pre_s0/CLK
6.850 -0.278 tSu 1 R21C28[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_pre_s0

Path Statistics:

Clock Skew 0.027
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.843, 86.242%; tC2Q: 0.294, 13.758%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%

Path9

Path Summary:

Slack 4.012
Data Arrival Time 2.838
Data Required Time 6.850
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/gmii_align_flag_s2
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.701 0.701 tNET RR 1 R9C11[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/gmii_align_flag_s2/CLK
0.995 0.294 tC2Q RF 4 R9C11[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/gmii_align_flag_s2/Q
2.838 1.843 tNET FF 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.128 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
6.850 -0.278 tSu 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0

Path Statistics:

Clock Skew 0.027
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.843, 86.242%; tC2Q: 0.294, 13.758%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%

Path10

Path Summary:

Slack 4.079
Data Arrival Time 2.735
Data Required Time 6.814
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_0_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.735 1.713 tNET FF 1 R16C25[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.092 0.692 tNET RR 1 R16C25[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_0_s0/CLK
6.814 -0.278 tSu 1 R16C25[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_0_s0

Path Statistics:

Clock Skew -0.036
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.713, 85.351%; tC2Q: 0.294, 14.649%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.692, 100.000%

Path11

Path Summary:

Slack 4.079
Data Arrival Time 2.735
Data Required Time 6.814
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_1_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.735 1.713 tNET FF 1 R16C25[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.092 0.692 tNET RR 1 R16C25[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_1_s0/CLK
6.814 -0.278 tSu 1 R16C25[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_1_s0

Path Statistics:

Clock Skew -0.036
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.713, 85.351%; tC2Q: 0.294, 14.649%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.692, 100.000%

Path12

Path Summary:

Slack 4.378
Data Arrival Time 2.434
Data Required Time 6.812
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_2_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.434 1.412 tNET FF 1 R15C25[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.090 0.691 tNET RR 1 R15C25[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_2_s0/CLK
6.812 -0.278 tSu 1 R15C25[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_2_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.412, 82.767%; tC2Q: 0.294, 17.233%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.691, 100.000%

Path13

Path Summary:

Slack 4.378
Data Arrival Time 2.434
Data Required Time 6.812
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_6_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.434 1.412 tNET FF 1 R15C25[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.090 0.691 tNET RR 1 R15C25[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_6_s0/CLK
6.812 -0.278 tSu 1 R15C25[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_6_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.412, 82.767%; tC2Q: 0.294, 17.233%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.691, 100.000%

Path14

Path Summary:

Slack 4.383
Data Arrival Time 2.408
Data Required Time 6.791
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_0_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.408 1.386 tNET FF 1 R12C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.069 0.669 tNET RR 1 R12C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_0_s0/CLK
6.791 -0.278 tSu 1 R12C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_addr_0_s0

Path Statistics:

Clock Skew -0.059
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.386, 82.500%; tC2Q: 0.294, 17.500%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path15

Path Summary:

Slack 4.383
Data Arrival Time 2.408
Data Required Time 6.791
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_5_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.408 1.386 tNET FF 1 R12C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.069 0.669 tNET RR 1 R12C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_5_s0/CLK
6.791 -0.278 tSu 1 R12C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_5_s0

Path Statistics:

Clock Skew -0.059
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.386, 82.500%; tC2Q: 0.294, 17.500%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path16

Path Summary:

Slack 4.383
Data Arrival Time 2.408
Data Required Time 6.791
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_8_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.408 1.386 tNET FF 1 R12C26[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.069 0.669 tNET RR 1 R12C26[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_8_s0/CLK
6.791 -0.278 tSu 1 R12C26[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_8_s0

Path Statistics:

Clock Skew -0.059
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.386, 82.500%; tC2Q: 0.294, 17.500%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path17

Path Summary:

Slack 4.383
Data Arrival Time 2.408
Data Required Time 6.791
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_9_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.408 1.386 tNET FF 1 R12C26[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.069 0.669 tNET RR 1 R12C26[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_9_s0/CLK
6.791 -0.278 tSu 1 R12C26[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_9_s0

Path Statistics:

Clock Skew -0.059
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.386, 82.500%; tC2Q: 0.294, 17.500%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.669, 100.000%

Path18

Path Summary:

Slack 4.542
Data Arrival Time 2.254
Data Required Time 6.795
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_4_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.254 1.232 tNET FF 1 R13C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.073 0.674 tNET RR 1 R13C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_4_s0/CLK
6.795 -0.278 tSu 1 R13C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_4_s0

Path Statistics:

Clock Skew -0.054
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.232, 80.734%; tC2Q: 0.294, 19.266%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.674, 100.000%

Path19

Path Summary:

Slack 4.542
Data Arrival Time 2.254
Data Required Time 6.795
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_7_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.254 1.232 tNET FF 1 R13C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.073 0.674 tNET RR 1 R13C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_7_s0/CLK
6.795 -0.278 tSu 1 R13C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_7_s0

Path Statistics:

Clock Skew -0.054
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.232, 80.734%; tC2Q: 0.294, 19.266%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.674, 100.000%

Path20

Path Summary:

Slack 4.673
Data Arrival Time 2.133
Data Required Time 6.806
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_3_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.133 1.111 tNET FF 1 R16C26[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R16C26[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_3_s0/CLK
6.806 -0.278 tSu 1 R16C26[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_dat_d1_3_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.111, 79.075%; tC2Q: 0.294, 20.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path21

Path Summary:

Slack 4.673
Data Arrival Time 2.133
Data Required Time 6.806
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_0_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.133 1.111 tNET FF 1 R16C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R16C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_0_s0/CLK
6.806 -0.278 tSu 1 R16C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_0_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.111, 79.075%; tC2Q: 0.294, 20.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path22

Path Summary:

Slack 4.673
Data Arrival Time 2.133
Data Required Time 6.806
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_1_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.133 1.111 tNET FF 1 R16C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R16C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_1_s0/CLK
6.806 -0.278 tSu 1 R16C26[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_1_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.111, 79.075%; tC2Q: 0.294, 20.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path23

Path Summary:

Slack 4.673
Data Arrival Time 2.133
Data Required Time 6.806
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_2_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.133 1.111 tNET FF 1 R16C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R16C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_2_s0/CLK
6.806 -0.278 tSu 1 R16C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_2_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.111, 79.075%; tC2Q: 0.294, 20.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path24

Path Summary:

Slack 4.673
Data Arrival Time 2.133
Data Required Time 6.806
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_3_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.133 1.111 tNET FF 1 R16C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R16C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_3_s0/CLK
6.806 -0.278 tSu 1 R16C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_3_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.111, 79.075%; tC2Q: 0.294, 20.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Path25

Path Summary:

Slack 4.673
Data Arrival Time 2.133
Data Required Time 6.806
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_4_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.728 0.728 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
1.022 0.294 tC2Q RF 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
2.133 1.111 tNET FF 1 R16C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
7.084 0.684 tNET RR 1 R16C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_4_s0/CLK
6.806 -0.278 tSu 1 R16C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_occupancy_4_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.728, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.111, 79.075%; tC2Q: 0.294, 20.925%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.468
Data Arrival Time 1.213
Data Required Time 0.745
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/reset_o_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.892 0.311 tNET RR 1 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/CLK
1.036 0.144 tC2Q RR 7 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q
1.213 0.177 tNET RR 1 R6C2[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/reset_o_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.896 0.315 tNET RR 1 R6C2[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/reset_o_s0/CLK
0.745 -0.151 tHld 1 R6C2[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/reset_o_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 65.150%; route: 0.311, 34.850%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.177, 55.140%; tC2Q: 0.144, 44.860%
Required Clock Path Delay cell: 0.581, 64.859%; route: 0.315, 35.141%

Path2

Path Summary:

Slack 0.468
Data Arrival Time 1.213
Data Required Time 0.745
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/resetn_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.892 0.311 tNET RR 1 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/CLK
1.036 0.144 tC2Q RR 7 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q
1.213 0.177 tNET RR 1 R6C2[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/resetn_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.896 0.315 tNET RR 1 R6C2[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/resetn_s0/CLK
0.745 -0.151 tHld 1 R6C2[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/resetn_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 65.150%; route: 0.311, 34.850%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.177, 55.140%; tC2Q: 0.144, 44.860%
Required Clock Path Delay cell: 0.581, 64.859%; route: 0.315, 35.141%

Path3

Path Summary:

Slack 0.486
Data Arrival Time 0.620
Data Required Time 0.134
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_5_s0
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.281 0.281 tNET RR 1 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/CLK
0.425 0.144 tC2Q RR 40 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q
0.620 0.195 tNET RR 1 R14C25[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.285 0.285 tNET RR 1 R14C25[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_5_s0/CLK
0.134 -0.151 tHld 1 R14C25[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_5_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.285, 100.000%

Path4

Path Summary:

Slack 0.486
Data Arrival Time 0.620
Data Required Time 0.134
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_9_s0
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.281 0.281 tNET RR 1 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/CLK
0.425 0.144 tC2Q RR 40 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q
0.620 0.195 tNET RR 1 R14C25[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.285 0.285 tNET RR 1 R14C25[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_9_s0/CLK
0.134 -0.151 tHld 1 R14C25[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_9_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.285, 100.000%

Path5

Path Summary:

Slack 0.496
Data Arrival Time 0.664
Data Required Time 0.168
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_0_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.664 0.199 tNET RR 1 R22C28[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.319 0.319 tNET RR 1 R22C28[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_0_s0/CLK
0.168 -0.151 tHld 1 R22C28[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_0_s0

Path Statistics:

Clock Skew -0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.199, 58.017%; tC2Q: 0.144, 41.983%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.319, 100.000%

Path6

Path Summary:

Slack 0.496
Data Arrival Time 0.664
Data Required Time 0.168
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_1_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.664 0.199 tNET RR 1 R22C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.319 0.319 tNET RR 1 R22C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_1_s0/CLK
0.168 -0.151 tHld 1 R22C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/check_wr_i2_cnt_1_s0

Path Statistics:

Clock Skew -0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.199, 58.017%; tC2Q: 0.144, 41.983%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.319, 100.000%

Path7

Path Summary:

Slack 0.500
Data Arrival Time 0.666
Data Required Time 0.166
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_4_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.666 0.201 tNET RR 1 R21C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.317 0.317 tNET RR 1 R21C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_4_s0/CLK
0.166 -0.151 tHld 1 R21C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_4_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.317, 100.000%

Path8

Path Summary:

Slack 0.502
Data Arrival Time 0.666
Data Required Time 0.164
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_6_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.666 0.201 tNET RR 1 R22C27[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.315 0.315 tNET RR 1 R22C27[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_6_s0/CLK
0.164 -0.151 tHld 1 R22C27[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_6_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.315, 100.000%

Path9

Path Summary:

Slack 0.503
Data Arrival Time 0.666
Data Required Time 0.162
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_0_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.666 0.201 tNET RR 1 R23C27[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.313 0.313 tNET RR 1 R23C27[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_0_s0/CLK
0.162 -0.151 tHld 1 R23C27[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_0_s0

Path Statistics:

Clock Skew -0.007
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.313, 100.000%

Path10

Path Summary:

Slack 0.503
Data Arrival Time 0.666
Data Required Time 0.162
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_2_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.666 0.201 tNET RR 1 R23C27[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.313 0.313 tNET RR 1 R23C27[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_2_s0/CLK
0.162 -0.151 tHld 1 R23C27[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_2_s0

Path Statistics:

Clock Skew -0.007
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.313, 100.000%

Path11

Path Summary:

Slack 0.504
Data Arrival Time 0.664
Data Required Time 0.160
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_4_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.664 0.199 tNET RR 1 R22C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.311 0.311 tNET RR 1 R22C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_4_s0/CLK
0.160 -0.151 tHld 1 R22C26[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_4_s0

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.199, 58.017%; tC2Q: 0.144, 41.983%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.311, 100.000%

Path12

Path Summary:

Slack 0.504
Data Arrival Time 0.666
Data Required Time 0.162
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_2_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.666 0.201 tNET RR 1 R21C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.313 0.313 tNET RR 1 R21C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_2_s0/CLK
0.162 -0.151 tHld 1 R21C26[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_2_s0

Path Statistics:

Clock Skew -0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.313, 100.000%

Path13

Path Summary:

Slack 0.504
Data Arrival Time 0.666
Data Required Time 0.162
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_6_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.666 0.201 tNET RR 1 R21C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.313 0.313 tNET RR 1 R21C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_6_s0/CLK
0.162 -0.151 tHld 1 R21C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_6_s0

Path Statistics:

Clock Skew -0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.313, 100.000%

Path14

Path Summary:

Slack 0.521
Data Arrival Time 0.660
Data Required Time 0.139
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_wr_addr_gray_tmp_4_s0
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.281 0.281 tNET RR 1 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/CLK
0.425 0.144 tC2Q RR 40 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q
0.660 0.235 tNET RR 1 R11C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_wr_addr_gray_tmp_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.290 0.290 tNET RR 1 R11C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_wr_addr_gray_tmp_4_s0/CLK
0.139 -0.151 tHld 1 R11C26[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_wr_addr_gray_tmp_4_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.235, 62.005%; tC2Q: 0.144, 37.995%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.290, 100.000%

Path15

Path Summary:

Slack 0.535
Data Arrival Time 0.703
Data Required Time 0.168
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_0_s0
Launch Clk clk_os:[R]
Latch Clk clk_os:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.321 0.321 tNET RR 1 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/CLK
0.465 0.144 tC2Q RR 41 R21C28[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_wr_s0/Q
0.703 0.238 tNET RR 1 R20C27[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR 770 LEFTSIDE[0] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.319 0.319 tNET RR 1 R20C27[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_0_s0/CLK
0.168 -0.151 tHld 1 R20C27[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/wr_rd_addr_gray_tmp_0_s0

Path Statistics:

Clock Skew -0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.321, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 62.304%; tC2Q: 0.144, 37.696%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.319, 100.000%

Path16

Path Summary:

Slack 0.569
Data Arrival Time 1.308
Data Required Time 0.739
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_0_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.892 0.311 tNET RR 1 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/CLK
1.036 0.144 tC2Q RR 7 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q
1.308 0.272 tNET RR 1 R7C3[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.890 0.309 tNET RR 1 R7C3[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_0_s0/CLK
0.739 -0.151 tHld 1 R7C3[1][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_0_s0

Path Statistics:

Clock Skew -0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 65.150%; route: 0.311, 34.850%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 65.385%; tC2Q: 0.144, 34.615%
Required Clock Path Delay cell: 0.581, 65.278%; route: 0.309, 34.722%

Path17

Path Summary:

Slack 0.569
Data Arrival Time 1.308
Data Required Time 0.739
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_1_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.892 0.311 tNET RR 1 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/CLK
1.036 0.144 tC2Q RR 7 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q
1.308 0.272 tNET RR 1 R7C3[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.890 0.309 tNET RR 1 R7C3[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_1_s0/CLK
0.739 -0.151 tHld 1 R7C3[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_1_s0

Path Statistics:

Clock Skew -0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 65.150%; route: 0.311, 34.850%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 65.385%; tC2Q: 0.144, 34.615%
Required Clock Path Delay cell: 0.581, 65.278%; route: 0.309, 34.722%

Path18

Path Summary:

Slack 0.569
Data Arrival Time 1.308
Data Required Time 0.739
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_2_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.892 0.311 tNET RR 1 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/CLK
1.036 0.144 tC2Q RR 7 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q
1.308 0.272 tNET RR 1 R7C3[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.890 0.309 tNET RR 1 R7C3[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_2_s0/CLK
0.739 -0.151 tHld 1 R7C3[0][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_2_s0

Path Statistics:

Clock Skew -0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 65.150%; route: 0.311, 34.850%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 65.385%; tC2Q: 0.144, 34.615%
Required Clock Path Delay cell: 0.581, 65.278%; route: 0.309, 34.722%

Path19

Path Summary:

Slack 0.569
Data Arrival Time 1.308
Data Required Time 0.739
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_3_s0
Launch Clk board_clk:[R]
Latch Clk board_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.892 0.311 tNET RR 1 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/CLK
1.036 0.144 tC2Q RR 7 R6C3[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/rst_n_s0/Q
1.308 0.272 tNET RR 1 R7C3[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 board_clk
0.000 0.000 tCL RR 1 IOB29[A] board_clk_ibuf/I
0.581 0.581 tINS RR 33 IOB29[A] board_clk_ibuf/O
0.890 0.309 tNET RR 1 R7C3[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_3_s0/CLK
0.739 -0.151 tHld 1 R7C3[0][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/delay_cnt_3_s0

Path Statistics:

Clock Skew -0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 65.150%; route: 0.311, 34.850%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 65.385%; tC2Q: 0.144, 34.615%
Required Clock Path Delay cell: 0.581, 65.278%; route: 0.309, 34.722%

Path20

Path Summary:

Slack 0.580
Data Arrival Time 0.718
Data Required Time 0.138
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_3_s0
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.281 0.281 tNET RR 1 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/CLK
0.425 0.144 tC2Q RR 40 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q
0.718 0.293 tNET RR 1 R15C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R15C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_3_s0/CLK
0.138 -0.151 tHld 1 R15C25[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_3_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.293, 67.048%; tC2Q: 0.144, 32.952%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path21

Path Summary:

Slack 0.580
Data Arrival Time 0.718
Data Required Time 0.138
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_4_s0
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.281 0.281 tNET RR 1 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/CLK
0.425 0.144 tC2Q RR 40 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q
0.718 0.293 tNET RR 1 R15C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R15C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_4_s0/CLK
0.138 -0.151 tHld 1 R15C25[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_4_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.293, 67.048%; tC2Q: 0.144, 32.952%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path22

Path Summary:

Slack 0.580
Data Arrival Time 0.718
Data Required Time 0.138
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_8_s0
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.281 0.281 tNET RR 1 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/CLK
0.425 0.144 tC2Q RR 40 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q
0.718 0.293 tNET RR 1 R15C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.289 0.289 tNET RR 1 R15C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_8_s0/CLK
0.138 -0.151 tHld 1 R15C25[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_8_s0

Path Statistics:

Clock Skew 0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.293, 67.048%; tC2Q: 0.144, 32.952%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.289, 100.000%

Path23

Path Summary:

Slack 0.580
Data Arrival Time 0.722
Data Required Time 0.142
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d1_0_s3
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.281 0.281 tNET RR 1 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/CLK
0.425 0.144 tC2Q RR 40 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q
0.722 0.297 tNET RR 1 R14C27[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d1_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.293 0.293 tNET RR 1 R14C27[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d1_0_s3/CLK
0.142 -0.151 tHld 1 R14C27[3][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d1_0_s3

Path Statistics:

Clock Skew 0.012
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.297, 67.347%; tC2Q: 0.144, 32.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.293, 100.000%

Path24

Path Summary:

Slack 0.580
Data Arrival Time 0.722
Data Required Time 0.142
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_2_s0
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.281 0.281 tNET RR 1 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/CLK
0.425 0.144 tC2Q RR 40 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q
0.722 0.297 tNET RR 1 R14C27[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.293 0.293 tNET RR 1 R14C27[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_2_s0/CLK
0.142 -0.151 tHld 1 R14C27[2][B] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_2_s0

Path Statistics:

Clock Skew 0.012
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.297, 67.347%; tC2Q: 0.144, 32.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.293, 100.000%

Path25

Path Summary:

Slack 0.580
Data Arrival Time 0.722
Data Required Time 0.142
From u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0
To u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_6_s0
Launch Clk clk_mac:[R]
Latch Clk clk_mac:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.281 0.281 tNET RR 1 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/CLK
0.425 0.144 tC2Q RR 40 R12C26[1][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rst_n_rd_s0/Q
0.722 0.297 tNET RR 1 R14C27[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_mac
0.000 0.000 tCL RR 2398 PLL_T u_pll_hclk/PLLA_inst/CLKOUT4
0.293 0.293 tNET RR 1 R14C27[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_6_s0/CLK
0.142 -0.151 tHld 1 R14C27[2][A] u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/rd_dat_d2_6_s0

Path Statistics:

Clock Skew 0.012
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.281, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.297, 67.347%; tC2Q: 0.144, 32.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.293, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 1.944
Actual Width: 2.806
Required Width: 0.862
Type: Low Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.885 0.685 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
6.691 0.291 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack: 1.946
Actual Width: 2.808
Required Width: 0.862
Type: High Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_os
0.000 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
0.688 0.688 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.496 0.296 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_rx_elastic_buffer/mem_mem_0_0_s/CLKA

MPW3

MPW Summary:

Slack: 2.594
Actual Width: 2.794
Required Width: 0.200
Type: Low Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_30_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.928 0.728 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_30_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
6.723 0.323 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_30_s0/CLK

MPW4

MPW Summary:

Slack: 2.594
Actual Width: 2.794
Required Width: 0.200
Type: Low Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_27_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.928 0.728 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_27_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
6.723 0.323 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_27_s0/CLK

MPW5

MPW Summary:

Slack: 2.594
Actual Width: 2.794
Required Width: 0.200
Type: Low Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.928 0.728 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
6.723 0.323 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/ID_24_s0/CLK

MPW6

MPW Summary:

Slack: 2.594
Actual Width: 2.794
Required Width: 0.200
Type: Low Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d1_14_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.928 0.728 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d1_14_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
6.723 0.323 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d1_14_s1/CLK

MPW7

MPW Summary:

Slack: 2.594
Actual Width: 2.794
Required Width: 0.200
Type: Low Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_14_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.928 0.728 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_14_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
6.723 0.323 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/rx_config_d2_14_s1/CLK

MPW8

MPW Summary:

Slack: 2.594
Actual Width: 2.794
Required Width: 0.200
Type: Low Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/ability_matched_reg_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.928 0.728 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/ability_matched_reg_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
6.723 0.323 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/ability_matched_reg_6_s0/CLK

MPW9

MPW Summary:

Slack: 2.594
Actual Width: 2.794
Required Width: 0.200
Type: Low Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/acknowledge_match_s2

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.928 0.728 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/acknowledge_match_s2/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
6.723 0.323 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_ge_pcs/u_ge_rx/acknowledge_match_s2/CLK

MPW10

MPW Summary:

Slack: 2.594
Actual Width: 2.794
Required Width: 0.200
Type: Low Pulse Width
Clock: clk_os
Objects: u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/IDD_30_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 clk_os
3.200 0.000 tCL FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
3.928 0.728 tNET FF u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/IDD_30_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 clk_os
6.400 0.000 tCL RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT
6.723 0.323 tNET RR u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_os_pma_pcs_rx/u_cdr/IDD_30_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
2398 tx_mac_clk 2.025 0.730
2004 clk_uart 88.441 0.730
955 rstn_uart 94.630 2.052
770 share_clk4_o 0.604 0.730
196 rd_ptr[2] 96.026 2.190
192 rd_ptr[2] 95.491 1.595
162 rx_pause_state 5.436 1.769
150 rx_mac_valid_d3 4.857 2.042
134 uart_addr[4] 90.554 2.727
125 latch_data_end 5.195 2.052

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R24C32 58.33%
R23C32 54.17%
R22C32 51.39%
R22C35 51.39%
R33C19 50.00%
R21C23 50.00%
R23C33 50.00%
R20C23 47.22%
R33C20 47.22%
R26C38 47.22%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name board_clk -period 20 -waveform {0 10} [get_pins {board_clk_ibuf/I}]
TC_GENERATED_CLOCK Actived create_generated_clock -name hclk -source [get_pins {board_clk_ibuf/I}] -master_clock board_clk -divide_by 2 -multiply_by 25 [get_pins {u_pll_hclk/PLLA_inst/CLKOUT0}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk_mac -source [get_pins {board_clk_ibuf/I}] -master_clock board_clk -divide_by 10 -multiply_by 25 [get_pins {u_pll_hclk/PLLA_inst/CLKOUT4}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk_uart -source [get_pins {board_clk_ibuf/I}] -master_clock board_clk -divide_by 80 -multiply_by 16 [get_pins {u_pll_uart/PLLA_inst/CLKOUT0}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk_os -source [get_pins {u_pll_hclk/PLLA_inst/CLKOUT0}] -master_clock hclk -divide_by 4 -multiply_by 1 [get_pins {u_giga_serial_ethernet_lvds_top/u_giga_serial_ethernet/u_share_logic/clkdiv_inst/CLKOUT}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {board_clk clk_uart clk_mac}] -to [get_clocks {clk_os}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_uart clk_os board_clk}] -to [get_clocks {clk_mac}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_mac clk_os}] -to [get_clocks {clk_uart}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {board_clk}] -to [get_clocks {hclk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_uart}] -to [get_clocks {board_clk}]