Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\button.v
E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\mac_rx_model_word.v
E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\mac_tx_model_word.v
E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\pll_uart\pll_uart.v
E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\serdes\serdes.v
E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\serdes\two_giga_serial_ethernet\two_giga_serial_ethernet.v
E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\sysreg.v
E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\top.v
E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\uart_to_bus\uart_to_bus.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Tue Aug 15 14:00:21 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 161.605MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.214s, Peak memory usage = 161.605MB
    Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.18s, Peak memory usage = 161.605MB
    Optimizing Phase 2: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.357s, Peak memory usage = 161.605MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.128s, Peak memory usage = 161.605MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 161.605MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 161.605MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 161.605MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.606s, Peak memory usage = 161.605MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 161.605MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 161.605MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 163.387MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.383s, Peak memory usage = 163.387MB
Generate output files:
    CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.371s, Peak memory usage = 167.195MB
Total Time and Memory Usage CPU time = 0h 0m 8s, Elapsed time = 0h 0m 9s, Peak memory usage = 167.195MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 9
I/O Buf 8
    IBUF 2
    OBUF 5
    TLVDS_IBUF 1
Register 4435
    DFFSE 6
    DFFRE 145
    DFFPE 159
    DFFCE 4125
LUT 4341
    LUT2 615
    LUT3 1211
    LUT4 2515
ALU 389
    ALU 389
SSRAM 35
    RAM16S4 10
    RAM16SDP4 25
INV 35
    INV 35
CLOCK 2
    PLL 1
    OSC 1
GTR12_QUAD 1

Resource Utilization Summary

Resource Usage Utilization
Logic 4975(4376 LUT, 389 ALU, 35 RAM16) / 138240 4%
Register 4435 / 139140 4%
  --Register as Latch 0 / 139140 0%
  --Register as FF 4435 / 139140 4%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
u_osc/OSCOUT.default_clk Base 19.048 52.5 0.000 9.524 u_osc/OSCOUT
board_clk_p Base 5.000 200.0 0.000 2.500 u_board_clk/I
u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk Generated 100.000 10.0 0.000 50.000 u_board_clk/I board_clk_p u_pll_uart/PLL_inst/CLKOUT0

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_osc/OSCOUT.default_clk 52.5(MHz) 503.5(MHz) 3 TOP
2 u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk 10.0(MHz) 147.0(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.061
Data Arrival Time 98.877
Data Required Time 100.938
From uart1/bout_s0
To u_sysreg/uart_rdata_5_s0
Launch Clk u_osc/OSCOUT.default_clk[R]
Latch Clk u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
95.238 0.000 u_osc/OSCOUT.default_clk
95.238 0.000 tCL RR 32 u_osc/OSCOUT
95.418 0.180 tNET RR 1 uart1/bout_s0/CLK
95.650 0.232 tC2Q RF 2 uart1/bout_s0/Q
95.887 0.237 tNET FF 1 rstn_ip_s0/I1
96.442 0.555 tINS FF 2 rstn_ip_s0/F
96.679 0.237 tNET FF 1 u_sysreg/n1787_s41/I0
97.196 0.517 tINS FF 1 u_sysreg/n1787_s41/F
97.433 0.237 tNET FF 1 u_sysreg/n1787_s36/I2
97.886 0.453 tINS FF 1 u_sysreg/n1787_s36/F
98.123 0.237 tNET FF 1 u_sysreg/n1787_s35/I0
98.640 0.517 tINS FF 1 u_sysreg/n1787_s35/F
98.877 0.237 tNET FF 1 u_sysreg/uart_rdata_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
100.000 0.000 u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk
100.828 0.829 tCL RR 1248 u_pll_uart/PLL_inst/CLKOUT0
101.008 0.180 tNET RR 1 u_sysreg/uart_rdata_5_s0/CLK
100.973 -0.035 tUnc u_sysreg/uart_rdata_5_s0
100.938 -0.035 tSu 1 u_sysreg/uart_rdata_5_s0
Path Statistics:
Clock Skew: 0.829
Setup Relationship: 4.762
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 2.042, 59.035%; route: 1.185, 34.258%; tC2Q: 0.232, 6.707%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 2

Path Summary:
Slack 3.394
Data Arrival Time 301.478
Data Required Time 304.872
From u_sysreg/reg0x0030_0_s0
To uart1/temp_0_s0
Launch Clk u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk[R]
Latch Clk u_osc/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
300.000 0.000 u_pll_uart/PLL_inst/CLKOUT0.default_gen_clk
300.828 0.829 tCL RR 1248 u_pll_uart/PLL_inst/CLKOUT0
301.009 0.180 tNET RR 1 u_sysreg/reg0x0030_0_s0/CLK
301.241 0.232 tC2Q RF 2 u_sysreg/reg0x0030_0_s0/Q
301.478 0.237 tNET FF 1 uart1/temp_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
304.762 0.000 u_osc/OSCOUT.default_clk
304.762 0.000 tCL RR 32 u_osc/OSCOUT
304.942 0.180 tNET RR 1 uart1/temp_0_s0/CLK
304.907 -0.035 tUnc uart1/temp_0_s0
304.872 -0.035 tSu 1 uart1/temp_0_s0
Path Statistics:
Clock Skew: -0.829
Setup Relationship: 4.762
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 3

Path Summary:
Slack 17.062
Data Arrival Time 2.131
Data Required Time 19.193
From uart1/temp_7_s0
To uart1/bout_s0
Launch Clk u_osc/OSCOUT.default_clk[R]
Latch Clk u_osc/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_osc/OSCOUT.default_clk
0.000 0.000 tCL RR 32 u_osc/OSCOUT
0.180 0.180 tNET RR 1 uart1/temp_7_s0/CLK
0.412 0.232 tC2Q RF 2 uart1/temp_7_s0/Q
0.649 0.237 tNET FF 1 uart1/n5_s1/I1
1.204 0.555 tINS FF 1 uart1/n5_s1/F
1.441 0.237 tNET FF 1 uart1/n5_s0/I2
1.894 0.453 tINS FF 1 uart1/n5_s0/F
2.131 0.237 tNET FF 1 uart1/bout_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
19.048 0.000 u_osc/OSCOUT.default_clk
19.048 0.000 tCL RR 32 u_osc/OSCOUT
19.228 0.180 tNET RR 1 uart1/bout_s0/CLK
19.193 -0.035 tSu 1 uart1/bout_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 19.048
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 1.008, 51.666%; route: 0.711, 36.443%; tC2Q: 0.232, 11.891%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 4

Path Summary:
Slack 17.062
Data Arrival Time 2.131
Data Required Time 19.193
From sw1/temp_7_s0
To sw1/bout_s0
Launch Clk u_osc/OSCOUT.default_clk[R]
Latch Clk u_osc/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_osc/OSCOUT.default_clk
0.000 0.000 tCL RR 32 u_osc/OSCOUT
0.180 0.180 tNET RR 1 sw1/temp_7_s0/CLK
0.412 0.232 tC2Q RF 2 sw1/temp_7_s0/Q
0.649 0.237 tNET FF 1 sw1/n5_s1/I1
1.204 0.555 tINS FF 1 sw1/n5_s1/F
1.441 0.237 tNET FF 1 sw1/n5_s0/I2
1.894 0.453 tINS FF 1 sw1/n5_s0/F
2.131 0.237 tNET FF 1 sw1/bout_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
19.048 0.000 u_osc/OSCOUT.default_clk
19.048 0.000 tCL RR 32 u_osc/OSCOUT
19.228 0.180 tNET RR 1 sw1/bout_s0/CLK
19.193 -0.035 tSu 1 sw1/bout_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 19.048
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 1.008, 51.666%; route: 0.711, 36.443%; tC2Q: 0.232, 11.891%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 5

Path Summary:
Slack 17.752
Data Arrival Time 1.441
Data Required Time 19.193
From uart1/bout_s0
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_s0
Launch Clk u_osc/OSCOUT.default_clk[R]
Latch Clk u_osc/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_osc/OSCOUT.default_clk
0.000 0.000 tCL RR 32 u_osc/OSCOUT
0.180 0.180 tNET RR 1 uart1/bout_s0/CLK
0.412 0.232 tC2Q RF 2 uart1/bout_s0/Q
0.649 0.237 tNET FF 1 rstn_ip_s0/I1
1.204 0.555 tINS FF 2 rstn_ip_s0/F
1.441 0.237 tNET FF 1 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
19.048 0.000 u_osc/OSCOUT.default_clk
19.048 0.000 tCL RR 32 u_osc/OSCOUT
19.228 0.180 tNET RR 1 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_s0/CLK
19.193 -0.035 tSu 1 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/ge_pcs_rstn_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 19.048
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.555, 44.013%; route: 0.474, 37.589%; tC2Q: 0.232, 18.398%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%