Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-3 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Mon Jul 24 16:39:09 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Uart_to_Bus_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.584s, Peak memory usage = 49.000MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 49.000MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 49.000MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 49.000MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 49.000MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 49.000MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 49.000MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 49.000MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 49.000MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 49.000MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 49.000MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 49.000MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 60.816MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 60.816MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 60.816MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 60.816MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 90 |
I/O Buf | 90 |
    IBUF | 37 |
    OBUF | 53 |
Register | 656 |
    DFFRE | 9 |
    DFFPE | 9 |
    DFFCE | 638 |
LUT | 505 |
    LUT2 | 125 |
    LUT3 | 148 |
    LUT4 | 232 |
ALU | 40 |
    ALU | 40 |
SSRAM | 25 |
    RAM16SDP4 | 25 |
INV | 11 |
    INV | 11 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 706(516 LUTs, 40 ALUs, 25 SSRAMs) / 138240 | <1% |
Register | 656 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 656 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_i_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_i | 100.0(MHz) | 194.0(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.846 |
Data Arrival Time | 5.981 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 32 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_3_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_3_s5/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s67/I1 |
2.679 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s67/F |
2.916 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s58/I2 |
3.369 | 0.453 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s58/F |
3.606 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s53/I1 |
4.161 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s53/F |
4.398 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/I1 |
4.952 | 0.555 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/F |
5.189 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n260_s44/I1 |
5.744 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n260_s44/F |
5.981 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.228, 63.059%; route: 1.659, 32.409%; tC2Q: 0.232, 4.532% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 4.846 |
Data Arrival Time | 5.981 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 32 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_3_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_3_s5/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s67/I1 |
2.679 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s67/F |
2.916 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s58/I2 |
3.369 | 0.453 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s58/F |
3.606 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s53/I1 |
4.161 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s53/F |
4.398 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/I1 |
4.952 | 0.555 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/F |
5.189 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n259_s43/I1 |
5.744 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n259_s43/F |
5.981 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.228, 63.059%; route: 1.659, 32.409%; tC2Q: 0.232, 4.532% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 4.948 |
Data Arrival Time | 5.879 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1/CLK |
1.095 | 0.232 | tC2Q | RF | 32 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_2_s1/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_3_s5/I1 |
1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/fsm_st_curr_3_s5/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s67/I1 |
2.679 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s67/F |
2.916 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s58/I2 |
3.369 | 0.453 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s58/F |
3.606 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s53/I1 |
4.161 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s53/F |
4.398 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/I1 |
4.952 | 0.555 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s49/F |
5.189 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s46/I2 |
5.642 | 0.453 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s46/F |
5.879 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.126, 62.308%; route: 1.659, 33.068%; tC2Q: 0.232, 4.624% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 4.986 |
Data Arrival Time | 5.842 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 11 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/uart_tx_led_o_d_s0/I1 |
1.887 | 0.555 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/uart_tx_led_o_d_s0/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n251_s48/I2 |
2.577 | 0.453 | tINS | FF | 12 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n251_s48/F |
2.814 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s46/I1 |
3.369 | 0.555 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s46/F |
3.606 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s48/I1 |
4.161 | 0.555 | tINS | FF | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s48/F |
4.398 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s46/I0 |
4.915 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s46/F |
5.152 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s43/I2 |
5.605 | 0.453 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s43/F |
5.842 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 4.986 |
Data Arrival Time | 5.842 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 11 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/uart_tx_led_o_d_s0/I1 |
1.887 | 0.555 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/uart_tx_led_o_d_s0/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n251_s48/I2 |
2.577 | 0.453 | tINS | FF | 12 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n251_s48/F |
2.814 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s46/I1 |
3.369 | 0.555 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s46/F |
3.606 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s48/I1 |
4.161 | 0.555 | tINS | FF | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s48/F |
4.398 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s47/I0 |
4.915 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s47/F |
5.152 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s45/I2 |
5.605 | 0.453 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s45/F |
5.842 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 681 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |