Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\SERDES_IP\IPlib\25GSERETH\data\ge_pcs.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\SERDES_IP\IPlib\25GSERETH\data\ge_pcs_wrap.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Tue Aug 15 13:59:53 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Two_Giga_Serial_Ethernet_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.836s, Peak memory usage = 56.484MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 56.484MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.202s, Peak memory usage = 56.484MB
    Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 56.484MB
    Optimizing Phase 2: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.361s, Peak memory usage = 56.484MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 56.484MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 56.484MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 56.484MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 56.484MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.381s, Peak memory usage = 56.484MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 56.484MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 56.484MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 71.125MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.365s, Peak memory usage = 71.125MB
Generate output files:
    CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.388s, Peak memory usage = 71.125MB
Total Time and Memory Usage CPU time = 0h 0m 15s, Elapsed time = 0h 0m 15s, Peak memory usage = 71.125MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 457
I/O Buf 455
    IBUF 194
    OBUF 261
Register 2247
    DFFSE 6
    DFFRE 98
    DFFPE 86
    DFFCE 2057
LUT 2421
    LUT2 392
    LUT3 572
    LUT4 1457
ALU 83
    ALU 83
SSRAM 10
    RAM16S4 10
INV 16
    INV 16

Resource Utilization Summary

Resource Usage Utilization
Logic 2580(2437 LUT, 83 ALU, 10 RAM16) / 138240 2%
Register 2247 / 139140 2%
  --Register as Latch 0 / 139140 0%
  --Register as FF 2247 / 139140 2%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
serdes_pcs_tx_clk_i Base 10.000 100.0 0.000 5.000 serdes_pcs_tx_clk_i_ibuf/I
serdes_pcs_rx_clk_i Base 10.000 100.0 0.000 5.000 serdes_pcs_rx_clk_i_ibuf/I
clk_in_i Base 10.000 100.0 0.000 5.000 clk_in_i_ibuf/I
miim_hs_clk_i Base 10.000 100.0 0.000 5.000 miim_hs_clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 serdes_pcs_tx_clk_i 100.0(MHz) 225.9(MHz) 6 TOP
2 serdes_pcs_rx_clk_i 100.0(MHz) 224.0(MHz) 6 TOP
3 clk_in_i 100.0(MHz) 1984.1(MHz) 1 TOP
4 miim_hs_clk_i 100.0(MHz) 241.5(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From u_ge_pcs/u_mac_rx_ctrl/vlan_reg_2_s1
To u_ge_pcs/u_mac_rx_ctrl/rx_lgt_err_s0
Launch Clk serdes_pcs_rx_clk_i[R]
Latch Clk serdes_pcs_rx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_rx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
0.683 0.683 tINS RR 1167 serdes_pcs_rx_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_ge_pcs/u_mac_rx_ctrl/vlan_reg_2_s1/CLK
1.095 0.232 tC2Q RF 2 u_ge_pcs/u_mac_rx_ctrl/vlan_reg_2_s1/Q
1.332 0.237 tNET FF 1 u_ge_pcs/u_mac_rx_ctrl/n1571_s4/I1
1.887 0.555 tINS FF 1 u_ge_pcs/u_mac_rx_ctrl/n1571_s4/F
2.124 0.237 tNET FF 1 u_ge_pcs/u_mac_rx_ctrl/n1571_s2/I1
2.679 0.555 tINS FF 2 u_ge_pcs/u_mac_rx_ctrl/n1571_s2/F
2.916 0.237 tNET FF 1 u_ge_pcs/u_mac_rx_ctrl/n1486_s4/I1
3.471 0.555 tINS FF 1 u_ge_pcs/u_mac_rx_ctrl/n1486_s4/F
3.708 0.237 tNET FF 1 u_ge_pcs/u_mac_rx_ctrl/n1486_s2/I1
4.263 0.555 tINS FF 1 u_ge_pcs/u_mac_rx_ctrl/n1486_s2/F
4.500 0.237 tNET FF 1 u_ge_pcs/u_mac_rx_ctrl/n1486_s1/I1
5.055 0.555 tINS FF 1 u_ge_pcs/u_mac_rx_ctrl/n1486_s1/F
5.292 0.237 tNET FF 1 u_ge_pcs/u_mac_rx_ctrl/rx_lgt_err_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_rx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
10.682 0.683 tINS RR 1167 serdes_pcs_rx_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_ge_pcs/u_mac_rx_ctrl/rx_lgt_err_s0/CLK
10.828 -0.035 tSu 1 u_ge_pcs/u_mac_rx_ctrl/rx_lgt_err_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 5.574
Data Arrival Time 5.253
Data Required Time 10.828
From u_ge_pcs/u_ge_rx/c_state_d1_0_s0
To u_ge_pcs/u_ge_rx/gmii_rxd_m_set_h_s0
Launch Clk serdes_pcs_rx_clk_i[R]
Latch Clk serdes_pcs_rx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_rx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
0.683 0.683 tINS RR 1167 serdes_pcs_rx_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_ge_pcs/u_ge_rx/c_state_d1_0_s0/CLK
1.095 0.232 tC2Q RF 22 u_ge_pcs/u_ge_rx/c_state_d1_0_s0/Q
1.332 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n2191_s9/I1
1.887 0.555 tINS FF 1 u_ge_pcs/u_ge_rx/n2191_s9/F
2.124 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n2191_s5/I0
2.641 0.517 tINS FF 4 u_ge_pcs/u_ge_rx/n2191_s5/F
2.878 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n2150_s11/I1
3.433 0.555 tINS FF 3 u_ge_pcs/u_ge_rx/n2150_s11/F
3.670 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n2171_s9/I1
4.225 0.555 tINS FF 1 u_ge_pcs/u_ge_rx/n2171_s9/F
4.462 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n2171_s8/I1
5.016 0.555 tINS FF 1 u_ge_pcs/u_ge_rx/n2171_s8/F
5.253 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/gmii_rxd_m_set_h_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_rx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
10.682 0.683 tINS RR 1167 serdes_pcs_rx_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_ge_pcs/u_ge_rx/gmii_rxd_m_set_h_s0/CLK
10.828 -0.035 tSu 1 u_ge_pcs/u_ge_rx/gmii_rxd_m_set_h_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.737, 62.332%; route: 1.422, 32.384%; tC2Q: 0.232, 5.284%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.574
Data Arrival Time 5.253
Data Required Time 10.828
From u_ge_pcs/u_ge_rx/check_end_R_R_R_1_s0
To u_ge_pcs/u_ge_rx/c_state_2_s0
Launch Clk serdes_pcs_rx_clk_i[R]
Latch Clk serdes_pcs_rx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_rx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
0.683 0.683 tINS RR 1167 serdes_pcs_rx_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_ge_pcs/u_ge_rx/check_end_R_R_R_1_s0/CLK
1.095 0.232 tC2Q RF 13 u_ge_pcs/u_ge_rx/check_end_R_R_R_1_s0/Q
1.332 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n_state_2_s19/I1
1.887 0.555 tINS FF 1 u_ge_pcs/u_ge_rx/n_state_2_s19/F
2.124 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n_state_2_s12/I1
2.679 0.555 tINS FF 1 u_ge_pcs/u_ge_rx/n_state_2_s12/F
2.916 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n_state_2_s6/I0
3.433 0.517 tINS FF 1 u_ge_pcs/u_ge_rx/n_state_2_s6/F
3.670 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n_state_2_s3/I1
4.225 0.555 tINS FF 1 u_ge_pcs/u_ge_rx/n_state_2_s3/F
4.462 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/n_state_2_s1/I1
5.016 0.555 tINS FF 1 u_ge_pcs/u_ge_rx/n_state_2_s1/F
5.253 0.237 tNET FF 1 u_ge_pcs/u_ge_rx/c_state_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_rx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
10.682 0.683 tINS RR 1167 serdes_pcs_rx_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_ge_pcs/u_ge_rx/c_state_2_s0/CLK
10.828 -0.035 tSu 1 u_ge_pcs/u_ge_rx/c_state_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.737, 62.332%; route: 1.422, 32.384%; tC2Q: 0.232, 5.284%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.574
Data Arrival Time 5.253
Data Required Time 10.828
From u_ge_pcs/u_ge_tx/encode_txd_2_s0
To u_ge_pcs/u_ge_tx/encode_txd_8_s0
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.683 0.683 tINS RR 1008 serdes_pcs_tx_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_2_s0/CLK
1.095 0.232 tC2Q RF 4 u_ge_pcs/u_ge_tx/encode_txd_2_s0/Q
1.332 0.237 tNET FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s4/I1
1.887 0.555 tINS FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s4/F
2.124 0.237 tNET FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/I1
2.679 0.555 tINS FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/F
2.916 0.237 tNET FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/I0
3.433 0.517 tINS FF 5 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/F
3.670 0.237 tNET FF 1 u_ge_pcs/u_ge_tx/n394_s3/I1
4.225 0.555 tINS FF 2 u_ge_pcs/u_ge_tx/n394_s3/F
4.462 0.237 tNET FF 1 u_ge_pcs/u_ge_tx/n394_s1/I1
5.016 0.555 tINS FF 1 u_ge_pcs/u_ge_tx/n394_s1/F
5.253 0.237 tNET FF 1 u_ge_pcs/u_ge_tx/encode_txd_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.682 0.683 tINS RR 1008 serdes_pcs_tx_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_8_s0/CLK
10.828 -0.035 tSu 1 u_ge_pcs/u_ge_tx/encode_txd_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.737, 62.332%; route: 1.422, 32.384%; tC2Q: 0.232, 5.284%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.574
Data Arrival Time 5.253
Data Required Time 10.828
From u_ge_pcs/u_ge_tx/encode_txd_2_s0
To u_ge_pcs/u_ge_tx/encode_txd_12_s0
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.683 0.683 tINS RR 1008 serdes_pcs_tx_clk_i_ibuf/O
0.863 0.180 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_2_s0/CLK
1.095 0.232 tC2Q RF 4 u_ge_pcs/u_ge_tx/encode_txd_2_s0/Q
1.332 0.237 tNET FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s4/I1
1.887 0.555 tINS FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s4/F
2.124 0.237 tNET FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/I1
2.679 0.555 tINS FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/F
2.916 0.237 tNET FF 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/I0
3.433 0.517 tINS FF 5 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/F
3.670 0.237 tNET FF 1 u_ge_pcs/u_ge_tx/n390_s2/I1
4.225 0.555 tINS FF 1 u_ge_pcs/u_ge_tx/n390_s2/F
4.462 0.237 tNET FF 1 u_ge_pcs/u_ge_tx/n390_s4/I1
5.016 0.555 tINS FF 1 u_ge_pcs/u_ge_tx/n390_s4/F
5.253 0.237 tNET FF 1 u_ge_pcs/u_ge_tx/encode_txd_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.682 0.683 tINS RR 1008 serdes_pcs_tx_clk_i_ibuf/O
10.863 0.180 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_12_s0/CLK
10.828 -0.035 tSu 1 u_ge_pcs/u_ge_tx/encode_txd_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.737, 62.332%; route: 1.422, 32.384%; tC2Q: 0.232, 5.284%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%