Timing Messages

Report Title Timing Analysis Report
Design File E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\fpga_project.cst
Timing Constraint File E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.0\ref_design\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\fpga_project.sdc
Version V1.9.9 Beta-3
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138B
Device Version B
Created Time Tue Aug 15 14:01:11 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 85C ES
Hold Delay Model Fast 0.945V 0C ES
Numbers of Paths Analyzed 13726
Numbers of Endpoints Analyzed 10102
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
rx_mac_clk Base 6.400 156.250 0.000 3.200 rx_mac_clk
tx_mac_clk Base 6.400 156.250 0.000 3.200 tx_mac_clk
clk_in Base 19.048 52.499 0.000 10.000 clk_in
board_clk Base 5.000 200.000 0.000 2.500 board_clk
clk_uart Generated 100.000 10.000 0.000 50.000 board_clk board_clk clk_uart
board_clk_p Base 5.000 200.000 0.000 2.500 u_board_clk/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 rx_mac_clk 156.250(MHz) 158.035(MHz) 6 TOP
2 tx_mac_clk 156.250(MHz) 158.687(MHz) 5 TOP
3 clk_in 52.499(MHz) 176.045(MHz) 2 TOP
4 clk_uart 10.000(MHz) 79.304(MHz) 8 TOP

No timing paths to get frequency of board_clk!

No timing paths to get frequency of board_clk_p!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
rx_mac_clk Setup 0.000 0
rx_mac_clk Hold 0.000 0
tx_mac_clk Setup 0.000 0
tx_mac_clk Hold 0.000 0
clk_in Setup 0.000 0
clk_in Hold 0.000 0
board_clk Setup 0.000 0
board_clk Hold 0.000 0
clk_uart Setup 0.000 0
clk_uart Hold 0.000 0
board_clk_p Setup 0.000 0
board_clk_p Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.072 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_2_s0/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1/CE rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.293
2 0.097 u_mac_rx_model_word/pause_address_31_s1/Q u_mac_rx_model_word/pause_address_39_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.268
3 0.097 u_mac_rx_model_word/pause_address_31_s1/Q u_mac_rx_model_word/pause_address_40_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.268
4 0.098 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_4_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 6.267
5 0.098 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_5_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 6.267
6 0.098 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_7_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 6.267
7 0.098 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_8_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 6.267
8 0.103 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_14_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 6.262
9 0.103 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_15_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 6.262
10 0.105 u_mac_rx_model_word/pause_address_31_s1/Q u_mac_rx_model_word/pause_address_38_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.260
11 0.147 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_3_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 6.218
12 0.178 u_mac_rx_model_word/pause_address_14_s1/Q u_mac_rx_model_word/pause_address_42_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.187
13 0.179 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_2_s0/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.186
14 0.194 u_mac_rx_model_word/pause_address_14_s1/Q u_mac_rx_model_word/pause_address_33_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.171
15 0.197 u_mac_rx_model_word/rx_mac_valid_d1_s0/Q u_mac_rx_model_word/rx_data_cnt_15_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.168
16 0.256 u_mac_rx_model_word/pause_address_14_s1/Q u_mac_rx_model_word/pause_address_31_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.109
17 0.256 u_mac_rx_model_word/pause_address_14_s1/Q u_mac_rx_model_word/pause_address_34_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.109
18 0.281 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 6.084
19 0.295 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_8_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/ability_match_s0/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.070
20 0.297 u_mac_rx_model_word/pause_address_14_s1/Q u_mac_rx_model_word/pause_address_47_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.068
21 0.323 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.042
22 0.326 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_4_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_11_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.039
23 0.338 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_3_s1/CE tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 6.027
24 0.346 u_mac_rx_model_word/rx_mac_ub_invalid_d3_s0/Q u_mac_rx_model_word/rx_data_cnt_pause_15_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.019
25 0.354 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_2_s0/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_h_s0/D rx_mac_clk:[R] rx_mac_clk:[R] 6.400 0.000 6.011

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.308 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_47_s0/Q u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s/DI[3] clk_uart:[R] clk_uart:[R] 0.000 0.000 0.320
2 0.308 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_46_s0/Q u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s/DI[2] clk_uart:[R] clk_uart:[R] 0.000 0.000 0.320
3 0.308 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_45_s0/Q u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s/DI[1] clk_uart:[R] clk_uart:[R] 0.000 0.000 0.320
4 0.308 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_38_s0/Q u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s/DI[2] clk_uart:[R] clk_uart:[R] 0.000 0.000 0.320
5 0.308 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_36_s0/Q u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s/DI[0] clk_uart:[R] clk_uart:[R] 0.000 0.000 0.320
6 0.315 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_35_s0/Q u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_8_s/DI[3] clk_uart:[R] clk_uart:[R] 0.000 0.000 0.327
7 0.324 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/gmii_txd_d2_0_s2/Q u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/gmii_txd_d2_0_s14/AD[0] tx_mac_clk:[R] tx_mac_clk:[R] 0.000 0.000 0.336
8 0.331 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_1_s0/Q u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s/WAD[1] clk_uart:[R] clk_uart:[R] 0.000 0.000 0.343
9 0.425 u_mac_rx_model_word/rx_cnt_13_s3/Q u_mac_rx_model_word/rx_cnt_13_s3/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
10 0.425 u_mac_rx_model_word/rx_cnt_23_s3/Q u_mac_rx_model_word/rx_cnt_23_s3/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
11 0.425 u_mac_rx_model_word/rx_cnt_er_s9/Q u_mac_rx_model_word/rx_cnt_er_s9/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
12 0.425 u_mac_rx_model_word/data_start_byte_7_s0/Q u_mac_rx_model_word/data_start_byte_7_s0/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
13 0.425 u_mac_rx_model_word/rx_data_cnt_pause_2_s1/Q u_mac_rx_model_word/rx_data_cnt_pause_2_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
14 0.425 u_mac_rx_model_word/rx_data_cnt_pause_5_s1/Q u_mac_rx_model_word/rx_data_cnt_pause_5_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
15 0.425 u_mac_rx_model_word/rx_data_cnt_pause_6_s1/Q u_mac_rx_model_word/rx_data_cnt_pause_6_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
16 0.425 u_mac_rx_model_word/shift_reg_pause_1_s1/Q u_mac_rx_model_word/shift_reg_pause_1_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
17 0.425 u_mac_rx_model_word/shift_reg_pause_4_s1/Q u_mac_rx_model_word/shift_reg_pause_4_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
18 0.425 u_mac_rx_model_word/shift_reg_pause_8_s1/Q u_mac_rx_model_word/shift_reg_pause_8_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
19 0.425 u_mac_rx_model_word/pause_address_29_s1/Q u_mac_rx_model_word/pause_address_29_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
20 0.425 u_mac_rx_model_word/pause_value_4_s1/Q u_mac_rx_model_word/pause_value_4_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
21 0.425 u_mac_rx_model_word/rx_data_cnt_4_s1/Q u_mac_rx_model_word/rx_data_cnt_4_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
22 0.425 u_mac_rx_model_word/data_increase_add_1_0_s1/Q u_mac_rx_model_word/data_increase_add_1_0_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
23 0.425 u_mac_rx_model_word/shift_reg_3_s1/Q u_mac_rx_model_word/shift_reg_3_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
24 0.425 u_mac_rx_model_word/shift_reg_8_s1/Q u_mac_rx_model_word/shift_reg_8_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436
25 0.425 u_mac_rx_model_word/shift_reg_18_s1/Q u_mac_rx_model_word/shift_reg_18_s1/D rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/update_data_end_s2/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
2 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/latch_data_end_s2/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
3 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_0_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
4 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_1_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
5 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_4_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
6 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_7_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
7 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_10_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
8 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_13_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
9 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_16_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
10 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_23_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
11 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_28_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
12 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_30_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
13 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_cnt_er_s8/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
14 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_data_cnt_last_s4/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
15 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/tx_data_cnt_1_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
16 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_increase_1_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
17 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_length_0_s3/PRESET tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
18 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_length_1_s3/PRESET tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
19 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_length_2_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
20 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_length_3_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
21 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_length_4_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
22 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_length_5_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
23 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_length_6_s3/PRESET tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
24 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_length_7_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928
25 3.437 tx_mac_rst_n_s0/Q u_mac_tx_model_word/data_length_8_s3/CLEAR tx_mac_clk:[R] tx_mac_clk:[R] 6.400 0.000 2.928

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/update_data_end_s2/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
2 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/latch_data_end_s2/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
3 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_0_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
4 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_1_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
5 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_4_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
6 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_7_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
7 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_10_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
8 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_13_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
9 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_16_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
10 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_21_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
11 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_23_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
12 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_28_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
13 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_30_s3/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
14 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_er_s9/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
15 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_error_all_check_s4/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
16 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_error_all_pause_check_s4/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
17 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_error_all_data_check_s4/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
18 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_data_cnt_last_s5/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
19 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_pause_state_s5/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
20 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_2_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
21 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_3_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
22 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_5_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
23 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_6_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
24 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_8_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689
25 1.678 rx_mac_rst_n_s0/Q u_mac_rx_model_word/rx_cnt_9_s1/CLEAR rx_mac_clk:[R] rx_mac_clk:[R] 0.000 0.000 1.689

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.123 3.123 1.000 Low Pulse Width rx_mac_clk configuration_vector_12_s0
2 2.123 3.123 1.000 Low Pulse Width rx_mac_clk u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_decode_rxd_d2_11_s0
3 2.123 3.123 1.000 Low Pulse Width rx_mac_clk u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rxd_m_set_l_s0
4 2.123 3.123 1.000 Low Pulse Width rx_mac_clk u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_dv_reg_d1_5_s0
5 2.123 3.123 1.000 Low Pulse Width rx_mac_clk u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_col_reg_d1_1_s0
6 2.123 3.123 1.000 Low Pulse Width rx_mac_clk u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_mac_data_9_s1
7 2.123 3.123 1.000 Low Pulse Width rx_mac_clk u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_12_s1
8 2.123 3.123 1.000 Low Pulse Width rx_mac_clk u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s1
9 2.123 3.123 1.000 Low Pulse Width rx_mac_clk u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_0_s1
10 2.123 3.123 1.000 Low Pulse Width rx_mac_clk u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/vlan_reg_14_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.072
Data Arrival Time 9.536
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_2_s0
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R40C65[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_2_s0/CLK
3.475 0.232 tC2Q RF 23 R40C65[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_2_s0/Q
4.720 1.245 tNET FF 1 R43C71[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1845_s10/I0
5.237 0.517 tINS FF 3 R43C71[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n1845_s10/F
5.660 0.423 tNET FF 1 R41C70[3][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s10/I1
6.177 0.517 tINS FF 1 R41C70[3][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s10/F
6.575 0.398 tNET FF 1 R42C70[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s6/I3
7.130 0.555 tINS FF 2 R42C70[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s6/F
7.833 0.703 tNET FF 1 R40C75[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s4/I2
8.388 0.555 tINS FF 1 R40C75[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s4/F
8.928 0.539 tNET FF 1 R40C84[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s3/I2
9.390 0.462 tINS FR 1 R40C84[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s3/F
9.536 0.146 tNET RR 1 R40C84[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R40C84[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1/CLK
9.608 -0.035 tSu 1 R40C84[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.606, 41.413%; route: 3.455, 54.900%; tC2Q: 0.232, 3.687%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path2

Path Summary:

Slack 0.097
Data Arrival Time 9.512
Data Required Time 9.608
From u_mac_rx_model_word/pause_address_31_s1
To u_mac_rx_model_word/pause_address_39_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R47C126[1][A] u_mac_rx_model_word/pause_address_31_s1/CLK
3.475 0.232 tC2Q RF 5 R47C126[1][A] u_mac_rx_model_word/pause_address_31_s1/Q
4.692 1.217 tNET FF 1 R52C124[2][A] u_mac_rx_model_word/n1603_s1/I2
5.145 0.453 tINS FF 3 R52C124[2][A] u_mac_rx_model_word/n1603_s1/F
6.012 0.866 tNET FF 1 R47C126[2][A] u_mac_rx_model_word/n1592_s3/I2
6.567 0.555 tINS FF 2 R47C126[2][A] u_mac_rx_model_word/n1592_s3/F
7.114 0.548 tNET FF 1 R53C126[0][B] u_mac_rx_model_word/n1600_s1/I2
7.567 0.453 tINS FF 4 R53C126[0][B] u_mac_rx_model_word/n1600_s1/F
8.274 0.707 tNET FF 1 R53C132[2][A] u_mac_rx_model_word/n1597_s2/I2
8.791 0.517 tINS FF 3 R53C132[2][A] u_mac_rx_model_word/n1597_s2/F
9.050 0.259 tNET FF 1 R52C132[1][A] u_mac_rx_model_word/n1598_s0/I2
9.512 0.462 tINS FR 1 R52C132[1][A] u_mac_rx_model_word/n1598_s0/F
9.512 0.000 tNET RR 1 R52C132[1][A] u_mac_rx_model_word/pause_address_39_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R52C132[1][A] u_mac_rx_model_word/pause_address_39_s1/CLK
9.608 -0.035 tSu 1 R52C132[1][A] u_mac_rx_model_word/pause_address_39_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.440, 38.925%; route: 3.596, 57.374%; tC2Q: 0.232, 3.701%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path3

Path Summary:

Slack 0.097
Data Arrival Time 9.512
Data Required Time 9.608
From u_mac_rx_model_word/pause_address_31_s1
To u_mac_rx_model_word/pause_address_40_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R47C126[1][A] u_mac_rx_model_word/pause_address_31_s1/CLK
3.475 0.232 tC2Q RF 5 R47C126[1][A] u_mac_rx_model_word/pause_address_31_s1/Q
4.692 1.217 tNET FF 1 R52C124[2][A] u_mac_rx_model_word/n1603_s1/I2
5.145 0.453 tINS FF 3 R52C124[2][A] u_mac_rx_model_word/n1603_s1/F
6.012 0.866 tNET FF 1 R47C126[2][A] u_mac_rx_model_word/n1592_s3/I2
6.567 0.555 tINS FF 2 R47C126[2][A] u_mac_rx_model_word/n1592_s3/F
7.114 0.548 tNET FF 1 R53C126[0][B] u_mac_rx_model_word/n1600_s1/I2
7.567 0.453 tINS FF 4 R53C126[0][B] u_mac_rx_model_word/n1600_s1/F
8.274 0.707 tNET FF 1 R53C132[2][A] u_mac_rx_model_word/n1597_s2/I2
8.791 0.517 tINS FF 3 R53C132[2][A] u_mac_rx_model_word/n1597_s2/F
9.050 0.259 tNET FF 1 R52C132[1][B] u_mac_rx_model_word/n1597_s0/I2
9.512 0.462 tINS FR 1 R52C132[1][B] u_mac_rx_model_word/n1597_s0/F
9.512 0.000 tNET RR 1 R52C132[1][B] u_mac_rx_model_word/pause_address_40_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R52C132[1][B] u_mac_rx_model_word/pause_address_40_s1/CLK
9.608 -0.035 tSu 1 R52C132[1][B] u_mac_rx_model_word/pause_address_40_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.440, 38.925%; route: 3.596, 57.374%; tC2Q: 0.232, 3.701%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path4

Path Summary:

Slack 0.098
Data Arrival Time 9.510
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_4_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/CLK
3.475 0.232 tC2Q RF 16 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q
4.647 1.172 tNET FF 1 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/I3
5.164 0.517 tINS FF 7 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/F
5.880 0.716 tNET FF 1 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/I1
6.251 0.371 tINS FF 3 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/F
6.966 0.714 tNET FF 1 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/I3
7.483 0.517 tINS FF 3 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/F
8.401 0.919 tNET FF 1 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/I3
8.728 0.327 tINS FR 15 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/F
9.510 0.782 tNET RR 1 R45C70[3][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_4_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R45C70[3][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_4_s1/CLK
9.608 -0.035 tSu 1 R45C70[3][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.732, 27.638%; route: 4.303, 68.660%; tC2Q: 0.232, 3.702%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path5

Path Summary:

Slack 0.098
Data Arrival Time 9.510
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_5_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/CLK
3.475 0.232 tC2Q RF 16 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q
4.647 1.172 tNET FF 1 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/I3
5.164 0.517 tINS FF 7 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/F
5.880 0.716 tNET FF 1 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/I1
6.251 0.371 tINS FF 3 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/F
6.966 0.714 tNET FF 1 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/I3
7.483 0.517 tINS FF 3 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/F
8.401 0.919 tNET FF 1 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/I3
8.728 0.327 tINS FR 15 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/F
9.510 0.782 tNET RR 1 R45C70[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_5_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R45C70[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_5_s1/CLK
9.608 -0.035 tSu 1 R45C70[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.732, 27.638%; route: 4.303, 68.660%; tC2Q: 0.232, 3.702%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path6

Path Summary:

Slack 0.098
Data Arrival Time 9.510
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_7_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/CLK
3.475 0.232 tC2Q RF 16 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q
4.647 1.172 tNET FF 1 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/I3
5.164 0.517 tINS FF 7 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/F
5.880 0.716 tNET FF 1 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/I1
6.251 0.371 tINS FF 3 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/F
6.966 0.714 tNET FF 1 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/I3
7.483 0.517 tINS FF 3 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/F
8.401 0.919 tNET FF 1 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/I3
8.728 0.327 tINS FR 15 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/F
9.510 0.782 tNET RR 1 R45C70[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_7_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R45C70[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_7_s1/CLK
9.608 -0.035 tSu 1 R45C70[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.732, 27.638%; route: 4.303, 68.660%; tC2Q: 0.232, 3.702%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path7

Path Summary:

Slack 0.098
Data Arrival Time 9.510
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_8_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/CLK
3.475 0.232 tC2Q RF 16 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q
4.647 1.172 tNET FF 1 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/I3
5.164 0.517 tINS FF 7 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/F
5.880 0.716 tNET FF 1 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/I1
6.251 0.371 tINS FF 3 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/F
6.966 0.714 tNET FF 1 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/I3
7.483 0.517 tINS FF 3 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/F
8.401 0.919 tNET FF 1 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/I3
8.728 0.327 tINS FR 15 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/F
9.510 0.782 tNET RR 1 R45C70[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_8_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R45C70[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_8_s1/CLK
9.608 -0.035 tSu 1 R45C70[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.732, 27.638%; route: 4.303, 68.660%; tC2Q: 0.232, 3.702%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path8

Path Summary:

Slack 0.103
Data Arrival Time 9.506
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_14_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/CLK
3.475 0.232 tC2Q RF 16 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q
4.647 1.172 tNET FF 1 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/I3
5.164 0.517 tINS FF 7 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/F
5.880 0.716 tNET FF 1 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/I1
6.251 0.371 tINS FF 3 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/F
6.966 0.714 tNET FF 1 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/I3
7.483 0.517 tINS FF 3 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/F
8.401 0.919 tNET FF 1 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/I3
8.728 0.327 tINS FR 15 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/F
9.506 0.777 tNET RR 1 R45C71[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_14_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R45C71[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_14_s1/CLK
9.608 -0.035 tSu 1 R45C71[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_14_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.732, 27.658%; route: 4.298, 68.638%; tC2Q: 0.232, 3.705%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path9

Path Summary:

Slack 0.103
Data Arrival Time 9.506
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_15_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/CLK
3.475 0.232 tC2Q RF 16 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q
4.647 1.172 tNET FF 1 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/I3
5.164 0.517 tINS FF 7 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/F
5.880 0.716 tNET FF 1 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/I1
6.251 0.371 tINS FF 3 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/F
6.966 0.714 tNET FF 1 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/I3
7.483 0.517 tINS FF 3 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/F
8.401 0.919 tNET FF 1 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/I3
8.728 0.327 tINS FR 15 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/F
9.506 0.777 tNET RR 1 R45C71[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_15_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R45C71[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_15_s1/CLK
9.608 -0.035 tSu 1 R45C71[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_15_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.732, 27.658%; route: 4.298, 68.638%; tC2Q: 0.232, 3.705%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path10

Path Summary:

Slack 0.105
Data Arrival Time 9.503
Data Required Time 9.608
From u_mac_rx_model_word/pause_address_31_s1
To u_mac_rx_model_word/pause_address_38_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R47C126[1][A] u_mac_rx_model_word/pause_address_31_s1/CLK
3.475 0.232 tC2Q RF 5 R47C126[1][A] u_mac_rx_model_word/pause_address_31_s1/Q
4.692 1.217 tNET FF 1 R52C124[2][A] u_mac_rx_model_word/n1603_s1/I2
5.145 0.453 tINS FF 3 R52C124[2][A] u_mac_rx_model_word/n1603_s1/F
6.012 0.866 tNET FF 1 R47C126[2][A] u_mac_rx_model_word/n1592_s3/I2
6.567 0.555 tINS FF 2 R47C126[2][A] u_mac_rx_model_word/n1592_s3/F
7.114 0.548 tNET FF 1 R53C126[0][B] u_mac_rx_model_word/n1600_s1/I2
7.567 0.453 tINS FF 4 R53C126[0][B] u_mac_rx_model_word/n1600_s1/F
8.274 0.707 tNET FF 1 R53C132[2][A] u_mac_rx_model_word/n1597_s2/I2
8.791 0.517 tINS FF 3 R53C132[2][A] u_mac_rx_model_word/n1597_s2/F
9.041 0.250 tNET FF 1 R51C132[1][B] u_mac_rx_model_word/n1599_s1/I2
9.503 0.462 tINS FR 1 R51C132[1][B] u_mac_rx_model_word/n1599_s1/F
9.503 0.000 tNET RR 1 R51C132[1][B] u_mac_rx_model_word/pause_address_38_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R51C132[1][B] u_mac_rx_model_word/pause_address_38_s1/CLK
9.608 -0.035 tSu 1 R51C132[1][B] u_mac_rx_model_word/pause_address_38_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.440, 38.978%; route: 3.588, 57.316%; tC2Q: 0.232, 3.706%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path11

Path Summary:

Slack 0.147
Data Arrival Time 9.461
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_3_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/CLK
3.475 0.232 tC2Q RF 16 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q
4.647 1.172 tNET FF 1 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/I3
5.164 0.517 tINS FF 7 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/F
5.880 0.716 tNET FF 1 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/I1
6.251 0.371 tINS FF 3 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/F
6.966 0.714 tNET FF 1 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/I3
7.483 0.517 tINS FF 3 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/F
8.401 0.919 tNET FF 1 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/I3
8.728 0.327 tINS FR 15 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/F
9.461 0.733 tNET RR 1 R52C69[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R52C69[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_3_s1/CLK
9.608 -0.035 tSu 1 R52C69[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.732, 27.855%; route: 4.254, 68.414%; tC2Q: 0.232, 3.731%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path12

Path Summary:

Slack 0.178
Data Arrival Time 9.431
Data Required Time 9.608
From u_mac_rx_model_word/pause_address_14_s1
To u_mac_rx_model_word/pause_address_42_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/CLK
3.475 0.232 tC2Q RF 4 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/Q
4.712 1.236 tNET FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/I1
5.083 0.371 tINS FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/F
5.333 0.250 tNET FF 1 R52C126[0][A] u_mac_rx_model_word/n1621_s2/I3
5.888 0.555 tINS FF 3 R52C126[0][A] u_mac_rx_model_word/n1621_s2/F
6.608 0.720 tNET FF 1 R53C120[1][A] u_mac_rx_model_word/n1617_s1/I1
7.061 0.453 tINS FF 12 R53C120[1][A] u_mac_rx_model_word/n1617_s1/F
7.794 0.733 tNET FF 1 R54C126[3][A] u_mac_rx_model_word/n1590_s1/I1
8.165 0.371 tINS FF 17 R54C126[3][A] u_mac_rx_model_word/n1590_s1/F
8.882 0.716 tNET FF 1 R53C123[1][A] u_mac_rx_model_word/n1595_s0/I0
9.431 0.549 tINS FR 1 R53C123[1][A] u_mac_rx_model_word/n1595_s0/F
9.431 0.000 tNET RR 1 R53C123[1][A] u_mac_rx_model_word/pause_address_42_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R53C123[1][A] u_mac_rx_model_word/pause_address_42_s1/CLK
9.608 -0.035 tSu 1 R53C123[1][A] u_mac_rx_model_word/pause_address_42_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.299, 37.157%; route: 3.656, 59.093%; tC2Q: 0.232, 3.750%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path13

Path Summary:

Slack 0.179
Data Arrival Time 9.430
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_2_s0
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R40C68[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0/CLK
3.475 0.232 tC2Q RF 26 R40C68[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0/Q
4.224 0.748 tNET FF 1 R42C77[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n938_s4/I0
4.779 0.555 tINS FF 6 R42C77[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n938_s4/F
5.900 1.121 tNET FF 1 R42C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s11/I1
6.271 0.371 tINS FF 4 R42C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s11/F
6.937 0.666 tNET FF 1 R40C73[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n_state_1_s8/I1
7.454 0.517 tINS FF 2 R40C73[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n_state_1_s8/F
8.164 0.710 tNET FF 1 R40C65[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n_state_2_s4/I0
8.734 0.570 tINS FR 1 R40C65[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n_state_2_s4/F
8.881 0.146 tNET RR 1 R40C65[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n_state_2_s1/I2
9.430 0.549 tINS RR 1 R40C65[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n_state_2_s1/F
9.430 0.000 tNET RR 1 R40C65[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R40C65[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_2_s0/CLK
9.608 -0.035 tSu 1 R40C65[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.562, 41.414%; route: 3.392, 54.836%; tC2Q: 0.232, 3.750%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path14

Path Summary:

Slack 0.194
Data Arrival Time 9.414
Data Required Time 9.608
From u_mac_rx_model_word/pause_address_14_s1
To u_mac_rx_model_word/pause_address_33_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/CLK
3.475 0.232 tC2Q RF 4 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/Q
4.712 1.236 tNET FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/I1
5.083 0.371 tINS FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/F
5.333 0.250 tNET FF 1 R52C126[0][A] u_mac_rx_model_word/n1621_s2/I3
5.888 0.555 tINS FF 3 R52C126[0][A] u_mac_rx_model_word/n1621_s2/F
6.608 0.720 tNET FF 1 R53C120[1][A] u_mac_rx_model_word/n1617_s1/I1
7.061 0.453 tINS FF 12 R53C120[1][A] u_mac_rx_model_word/n1617_s1/F
7.794 0.733 tNET FF 1 R54C126[3][A] u_mac_rx_model_word/n1590_s1/I1
8.165 0.371 tINS FF 17 R54C126[3][A] u_mac_rx_model_word/n1590_s1/F
8.865 0.700 tNET FF 1 R53C124[1][A] u_mac_rx_model_word/n1604_s0/I0
9.414 0.549 tINS FR 1 R53C124[1][A] u_mac_rx_model_word/n1604_s0/F
9.414 0.000 tNET RR 1 R53C124[1][A] u_mac_rx_model_word/pause_address_33_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R53C124[1][A] u_mac_rx_model_word/pause_address_33_s1/CLK
9.608 -0.035 tSu 1 R53C124[1][A] u_mac_rx_model_word/pause_address_33_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.299, 37.256%; route: 3.640, 58.984%; tC2Q: 0.232, 3.760%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path15

Path Summary:

Slack 0.197
Data Arrival Time 9.411
Data Required Time 9.608
From u_mac_rx_model_word/rx_mac_valid_d1_s0
To u_mac_rx_model_word/rx_data_cnt_15_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R48C118[2][A] u_mac_rx_model_word/rx_mac_valid_d1_s0/CLK
3.475 0.232 tC2Q RF 123 R48C118[2][A] u_mac_rx_model_word/rx_mac_valid_d1_s0/Q
5.037 1.561 tNET FF 1 R50C141[3][A] u_mac_rx_model_word/n1256_s2/I3
5.554 0.517 tINS FF 4 R50C141[3][A] u_mac_rx_model_word/n1256_s2/F
6.137 0.584 tNET FF 1 R52C140[2][B] u_mac_rx_model_word/n1253_s3/I3
6.686 0.549 tINS FR 5 R52C140[2][B] u_mac_rx_model_word/n1253_s3/F
6.872 0.186 tNET RR 1 R52C139[3][B] u_mac_rx_model_word/n1247_s2/I1
7.325 0.453 tINS RF 4 R52C139[3][B] u_mac_rx_model_word/n1247_s2/F
7.905 0.580 tNET FF 1 R53C140[1][A] u_mac_rx_model_word/n1244_s3/I1
8.460 0.555 tINS FF 2 R53C140[1][A] u_mac_rx_model_word/n1244_s3/F
8.862 0.403 tNET FF 1 R51C140[0][A] u_mac_rx_model_word/n1243_s1/I1
9.411 0.549 tINS FR 1 R51C140[0][A] u_mac_rx_model_word/n1243_s1/F
9.411 0.000 tNET RR 1 R51C140[0][A] u_mac_rx_model_word/rx_data_cnt_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R51C140[0][A] u_mac_rx_model_word/rx_data_cnt_15_s1/CLK
9.608 -0.035 tSu 1 R51C140[0][A] u_mac_rx_model_word/rx_data_cnt_15_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.623, 42.526%; route: 3.313, 53.713%; tC2Q: 0.232, 3.761%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path16

Path Summary:

Slack 0.256
Data Arrival Time 9.352
Data Required Time 9.608
From u_mac_rx_model_word/pause_address_14_s1
To u_mac_rx_model_word/pause_address_31_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/CLK
3.475 0.232 tC2Q RF 4 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/Q
4.712 1.236 tNET FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/I1
5.083 0.371 tINS FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/F
5.333 0.250 tNET FF 1 R52C126[0][A] u_mac_rx_model_word/n1621_s2/I3
5.888 0.555 tINS FF 3 R52C126[0][A] u_mac_rx_model_word/n1621_s2/F
6.608 0.720 tNET FF 1 R53C120[1][A] u_mac_rx_model_word/n1617_s1/I1
7.061 0.453 tINS FF 12 R53C120[1][A] u_mac_rx_model_word/n1617_s1/F
7.794 0.733 tNET FF 1 R54C126[3][A] u_mac_rx_model_word/n1590_s1/I1
8.165 0.371 tINS FF 17 R54C126[3][A] u_mac_rx_model_word/n1590_s1/F
8.890 0.725 tNET FF 1 R47C126[1][A] u_mac_rx_model_word/n1606_s1/I0
9.352 0.462 tINS FR 1 R47C126[1][A] u_mac_rx_model_word/n1606_s1/F
9.352 0.000 tNET RR 1 R47C126[1][A] u_mac_rx_model_word/pause_address_31_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R47C126[1][A] u_mac_rx_model_word/pause_address_31_s1/CLK
9.608 -0.035 tSu 1 R47C126[1][A] u_mac_rx_model_word/pause_address_31_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.212, 36.210%; route: 3.665, 59.992%; tC2Q: 0.232, 3.798%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path17

Path Summary:

Slack 0.256
Data Arrival Time 9.352
Data Required Time 9.608
From u_mac_rx_model_word/pause_address_14_s1
To u_mac_rx_model_word/pause_address_34_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/CLK
3.475 0.232 tC2Q RF 4 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/Q
4.712 1.236 tNET FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/I1
5.083 0.371 tINS FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/F
5.333 0.250 tNET FF 1 R52C126[0][A] u_mac_rx_model_word/n1621_s2/I3
5.888 0.555 tINS FF 3 R52C126[0][A] u_mac_rx_model_word/n1621_s2/F
6.608 0.720 tNET FF 1 R53C120[1][A] u_mac_rx_model_word/n1617_s1/I1
7.061 0.453 tINS FF 12 R53C120[1][A] u_mac_rx_model_word/n1617_s1/F
7.794 0.733 tNET FF 1 R54C126[3][A] u_mac_rx_model_word/n1590_s1/I1
8.165 0.371 tINS FF 17 R54C126[3][A] u_mac_rx_model_word/n1590_s1/F
8.890 0.725 tNET FF 1 R47C126[0][B] u_mac_rx_model_word/n1603_s0/I0
9.352 0.462 tINS FR 1 R47C126[0][B] u_mac_rx_model_word/n1603_s0/F
9.352 0.000 tNET RR 1 R47C126[0][B] u_mac_rx_model_word/pause_address_34_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R47C126[0][B] u_mac_rx_model_word/pause_address_34_s1/CLK
9.608 -0.035 tSu 1 R47C126[0][B] u_mac_rx_model_word/pause_address_34_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.212, 36.210%; route: 3.665, 59.992%; tC2Q: 0.232, 3.798%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path18

Path Summary:

Slack 0.281
Data Arrival Time 9.327
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/CLK
3.475 0.232 tC2Q RF 16 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q
4.647 1.172 tNET FF 1 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/I3
5.164 0.517 tINS FF 7 R47C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s3/F
5.880 0.716 tNET FF 1 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/I1
6.251 0.371 tINS FF 3 R50C66[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n826_s0/F
6.966 0.714 tNET FF 1 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/I3
7.483 0.517 tINS FF 3 R48C71[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s2/F
8.401 0.919 tNET FF 1 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/I3
8.728 0.327 tINS FR 15 R51C68[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n905_s5/F
9.327 0.599 tNET RR 1 R45C69[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R45C69[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1/CLK
9.608 -0.035 tSu 1 R45C69[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/back_cnt_12_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.732, 28.470%; route: 4.120, 67.717%; tC2Q: 0.232, 3.813%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path19

Path Summary:

Slack 0.295
Data Arrival Time 9.313
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_8_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/ability_match_s0
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R42C83[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_8_s1/CLK
3.475 0.232 tC2Q RF 5 R42C83[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_8_s1/Q
4.799 1.323 tNET FF 1 R40C78[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n729_s0/I0
5.348 0.549 tINS FR 1 R40C78[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n729_s0/COUT
5.348 0.000 tNET RR 1 R40C78[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n730_s0/CIN
5.383 0.035 tINS RF 1 R40C78[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n730_s0/COUT
5.383 0.000 tNET FF 1 R40C78[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n731_s0/CIN
5.418 0.035 tINS FF 1 R40C78[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n731_s0/COUT
6.056 0.638 tNET FF 1 R40C80[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/ability_matched_s3/I1
6.573 0.517 tINS FF 2 R40C80[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/ability_matched_s3/F
7.406 0.833 tNET FF 1 R41C64[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/ability_matched_s1/I3
7.777 0.371 tINS FF 8 R41C64[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/ability_matched_s1/F
9.313 1.536 tNET FF 1 R40C45[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/ability_match_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R40C45[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/ability_match_s0/CLK
9.608 -0.035 tSu 1 R40C45[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/ability_match_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.507, 24.833%; route: 4.331, 71.345%; tC2Q: 0.232, 3.822%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path20

Path Summary:

Slack 0.297
Data Arrival Time 9.311
Data Required Time 9.608
From u_mac_rx_model_word/pause_address_14_s1
To u_mac_rx_model_word/pause_address_47_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/CLK
3.475 0.232 tC2Q RF 4 R47C129[1][A] u_mac_rx_model_word/pause_address_14_s1/Q
4.712 1.236 tNET FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/I1
5.083 0.371 tINS FF 1 R50C126[1][B] u_mac_rx_model_word/n1621_s7/F
5.333 0.250 tNET FF 1 R52C126[0][A] u_mac_rx_model_word/n1621_s2/I3
5.888 0.555 tINS FF 3 R52C126[0][A] u_mac_rx_model_word/n1621_s2/F
6.608 0.720 tNET FF 1 R53C120[1][A] u_mac_rx_model_word/n1617_s1/I1
7.061 0.453 tINS FF 12 R53C120[1][A] u_mac_rx_model_word/n1617_s1/F
7.794 0.733 tNET FF 1 R54C126[3][A] u_mac_rx_model_word/n1590_s1/I1
8.165 0.371 tINS FF 17 R54C126[3][A] u_mac_rx_model_word/n1590_s1/F
8.741 0.576 tNET FF 1 R50C126[0][B] u_mac_rx_model_word/n1590_s0/I0
9.311 0.570 tINS FR 1 R50C126[0][B] u_mac_rx_model_word/n1590_s0/F
9.311 0.000 tNET RR 1 R50C126[0][B] u_mac_rx_model_word/pause_address_47_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R50C126[0][B] u_mac_rx_model_word/pause_address_47_s1/CLK
9.608 -0.035 tSu 1 R50C126[0][B] u_mac_rx_model_word/pause_address_47_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.320, 38.236%; route: 3.516, 57.941%; tC2Q: 0.232, 3.824%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path21

Path Summary:

Slack 0.323
Data Arrival Time 9.286
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R40C68[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0/CLK
3.475 0.232 tC2Q RF 26 R40C68[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_3_s0/Q
4.224 0.748 tNET FF 1 R42C77[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n938_s4/I0
4.779 0.555 tINS FF 6 R42C77[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n938_s4/F
5.416 0.637 tNET FF 1 R43C70[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s19/I0
5.787 0.371 tINS FF 7 R43C70[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_config_cnt_2_s19/F
6.860 1.073 tNET FF 1 R41C74[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_set_h_s3/I2
7.313 0.453 tINS FF 2 R41C74[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_set_h_s3/F
7.735 0.422 tNET FF 1 R41C77[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_set_h_s1/I2
8.188 0.453 tINS FF 2 R41C77[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_set_h_s1/F
9.286 1.097 tNET FF 1 R40C84[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R40C84[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1/CLK
9.608 -0.035 tSu 1 R40C84[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/receiving_m_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.832, 30.319%; route: 3.978, 65.841%; tC2Q: 0.232, 3.840%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path22

Path Summary:

Slack 0.326
Data Arrival Time 9.283
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_4_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_11_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R56C46[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_4_s1/CLK
3.475 0.232 tC2Q RF 19 R56C46[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rxd_reg_d1_4_s1/Q
5.695 2.220 tNET FF 1 R51C57[3][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n700_s9/I0
6.148 0.453 tINS FF 2 R51C57[3][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n700_s9/F
6.403 0.254 tNET FF 1 R53C57[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n696_s6/I3
6.856 0.453 tINS FF 2 R53C57[1][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n696_s6/F
7.519 0.664 tNET FF 1 R51C55[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n693_s3/I2
8.074 0.555 tINS FF 1 R51C55[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n693_s3/F
8.734 0.659 tNET FF 1 R49C53[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n693_s2/I1
9.283 0.549 tINS FR 1 R49C53[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/n693_s2/F
9.283 0.000 tNET RR 1 R49C53[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R49C53[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_11_s1/CLK
9.608 -0.035 tSu 1 R49C53[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/crc_reg_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.010, 33.281%; route: 3.797, 62.877%; tC2Q: 0.232, 3.841%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path23

Path Summary:

Slack 0.338
Data Arrival Time 9.271
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_3_s1
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/CLK
3.475 0.232 tC2Q RF 16 R53C80[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s1/Q
3.918 0.443 tNET FF 1 R54C79[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s2/I1
4.473 0.555 tINS FF 4 R54C79[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n676_s2/F
5.556 1.083 tNET FF 1 R51C70[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n1102_s0/I3
6.126 0.570 tINS FR 13 R51C70[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/n1102_s0/F
6.308 0.182 tNET RR 1 R52C70[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s3/I2
6.679 0.371 tINS RF 2 R52C70[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_2_s3/F
7.866 1.187 tNET FF 1 R53C81[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_0_s4/I1
8.436 0.570 tINS FR 2 R53C81[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_0_s4/F
8.613 0.177 tNET RR 1 R53C80[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_3_s3/I3
8.940 0.327 tINS RR 1 R53C80[3][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_3_s3/F
9.271 0.331 tNET RR 1 R53C79[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R53C79[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_3_s1/CLK
9.608 -0.035 tSu 1 R53C79[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/c_state_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.393, 39.702%; route: 3.402, 56.449%; tC2Q: 0.232, 3.849%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path24

Path Summary:

Slack 0.346
Data Arrival Time 9.262
Data Required Time 9.608
From u_mac_rx_model_word/rx_mac_ub_invalid_d3_s0
To u_mac_rx_model_word/rx_data_cnt_pause_15_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R48C143[0][A] u_mac_rx_model_word/rx_mac_ub_invalid_d3_s0/CLK
3.475 0.232 tC2Q RF 3 R48C143[0][A] u_mac_rx_model_word/rx_mac_ub_invalid_d3_s0/Q
4.697 1.221 tNET FF 1 R54C138[2][B] u_mac_rx_model_word/n2371_s2/I1
5.150 0.453 tINS FF 8 R54C138[2][B] u_mac_rx_model_word/n2371_s2/F
6.556 1.406 tNET FF 1 R53C132[0][B] u_mac_rx_model_word/n2362_s2/I2
7.009 0.453 tINS FF 4 R53C132[0][B] u_mac_rx_model_word/n2362_s2/F
7.678 0.670 tNET FF 1 R51C133[0][B] u_mac_rx_model_word/n2359_s3/I3
8.049 0.371 tINS FF 2 R51C133[0][B] u_mac_rx_model_word/n2359_s3/F
8.713 0.664 tNET FF 1 R53C135[0][B] u_mac_rx_model_word/n2358_s1/I1
9.262 0.549 tINS FR 1 R53C135[0][B] u_mac_rx_model_word/n2358_s1/F
9.262 0.000 tNET RR 1 R53C135[0][B] u_mac_rx_model_word/rx_data_cnt_pause_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R53C135[0][B] u_mac_rx_model_word/rx_data_cnt_pause_15_s1/CLK
9.608 -0.035 tSu 1 R53C135[0][B] u_mac_rx_model_word/rx_data_cnt_pause_15_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 1.826, 30.338%; route: 3.961, 65.808%; tC2Q: 0.232, 3.854%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path25

Path Summary:

Slack 0.354
Data Arrival Time 9.255
Data Required Time 9.608
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_2_s0
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_h_s0
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R43C66[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_2_s0/CLK
3.475 0.232 tC2Q RF 16 R43C66[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/c_state_d1_2_s0/Q
5.038 1.563 tNET FF 1 R43C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s26/I0
5.409 0.371 tINS FF 2 R43C70[0][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s26/F
5.667 0.259 tNET FF 1 R41C70[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s22/I3
6.222 0.555 tINS FF 5 R41C70[1][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2146_s22/F
6.903 0.681 tNET FF 1 R40C73[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2188_s2/I3
7.274 0.371 tINS FF 2 R40C73[2][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2188_s2/F
7.818 0.544 tNET FF 1 R40C67[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2167_s12/I0
8.271 0.453 tINS FF 1 R40C67[2][B] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2167_s12/F
8.685 0.414 tNET FF 1 R40C66[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2167_s10/I3
9.255 0.570 tINS FR 1 R40C66[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/n2167_s10/F
9.255 0.000 tNET RR 1 R40C66[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_h_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R40C66[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_h_s0/CLK
9.608 -0.035 tSu 1 R40C66[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rx_er_m_set_h_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 2.320, 38.593%; route: 3.459, 57.548%; tC2Q: 0.232, 3.859%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.308
Data Arrival Time 3.504
Data Required Time 3.196
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_47_s0
To u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s
Launch Clk clk_uart:[R]
Latch Clk clk_uart:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R54C97[0][A] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_47_s0/CLK
3.385 0.201 tC2Q RF 1 R54C97[0][A] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_47_s0/Q
3.504 0.119 tNET FF 1 R53C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R53C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s/CLK
3.196 0.012 tHld 1 R53C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path2

Path Summary:

Slack 0.308
Data Arrival Time 3.504
Data Required Time 3.196
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_46_s0
To u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s
Launch Clk clk_uart:[R]
Latch Clk clk_uart:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R54C97[0][B] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_46_s0/CLK
3.385 0.201 tC2Q RF 1 R54C97[0][B] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_46_s0/Q
3.504 0.119 tNET FF 1 R53C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R53C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s/CLK
3.196 0.012 tHld 1 R53C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path3

Path Summary:

Slack 0.308
Data Arrival Time 3.504
Data Required Time 3.196
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_45_s0
To u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s
Launch Clk clk_uart:[R]
Latch Clk clk_uart:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R54C97[1][A] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_45_s0/CLK
3.385 0.201 tC2Q RF 1 R54C97[1][A] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_45_s0/Q
3.504 0.119 tNET FF 1 R53C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R53C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s/CLK
3.196 0.012 tHld 1 R53C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_11_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path4

Path Summary:

Slack 0.308
Data Arrival Time 3.504
Data Required Time 3.196
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_38_s0
To u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s
Launch Clk clk_uart:[R]
Latch Clk clk_uart:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R50C97[0][B] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_38_s0/CLK
3.385 0.201 tC2Q RF 1 R50C97[0][B] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_38_s0/Q
3.504 0.119 tNET FF 1 R51C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R51C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s/CLK
3.196 0.012 tHld 1 R51C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path5

Path Summary:

Slack 0.308
Data Arrival Time 3.504
Data Required Time 3.196
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_36_s0
To u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s
Launch Clk clk_uart:[R]
Latch Clk clk_uart:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R50C97[0][A] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_36_s0/CLK
3.385 0.201 tC2Q RF 1 R50C97[0][A] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_36_s0/Q
3.504 0.119 tNET FF 1 R51C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R51C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s/CLK
3.196 0.012 tHld 1 R51C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.119, 37.200%; tC2Q: 0.201, 62.800%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path6

Path Summary:

Slack 0.315
Data Arrival Time 3.511
Data Required Time 3.196
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_35_s0
To u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_8_s
Launch Clk clk_uart:[R]
Latch Clk clk_uart:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R54C101[0][A] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_35_s0/CLK
3.386 0.202 tC2Q RR 1 R54C101[0][A] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_35_s0/Q
3.511 0.125 tNET RR 1 R54C99 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_8_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R54C99 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_8_s/CLK
3.196 0.012 tHld 1 R54C99 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_8_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.125, 38.162%; tC2Q: 0.202, 61.838%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path7

Path Summary:

Slack 0.324
Data Arrival Time 3.521
Data Required Time 3.196
From u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/gmii_txd_d2_0_s2
To u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/gmii_txd_d2_0_s14
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R43C50[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/gmii_txd_d2_0_s2/CLK
3.385 0.201 tC2Q RF 11 R43C50[0][A] u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/gmii_txd_d2_0_s2/Q
3.521 0.135 tNET FF 1 R42C50 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/gmii_txd_d2_0_s14/AD[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R42C50 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/gmii_txd_d2_0_s14/CLK
3.196 0.012 tHld 1 R42C50 u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/gmii_txd_d2_0_s14

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.135, 40.259%; tC2Q: 0.201, 59.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path8

Path Summary:

Slack 0.331
Data Arrival Time 3.527
Data Required Time 3.196
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_1_s0
To u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s
Launch Clk clk_uart:[R]
Latch Clk clk_uart:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R50C97[2][B] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_1_s0/CLK
3.385 0.201 tC2Q RF 18 R50C97[2][B] u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_1_s0/Q
3.527 0.142 tNET FF 1 R51C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s/WAD[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_uart
0.000 0.000 tCL RR 1248 PLL_L[0] u_pll_uart/PLL_inst/CLKOUT0
3.184 3.184 tNET RR 1 R51C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s/CLK
3.196 0.012 tHld 1 R51C97 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_0_9_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.142, 41.401%; tC2Q: 0.201, 58.599%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path9

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/rx_cnt_13_s3
To u_mac_rx_model_word/rx_cnt_13_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C123[0][A] u_mac_rx_model_word/rx_cnt_13_s3/CLK
3.386 0.202 tC2Q RR 5 R47C123[0][A] u_mac_rx_model_word/rx_cnt_13_s3/Q
3.389 0.002 tNET RR 1 R47C123[0][A] u_mac_rx_model_word/n2625_s6/I2
3.621 0.232 tINS RF 1 R47C123[0][A] u_mac_rx_model_word/n2625_s6/F
3.621 0.000 tNET FF 1 R47C123[0][A] u_mac_rx_model_word/rx_cnt_13_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C123[0][A] u_mac_rx_model_word/rx_cnt_13_s3/CLK
3.195 0.011 tHld 1 R47C123[0][A] u_mac_rx_model_word/rx_cnt_13_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path10

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/rx_cnt_23_s3
To u_mac_rx_model_word/rx_cnt_23_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C123[1][A] u_mac_rx_model_word/rx_cnt_23_s3/CLK
3.386 0.202 tC2Q RR 6 R44C123[1][A] u_mac_rx_model_word/rx_cnt_23_s3/Q
3.389 0.002 tNET RR 1 R44C123[1][A] u_mac_rx_model_word/n2615_s6/I2
3.621 0.232 tINS RF 1 R44C123[1][A] u_mac_rx_model_word/n2615_s6/F
3.621 0.000 tNET FF 1 R44C123[1][A] u_mac_rx_model_word/rx_cnt_23_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C123[1][A] u_mac_rx_model_word/rx_cnt_23_s3/CLK
3.195 0.011 tHld 1 R44C123[1][A] u_mac_rx_model_word/rx_cnt_23_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path11

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/rx_cnt_er_s9
To u_mac_rx_model_word/rx_cnt_er_s9
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C115[0][A] u_mac_rx_model_word/rx_cnt_er_s9/CLK
3.386 0.202 tC2Q RR 2 R47C115[0][A] u_mac_rx_model_word/rx_cnt_er_s9/Q
3.389 0.002 tNET RR 1 R47C115[0][A] u_mac_tx_model_word/n1072_s14/I1
3.621 0.232 tINS RF 1 R47C115[0][A] u_mac_tx_model_word/n1072_s14/F
3.621 0.000 tNET FF 1 R47C115[0][A] u_mac_rx_model_word/rx_cnt_er_s9/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C115[0][A] u_mac_rx_model_word/rx_cnt_er_s9/CLK
3.195 0.011 tHld 1 R47C115[0][A] u_mac_rx_model_word/rx_cnt_er_s9

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path12

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/data_start_byte_7_s0
To u_mac_rx_model_word/data_start_byte_7_s0
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C136[0][A] u_mac_rx_model_word/data_start_byte_7_s0/CLK
3.386 0.202 tC2Q RR 3 R44C136[0][A] u_mac_rx_model_word/data_start_byte_7_s0/Q
3.389 0.002 tNET RR 1 R44C136[0][A] u_mac_rx_model_word/n427_s/I1
3.621 0.232 tINS RF 1 R44C136[0][A] u_mac_rx_model_word/n427_s/SUM
3.621 0.000 tNET FF 1 R44C136[0][A] u_mac_rx_model_word/data_start_byte_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C136[0][A] u_mac_rx_model_word/data_start_byte_7_s0/CLK
3.195 0.011 tHld 1 R44C136[0][A] u_mac_rx_model_word/data_start_byte_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path13

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/rx_data_cnt_pause_2_s1
To u_mac_rx_model_word/rx_data_cnt_pause_2_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R54C135[0][A] u_mac_rx_model_word/rx_data_cnt_pause_2_s1/CLK
3.386 0.202 tC2Q RR 5 R54C135[0][A] u_mac_rx_model_word/rx_data_cnt_pause_2_s1/Q
3.389 0.002 tNET RR 1 R54C135[0][A] u_mac_rx_model_word/n2371_s1/I0
3.621 0.232 tINS RF 1 R54C135[0][A] u_mac_rx_model_word/n2371_s1/F
3.621 0.000 tNET FF 1 R54C135[0][A] u_mac_rx_model_word/rx_data_cnt_pause_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R54C135[0][A] u_mac_rx_model_word/rx_data_cnt_pause_2_s1/CLK
3.195 0.011 tHld 1 R54C135[0][A] u_mac_rx_model_word/rx_data_cnt_pause_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path14

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/rx_data_cnt_pause_5_s1
To u_mac_rx_model_word/rx_data_cnt_pause_5_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R54C135[1][A] u_mac_rx_model_word/rx_data_cnt_pause_5_s1/CLK
3.386 0.202 tC2Q RR 2 R54C135[1][A] u_mac_rx_model_word/rx_data_cnt_pause_5_s1/Q
3.389 0.002 tNET RR 1 R54C135[1][A] u_mac_rx_model_word/n2368_s1/I2
3.621 0.232 tINS RF 1 R54C135[1][A] u_mac_rx_model_word/n2368_s1/F
3.621 0.000 tNET FF 1 R54C135[1][A] u_mac_rx_model_word/rx_data_cnt_pause_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R54C135[1][A] u_mac_rx_model_word/rx_data_cnt_pause_5_s1/CLK
3.195 0.011 tHld 1 R54C135[1][A] u_mac_rx_model_word/rx_data_cnt_pause_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path15

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/rx_data_cnt_pause_6_s1
To u_mac_rx_model_word/rx_data_cnt_pause_6_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R53C133[1][A] u_mac_rx_model_word/rx_data_cnt_pause_6_s1/CLK
3.386 0.202 tC2Q RR 4 R53C133[1][A] u_mac_rx_model_word/rx_data_cnt_pause_6_s1/Q
3.389 0.002 tNET RR 1 R53C133[1][A] u_mac_rx_model_word/n2367_s3/I0
3.621 0.232 tINS RF 1 R53C133[1][A] u_mac_rx_model_word/n2367_s3/F
3.621 0.000 tNET FF 1 R53C133[1][A] u_mac_rx_model_word/rx_data_cnt_pause_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R53C133[1][A] u_mac_rx_model_word/rx_data_cnt_pause_6_s1/CLK
3.195 0.011 tHld 1 R53C133[1][A] u_mac_rx_model_word/rx_data_cnt_pause_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path16

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/shift_reg_pause_1_s1
To u_mac_rx_model_word/shift_reg_pause_1_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R50C128[0][A] u_mac_rx_model_word/shift_reg_pause_1_s1/CLK
3.386 0.202 tC2Q RR 2 R50C128[0][A] u_mac_rx_model_word/shift_reg_pause_1_s1/Q
3.389 0.002 tNET RR 1 R50C128[0][A] u_mac_rx_model_word/n2128_s0/I1
3.621 0.232 tINS RF 1 R50C128[0][A] u_mac_rx_model_word/n2128_s0/F
3.621 0.000 tNET FF 1 R50C128[0][A] u_mac_rx_model_word/shift_reg_pause_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R50C128[0][A] u_mac_rx_model_word/shift_reg_pause_1_s1/CLK
3.195 0.011 tHld 1 R50C128[0][A] u_mac_rx_model_word/shift_reg_pause_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path17

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/shift_reg_pause_4_s1
To u_mac_rx_model_word/shift_reg_pause_4_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C129[0][A] u_mac_rx_model_word/shift_reg_pause_4_s1/CLK
3.386 0.202 tC2Q RR 2 R44C129[0][A] u_mac_rx_model_word/shift_reg_pause_4_s1/Q
3.389 0.002 tNET RR 1 R44C129[0][A] u_mac_rx_model_word/n2125_s0/I1
3.621 0.232 tINS RF 1 R44C129[0][A] u_mac_rx_model_word/n2125_s0/F
3.621 0.000 tNET FF 1 R44C129[0][A] u_mac_rx_model_word/shift_reg_pause_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C129[0][A] u_mac_rx_model_word/shift_reg_pause_4_s1/CLK
3.195 0.011 tHld 1 R44C129[0][A] u_mac_rx_model_word/shift_reg_pause_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path18

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/shift_reg_pause_8_s1
To u_mac_rx_model_word/shift_reg_pause_8_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R50C128[1][A] u_mac_rx_model_word/shift_reg_pause_8_s1/CLK
3.386 0.202 tC2Q RR 2 R50C128[1][A] u_mac_rx_model_word/shift_reg_pause_8_s1/Q
3.389 0.002 tNET RR 1 R50C128[1][A] u_mac_rx_model_word/n2121_s0/I1
3.621 0.232 tINS RF 1 R50C128[1][A] u_mac_rx_model_word/n2121_s0/F
3.621 0.000 tNET FF 1 R50C128[1][A] u_mac_rx_model_word/shift_reg_pause_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R50C128[1][A] u_mac_rx_model_word/shift_reg_pause_8_s1/CLK
3.195 0.011 tHld 1 R50C128[1][A] u_mac_rx_model_word/shift_reg_pause_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path19

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/pause_address_29_s1
To u_mac_rx_model_word/pause_address_29_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R54C124[0][A] u_mac_rx_model_word/pause_address_29_s1/CLK
3.386 0.202 tC2Q RR 3 R54C124[0][A] u_mac_rx_model_word/pause_address_29_s1/Q
3.389 0.002 tNET RR 1 R54C124[0][A] u_mac_rx_model_word/n1608_s0/I3
3.621 0.232 tINS RF 1 R54C124[0][A] u_mac_rx_model_word/n1608_s0/F
3.621 0.000 tNET FF 1 R54C124[0][A] u_mac_rx_model_word/pause_address_29_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R54C124[0][A] u_mac_rx_model_word/pause_address_29_s1/CLK
3.195 0.011 tHld 1 R54C124[0][A] u_mac_rx_model_word/pause_address_29_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path20

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/pause_value_4_s1
To u_mac_rx_model_word/pause_value_4_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C131[1][A] u_mac_rx_model_word/pause_value_4_s1/CLK
3.386 0.202 tC2Q RR 5 R47C131[1][A] u_mac_rx_model_word/pause_value_4_s1/Q
3.389 0.002 tNET RR 1 R47C131[1][A] u_mac_rx_model_word/n1514_s0/I3
3.621 0.232 tINS RF 1 R47C131[1][A] u_mac_rx_model_word/n1514_s0/F
3.621 0.000 tNET FF 1 R47C131[1][A] u_mac_rx_model_word/pause_value_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C131[1][A] u_mac_rx_model_word/pause_value_4_s1/CLK
3.195 0.011 tHld 1 R47C131[1][A] u_mac_rx_model_word/pause_value_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path21

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/rx_data_cnt_4_s1
To u_mac_rx_model_word/rx_data_cnt_4_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R52C141[0][A] u_mac_rx_model_word/rx_data_cnt_4_s1/CLK
3.386 0.202 tC2Q RR 6 R52C141[0][A] u_mac_rx_model_word/rx_data_cnt_4_s1/Q
3.389 0.002 tNET RR 1 R52C141[0][A] u_mac_rx_model_word/n1254_s1/I2
3.621 0.232 tINS RF 1 R52C141[0][A] u_mac_rx_model_word/n1254_s1/F
3.621 0.000 tNET FF 1 R52C141[0][A] u_mac_rx_model_word/rx_data_cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R52C141[0][A] u_mac_rx_model_word/rx_data_cnt_4_s1/CLK
3.195 0.011 tHld 1 R52C141[0][A] u_mac_rx_model_word/rx_data_cnt_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path22

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/data_increase_add_1_0_s1
To u_mac_rx_model_word/data_increase_add_1_0_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C135[0][A] u_mac_rx_model_word/data_increase_add_1_0_s1/CLK
3.386 0.202 tC2Q RR 2 R47C135[0][A] u_mac_rx_model_word/data_increase_add_1_0_s1/Q
3.389 0.002 tNET RR 1 R47C135[0][A] u_mac_rx_model_word/n1166_s0/I0
3.621 0.232 tINS RF 1 R47C135[0][A] u_mac_rx_model_word/n1166_s0/F
3.621 0.000 tNET FF 1 R47C135[0][A] u_mac_rx_model_word/data_increase_add_1_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C135[0][A] u_mac_rx_model_word/data_increase_add_1_0_s1/CLK
3.195 0.011 tHld 1 R47C135[0][A] u_mac_rx_model_word/data_increase_add_1_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path23

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/shift_reg_3_s1
To u_mac_rx_model_word/shift_reg_3_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R49C132[1][A] u_mac_rx_model_word/shift_reg_3_s1/CLK
3.386 0.202 tC2Q RR 2 R49C132[1][A] u_mac_rx_model_word/shift_reg_3_s1/Q
3.389 0.002 tNET RR 1 R49C132[1][A] u_mac_rx_model_word/n952_s3/I0
3.621 0.232 tINS RF 1 R49C132[1][A] u_mac_rx_model_word/n952_s3/F
3.621 0.000 tNET FF 1 R49C132[1][A] u_mac_rx_model_word/shift_reg_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R49C132[1][A] u_mac_rx_model_word/shift_reg_3_s1/CLK
3.195 0.011 tHld 1 R49C132[1][A] u_mac_rx_model_word/shift_reg_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path24

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/shift_reg_8_s1
To u_mac_rx_model_word/shift_reg_8_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R48C133[1][A] u_mac_rx_model_word/shift_reg_8_s1/CLK
3.386 0.202 tC2Q RR 2 R48C133[1][A] u_mac_rx_model_word/shift_reg_8_s1/Q
3.389 0.002 tNET RR 1 R48C133[1][A] u_mac_rx_model_word/n947_s3/I0
3.621 0.232 tINS RF 1 R48C133[1][A] u_mac_rx_model_word/n947_s3/F
3.621 0.000 tNET FF 1 R48C133[1][A] u_mac_rx_model_word/shift_reg_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R48C133[1][A] u_mac_rx_model_word/shift_reg_8_s1/CLK
3.195 0.011 tHld 1 R48C133[1][A] u_mac_rx_model_word/shift_reg_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path25

Path Summary:

Slack 0.425
Data Arrival Time 3.621
Data Required Time 3.195
From u_mac_rx_model_word/shift_reg_18_s1
To u_mac_rx_model_word/shift_reg_18_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R50C132[1][A] u_mac_rx_model_word/shift_reg_18_s1/CLK
3.386 0.202 tC2Q RR 2 R50C132[1][A] u_mac_rx_model_word/shift_reg_18_s1/Q
3.389 0.002 tNET RR 1 R50C132[1][A] u_mac_rx_model_word/n937_s1/I0
3.621 0.232 tINS RF 1 R50C132[1][A] u_mac_rx_model_word/n937_s1/F
3.621 0.000 tNET FF 1 R50C132[1][A] u_mac_rx_model_word/shift_reg_18_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R50C132[1][A] u_mac_rx_model_word/shift_reg_18_s1/CLK
3.195 0.011 tHld 1 R50C132[1][A] u_mac_rx_model_word/shift_reg_18_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/update_data_end_s2
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R41C140[0][A] u_mac_tx_model_word/update_data_end_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R41C140[0][A] u_mac_tx_model_word/update_data_end_s2/CLK
9.608 -0.035 tSu 1 R41C140[0][A] u_mac_tx_model_word/update_data_end_s2

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path2

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/latch_data_end_s2
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R41C140[2][A] u_mac_tx_model_word/latch_data_end_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R41C140[2][A] u_mac_tx_model_word/latch_data_end_s2/CLK
9.608 -0.035 tSu 1 R41C140[2][A] u_mac_tx_model_word/latch_data_end_s2

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path3

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_0_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C120[0][B] u_mac_tx_model_word/tx_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C120[0][B] u_mac_tx_model_word/tx_cnt_0_s3/CLK
9.608 -0.035 tSu 1 R43C120[0][B] u_mac_tx_model_word/tx_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path4

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_1_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C119[0][A] u_mac_tx_model_word/tx_cnt_1_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C119[0][A] u_mac_tx_model_word/tx_cnt_1_s3/CLK
9.608 -0.035 tSu 1 R43C119[0][A] u_mac_tx_model_word/tx_cnt_1_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path5

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_4_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C120[0][A] u_mac_tx_model_word/tx_cnt_4_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C120[0][A] u_mac_tx_model_word/tx_cnt_4_s3/CLK
9.608 -0.035 tSu 1 R43C120[0][A] u_mac_tx_model_word/tx_cnt_4_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path6

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_7_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C119[0][B] u_mac_tx_model_word/tx_cnt_7_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C119[0][B] u_mac_tx_model_word/tx_cnt_7_s3/CLK
9.608 -0.035 tSu 1 R43C119[0][B] u_mac_tx_model_word/tx_cnt_7_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path7

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_10_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R42C119[2][A] u_mac_tx_model_word/tx_cnt_10_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R42C119[2][A] u_mac_tx_model_word/tx_cnt_10_s3/CLK
9.608 -0.035 tSu 1 R42C119[2][A] u_mac_tx_model_word/tx_cnt_10_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path8

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_13_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R40C121[0][A] u_mac_tx_model_word/tx_cnt_13_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R40C121[0][A] u_mac_tx_model_word/tx_cnt_13_s3/CLK
9.608 -0.035 tSu 1 R40C121[0][A] u_mac_tx_model_word/tx_cnt_13_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path9

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_16_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R40C120[2][A] u_mac_tx_model_word/tx_cnt_16_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R40C120[2][A] u_mac_tx_model_word/tx_cnt_16_s3/CLK
9.608 -0.035 tSu 1 R40C120[2][A] u_mac_tx_model_word/tx_cnt_16_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path10

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_23_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R42C119[1][A] u_mac_tx_model_word/tx_cnt_23_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R42C119[1][A] u_mac_tx_model_word/tx_cnt_23_s3/CLK
9.608 -0.035 tSu 1 R42C119[1][A] u_mac_tx_model_word/tx_cnt_23_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path11

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_28_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R40C119[1][A] u_mac_tx_model_word/tx_cnt_28_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R40C119[1][A] u_mac_tx_model_word/tx_cnt_28_s3/CLK
9.608 -0.035 tSu 1 R40C119[1][A] u_mac_tx_model_word/tx_cnt_28_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path12

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_30_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R42C118[1][A] u_mac_tx_model_word/tx_cnt_30_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R42C118[1][A] u_mac_tx_model_word/tx_cnt_30_s3/CLK
9.608 -0.035 tSu 1 R42C118[1][A] u_mac_tx_model_word/tx_cnt_30_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path13

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_cnt_er_s8
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R42C119[1][B] u_mac_tx_model_word/tx_cnt_er_s8/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R42C119[1][B] u_mac_tx_model_word/tx_cnt_er_s8/CLK
9.608 -0.035 tSu 1 R42C119[1][B] u_mac_tx_model_word/tx_cnt_er_s8

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path14

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_data_cnt_last_s4
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R42C124[2][B] u_mac_tx_model_word/tx_data_cnt_last_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R42C124[2][B] u_mac_tx_model_word/tx_data_cnt_last_s4/CLK
9.608 -0.035 tSu 1 R42C124[2][B] u_mac_tx_model_word/tx_data_cnt_last_s4

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path15

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/tx_data_cnt_1_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R41C136[2][A] u_mac_tx_model_word/tx_data_cnt_1_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R41C136[2][A] u_mac_tx_model_word/tx_data_cnt_1_s3/CLK
9.608 -0.035 tSu 1 R41C136[2][A] u_mac_tx_model_word/tx_data_cnt_1_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path16

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_increase_1_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R42C137[0][A] u_mac_tx_model_word/data_increase_1_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R42C137[0][A] u_mac_tx_model_word/data_increase_1_s3/CLK
9.608 -0.035 tSu 1 R42C137[0][A] u_mac_tx_model_word/data_increase_1_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path17

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_length_0_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R42C124[2][A] u_mac_tx_model_word/data_length_0_s3/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R42C124[2][A] u_mac_tx_model_word/data_length_0_s3/CLK
9.608 -0.035 tSu 1 R42C124[2][A] u_mac_tx_model_word/data_length_0_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path18

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_length_1_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R42C124[0][A] u_mac_tx_model_word/data_length_1_s3/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R42C124[0][A] u_mac_tx_model_word/data_length_1_s3/CLK
9.608 -0.035 tSu 1 R42C124[0][A] u_mac_tx_model_word/data_length_1_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path19

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_length_2_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C135[1][A] u_mac_tx_model_word/data_length_2_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C135[1][A] u_mac_tx_model_word/data_length_2_s3/CLK
9.608 -0.035 tSu 1 R43C135[1][A] u_mac_tx_model_word/data_length_2_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path20

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_length_3_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C135[0][B] u_mac_tx_model_word/data_length_3_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C135[0][B] u_mac_tx_model_word/data_length_3_s3/CLK
9.608 -0.035 tSu 1 R43C135[0][B] u_mac_tx_model_word/data_length_3_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path21

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_length_4_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C122[1][A] u_mac_tx_model_word/data_length_4_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C122[1][A] u_mac_tx_model_word/data_length_4_s3/CLK
9.608 -0.035 tSu 1 R43C122[1][A] u_mac_tx_model_word/data_length_4_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path22

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_length_5_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C123[2][A] u_mac_tx_model_word/data_length_5_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C123[2][A] u_mac_tx_model_word/data_length_5_s3/CLK
9.608 -0.035 tSu 1 R43C123[2][A] u_mac_tx_model_word/data_length_5_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path23

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_length_6_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C122[2][B] u_mac_tx_model_word/data_length_6_s3/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C122[2][B] u_mac_tx_model_word/data_length_6_s3/CLK
9.608 -0.035 tSu 1 R43C122[2][B] u_mac_tx_model_word/data_length_6_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path24

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_length_7_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R40C125[3][A] u_mac_tx_model_word/data_length_7_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R40C125[3][A] u_mac_tx_model_word/data_length_7_s3/CLK
9.608 -0.035 tSu 1 R40C125[3][A] u_mac_tx_model_word/data_length_7_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Path25

Path Summary:

Slack 3.437
Data Arrival Time 6.171
Data Required Time 9.608
From tx_mac_rst_n_s0
To u_mac_tx_model_word/data_length_8_s3
Launch Clk tx_mac_clk:[R]
Latch Clk tx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tx_mac_clk
0.000 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
3.243 3.243 tNET RR 1 R45C118[3][B] tx_mac_rst_n_s0/CLK
3.475 0.232 tC2Q RF 353 R45C118[3][B] tx_mac_rst_n_s0/Q
6.171 2.696 tNET FF 1 R43C122[0][B] u_mac_tx_model_word/data_length_8_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.400 6.400 active clock edge time
6.400 0.000 tx_mac_clk
6.400 0.000 tCL RR 1252 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
9.643 3.243 tNET RR 1 R43C122[0][B] u_mac_tx_model_word/data_length_8_s3/CLK
9.608 -0.035 tSu 1 R43C122[0][B] u_mac_tx_model_word/data_length_8_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 6.400
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.696, 92.076%; tC2Q: 0.232, 7.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.243, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/update_data_end_s2
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R45C139[0][A] u_mac_rx_model_word/update_data_end_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C139[0][A] u_mac_rx_model_word/update_data_end_s2/CLK
3.195 0.011 tHld 1 R45C139[0][A] u_mac_rx_model_word/update_data_end_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path2

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/latch_data_end_s2
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R45C139[0][B] u_mac_rx_model_word/latch_data_end_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C139[0][B] u_mac_rx_model_word/latch_data_end_s2/CLK
3.195 0.011 tHld 1 R45C139[0][B] u_mac_rx_model_word/latch_data_end_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path3

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_0_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C123[2][A] u_mac_rx_model_word/rx_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C123[2][A] u_mac_rx_model_word/rx_cnt_0_s3/CLK
3.195 0.011 tHld 1 R44C123[2][A] u_mac_rx_model_word/rx_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path4

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_1_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C124[0][A] u_mac_rx_model_word/rx_cnt_1_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C124[0][A] u_mac_rx_model_word/rx_cnt_1_s3/CLK
3.195 0.011 tHld 1 R44C124[0][A] u_mac_rx_model_word/rx_cnt_1_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path5

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_4_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C123[0][A] u_mac_rx_model_word/rx_cnt_4_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C123[0][A] u_mac_rx_model_word/rx_cnt_4_s3/CLK
3.195 0.011 tHld 1 R44C123[0][A] u_mac_rx_model_word/rx_cnt_4_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path6

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_7_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C123[0][B] u_mac_rx_model_word/rx_cnt_7_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C123[0][B] u_mac_rx_model_word/rx_cnt_7_s3/CLK
3.195 0.011 tHld 1 R44C123[0][B] u_mac_rx_model_word/rx_cnt_7_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path7

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_10_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R47C123[1][A] u_mac_rx_model_word/rx_cnt_10_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C123[1][A] u_mac_rx_model_word/rx_cnt_10_s3/CLK
3.195 0.011 tHld 1 R47C123[1][A] u_mac_rx_model_word/rx_cnt_10_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path8

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_13_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R47C123[0][A] u_mac_rx_model_word/rx_cnt_13_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C123[0][A] u_mac_rx_model_word/rx_cnt_13_s3/CLK
3.195 0.011 tHld 1 R47C123[0][A] u_mac_rx_model_word/rx_cnt_13_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path9

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_16_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C123[1][B] u_mac_rx_model_word/rx_cnt_16_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C123[1][B] u_mac_rx_model_word/rx_cnt_16_s3/CLK
3.195 0.011 tHld 1 R44C123[1][B] u_mac_rx_model_word/rx_cnt_16_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path10

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_21_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R47C123[0][B] u_mac_rx_model_word/rx_cnt_21_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C123[0][B] u_mac_rx_model_word/rx_cnt_21_s3/CLK
3.195 0.011 tHld 1 R47C123[0][B] u_mac_rx_model_word/rx_cnt_21_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path11

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_23_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C123[1][A] u_mac_rx_model_word/rx_cnt_23_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C123[1][A] u_mac_rx_model_word/rx_cnt_23_s3/CLK
3.195 0.011 tHld 1 R44C123[1][A] u_mac_rx_model_word/rx_cnt_23_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path12

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_28_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R47C123[2][A] u_mac_rx_model_word/rx_cnt_28_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C123[2][A] u_mac_rx_model_word/rx_cnt_28_s3/CLK
3.195 0.011 tHld 1 R47C123[2][A] u_mac_rx_model_word/rx_cnt_28_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path13

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_30_s3
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R47C123[1][B] u_mac_rx_model_word/rx_cnt_30_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C123[1][B] u_mac_rx_model_word/rx_cnt_30_s3/CLK
3.195 0.011 tHld 1 R47C123[1][B] u_mac_rx_model_word/rx_cnt_30_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path14

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_er_s9
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R47C115[0][A] u_mac_rx_model_word/rx_cnt_er_s9/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C115[0][A] u_mac_rx_model_word/rx_cnt_er_s9/CLK
3.195 0.011 tHld 1 R47C115[0][A] u_mac_rx_model_word/rx_cnt_er_s9

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path15

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_error_all_check_s4
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R48C116[3][A] u_mac_rx_model_word/rx_error_all_check_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R48C116[3][A] u_mac_rx_model_word/rx_error_all_check_s4/CLK
3.195 0.011 tHld 1 R48C116[3][A] u_mac_rx_model_word/rx_error_all_check_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path16

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_error_all_pause_check_s4
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R56C128[0][A] u_mac_rx_model_word/rx_error_all_pause_check_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R56C128[0][A] u_mac_rx_model_word/rx_error_all_pause_check_s4/CLK
3.195 0.011 tHld 1 R56C128[0][A] u_mac_rx_model_word/rx_error_all_pause_check_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path17

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_error_all_data_check_s4
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R56C128[0][B] u_mac_rx_model_word/rx_error_all_data_check_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R56C128[0][B] u_mac_rx_model_word/rx_error_all_data_check_s4/CLK
3.195 0.011 tHld 1 R56C128[0][B] u_mac_rx_model_word/rx_error_all_data_check_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path18

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_data_cnt_last_s5
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R50C139[3][A] u_mac_rx_model_word/rx_data_cnt_last_s5/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R50C139[3][A] u_mac_rx_model_word/rx_data_cnt_last_s5/CLK
3.195 0.011 tHld 1 R50C139[3][A] u_mac_rx_model_word/rx_data_cnt_last_s5

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path19

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_pause_state_s5
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R52C136[3][A] u_mac_rx_model_word/rx_pause_state_s5/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R52C136[3][A] u_mac_rx_model_word/rx_pause_state_s5/CLK
3.195 0.011 tHld 1 R52C136[3][A] u_mac_rx_model_word/rx_pause_state_s5

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path20

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_2_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R45C121[0][A] u_mac_rx_model_word/rx_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C121[0][A] u_mac_rx_model_word/rx_cnt_2_s1/CLK
3.195 0.011 tHld 1 R45C121[0][A] u_mac_rx_model_word/rx_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path21

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_3_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C121[0][A] u_mac_rx_model_word/rx_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C121[0][A] u_mac_rx_model_word/rx_cnt_3_s1/CLK
3.195 0.011 tHld 1 R44C121[0][A] u_mac_rx_model_word/rx_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path22

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_5_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C121[1][A] u_mac_rx_model_word/rx_cnt_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C121[1][A] u_mac_rx_model_word/rx_cnt_5_s1/CLK
3.195 0.011 tHld 1 R44C121[1][A] u_mac_rx_model_word/rx_cnt_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path23

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_6_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C121[0][B] u_mac_rx_model_word/rx_cnt_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C121[0][B] u_mac_rx_model_word/rx_cnt_6_s1/CLK
3.195 0.011 tHld 1 R44C121[0][B] u_mac_rx_model_word/rx_cnt_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path24

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_8_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R44C121[2][A] u_mac_rx_model_word/rx_cnt_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R44C121[2][A] u_mac_rx_model_word/rx_cnt_8_s1/CLK
3.195 0.011 tHld 1 R44C121[2][A] u_mac_rx_model_word/rx_cnt_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Path25

Path Summary:

Slack 1.678
Data Arrival Time 4.873
Data Required Time 3.195
From rx_mac_rst_n_s0
To u_mac_rx_model_word/rx_cnt_9_s1
Launch Clk rx_mac_clk:[R]
Latch Clk rx_mac_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R45C119[2][B] rx_mac_rst_n_s0/CLK
3.386 0.202 tC2Q RR 816 R45C119[2][B] rx_mac_rst_n_s0/Q
4.873 1.487 tNET RR 1 R47C121[0][A] u_mac_rx_model_word/rx_cnt_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rx_mac_clk
0.000 0.000 tCL RR 1938 - u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
3.184 3.184 tNET RR 1 R47C121[0][A] u_mac_rx_model_word/rx_cnt_9_s1/CLK
3.195 0.011 tHld 1 R47C121[0][A] u_mac_rx_model_word/rx_cnt_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.487, 88.039%; tC2Q: 0.202, 11.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 3.184, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: configuration_vector_12_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF configuration_vector_12_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR configuration_vector_12_s0/CLK

MPW2

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_decode_rxd_d2_11_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_decode_rxd_d2_11_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/rx_decode_rxd_d2_11_s0/CLK

MPW3

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rxd_m_set_l_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rxd_m_set_l_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/gmii_rxd_m_set_l_s0/CLK

MPW4

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_dv_reg_d1_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_dv_reg_d1_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_rx_dv_reg_d1_5_s0/CLK

MPW5

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_col_reg_d1_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_col_reg_d1_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/gmii_col_reg_d1_1_s0/CLK

MPW6

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_mac_data_9_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_mac_data_9_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_mac_data_9_s1/CLK

MPW7

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_12_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_12_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_12_s1/CLK

MPW8

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_4_s1/CLK

MPW9

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_0_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_0_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/rx_frm_lgt_reg_0_s1/CLK

MPW10

MPW Summary:

Slack: 2.123
Actual Width: 3.123
Required Width: 1.000
Type: Low Pulse Width
Clock: rx_mac_clk
Objects: u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/vlan_reg_14_s1

Late clock Path:

AT DELAY TYPE RF NODE
3.200 0.000 active clock edge time
3.200 0.000 rx_mac_clk
3.200 0.000 tCL FF u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.461 3.261 tNET FF u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/vlan_reg_14_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
6.400 0.000 active clock edge time
6.400 0.000 rx_mac_clk
6.400 0.000 tCL RR u_Serdes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
9.584 3.184 tNET RR u_Serdes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/vlan_reg_14_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
1938 rx_mac_clk 0.072 3.261
1252 tx_mac_clk 0.098 3.261
1248 clk_uart 87.390 3.261
1002 rstn_uart 95.181 2.903
199 crc_result_valid 1.939 2.994
162 rx_pause_state 3.247 2.515
148 rx_mac_valid_d3 0.685 2.819
148 n1465_4 2.865 1.418
133 latch_data_end_8 3.683 2.059
123 rx_mac_valid_d1 0.197 1.884

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R42C91 75.00%
R42C92 75.00%
R50C97 75.00%
R52C74 73.61%
R43C92 72.22%
R42C93 72.22%
R42C95 69.44%
R42C99 69.44%
R47C70 69.44%
R51C92 66.67%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name rx_mac_clk -period 6.4 -waveform {0 3.2} [get_nets {rx_mac_clk}]
TC_CLOCK Actived create_clock -name tx_mac_clk -period 6.4 -waveform {0 3.2} [get_nets {tx_mac_clk}]
TC_CLOCK Actived create_clock -name clk_in -period 19.048 -waveform {0 10} [get_nets {clk_in}]
TC_CLOCK Actived create_clock -name board_clk -period 5 -waveform {0 2.5} [get_nets {board_clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk_uart -source [get_nets {board_clk}] -master_clock board_clk -divide_by 80 -multiply_by 4 [get_nets {clk_uart}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_in clk_uart }] -to [get_clocks {tx_mac_clk rx_mac_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {tx_mac_clk rx_mac_clk}] -to [get_clocks {clk_uart }]