Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_AEC_refDesign\proj\src\aec\aec.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_AEC_refDesign\proj\src\top.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_AEC_refDesign\proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.01 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Fri Mar 7 09:55:16 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.969s, Peak memory usage = 281.211MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.141s, Peak memory usage = 281.211MB Optimizing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 281.211MB Optimizing Phase 2: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.417s, Peak memory usage = 281.211MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 281.211MB Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 281.211MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 281.211MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 281.211MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.142s, Peak memory usage = 281.211MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.179s, Peak memory usage = 281.211MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 281.211MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 299.285MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.172s, Peak memory usage = 299.285MB Generate output files: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.33s, Peak memory usage = 303.879MB |
Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 303.879MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 39 |
I/O Buf | 39 |
    IBUF | 5 |
    OBUF | 34 |
Register | 2174 |
    DFFRE | 574 |
    DFFPE | 57 |
    DFFCE | 1543 |
LUT | 2471 |
    LUT2 | 287 |
    LUT3 | 436 |
    LUT4 | 1748 |
MUX | 1 |
    MUX16 | 1 |
ALU | 375 |
    ALU | 375 |
INV | 83 |
    INV | 83 |
DSP | |
    MULT27X36 | 4 |
BSRAM | 51 |
    SDPB | 41 |
    SDPX9B | 2 |
    pROM | 8 |
Black Box | 1 |
    GW_JTAG | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2937(2562 LUT, 375 ALU) / 23040 | 13% |
Register | 2174 / 23685 | 10% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 2174 / 23685 | 10% |
BSRAM | 51 / 56 | 92% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.000(MHz) | 106.765(MHz) | 13 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 0.634 |
Data Arrival Time | 9.678 |
Data Required Time | 10.311 |
From | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
To | AEC_uut/AEC_inst/acc_0_34_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 46 | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
0.669 | 0.294 | tC2Q | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/n10_s4/DOUT[0] |
1.044 | 0.375 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_26_s/I1 |
1.606 | 0.563 | tINS | RF | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_26_s/COUT |
1.606 | 0.000 | tNET | FF | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_27_s/CIN |
1.656 | 0.050 | tINS | FR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_27_s/COUT |
1.656 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_28_s/CIN |
1.706 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_28_s/COUT |
1.706 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_29_s/CIN |
1.756 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_29_s/COUT |
1.756 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_30_s/CIN |
1.806 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_30_s/COUT |
1.806 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_31_s/CIN |
1.856 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_31_s/COUT |
1.856 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_32_s/CIN |
1.906 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_32_s/COUT |
1.906 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_33_s/CIN |
1.956 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_33_s/COUT |
1.956 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_34_s/CIN |
2.006 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_34_s/COUT |
2.006 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_35_s/CIN |
2.056 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_35_s/COUT |
2.056 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_36_s/CIN |
2.106 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_36_s/COUT |
2.106 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_37_s/CIN |
2.156 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_37_s/COUT |
2.156 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_38_s/CIN |
2.206 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_38_s/COUT |
2.206 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_39_s/CIN |
2.256 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_39_s/COUT |
2.256 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_40_s/CIN |
2.306 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_40_s/COUT |
2.306 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_41_s/CIN |
2.356 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_41_s/COUT |
2.356 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_42_s/CIN |
2.406 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_42_s/COUT |
2.406 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_43_s/CIN |
2.456 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_43_s/COUT |
2.456 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_44_s/CIN |
2.506 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_44_s/COUT |
2.506 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_45_s/CIN |
2.556 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_45_s/COUT |
2.556 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_46_s/CIN |
2.606 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_46_s/COUT |
2.606 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_47_s/CIN |
2.656 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_47_s/COUT |
2.656 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_48_s/CIN |
2.706 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_48_s/COUT |
2.706 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_49_s/CIN |
2.756 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_49_s/COUT |
2.756 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_50_s/CIN |
2.806 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_50_s/COUT |
2.806 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_51_s/CIN |
2.856 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_51_s/COUT |
2.856 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_52_s/CIN |
2.906 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_52_s/COUT |
2.906 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_53_s/CIN |
2.956 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_53_s/COUT |
2.956 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_54_s/CIN |
3.006 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_54_s/COUT |
3.006 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_55_s/CIN |
3.056 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_55_s/COUT |
3.056 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_56_s/CIN |
3.106 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_56_s/COUT |
3.106 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_57_s/CIN |
3.156 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_57_s/COUT |
3.156 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_58_s/CIN |
3.206 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_58_s/COUT |
3.206 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_59_s/CIN |
3.256 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_59_s/COUT |
3.256 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_60_s/CIN |
3.306 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_60_s/COUT |
3.306 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_61_s/CIN |
3.356 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_61_s/COUT |
3.356 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_62_s/CIN |
3.406 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_62_s/COUT |
3.406 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_63_s/CIN |
3.456 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_63_s/COUT |
3.456 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_64_s/CIN |
3.506 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_64_s/COUT |
3.506 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_65_s/CIN |
3.556 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_65_s/COUT |
3.556 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_66_s/CIN |
3.606 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_66_s/COUT |
3.606 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_67_s/CIN |
3.656 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_67_s/COUT |
3.656 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_68_s/CIN |
3.706 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_68_s/COUT |
3.706 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_69_s/CIN |
3.756 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_69_s/COUT |
3.756 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_70_s/CIN |
3.806 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_70_s/COUT |
3.806 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_71_s/CIN |
4.050 | 0.244 | tINS | RR | 4 | AEC_uut/AEC_inst/mult36x36_0/mult36x36_0_mult_result_71_s/SUM |
4.425 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_35_s13/I1 |
4.941 | 0.516 | tINS | RR | 2 | AEC_uut/AEC_inst/value_for_acc_0_add_35_s13/F |
5.316 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_34_s15/I2 |
5.778 | 0.461 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_34_s15/F |
6.153 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_34_s10/I1 |
6.669 | 0.516 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_34_s10/F |
7.044 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_34_s7/I3 |
7.306 | 0.262 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_34_s7/F |
7.681 | 0.375 | tNET | RR | 2 | AEC_uut/AEC_inst/n1521_s/I1 |
8.411 | 0.730 | tINS | RR | 1 | AEC_uut/AEC_inst/n1521_s/SUM |
8.786 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/n1557_s2/I1 |
9.303 | 0.516 | tINS | RR | 1 | AEC_uut/AEC_inst/n1557_s2/F |
9.678 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/acc_0_34_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/acc_0_34_s1/CLK |
10.311 | -0.064 | tSu | 1 | AEC_uut/AEC_inst/acc_0_34_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 6.009, 64.592%; route: 3.000, 32.249%; tC2Q: 0.294, 3.159% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 0.961 |
Data Arrival Time | 9.350 |
Data Required Time | 10.311 |
From | AEC_uut/AEC_inst/mult36x36_1/n10_s4 |
To | AEC_uut/AEC_inst/acc_0_33_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 46 | AEC_uut/AEC_inst/mult36x36_1/n10_s4/CLK[0] |
0.669 | 0.294 | tC2Q | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/n10_s4/DOUT[0] |
1.044 | 0.375 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_26_s/I1 |
1.606 | 0.563 | tINS | RF | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_26_s/COUT |
1.606 | 0.000 | tNET | FF | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_27_s/CIN |
1.656 | 0.050 | tINS | FR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_27_s/COUT |
1.656 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_28_s/CIN |
1.706 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_28_s/COUT |
1.706 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_29_s/CIN |
1.756 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_29_s/COUT |
1.756 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_30_s/CIN |
1.806 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_30_s/COUT |
1.806 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_31_s/CIN |
1.856 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_31_s/COUT |
1.856 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_32_s/CIN |
1.906 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_32_s/COUT |
1.906 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_33_s/CIN |
1.956 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_33_s/COUT |
1.956 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_34_s/CIN |
2.006 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_34_s/COUT |
2.006 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_35_s/CIN |
2.056 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_35_s/COUT |
2.056 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_36_s/CIN |
2.106 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_36_s/COUT |
2.106 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_37_s/CIN |
2.156 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_37_s/COUT |
2.156 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_38_s/CIN |
2.206 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_38_s/COUT |
2.206 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_39_s/CIN |
2.256 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_39_s/COUT |
2.256 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_40_s/CIN |
2.306 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_40_s/COUT |
2.306 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_41_s/CIN |
2.356 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_41_s/COUT |
2.356 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_42_s/CIN |
2.406 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_42_s/COUT |
2.406 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_43_s/CIN |
2.456 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_43_s/COUT |
2.456 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_44_s/CIN |
2.506 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_44_s/COUT |
2.506 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_45_s/CIN |
2.556 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_45_s/COUT |
2.556 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_46_s/CIN |
2.606 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_46_s/COUT |
2.606 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_47_s/CIN |
2.656 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_47_s/COUT |
2.656 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_48_s/CIN |
2.706 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_48_s/COUT |
2.706 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_49_s/CIN |
2.756 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_49_s/COUT |
2.756 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_50_s/CIN |
2.806 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_50_s/COUT |
2.806 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_51_s/CIN |
2.856 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_51_s/COUT |
2.856 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_52_s/CIN |
2.906 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_52_s/COUT |
2.906 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_53_s/CIN |
2.956 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_53_s/COUT |
2.956 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_54_s/CIN |
3.006 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_54_s/COUT |
3.006 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_55_s/CIN |
3.056 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_55_s/COUT |
3.056 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_56_s/CIN |
3.106 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_56_s/COUT |
3.106 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_57_s/CIN |
3.156 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_57_s/COUT |
3.156 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_58_s/CIN |
3.206 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_58_s/COUT |
3.206 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_59_s/CIN |
3.256 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_59_s/COUT |
3.256 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_60_s/CIN |
3.500 | 0.244 | tINS | RR | 4 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_60_s/SUM |
3.875 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s20/I1 |
4.391 | 0.516 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s20/F |
4.766 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s13/I2 |
5.228 | 0.461 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s13/F |
5.603 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s10/I3 |
5.865 | 0.262 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s10/F |
6.240 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s7/I3 |
6.503 | 0.262 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s7/F |
6.878 | 0.375 | tNET | RR | 2 | AEC_uut/AEC_inst/n1531_s/I1 |
7.440 | 0.563 | tINS | RF | 1 | AEC_uut/AEC_inst/n1531_s/COUT |
7.440 | 0.000 | tNET | FF | 2 | AEC_uut/AEC_inst/n1530_s/CIN |
7.490 | 0.050 | tINS | FR | 1 | AEC_uut/AEC_inst/n1530_s/COUT |
7.490 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1529_s/CIN |
7.540 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1529_s/COUT |
7.540 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1528_s/CIN |
7.590 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1528_s/COUT |
7.590 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1527_s/CIN |
7.640 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1527_s/COUT |
7.640 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1526_s/CIN |
7.690 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1526_s/COUT |
7.690 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1525_s/CIN |
7.740 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1525_s/COUT |
7.740 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1524_s/CIN |
7.790 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1524_s/COUT |
7.790 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1523_s/CIN |
7.840 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1523_s/COUT |
7.840 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1522_s/CIN |
8.084 | 0.244 | tINS | RR | 1 | AEC_uut/AEC_inst/n1522_s/SUM |
8.459 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/n1558_s2/I1 |
8.975 | 0.516 | tINS | RR | 1 | AEC_uut/AEC_inst/n1558_s2/F |
9.350 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/acc_0_33_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/acc_0_33_s1/CLK |
10.311 | -0.064 | tSu | 1 | AEC_uut/AEC_inst/acc_0_33_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 5.681, 63.300%; route: 3.000, 33.426%; tC2Q: 0.294, 3.274% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 1.011 |
Data Arrival Time | 9.300 |
Data Required Time | 10.311 |
From | AEC_uut/AEC_inst/mult36x36_1/n10_s4 |
To | AEC_uut/AEC_inst/acc_0_32_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 46 | AEC_uut/AEC_inst/mult36x36_1/n10_s4/CLK[0] |
0.669 | 0.294 | tC2Q | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/n10_s4/DOUT[0] |
1.044 | 0.375 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_26_s/I1 |
1.606 | 0.563 | tINS | RF | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_26_s/COUT |
1.606 | 0.000 | tNET | FF | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_27_s/CIN |
1.656 | 0.050 | tINS | FR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_27_s/COUT |
1.656 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_28_s/CIN |
1.706 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_28_s/COUT |
1.706 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_29_s/CIN |
1.756 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_29_s/COUT |
1.756 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_30_s/CIN |
1.806 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_30_s/COUT |
1.806 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_31_s/CIN |
1.856 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_31_s/COUT |
1.856 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_32_s/CIN |
1.906 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_32_s/COUT |
1.906 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_33_s/CIN |
1.956 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_33_s/COUT |
1.956 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_34_s/CIN |
2.006 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_34_s/COUT |
2.006 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_35_s/CIN |
2.056 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_35_s/COUT |
2.056 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_36_s/CIN |
2.106 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_36_s/COUT |
2.106 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_37_s/CIN |
2.156 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_37_s/COUT |
2.156 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_38_s/CIN |
2.206 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_38_s/COUT |
2.206 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_39_s/CIN |
2.256 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_39_s/COUT |
2.256 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_40_s/CIN |
2.306 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_40_s/COUT |
2.306 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_41_s/CIN |
2.356 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_41_s/COUT |
2.356 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_42_s/CIN |
2.406 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_42_s/COUT |
2.406 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_43_s/CIN |
2.456 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_43_s/COUT |
2.456 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_44_s/CIN |
2.506 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_44_s/COUT |
2.506 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_45_s/CIN |
2.556 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_45_s/COUT |
2.556 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_46_s/CIN |
2.606 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_46_s/COUT |
2.606 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_47_s/CIN |
2.656 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_47_s/COUT |
2.656 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_48_s/CIN |
2.706 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_48_s/COUT |
2.706 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_49_s/CIN |
2.756 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_49_s/COUT |
2.756 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_50_s/CIN |
2.806 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_50_s/COUT |
2.806 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_51_s/CIN |
2.856 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_51_s/COUT |
2.856 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_52_s/CIN |
2.906 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_52_s/COUT |
2.906 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_53_s/CIN |
2.956 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_53_s/COUT |
2.956 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_54_s/CIN |
3.006 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_54_s/COUT |
3.006 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_55_s/CIN |
3.056 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_55_s/COUT |
3.056 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_56_s/CIN |
3.106 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_56_s/COUT |
3.106 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_57_s/CIN |
3.156 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_57_s/COUT |
3.156 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_58_s/CIN |
3.206 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_58_s/COUT |
3.206 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_59_s/CIN |
3.256 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_59_s/COUT |
3.256 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_60_s/CIN |
3.500 | 0.244 | tINS | RR | 4 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_60_s/SUM |
3.875 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s20/I1 |
4.391 | 0.516 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s20/F |
4.766 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s13/I2 |
5.228 | 0.461 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s13/F |
5.603 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s10/I3 |
5.865 | 0.262 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s10/F |
6.240 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s7/I3 |
6.503 | 0.262 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s7/F |
6.878 | 0.375 | tNET | RR | 2 | AEC_uut/AEC_inst/n1531_s/I1 |
7.440 | 0.563 | tINS | RF | 1 | AEC_uut/AEC_inst/n1531_s/COUT |
7.440 | 0.000 | tNET | FF | 2 | AEC_uut/AEC_inst/n1530_s/CIN |
7.490 | 0.050 | tINS | FR | 1 | AEC_uut/AEC_inst/n1530_s/COUT |
7.490 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1529_s/CIN |
7.540 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1529_s/COUT |
7.540 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1528_s/CIN |
7.590 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1528_s/COUT |
7.590 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1527_s/CIN |
7.640 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1527_s/COUT |
7.640 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1526_s/CIN |
7.690 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1526_s/COUT |
7.690 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1525_s/CIN |
7.740 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1525_s/COUT |
7.740 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1524_s/CIN |
7.790 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1524_s/COUT |
7.790 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1523_s/CIN |
8.034 | 0.244 | tINS | RR | 1 | AEC_uut/AEC_inst/n1523_s/SUM |
8.409 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/n1559_s2/I1 |
8.925 | 0.516 | tINS | RR | 1 | AEC_uut/AEC_inst/n1559_s2/F |
9.300 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/acc_0_32_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/acc_0_32_s1/CLK |
10.311 | -0.064 | tSu | 1 | AEC_uut/AEC_inst/acc_0_32_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 5.631, 63.094%; route: 3.000, 33.613%; tC2Q: 0.294, 3.293% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 1.032 |
Data Arrival Time | 5.499 |
Data Required Time | 6.531 |
From | AEC_uut/AEC_inst/MatrixInverse_inst/need_process_array_1_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s3 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/MatrixInverse_inst/need_process_array_1_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 3 | AEC_uut/AEC_inst/MatrixInverse_inst/need_process_array_1_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/mult_data_0_b_34_s13/I0 |
1.659 | 0.526 | tINS | RR | 16 | AEC_uut/AEC_inst/mult_data_0_b_34_s13/F |
2.034 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/mult_data_0_a_35_s11/I2 |
2.495 | 0.461 | tINS | RR | 58 | AEC_uut/AEC_inst/mult_data_0_a_35_s11/F |
2.870 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/mult_data_0_b_0_s10/I1 |
3.386 | 0.516 | tINS | RR | 1 | AEC_uut/AEC_inst/mult_data_0_b_0_s10/F |
3.761 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/mult_data_0_b_0_s7/I2 |
4.222 | 0.461 | tINS | RR | 2 | AEC_uut/AEC_inst/mult_data_0_b_0_s7/F |
4.597 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/mult_data_0_b_0_s6/I0 |
5.124 | 0.526 | tINS | RR | 1 | AEC_uut/AEC_inst/mult_data_0_b_0_s6/F |
5.499 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/n10_s3/A[0] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/mult36x36_0/n10_s3/CLK[0] |
6.531 | -3.844 | tSu | 1 | AEC_uut/AEC_inst/mult36x36_0/n10_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.491, 48.622%; route: 2.250, 43.913%; tC2Q: 0.382, 7.465% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 1.061 |
Data Arrival Time | 9.250 |
Data Required Time | 10.311 |
From | AEC_uut/AEC_inst/mult36x36_1/n10_s4 |
To | AEC_uut/AEC_inst/acc_0_31_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 46 | AEC_uut/AEC_inst/mult36x36_1/n10_s4/CLK[0] |
0.669 | 0.294 | tC2Q | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/n10_s4/DOUT[0] |
1.044 | 0.375 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_26_s/I1 |
1.606 | 0.563 | tINS | RF | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_26_s/COUT |
1.606 | 0.000 | tNET | FF | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_27_s/CIN |
1.656 | 0.050 | tINS | FR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_27_s/COUT |
1.656 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_28_s/CIN |
1.706 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_28_s/COUT |
1.706 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_29_s/CIN |
1.756 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_29_s/COUT |
1.756 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_30_s/CIN |
1.806 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_30_s/COUT |
1.806 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_31_s/CIN |
1.856 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_31_s/COUT |
1.856 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_32_s/CIN |
1.906 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_32_s/COUT |
1.906 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_33_s/CIN |
1.956 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_33_s/COUT |
1.956 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_34_s/CIN |
2.006 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_34_s/COUT |
2.006 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_35_s/CIN |
2.056 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_35_s/COUT |
2.056 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_36_s/CIN |
2.106 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_36_s/COUT |
2.106 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_37_s/CIN |
2.156 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_37_s/COUT |
2.156 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_38_s/CIN |
2.206 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_38_s/COUT |
2.206 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_39_s/CIN |
2.256 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_39_s/COUT |
2.256 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_40_s/CIN |
2.306 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_40_s/COUT |
2.306 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_41_s/CIN |
2.356 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_41_s/COUT |
2.356 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_42_s/CIN |
2.406 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_42_s/COUT |
2.406 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_43_s/CIN |
2.456 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_43_s/COUT |
2.456 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_44_s/CIN |
2.506 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_44_s/COUT |
2.506 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_45_s/CIN |
2.556 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_45_s/COUT |
2.556 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_46_s/CIN |
2.606 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_46_s/COUT |
2.606 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_47_s/CIN |
2.656 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_47_s/COUT |
2.656 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_48_s/CIN |
2.706 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_48_s/COUT |
2.706 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_49_s/CIN |
2.756 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_49_s/COUT |
2.756 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_50_s/CIN |
2.806 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_50_s/COUT |
2.806 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_51_s/CIN |
2.856 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_51_s/COUT |
2.856 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_52_s/CIN |
2.906 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_52_s/COUT |
2.906 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_53_s/CIN |
2.956 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_53_s/COUT |
2.956 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_54_s/CIN |
3.006 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_54_s/COUT |
3.006 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_55_s/CIN |
3.056 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_55_s/COUT |
3.056 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_56_s/CIN |
3.106 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_56_s/COUT |
3.106 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_57_s/CIN |
3.156 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_57_s/COUT |
3.156 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_58_s/CIN |
3.206 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_58_s/COUT |
3.206 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_59_s/CIN |
3.256 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_59_s/COUT |
3.256 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_60_s/CIN |
3.500 | 0.244 | tINS | RR | 4 | AEC_uut/AEC_inst/mult36x36_1/mult36x36_1_mult_result_60_s/SUM |
3.875 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s20/I1 |
4.391 | 0.516 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s20/F |
4.766 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s13/I2 |
5.228 | 0.461 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s13/F |
5.603 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s10/I3 |
5.865 | 0.262 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s10/F |
6.240 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s7/I3 |
6.503 | 0.262 | tINS | RR | 1 | AEC_uut/AEC_inst/value_for_acc_0_add_24_s7/F |
6.878 | 0.375 | tNET | RR | 2 | AEC_uut/AEC_inst/n1531_s/I1 |
7.440 | 0.563 | tINS | RF | 1 | AEC_uut/AEC_inst/n1531_s/COUT |
7.440 | 0.000 | tNET | FF | 2 | AEC_uut/AEC_inst/n1530_s/CIN |
7.490 | 0.050 | tINS | FR | 1 | AEC_uut/AEC_inst/n1530_s/COUT |
7.490 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1529_s/CIN |
7.540 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1529_s/COUT |
7.540 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1528_s/CIN |
7.590 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1528_s/COUT |
7.590 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1527_s/CIN |
7.640 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1527_s/COUT |
7.640 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1526_s/CIN |
7.690 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1526_s/COUT |
7.690 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1525_s/CIN |
7.740 | 0.050 | tINS | RR | 1 | AEC_uut/AEC_inst/n1525_s/COUT |
7.740 | 0.000 | tNET | RR | 2 | AEC_uut/AEC_inst/n1524_s/CIN |
7.984 | 0.244 | tINS | RR | 1 | AEC_uut/AEC_inst/n1524_s/SUM |
8.359 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/n1560_s2/I1 |
8.875 | 0.516 | tINS | RR | 1 | AEC_uut/AEC_inst/n1560_s2/F |
9.250 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/acc_0_31_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 1863 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | AEC_uut/AEC_inst/acc_0_31_s1/CLK |
10.311 | -0.064 | tSu | 1 | AEC_uut/AEC_inst/acc_0_31_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 5.581, 62.887%; route: 3.000, 33.802%; tC2Q: 0.294, 3.311% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |