Timing Messages
Report Title | Timing Analysis Report |
Design File | C:\Gowin\Gowin_V1.9.10.02_x64\IDE\bin\Documents\AEC_ref\impl\gwsynthesis\AEC_ref.vg |
Physical Constraints File | C:\Gowin\Gowin_V1.9.10.02_x64\IDE\bin\Documents\AEC_ref\src\AEC_ref.cst |
Timing Constraint File | C:\Gowin\Gowin_V1.9.10.02_x64\IDE\bin\Documents\AEC_ref\src\AEC_ref.sdc |
Tool Version | V1.9.11.01 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Thu Feb 27 15:20:48 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C ES |
Hold Delay Model | Fast 0.945V 85C ES |
Numbers of Paths Analyzed | 7836 |
Numbers of Endpoints Analyzed | 8751 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 1 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk1 | Base | 50.000 | 20.000 | 0.000 | 10.000 | clk | ||
2 | tck | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk1 | 20.000(MHz) | 86.908(MHz) | 4 | TOP |
2 | tck | 20.000(MHz) | 124.045(MHz) | 6 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk1 | Setup | 0.000 | 0 |
clk1 | Hold | 0.000 | 0 |
tck | Setup | 0.000 | 0 |
tck | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 38.494 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[5] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.901 |
2 | 38.615 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s3/A[0] | clk1:[R] | clk1:[R] | 50.000 | 0.004 | 7.537 |
3 | 38.777 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[10] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.799 |
4 | 38.779 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[9] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.804 |
5 | 38.782 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[17] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.804 |
6 | 38.784 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[12] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.661 |
7 | 38.790 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[11] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.661 |
8 | 38.846 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[14] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.799 |
9 | 38.847 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[3] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.544 |
10 | 38.855 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[13] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.804 |
11 | 38.880 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[15] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.804 |
12 | 38.880 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/B[31] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 8.039 |
13 | 38.892 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s3/A[13] | clk1:[R] | clk1:[R] | 50.000 | 0.004 | 7.757 |
14 | 38.892 | AEC_uut/AEC_inst/state_0_s0/Q | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[16] | clk1:[R] | clk1:[R] | 50.000 | -0.006 | 7.661 |
15 | 22.774 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/CE | tck:[F] | tck:[R] | 25.000 | -0.003 | 1.918 |
16 | 22.774 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q | gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0/CE | tck:[F] | tck:[R] | 25.000 | -0.003 | 1.918 |
17 | 22.774 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q | gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0/CE | tck:[F] | tck:[R] | 25.000 | -0.003 | 1.918 |
18 | 22.774 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q | gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0/CE | tck:[F] | tck:[R] | 25.000 | -0.003 | 1.918 |
19 | 22.774 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q | gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0/CE | tck:[F] | tck:[R] | 25.000 | -0.003 | 1.918 |
20 | 22.966 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CE | tck:[F] | tck:[R] | 25.000 | -0.013 | 1.735 |
21 | 22.966 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CE | tck:[F] | tck:[R] | 25.000 | -0.013 | 1.735 |
22 | 22.966 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q | gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CE | tck:[F] | tck:[R] | 25.000 | -0.013 | 1.735 |
23 | 22.966 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q | gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CE | tck:[F] | tck:[R] | 25.000 | -0.013 | 1.735 |
24 | 23.985 | gw_gao_inst_0/u_icon_top/tdi_d_s0/Q | gw_gao_inst_0/u_la0_top/data_register_99_s0/D | tck:[F] | tck:[R] | 25.000 | -0.007 | 0.959 |
25 | 24.092 | gw_gao_inst_0/u_icon_top/tdi_d_s0/Q | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/D | tck:[F] | tck:[R] | 25.000 | -0.012 | 0.856 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -0.407 | gw_gao_inst_0/u_la0_top/capture_window_sel_12_s1/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D | clk1:[R] | tck:[R] | 0.000 | -1.036 | 0.689 |
2 | 0.143 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_6_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[6] | clk1:[R] | clk1:[R] | 0.000 | 0.005 | 0.175 |
3 | 0.143 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_2_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[2] | clk1:[R] | clk1:[R] | 0.000 | 0.005 | 0.175 |
4 | 0.147 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_11_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[11] | clk1:[R] | clk1:[R] | 0.000 | 0.009 | 0.175 |
5 | 0.153 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1] | clk1:[R] | clk1:[R] | 0.000 | -0.005 | 0.195 |
6 | 0.153 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[1] | clk1:[R] | clk1:[R] | 0.000 | -0.005 | 0.195 |
7 | 0.193 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_13_s/DI[0] | clk1:[R] | clk1:[R] | 0.000 | -0.005 | 0.235 |
8 | 0.193 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[0] | clk1:[R] | clk1:[R] | 0.000 | -0.005 | 0.235 |
9 | 0.193 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0] | clk1:[R] | clk1:[R] | 0.000 | -0.005 | 0.235 |
10 | 0.193 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[0] | clk1:[R] | clk1:[R] | 0.000 | -0.005 | 0.235 |
11 | 0.205 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_4_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[4] | clk1:[R] | clk1:[R] | 0.000 | 0.005 | 0.237 |
12 | 0.205 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_1_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[1] | clk1:[R] | clk1:[R] | 0.000 | 0.005 | 0.237 |
13 | 0.206 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_5_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[5] | clk1:[R] | clk1:[R] | 0.000 | 0.005 | 0.238 |
14 | 0.206 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_0_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[0] | clk1:[R] | clk1:[R] | 0.000 | 0.005 | 0.238 |
15 | 0.209 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_10_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[10] | clk1:[R] | clk1:[R] | 0.000 | 0.009 | 0.237 |
16 | 0.209 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_9_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[9] | clk1:[R] | clk1:[R] | 0.000 | 0.009 | 0.237 |
17 | 0.210 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_15_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[15] | clk1:[R] | clk1:[R] | 0.000 | 0.009 | 0.238 |
18 | 0.210 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_13_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[13] | clk1:[R] | clk1:[R] | 0.000 | 0.009 | 0.238 |
19 | 0.216 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s/DI[0] | clk1:[R] | clk1:[R] | 0.000 | 0.010 | 0.243 |
20 | 0.216 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[0] | clk1:[R] | clk1:[R] | 0.000 | 0.010 | 0.243 |
21 | 0.216 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1] | clk1:[R] | clk1:[R] | 0.000 | 0.010 | 0.243 |
22 | 0.216 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] | clk1:[R] | clk1:[R] | 0.000 | 0.010 | 0.243 |
23 | 0.238 | AEC_uut/AEC_inst/Xn_buffer_inst/read_index_1_s1/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/ADB[6] | clk1:[R] | clk1:[R] | 0.000 | 0.017 | 0.256 |
24 | 0.247 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_3_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[3] | clk1:[R] | clk1:[R] | 0.000 | 0.005 | 0.279 |
25 | 0.251 | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_8_s0/Q | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[8] | clk1:[R] | clk1:[R] | 0.000 | 0.009 | 0.279 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
2 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
3 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
4 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
5 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
6 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
7 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
8 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
9 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
10 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
11 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk1:[F] | clk1:[R] | 40.000 | 0.032 | 2.477 |
12 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.020 | 2.489 |
13 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.026 | 2.483 |
14 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.026 | 2.483 |
15 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.026 | 2.483 |
16 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.032 | 2.477 |
17 | 37.144 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.032 | 2.477 |
18 | 37.148 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.014 | 2.491 |
19 | 37.148 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.014 | 2.491 |
20 | 37.148 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.014 | 2.491 |
21 | 37.148 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.014 | 2.491 |
22 | 37.148 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.014 | 2.491 |
23 | 37.148 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.014 | 2.491 |
24 | 37.148 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.012 | 2.493 |
25 | 37.148 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | clk1:[F] | clk1:[R] | 40.000 | 0.014 | 2.491 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 9.984 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR | clk1:[F] | tck:[R] | -10.000 | -1.033 | 1.000 |
2 | 9.984 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR | clk1:[F] | tck:[R] | -10.000 | -1.033 | 1.000 |
3 | 9.984 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR | clk1:[F] | tck:[R] | -10.000 | -1.033 | 1.000 |
4 | 11.047 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | -0.009 | 1.004 |
5 | 11.052 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | clk1:[F] | clk1:[R] | -10.000 | -0.010 | 1.009 |
6 | 11.054 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_12_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.002 | 0.998 |
7 | 11.054 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.002 | 0.998 |
8 | 11.054 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.002 | 0.998 |
9 | 11.054 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.002 | 0.998 |
10 | 11.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.997 |
11 | 11.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.997 |
12 | 11.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.997 |
13 | 11.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.997 |
14 | 11.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.997 |
15 | 11.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.997 |
16 | 11.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.997 |
17 | 11.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.011 | 0.993 |
18 | 11.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.011 | 0.993 |
19 | 11.058 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.998 |
20 | 11.058 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.998 |
21 | 11.058 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.998 |
22 | 11.058 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.998 |
23 | 11.058 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.998 |
24 | 11.058 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.998 |
25 | 11.058 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1/CLEAR | clk1:[F] | clk1:[R] | -10.000 | 0.007 | 0.998 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 7.759 | 8.759 | 1.000 | High Pulse Width | clk1 | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
2 | 7.759 | 8.759 | 1.000 | High Pulse Width | clk1 | AEC_uut/AEC_inst/mult36x36_1/n10_s4 |
3 | 7.762 | 8.762 | 1.000 | High Pulse Width | clk1 | AEC_uut/AEC_inst/Wn_buffer_inst/gowin_add_SDPX9B_Wn_Wn_0_0_s |
4 | 7.762 | 8.762 | 1.000 | High Pulse Width | clk1 | AEC_uut/AEC_inst/Wn_buffer_inst/gowin_add_SDPX9B_Wn_next_Wn_next_0_0_s |
5 | 7.762 | 8.762 | 1.000 | High Pulse Width | clk1 | echo_echo_0_3_s |
6 | 7.762 | 8.762 | 1.000 | High Pulse Width | clk1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_30_s |
7 | 7.762 | 8.762 | 1.000 | High Pulse Width | clk1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_31_s |
8 | 7.762 | 8.762 | 1.000 | High Pulse Width | clk1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_38_s |
9 | 7.762 | 8.762 | 1.000 | High Pulse Width | clk1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_39_s |
10 | 7.762 | 8.762 | 1.000 | High Pulse Width | clk1 | ref_ref_0_3_s |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 38.494 |
Data Arrival Time | 10.520 |
Data Required Time | 49.014 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.544 | 3.065 | tNET | RR | 1 | R31C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_31_s11/I1 |
8.060 | 0.516 | tINS | RR | 1 | R31C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_31_s11/F |
8.609 | 0.549 | tNET | RR | 1 | R26C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_31_s8/I3 |
9.070 | 0.461 | tINS | RR | 1 | R26C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_31_s8/F |
10.520 | 1.450 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.014 | -3.611 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.494, 18.906%; route: 6.025, 76.253%; tC2Q: 0.382, 4.841% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path2
Path Summary:
Slack | 38.615 |
Data Arrival Time | 10.157 |
Data Required Time | 48.772 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s3 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.573 | 3.094 | tNET | RR | 1 | R17C31[2][A] | AEC_uut/AEC_inst/mult_data_0_b_0_s9/I1 |
7.836 | 0.262 | tINS | RR | 1 | R17C31[2][A] | AEC_uut/AEC_inst/mult_data_0_b_0_s9/F |
8.373 | 0.537 | tNET | RR | 1 | R18C34[0][A] | AEC_uut/AEC_inst/mult_data_0_b_0_s6/I2 |
8.899 | 0.526 | tINS | RR | 1 | R18C34[0][A] | AEC_uut/AEC_inst/mult_data_0_b_0_s6/F |
10.157 | 1.258 | tNET | RR | 1 | DSP_R19[16] | AEC_uut/AEC_inst/mult36x36_0/n10_s3/A[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.616 | 1.933 | tNET | RR | 1 | DSP_R19[16] | AEC_uut/AEC_inst/mult36x36_0/n10_s3/CLK[0] |
48.772 | -3.844 | tSu | 1 | DSP_R19[16] | AEC_uut/AEC_inst/mult36x36_0/n10_s3 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.305, 17.313%; route: 5.850, 77.612%; tC2Q: 0.382, 5.075% |
Required Clock Path Delay | cell: 0.683, 26.093%; route: 1.933, 73.907% |
Path3
Path Summary:
Slack | 38.777 |
Data Arrival Time | 10.418 |
Data Required Time | 49.195 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.559 | 3.080 | tNET | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/I1 |
8.076 | 0.516 | tINS | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/F |
8.543 | 0.467 | tNET | RR | 1 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/I3 |
9.069 | 0.526 | tINS | RR | 18 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/F |
10.418 | 1.349 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.195 | -3.430 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 19.987%; route: 5.858, 75.108%; tC2Q: 0.382, 4.905% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path4
Path Summary:
Slack | 38.779 |
Data Arrival Time | 10.423 |
Data Required Time | 49.202 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.559 | 3.080 | tNET | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/I1 |
8.076 | 0.516 | tINS | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/F |
8.543 | 0.467 | tNET | RR | 1 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/I3 |
9.069 | 0.526 | tINS | RR | 18 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/F |
10.423 | 1.354 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.202 | -3.423 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 19.974%; route: 5.862, 75.124%; tC2Q: 0.382, 4.901% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path5
Path Summary:
Slack | 38.782 |
Data Arrival Time | 10.423 |
Data Required Time | 49.206 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.559 | 3.080 | tNET | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/I1 |
8.076 | 0.516 | tINS | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/F |
8.543 | 0.467 | tNET | RR | 1 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/I3 |
9.069 | 0.526 | tINS | RR | 18 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/F |
10.423 | 1.354 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[17] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.206 | -3.419 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 19.974%; route: 5.862, 75.124%; tC2Q: 0.382, 4.901% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path6
Path Summary:
Slack | 38.784 |
Data Arrival Time | 10.281 |
Data Required Time | 49.064 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.559 | 3.080 | tNET | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/I1 |
8.076 | 0.516 | tINS | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/F |
8.543 | 0.467 | tNET | RR | 1 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/I3 |
9.069 | 0.526 | tINS | RR | 18 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/F |
10.281 | 1.211 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.064 | -3.561 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 20.346%; route: 5.720, 74.661%; tC2Q: 0.382, 4.993% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path7
Path Summary:
Slack | 38.790 |
Data Arrival Time | 10.281 |
Data Required Time | 49.071 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.559 | 3.080 | tNET | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/I1 |
8.076 | 0.516 | tINS | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/F |
8.543 | 0.467 | tNET | RR | 1 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/I3 |
9.069 | 0.526 | tINS | RR | 18 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/F |
10.281 | 1.211 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.071 | -3.554 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 20.346%; route: 5.720, 74.661%; tC2Q: 0.382, 4.993% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path8
Path Summary:
Slack | 38.846 |
Data Arrival Time | 10.418 |
Data Required Time | 49.264 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.559 | 3.080 | tNET | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/I1 |
8.076 | 0.516 | tINS | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/F |
8.543 | 0.467 | tNET | RR | 1 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/I3 |
9.069 | 0.526 | tINS | RR | 18 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/F |
10.418 | 1.349 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[14] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.264 | -3.361 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 19.987%; route: 5.858, 75.108%; tC2Q: 0.382, 4.905% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path9
Path Summary:
Slack | 38.847 |
Data Arrival Time | 10.163 |
Data Required Time | 49.010 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.613 | 3.134 | tNET | RR | 1 | R22C38[2][B] | AEC_uut/AEC_inst/mult_data_0_b_29_s11/I1 |
8.139 | 0.526 | tINS | RR | 1 | R22C38[2][B] | AEC_uut/AEC_inst/mult_data_0_b_29_s11/F |
8.142 | 0.003 | tNET | RR | 1 | R22C38[2][A] | AEC_uut/AEC_inst/mult_data_0_b_29_s8/I3 |
8.668 | 0.526 | tINS | RR | 1 | R22C38[2][A] | AEC_uut/AEC_inst/mult_data_0_b_29_s8/F |
10.163 | 1.495 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.010 | -3.615 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.569, 20.795%; route: 5.592, 74.134%; tC2Q: 0.382, 5.070% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path10
Path Summary:
Slack | 38.855 |
Data Arrival Time | 10.423 |
Data Required Time | 49.278 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.559 | 3.080 | tNET | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/I1 |
8.076 | 0.516 | tINS | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/F |
8.543 | 0.467 | tNET | RR | 1 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/I3 |
9.069 | 0.526 | tINS | RR | 18 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/F |
10.423 | 1.354 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.278 | -3.347 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 19.974%; route: 5.862, 75.124%; tC2Q: 0.382, 4.901% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path11
Path Summary:
Slack | 38.880 |
Data Arrival Time | 10.423 |
Data Required Time | 49.303 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.559 | 3.080 | tNET | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/I1 |
8.076 | 0.516 | tINS | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/F |
8.543 | 0.467 | tNET | RR | 1 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/I3 |
9.069 | 0.526 | tINS | RR | 18 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/F |
10.423 | 1.354 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[15] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.303 | -3.322 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 19.974%; route: 5.862, 75.124%; tC2Q: 0.382, 4.901% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path12
Path Summary:
Slack | 38.880 |
Data Arrival Time | 10.658 |
Data Required Time | 49.538 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.581 | 3.101 | tNET | RR | 1 | R14C50[3][B] | AEC_uut/AEC_inst/mult_data_0_a_31_s10/I3 |
7.996 | 0.415 | tINS | RR | 1 | R14C50[3][B] | AEC_uut/AEC_inst/mult_data_0_a_31_s10/F |
8.654 | 0.659 | tNET | RR | 1 | R17C44[0][B] | AEC_uut/AEC_inst/mult_data_0_a_31_s8/I3 |
9.181 | 0.526 | tINS | RR | 1 | R17C44[0][B] | AEC_uut/AEC_inst/mult_data_0_a_31_s8/F |
9.183 | 0.003 | tNET | RR | 1 | R17C44[0][A] | AEC_uut/AEC_inst/mult_data_0_a_31_s6/I1 |
9.699 | 0.516 | tINS | RR | 2 | R17C44[0][A] | AEC_uut/AEC_inst/mult_data_0_a_31_s6/F |
10.658 | 0.959 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/B[31] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.538 | -3.087 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.974, 24.553%; route: 5.682, 70.689%; tC2Q: 0.382, 4.758% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path13
Path Summary:
Slack | 38.892 |
Data Arrival Time | 10.377 |
Data Required Time | 49.268 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s3 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.562 | 3.082 | tNET | RR | 1 | R34C40[1][B] | AEC_uut/AEC_inst/mult_data_0_b_13_s12/I1 |
8.078 | 0.516 | tINS | RR | 1 | R34C40[1][B] | AEC_uut/AEC_inst/mult_data_0_b_13_s12/F |
8.517 | 0.439 | tNET | RR | 1 | R22C40[2][B] | AEC_uut/AEC_inst/mult_data_0_b_13_s8/I3 |
9.043 | 0.526 | tINS | RR | 1 | R22C40[2][B] | AEC_uut/AEC_inst/mult_data_0_b_13_s8/F |
10.377 | 1.334 | tNET | RR | 1 | DSP_R19[16] | AEC_uut/AEC_inst/mult36x36_0/n10_s3/A[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.616 | 1.933 | tNET | RR | 1 | DSP_R19[16] | AEC_uut/AEC_inst/mult36x36_0/n10_s3/CLK[0] |
49.268 | -3.347 | tSu | 1 | DSP_R19[16] | AEC_uut/AEC_inst/mult36x36_0/n10_s3 |
Path Statistics:
Clock Skew | -0.004 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 20.093%; route: 5.816, 74.976%; tC2Q: 0.382, 4.931% |
Required Clock Path Delay | cell: 0.683, 26.093%; route: 1.933, 73.907% |
Path14
Path Summary:
Slack | 38.892 |
Data Arrival Time | 10.281 |
Data Required Time | 49.173 |
From | AEC_uut/AEC_inst/state_0_s0 |
To | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 17 | R34C50[3][A] | AEC_uut/AEC_inst/state_0_s0/Q |
3.963 | 0.961 | tNET | RR | 1 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/I2 |
4.479 | 0.516 | tINS | RR | 226 | R34C45[2][B] | AEC_uut/AEC_inst/E0_mult_en_1_s3/F |
7.559 | 3.080 | tNET | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/I1 |
8.076 | 0.516 | tINS | RR | 1 | R34C44[0][B] | AEC_uut/AEC_inst/mult_data_0_b_35_s12/F |
8.543 | 0.467 | tNET | RR | 1 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/I3 |
9.069 | 0.526 | tINS | RR | 18 | R29C44[0][A] | AEC_uut/AEC_inst/mult_data_0_b_35_s8/F |
10.281 | 1.211 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/A[16] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.625 | 1.942 | tNET | RR | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
49.173 | -3.452 | tSu | 1 | DSP_R19[18] | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Path Statistics:
Clock Skew | 0.006 |
Setup Relationship | 50.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.056%; route: 1.937, 73.944% |
Arrival Data Path Delay | cell: 1.559, 20.346%; route: 5.720, 74.661%; tC2Q: 0.382, 4.993% |
Required Clock Path Delay | cell: 0.683, 26.000%; route: 1.942, 74.000% |
Path15
Path Summary:
Slack | 22.774 |
Data Arrival Time | 30.969 |
Data Required Time | 53.743 |
From | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.051 | 2.676 | tNET | FF | 1 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
29.485 | 0.434 | tC2Q | FR | 3 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
29.673 | 0.188 | tNET | RR | 1 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/I1 |
30.189 | 0.516 | tINS | RR | 5 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/F |
30.969 | 0.780 | tNET | RR | 1 | R17C55[0][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.054 | 2.689 | tNET | RR | 1 | R17C55[0][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/CLK |
53.743 | -0.311 | tSu | 1 | R17C55[0][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 25.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.375, 33.940%; route: 2.676, 66.060% |
Arrival Data Path Delay | cell: 0.516, 26.923%; route: 0.968, 50.456%; tC2Q: 0.434, 22.621% |
Required Clock Path Delay | cell: 1.365, 33.667%; route: 2.689, 66.333% |
Path16
Path Summary:
Slack | 22.774 |
Data Arrival Time | 30.969 |
Data Required Time | 53.743 |
From | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To | gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.051 | 2.676 | tNET | FF | 1 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
29.485 | 0.434 | tC2Q | FR | 3 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
29.673 | 0.188 | tNET | RR | 1 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/I1 |
30.189 | 0.516 | tINS | RR | 5 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/F |
30.969 | 0.780 | tNET | RR | 1 | R17C55[3][B] | gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.054 | 2.689 | tNET | RR | 1 | R17C55[3][B] | gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0/CLK |
53.743 | -0.311 | tSu | 1 | R17C55[3][B] | gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 25.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.375, 33.940%; route: 2.676, 66.060% |
Arrival Data Path Delay | cell: 0.516, 26.923%; route: 0.968, 50.456%; tC2Q: 0.434, 22.621% |
Required Clock Path Delay | cell: 1.365, 33.667%; route: 2.689, 66.333% |
Path17
Path Summary:
Slack | 22.774 |
Data Arrival Time | 30.969 |
Data Required Time | 53.743 |
From | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To | gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.051 | 2.676 | tNET | FF | 1 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
29.485 | 0.434 | tC2Q | FR | 3 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
29.673 | 0.188 | tNET | RR | 1 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/I1 |
30.189 | 0.516 | tINS | RR | 5 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/F |
30.969 | 0.780 | tNET | RR | 1 | R17C55[3][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.054 | 2.689 | tNET | RR | 1 | R17C55[3][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0/CLK |
53.743 | -0.311 | tSu | 1 | R17C55[3][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 25.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.375, 33.940%; route: 2.676, 66.060% |
Arrival Data Path Delay | cell: 0.516, 26.923%; route: 0.968, 50.456%; tC2Q: 0.434, 22.621% |
Required Clock Path Delay | cell: 1.365, 33.667%; route: 2.689, 66.333% |
Path18
Path Summary:
Slack | 22.774 |
Data Arrival Time | 30.969 |
Data Required Time | 53.743 |
From | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To | gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.051 | 2.676 | tNET | FF | 1 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
29.485 | 0.434 | tC2Q | FR | 3 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
29.673 | 0.188 | tNET | RR | 1 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/I1 |
30.189 | 0.516 | tINS | RR | 5 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/F |
30.969 | 0.780 | tNET | RR | 1 | R17C55[2][B] | gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.054 | 2.689 | tNET | RR | 1 | R17C55[2][B] | gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0/CLK |
53.743 | -0.311 | tSu | 1 | R17C55[2][B] | gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 25.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.375, 33.940%; route: 2.676, 66.060% |
Arrival Data Path Delay | cell: 0.516, 26.923%; route: 0.968, 50.456%; tC2Q: 0.434, 22.621% |
Required Clock Path Delay | cell: 1.365, 33.667%; route: 2.689, 66.333% |
Path19
Path Summary:
Slack | 22.774 |
Data Arrival Time | 30.969 |
Data Required Time | 53.743 |
From | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To | gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.051 | 2.676 | tNET | FF | 1 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
29.485 | 0.434 | tC2Q | FR | 3 | R17C56[0][B] | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
29.673 | 0.188 | tNET | RR | 1 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/I1 |
30.189 | 0.516 | tINS | RR | 5 | R17C55[0][B] | gw_gao_inst_0/u_icon_top/n52_s0/F |
30.969 | 0.780 | tNET | RR | 1 | R17C55[2][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.054 | 2.689 | tNET | RR | 1 | R17C55[2][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0/CLK |
53.743 | -0.311 | tSu | 1 | R17C55[2][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0 |
Path Statistics:
Clock Skew | 0.003 |
Setup Relationship | 25.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.375, 33.940%; route: 2.676, 66.060% |
Arrival Data Path Delay | cell: 0.516, 26.923%; route: 0.968, 50.456%; tC2Q: 0.434, 22.621% |
Required Clock Path Delay | cell: 1.365, 33.667%; route: 2.689, 66.333% |
Path20
Path Summary:
Slack | 22.966 |
Data Arrival Time | 30.786 |
Data Required Time | 53.753 |
From | gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
To | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.051 | 2.676 | tNET | FF | 1 | R17C56[0][A] | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
29.485 | 0.434 | tC2Q | FR | 3 | R17C56[0][A] | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
29.625 | 0.140 | tNET | RR | 1 | R17C56[3][B] | gw_gao_inst_0/u_icon_top/n31_s1/I2 |
30.146 | 0.521 | tINS | RR | 1 | R17C56[3][B] | gw_gao_inst_0/u_icon_top/n31_s1/F |
30.149 | 0.003 | tNET | RR | 1 | R17C56[3][A] | gw_gao_inst_0/u_icon_top/n31_s0/I0 |
30.646 | 0.498 | tINS | RR | 4 | R17C56[3][A] | gw_gao_inst_0/u_icon_top/n31_s0/F |
30.786 | 0.140 | tNET | RR | 1 | R17C56[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.064 | 2.699 | tNET | RR | 1 | R17C56[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK |
53.753 | -0.311 | tSu | 1 | R17C56[1][A] | gw_gao_inst_0/u_icon_top/module_id_reg_0_s0 |
Path Statistics:
Clock Skew | 0.013 |
Setup Relationship | 25.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 1.375, 33.940%; route: 2.676, 66.060% |
Arrival Data Path Delay | cell: 1.019, 58.718%; route: 0.282, 16.282%; tC2Q: 0.434, 25.000% |
Required Clock Path Delay | cell: 1.365, 33.590%; route: 2.699, 66.410% |
Path21
Path Summary:
Slack | 22.966 |
Data Arrival Time | 30.786 |
Data Required Time | 53.753 |
From | gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
To | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.051 | 2.676 | tNET | FF | 1 | R17C56[0][A] | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
29.485 | 0.434 | tC2Q | FR | 3 | R17C56[0][A] | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
29.625 | 0.140 | tNET | RR | 1 | R17C56[3][B] | gw_gao_inst_0/u_icon_top/n31_s1/I2 |
30.146 | 0.521 | tINS | RR | 1 | R17C56[3][B] | gw_gao_inst_0/u_icon_top/n31_s1/F |
30.149 | 0.003 | tNET | RR | 1 | R17C56[3][A] | gw_gao_inst_0/u_icon_top/n31_s0/I0 |
30.646 | 0.498 | tINS | RR | 4 | R17C56[3][A] | gw_gao_inst_0/u_icon_top/n31_s0/F |
30.786 | 0.140 | tNET | RR | 1 | R17C56[1][B] | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.064 | 2.699 | tNET | RR | 1 | R17C56[1][B] | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK |
53.753 | -0.311 | tSu | 1 | R17C56[1][B] | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0 |
Path Statistics:
Clock Skew | 0.013 |
Setup Relationship | 25.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 1.375, 33.940%; route: 2.676, 66.060% |
Arrival Data Path Delay | cell: 1.019, 58.718%; route: 0.282, 16.282%; tC2Q: 0.434, 25.000% |
Required Clock Path Delay | cell: 1.365, 33.590%; route: 2.699, 66.410% |
Path22
Path Summary:
Slack | 22.966 |
Data Arrival Time | 30.786 |
Data Required Time | 53.753 |
From | gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
To | gw_gao_inst_0/u_icon_top/module_id_reg_2_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.051 | 2.676 | tNET | FF | 1 | R17C56[0][A] | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
29.485 | 0.434 | tC2Q | FR | 3 | R17C56[0][A] | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
29.625 | 0.140 | tNET | RR | 1 | R17C56[3][B] | gw_gao_inst_0/u_icon_top/n31_s1/I2 |
30.146 | 0.521 | tINS | RR | 1 | R17C56[3][B] | gw_gao_inst_0/u_icon_top/n31_s1/F |
30.149 | 0.003 | tNET | RR | 1 | R17C56[3][A] | gw_gao_inst_0/u_icon_top/n31_s0/I0 |
30.646 | 0.498 | tINS | RR | 4 | R17C56[3][A] | gw_gao_inst_0/u_icon_top/n31_s0/F |
30.786 | 0.140 | tNET | RR | 1 | R17C56[2][A] | gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.064 | 2.699 | tNET | RR | 1 | R17C56[2][A] | gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CLK |
53.753 | -0.311 | tSu | 1 | R17C56[2][A] | gw_gao_inst_0/u_icon_top/module_id_reg_2_s0 |
Path Statistics:
Clock Skew | 0.013 |
Setup Relationship | 25.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 1.375, 33.940%; route: 2.676, 66.060% |
Arrival Data Path Delay | cell: 1.019, 58.718%; route: 0.282, 16.282%; tC2Q: 0.434, 25.000% |
Required Clock Path Delay | cell: 1.365, 33.590%; route: 2.699, 66.410% |
Path23
Path Summary:
Slack | 22.966 |
Data Arrival Time | 30.786 |
Data Required Time | 53.753 |
From | gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
To | gw_gao_inst_0/u_icon_top/module_id_reg_3_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.051 | 2.676 | tNET | FF | 1 | R17C56[0][A] | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
29.485 | 0.434 | tC2Q | FR | 3 | R17C56[0][A] | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
29.625 | 0.140 | tNET | RR | 1 | R17C56[3][B] | gw_gao_inst_0/u_icon_top/n31_s1/I2 |
30.146 | 0.521 | tINS | RR | 1 | R17C56[3][B] | gw_gao_inst_0/u_icon_top/n31_s1/F |
30.149 | 0.003 | tNET | RR | 1 | R17C56[3][A] | gw_gao_inst_0/u_icon_top/n31_s0/I0 |
30.646 | 0.498 | tINS | RR | 4 | R17C56[3][A] | gw_gao_inst_0/u_icon_top/n31_s0/F |
30.786 | 0.140 | tNET | RR | 1 | R17C56[2][B] | gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.064 | 2.699 | tNET | RR | 1 | R17C56[2][B] | gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK |
53.753 | -0.311 | tSu | 1 | R17C56[2][B] | gw_gao_inst_0/u_icon_top/module_id_reg_3_s0 |
Path Statistics:
Clock Skew | 0.013 |
Setup Relationship | 25.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 1.375, 33.940%; route: 2.676, 66.060% |
Arrival Data Path Delay | cell: 1.019, 58.718%; route: 0.282, 16.282%; tC2Q: 0.434, 25.000% |
Required Clock Path Delay | cell: 1.365, 33.590%; route: 2.699, 66.410% |
Path24
Path Summary:
Slack | 23.985 |
Data Arrival Time | 30.001 |
Data Required Time | 53.986 |
From | gw_gao_inst_0/u_icon_top/tdi_d_s0 |
To | gw_gao_inst_0/u_la0_top/data_register_99_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.042 | 2.667 | tNET | FF | 1 | R17C55[1][A] | gw_gao_inst_0/u_icon_top/tdi_d_s0/CLK |
29.476 | 0.434 | tC2Q | FR | 2 | R17C55[1][A] | gw_gao_inst_0/u_icon_top/tdi_d_s0/Q |
30.001 | 0.525 | tNET | RR | 1 | R11C55[0][A] | gw_gao_inst_0/u_la0_top/data_register_99_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.049 | 2.684 | tNET | RR | 1 | R11C55[0][A] | gw_gao_inst_0/u_la0_top/data_register_99_s0/CLK |
53.986 | -0.064 | tSu | 1 | R11C55[0][A] | gw_gao_inst_0/u_la0_top/data_register_99_s0 |
Path Statistics:
Clock Skew | 0.007 |
Setup Relationship | 25.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.375, 34.019%; route: 2.667, 65.981% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.525, 54.759%; tC2Q: 0.434, 45.241% |
Required Clock Path Delay | cell: 1.365, 33.709%; route: 2.684, 66.291% |
Path25
Path Summary:
Slack | 24.092 |
Data Arrival Time | 29.898 |
Data Required Time | 53.991 |
From | gw_gao_inst_0/u_icon_top/tdi_d_s0 |
To | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0 |
Launch Clk | tck:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
25.000 | 25.000 | active clock edge time | ||||
25.000 | 0.000 | tck | ||||
25.000 | 0.000 | tCL | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
25.688 | 0.688 | tINS | FF | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
25.688 | 0.000 | tNET | FF | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
26.375 | 0.688 | tINS | FF | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
29.042 | 2.667 | tNET | FF | 1 | R17C55[1][A] | gw_gao_inst_0/u_icon_top/tdi_d_s0/CLK |
29.476 | 0.434 | tC2Q | FR | 2 | R17C55[1][A] | gw_gao_inst_0/u_icon_top/tdi_d_s0/Q |
29.898 | 0.422 | tNET | RR | 1 | R17C55[0][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | tck | ||||
50.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
50.682 | 0.683 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
50.682 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
51.365 | 0.683 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
54.054 | 2.689 | tNET | RR | 1 | R17C55[0][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/CLK |
53.991 | -0.064 | tSu | 1 | R17C55[0][A] | gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0 |
Path Statistics:
Clock Skew | 0.012 |
Setup Relationship | 25.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.375, 34.019%; route: 2.667, 65.981% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 49.343%; tC2Q: 0.434, 50.657% |
Required Clock Path Delay | cell: 1.365, 33.667%; route: 2.689, 66.333% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -0.407 |
Data Arrival Time | 2.066 |
Data Required Time | 2.472 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_12_s1 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
Launch Clk | clk1:[R] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.377 | 0.701 | tNET | RR | 1 | R15C58[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_12_s1/CLK |
1.521 | 0.144 | tC2Q | RR | 3 | R15C58[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_12_s1/Q |
1.811 | 0.290 | tNET | RR | 1 | R16C61[0][A] | gw_gao_inst_0/u_la0_top/n3327_s1/I2 |
2.066 | 0.255 | tINS | RF | 1 | R16C61[0][A] | gw_gao_inst_0/u_la0_top/n3327_s1/F |
2.066 | 0.000 | tNET | FF | 1 | R16C61[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.412 | 1.061 | tNET | RR | 1 | R16C61[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK |
2.447 | 0.035 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 | |||
2.472 | 0.025 | tHld | 1 | R16C61[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
Path Statistics:
Clock Skew | 1.036 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.074%; route: 0.701, 50.926% |
Arrival Data Path Delay | cell: 0.255, 37.010%; route: 0.290, 42.090%; tC2Q: 0.144, 20.900% |
Required Clock Path Delay | cell: 1.351, 56.006%; route: 1.061, 43.994% |
Path2
Path Summary:
Slack | 0.143 |
Data Arrival Time | 1.551 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_6_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C32[2][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_6_s0/CLK |
1.516 | 0.141 | tC2Q | RF | 1 | R27C32[2][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_6_s0/Q |
1.551 | 0.034 | tNET | FF | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.034, 19.429%; tC2Q: 0.141, 80.571% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path3
Path Summary:
Slack | 0.143 |
Data Arrival Time | 1.551 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_2_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C32[1][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_2_s0/CLK |
1.516 | 0.141 | tC2Q | RF | 1 | R27C32[1][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_2_s0/Q |
1.551 | 0.034 | tNET | FF | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.034, 19.429%; tC2Q: 0.141, 80.571% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path4
Path Summary:
Slack | 0.147 |
Data Arrival Time | 1.554 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_11_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R27C33[0][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_11_s0/CLK |
1.520 | 0.141 | tC2Q | RF | 1 | R27C33[0][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_11_s0/Q |
1.554 | 0.034 | tNET | FF | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.034, 19.429%; tC2Q: 0.141, 80.571% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path5
Path Summary:
Slack | 0.153 |
Data Arrival Time | 1.564 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C11[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 1 | R11C11[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_5_s0/Q |
1.564 | 0.054 | tNET | FF | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path6
Path Summary:
Slack | 0.153 |
Data Arrival Time | 1.569 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.374 | 0.698 | tNET | RR | 1 | R11C14[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/CLK |
1.515 | 0.141 | tC2Q | RF | 1 | R11C14[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q |
1.569 | 0.054 | tNET | FF | 1 | BSRAM_R10[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.181%; route: 0.698, 50.819% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path7
Path Summary:
Slack | 0.193 |
Data Arrival Time | 1.604 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_13_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C29[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 1 | R11C29[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q |
1.604 | 0.094 | tNET | FF | 1 | BSRAM_R10[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_13_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_13_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[8] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_13_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path8
Path Summary:
Slack | 0.193 |
Data Arrival Time | 1.604 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 1 | R11C17[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q |
1.604 | 0.094 | tNET | FF | 1 | BSRAM_R10[4] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[4] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[4] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path9
Path Summary:
Slack | 0.193 |
Data Arrival Time | 1.604 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C11[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 1 | R11C11[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q |
1.604 | 0.094 | tNET | FF | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path10
Path Summary:
Slack | 0.193 |
Data Arrival Time | 1.609 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.374 | 0.698 | tNET | RR | 1 | R11C14[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/CLK |
1.515 | 0.141 | tC2Q | RF | 1 | R11C14[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q |
1.609 | 0.094 | tNET | FF | 1 | BSRAM_R10[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.181%; route: 0.698, 50.819% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path11
Path Summary:
Slack | 0.205 |
Data Arrival Time | 1.612 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_4_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C32[0][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_4_s0/CLK |
1.520 | 0.144 | tC2Q | RR | 1 | R27C32[0][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_4_s0/Q |
1.612 | 0.093 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path12
Path Summary:
Slack | 0.205 |
Data Arrival Time | 1.612 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_1_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C32[1][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_1_s0/CLK |
1.520 | 0.144 | tC2Q | RR | 1 | R27C32[1][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_1_s0/Q |
1.612 | 0.093 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path13
Path Summary:
Slack | 0.206 |
Data Arrival Time | 1.613 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_5_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C32[2][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_5_s0/CLK |
1.516 | 0.141 | tC2Q | RF | 1 | R27C32[2][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_5_s0/Q |
1.613 | 0.097 | tNET | FF | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.097, 40.756%; tC2Q: 0.141, 59.244% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path14
Path Summary:
Slack | 0.206 |
Data Arrival Time | 1.613 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_0_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C32[3][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_0_s0/CLK |
1.516 | 0.141 | tC2Q | RF | 1 | R27C32[3][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_0_s0/Q |
1.613 | 0.097 | tNET | FF | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.097, 40.756%; tC2Q: 0.141, 59.244% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path15
Path Summary:
Slack | 0.209 |
Data Arrival Time | 1.616 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_10_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R27C33[1][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_10_s0/CLK |
1.523 | 0.144 | tC2Q | RR | 1 | R27C33[1][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_10_s0/Q |
1.616 | 0.093 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path16
Path Summary:
Slack | 0.209 |
Data Arrival Time | 1.616 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_9_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R27C33[1][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_9_s0/CLK |
1.523 | 0.144 | tC2Q | RR | 1 | R27C33[1][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_9_s0/Q |
1.616 | 0.093 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path17
Path Summary:
Slack | 0.210 |
Data Arrival Time | 1.617 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_15_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R27C33[2][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_15_s0/CLK |
1.520 | 0.141 | tC2Q | RF | 1 | R27C33[2][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_15_s0/Q |
1.617 | 0.097 | tNET | FF | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[15] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.097, 40.756%; tC2Q: 0.141, 59.244% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path18
Path Summary:
Slack | 0.210 |
Data Arrival Time | 1.617 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_13_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R27C33[3][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_13_s0/CLK |
1.520 | 0.141 | tC2Q | RF | 1 | R27C33[3][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_13_s0/Q |
1.617 | 0.097 | tNET | FF | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.097, 40.756%; tC2Q: 0.141, 59.244% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path19
Path Summary:
Slack | 0.216 |
Data Arrival Time | 1.628 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R26C59[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/CLK |
1.529 | 0.144 | tC2Q | RR | 1 | R26C59[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q |
1.628 | 0.099 | tNET | RR | 1 | BSRAM_R28[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R28[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R28[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_23_s |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path20
Path Summary:
Slack | 0.216 |
Data Arrival Time | 1.632 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.388 | 0.713 | tNET | RR | 1 | R26C14[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/CLK |
1.533 | 0.144 | tC2Q | RR | 1 | R26C14[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q |
1.632 | 0.099 | tNET | RR | 1 | BSRAM_R28[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R28[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R28[3] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.650%; route: 0.713, 51.350% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path21
Path Summary:
Slack | 0.216 |
Data Arrival Time | 1.628 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R26C11[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/CLK |
1.529 | 0.144 | tC2Q | RR | 1 | R26C11[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q |
1.628 | 0.099 | tNET | RR | 1 | BSRAM_R28[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R28[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R28[2] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path22
Path Summary:
Slack | 0.216 |
Data Arrival Time | 1.628 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R26C5[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK |
1.529 | 0.144 | tC2Q | RR | 1 | R26C5[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q |
1.628 | 0.099 | tNET | RR | 1 | BSRAM_R28[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R28[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R28[0] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path23
Path Summary:
Slack | 0.238 |
Data Arrival Time | 1.647 |
Data Required Time | 1.410 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/read_index_1_s1 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.391 | 0.716 | tNET | RR | 1 | R24C33[2][A] | AEC_uut/AEC_inst/Xn_buffer_inst/read_index_1_s1/CLK |
1.535 | 0.144 | tC2Q | RR | 7 | R24C33[2][A] | AEC_uut/AEC_inst/Xn_buffer_inst/read_index_1_s1/Q |
1.647 | 0.112 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/ADB[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKB |
1.410 | 0.035 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.017 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.553%; route: 0.716, 51.447% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.112, 43.750%; tC2Q: 0.144, 56.250% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path24
Path Summary:
Slack | 0.247 |
Data Arrival Time | 1.655 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_3_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C32[0][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_3_s0/CLK |
1.520 | 0.144 | tC2Q | RR | 1 | R27C32[0][B] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_3_s0/Q |
1.655 | 0.135 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.135, 48.387%; tC2Q: 0.144, 51.613% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path25
Path Summary:
Slack | 0.251 |
Data Arrival Time | 1.658 |
Data Required Time | 1.408 |
From | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_8_s0 |
To | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Launch Clk | clk1:[R] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R27C33[0][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_8_s0/CLK |
1.523 | 0.144 | tC2Q | RR | 1 | R27C33[0][A] | AEC_uut/AEC_inst/Xn_buffer_inst/x_prev_8_s0/Q |
1.658 | 0.135 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/DI[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R28[9] | AEC_uut/AEC_inst/Xn_buffer_inst/Xn_Xn_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.135, 48.387%; tC2Q: 0.144, 51.613% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C56[3][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C56[3][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C56[3][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path2
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path3
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path4
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path5
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C60[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C60[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C60[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path6
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C56[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C56[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C56[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path7
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C60[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C60[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C60[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path8
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C60[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C60[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C60[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path9
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path10
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R14C56[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R14C56[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK |
52.245 | -0.347 | tSu | 1 | R14C56[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path11
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.089 |
Data Required Time | 52.233 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.089 | 2.034 | tNET | FF | 1 | R30C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.581 | 1.898 | tNET | RR | 1 | R30C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
52.233 | -0.347 | tSu | 1 | R30C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -0.032 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.034, 82.135%; tC2Q: 0.442, 17.865% |
Required Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
Path12
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.101 |
Data Required Time | 52.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.101 | 2.046 | tNET | FF | 1 | R32C60[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.593 | 1.910 | tNET | RR | 1 | R32C60[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
52.245 | -0.347 | tSu | 1 | R32C60[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.046, 82.220%; tC2Q: 0.442, 17.780% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path13
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.095 |
Data Required Time | 52.239 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.095 | 2.040 | tNET | FF | 1 | R31C56[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.587 | 1.904 | tNET | RR | 1 | R31C56[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
52.239 | -0.347 | tSu | 1 | R31C56[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -0.026 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.040, 82.177%; tC2Q: 0.442, 17.823% |
Required Clock Path Delay | cell: 0.683, 26.383%; route: 1.904, 73.617% |
Path14
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.095 |
Data Required Time | 52.239 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.095 | 2.040 | tNET | FF | 1 | R31C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.587 | 1.904 | tNET | RR | 1 | R31C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
52.239 | -0.347 | tSu | 1 | R31C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | -0.026 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.040, 82.177%; tC2Q: 0.442, 17.823% |
Required Clock Path Delay | cell: 0.683, 26.383%; route: 1.904, 73.617% |
Path15
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.095 |
Data Required Time | 52.239 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.095 | 2.040 | tNET | FF | 1 | R31C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.587 | 1.904 | tNET | RR | 1 | R31C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
52.239 | -0.347 | tSu | 1 | R31C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | -0.026 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.040, 82.177%; tC2Q: 0.442, 17.823% |
Required Clock Path Delay | cell: 0.683, 26.383%; route: 1.904, 73.617% |
Path16
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.089 |
Data Required Time | 52.233 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.089 | 2.034 | tNET | FF | 1 | R30C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.581 | 1.898 | tNET | RR | 1 | R30C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLK |
52.233 | -0.347 | tSu | 1 | R30C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1 |
Path Statistics:
Clock Skew | -0.032 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.034, 82.135%; tC2Q: 0.442, 17.865% |
Required Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
Path17
Path Summary:
Slack | 37.144 |
Data Arrival Time | 15.089 |
Data Required Time | 52.233 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.089 | 2.034 | tNET | FF | 1 | R30C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.581 | 1.898 | tNET | RR | 1 | R30C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
52.233 | -0.347 | tSu | 1 | R30C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -0.032 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.034, 82.135%; tC2Q: 0.442, 17.865% |
Required Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
Path18
Path Summary:
Slack | 37.148 |
Data Arrival Time | 15.103 |
Data Required Time | 52.251 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.103 | 2.048 | tNET | FF | 1 | R15C56[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.599 | 1.916 | tNET | RR | 1 | R15C56[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
52.251 | -0.347 | tSu | 1 | R15C56[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.048, 82.233%; tC2Q: 0.442, 17.767% |
Required Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Path19
Path Summary:
Slack | 37.148 |
Data Arrival Time | 15.103 |
Data Required Time | 52.251 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.103 | 2.048 | tNET | FF | 1 | R15C56[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.599 | 1.916 | tNET | RR | 1 | R15C56[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK |
52.251 | -0.347 | tSu | 1 | R15C56[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.048, 82.233%; tC2Q: 0.442, 17.767% |
Required Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Path20
Path Summary:
Slack | 37.148 |
Data Arrival Time | 15.103 |
Data Required Time | 52.251 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.103 | 2.048 | tNET | FF | 1 | R15C56[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.599 | 1.916 | tNET | RR | 1 | R15C56[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
52.251 | -0.347 | tSu | 1 | R15C56[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.048, 82.233%; tC2Q: 0.442, 17.767% |
Required Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Path21
Path Summary:
Slack | 37.148 |
Data Arrival Time | 15.103 |
Data Required Time | 52.251 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.103 | 2.048 | tNET | FF | 1 | R15C56[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.599 | 1.916 | tNET | RR | 1 | R15C56[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
52.251 | -0.347 | tSu | 1 | R15C56[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.048, 82.233%; tC2Q: 0.442, 17.767% |
Required Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Path22
Path Summary:
Slack | 37.148 |
Data Arrival Time | 15.103 |
Data Required Time | 52.251 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.103 | 2.048 | tNET | FF | 1 | R15C56[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.599 | 1.916 | tNET | RR | 1 | R15C56[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK |
52.251 | -0.347 | tSu | 1 | R15C56[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.048, 82.233%; tC2Q: 0.442, 17.767% |
Required Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Path23
Path Summary:
Slack | 37.148 |
Data Arrival Time | 15.103 |
Data Required Time | 52.251 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.103 | 2.048 | tNET | FF | 1 | R15C56[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.599 | 1.916 | tNET | RR | 1 | R15C56[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
52.251 | -0.347 | tSu | 1 | R15C56[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.048, 82.233%; tC2Q: 0.442, 17.767% |
Required Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Path24
Path Summary:
Slack | 37.148 |
Data Arrival Time | 15.105 |
Data Required Time | 52.253 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.105 | 2.050 | tNET | FF | 1 | R16C60[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.601 | 1.918 | tNET | RR | 1 | R16C60[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
52.253 | -0.347 | tSu | 1 | R16C60[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.050, 82.247%; tC2Q: 0.442, 17.753% |
Required Clock Path Delay | cell: 0.683, 26.244%; route: 1.918, 73.756% |
Path25
Path Summary:
Slack | 37.148 |
Data Arrival Time | 15.103 |
Data Required Time | 52.251 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.688 | 0.688 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
12.613 | 1.925 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
13.055 | 0.442 | tC2Q | FF | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
15.103 | 2.048 | tNET | FF | 1 | R15C60[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
50.000 | 50.000 | active clock edge time | ||||
50.000 | 0.000 | clk1 | ||||
50.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
50.682 | 0.683 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
52.599 | 1.916 | tNET | RR | 1 | R15C60[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
52.251 | -0.347 | tSu | 1 | R15C60[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | -0.014 |
Setup Relationship | 40.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.316%; route: 1.925, 73.684% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.048, 82.233%; tC2Q: 0.442, 17.767% |
Required Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 9.984 |
Data Arrival Time | 12.378 |
Data Required Time | 2.394 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
Launch Clk | clk1:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.378 | 0.842 | tNET | RR | 1 | R16C61[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.412 | 1.061 | tNET | RR | 1 | R16C61[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK |
2.447 | 0.035 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 | |||
2.394 | -0.053 | tHld | 1 | R16C61[0][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0 |
Path Statistics:
Clock Skew | 1.033 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 84.192%; tC2Q: 0.158, 15.808% |
Required Clock Path Delay | cell: 1.351, 56.006%; route: 1.061, 43.994% |
Path2
Path Summary:
Slack | 9.984 |
Data Arrival Time | 12.378 |
Data Required Time | 2.394 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
Launch Clk | clk1:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.378 | 0.842 | tNET | RR | 1 | R16C61[0][B] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.412 | 1.061 | tNET | RR | 1 | R16C61[0][B] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK |
2.447 | 0.035 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 | |||
2.394 | -0.053 | tHld | 1 | R16C61[0][B] | gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0 |
Path Statistics:
Clock Skew | 1.033 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 84.192%; tC2Q: 0.158, 15.808% |
Required Clock Path Delay | cell: 1.351, 56.006%; route: 1.061, 43.994% |
Path3
Path Summary:
Slack | 9.984 |
Data Arrival Time | 12.378 |
Data Required Time | 2.394 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
Launch Clk | clk1:[F] |
Latch Clk | tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.378 | 0.842 | tNET | RR | 1 | R16C61[2][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 409 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.412 | 1.061 | tNET | RR | 1 | R16C61[2][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK |
2.447 | 0.035 | tUnc | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 | |||
2.394 | -0.053 | tHld | 1 | R16C61[2][A] | gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0 |
Path Statistics:
Clock Skew | 1.033 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.842, 84.192%; tC2Q: 0.158, 15.808% |
Required Clock Path Delay | cell: 1.351, 56.006%; route: 1.061, 43.994% |
Path4
Path Summary:
Slack | 11.047 |
Data Arrival Time | 12.383 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.383 | 0.846 | tNET | RR | 1 | R26C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.388 | 0.713 | tNET | RR | 1 | R26C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
1.336 | -0.053 | tHld | 1 | R26C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | 0.009 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.846, 84.263%; tC2Q: 0.158, 15.737% |
Required Clock Path Delay | cell: 0.675, 48.650%; route: 0.713, 51.350% |
Path5
Path Summary:
Slack | 11.052 |
Data Arrival Time | 12.388 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.388 | 0.851 | tNET | RR | 1 | R25C55[0][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R25C55[0][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
1.336 | -0.053 | tHld | 1 | R25C55[0][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | 0.010 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.851, 84.341%; tC2Q: 0.158, 15.659% |
Required Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Path6
Path Summary:
Slack | 11.054 |
Data Arrival Time | 12.377 |
Data Required Time | 1.324 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_12_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C58[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_12_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.377 | 0.701 | tNET | RR | 1 | R15C58[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_12_s1/CLK |
1.324 | -0.053 | tHld | 1 | R15C58[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_12_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.074%; route: 0.701, 50.926% |
Path7
Path Summary:
Slack | 11.054 |
Data Arrival Time | 12.377 |
Data Required Time | 1.324 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C62[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.377 | 0.701 | tNET | RR | 1 | R15C62[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
1.324 | -0.053 | tHld | 1 | R15C62[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.074%; route: 0.701, 50.926% |
Path8
Path Summary:
Slack | 11.054 |
Data Arrival Time | 12.377 |
Data Required Time | 1.324 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C62[1][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.377 | 0.701 | tNET | RR | 1 | R15C62[1][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
1.324 | -0.053 | tHld | 1 | R15C62[1][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.074%; route: 0.701, 50.926% |
Path9
Path Summary:
Slack | 11.054 |
Data Arrival Time | 12.377 |
Data Required Time | 1.324 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C58[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.377 | 0.701 | tNET | RR | 1 | R15C58[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
1.324 | -0.053 | tHld | 1 | R15C58[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | -0.002 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.074%; route: 0.701, 50.926% |
Path10
Path Summary:
Slack | 11.056 |
Data Arrival Time | 12.376 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.376 | 0.839 | tNET | RR | 1 | R14C58[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C58[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C58[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.839, 84.152%; tC2Q: 0.158, 15.848% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path11
Path Summary:
Slack | 11.056 |
Data Arrival Time | 12.376 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.376 | 0.839 | tNET | RR | 1 | R14C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.839, 84.152%; tC2Q: 0.158, 15.848% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path12
Path Summary:
Slack | 11.056 |
Data Arrival Time | 12.376 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.376 | 0.839 | tNET | RR | 1 | R14C58[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C58[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C58[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.839, 84.152%; tC2Q: 0.158, 15.848% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path13
Path Summary:
Slack | 11.056 |
Data Arrival Time | 12.376 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.376 | 0.839 | tNET | RR | 1 | R14C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.839, 84.152%; tC2Q: 0.158, 15.848% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path14
Path Summary:
Slack | 11.056 |
Data Arrival Time | 12.376 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.376 | 0.839 | tNET | RR | 1 | R14C58[3][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C58[3][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C58[3][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.839, 84.152%; tC2Q: 0.158, 15.848% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path15
Path Summary:
Slack | 11.056 |
Data Arrival Time | 12.376 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.376 | 0.839 | tNET | RR | 1 | R14C58[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C58[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C58[2][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.839, 84.152%; tC2Q: 0.158, 15.848% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path16
Path Summary:
Slack | 11.056 |
Data Arrival Time | 12.376 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.376 | 0.839 | tNET | RR | 1 | R14C58[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C58[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C58[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_9_s0 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.839, 84.152%; tC2Q: 0.158, 15.848% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path17
Path Summary:
Slack | 11.056 |
Data Arrival Time | 12.372 |
Data Required Time | 1.315 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.372 | 0.835 | tNET | RR | 1 | R31C62[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R31C62[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK |
1.316 | -0.053 | tHld | 1 | R31C62[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.835, 84.089%; tC2Q: 0.158, 15.911% |
Required Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Path18
Path Summary:
Slack | 11.056 |
Data Arrival Time | 12.372 |
Data Required Time | 1.315 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.372 | 0.835 | tNET | RR | 1 | R31C62[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R31C62[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLK |
1.316 | -0.053 | tHld | 1 | R31C62[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.835, 84.089%; tC2Q: 0.158, 15.911% |
Required Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Path19
Path Summary:
Slack | 11.058 |
Data Arrival Time | 12.377 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C55[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R15C55[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
1.319 | -0.053 | tHld | 1 | R15C55[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path20
Path Summary:
Slack | 11.058 |
Data Arrival Time | 12.377 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C61[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R15C61[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
1.319 | -0.053 | tHld | 1 | R15C61[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path21
Path Summary:
Slack | 11.058 |
Data Arrival Time | 12.377 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C57[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R15C57[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
1.319 | -0.053 | tHld | 1 | R15C57[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path22
Path Summary:
Slack | 11.058 |
Data Arrival Time | 12.377 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C55[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R15C55[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
1.319 | -0.053 | tHld | 1 | R15C55[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path23
Path Summary:
Slack | 11.058 |
Data Arrival Time | 12.377 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C55[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R15C55[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
1.319 | -0.053 | tHld | 1 | R15C55[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path24
Path Summary:
Slack | 11.058 |
Data Arrival Time | 12.377 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C57[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R15C57[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK |
1.319 | -0.053 | tHld | 1 | R15C57[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path25
Path Summary:
Slack | 11.058 |
Data Arrival Time | 12.377 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1 |
Launch Clk | clk1:[F] |
Latch Clk | clk1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk1 | ||||
10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | 1869 | IOB29[A] | clk_ibuf/O |
11.379 | 0.702 | tNET | FF | 1 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
11.537 | 0.158 | tC2Q | FR | 92 | R16C57[1][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
12.377 | 0.840 | tNET | RR | 1 | R15C57[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1 | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1869 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R15C57[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1/CLK |
1.319 | -0.053 | tHld | 1 | R15C57[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.130%; route: 0.702, 50.870% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.840, 84.172%; tC2Q: 0.158, 15.828% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 7.759 |
Actual Width: | 8.759 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | AEC_uut/AEC_inst/mult36x36_0/n10_s4 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.625 | 1.942 | tNET | RR | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.384 | 0.706 | tNET | FF | AEC_uut/AEC_inst/mult36x36_0/n10_s4/CLK[0] |
MPW2
MPW Summary:
Slack: | 7.759 |
Actual Width: | 8.759 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | AEC_uut/AEC_inst/mult36x36_1/n10_s4 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.625 | 1.942 | tNET | RR | AEC_uut/AEC_inst/mult36x36_1/n10_s4/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.384 | 0.706 | tNET | FF | AEC_uut/AEC_inst/mult36x36_1/n10_s4/CLK[0] |
MPW3
MPW Summary:
Slack: | 7.762 |
Actual Width: | 8.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | AEC_uut/AEC_inst/Wn_buffer_inst/gowin_add_SDPX9B_Wn_Wn_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | AEC_uut/AEC_inst/Wn_buffer_inst/gowin_add_SDPX9B_Wn_Wn_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.385 | 0.708 | tNET | FF | AEC_uut/AEC_inst/Wn_buffer_inst/gowin_add_SDPX9B_Wn_Wn_0_0_s/CLKA |
MPW4
MPW Summary:
Slack: | 7.762 |
Actual Width: | 8.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | AEC_uut/AEC_inst/Wn_buffer_inst/gowin_add_SDPX9B_Wn_next_Wn_next_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | AEC_uut/AEC_inst/Wn_buffer_inst/gowin_add_SDPX9B_Wn_next_Wn_next_0_0_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.385 | 0.708 | tNET | FF | AEC_uut/AEC_inst/Wn_buffer_inst/gowin_add_SDPX9B_Wn_next_Wn_next_0_0_s/CLKB |
MPW5
MPW Summary:
Slack: | 7.762 |
Actual Width: | 8.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | echo_echo_0_3_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | echo_echo_0_3_s/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.385 | 0.708 | tNET | FF | echo_echo_0_3_s/CLK |
MPW6
MPW Summary:
Slack: | 7.762 |
Actual Width: | 8.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_30_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_30_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.385 | 0.708 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_30_s/CLKA |
MPW7
MPW Summary:
Slack: | 7.762 |
Actual Width: | 8.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_31_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_31_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.385 | 0.708 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_31_s/CLKA |
MPW8
MPW Summary:
Slack: | 7.762 |
Actual Width: | 8.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_38_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_38_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.385 | 0.708 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_38_s/CLKA |
MPW9
MPW Summary:
Slack: | 7.762 |
Actual Width: | 8.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_39_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_39_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.385 | 0.708 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_39_s/CLKA |
MPW10
MPW Summary:
Slack: | 7.762 |
Actual Width: | 8.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk1 |
Objects: | ref_ref_0_3_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk1 | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | ref_ref_0_3_s/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk1 | ||
10.000 | 0.000 | tCL | FF | clk_ibuf/I |
10.677 | 0.678 | tINS | FF | clk_ibuf/O |
11.385 | 0.708 | tNET | FF | ref_ref_0_3_s/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1869 | clk_d | 38.494 | 1.975 |
409 | control0[0] | 41.938 | 2.733 |
226 | E0_mult_en_1_8 | 38.494 | 3.272 |
180 | n4529_3 | 43.328 | 2.496 |
153 | wn_buffer_in_valid_4 | 38.911 | 3.509 |
144 | n2988_5 | 42.285 | 3.025 |
132 | acc_reset | 44.041 | 2.529 |
118 | mult_data_0_a_24_11 | 40.248 | 2.724 |
108 | Wn_data_out_0_254 | 40.133 | 2.808 |
105 | mult36x36_0_valid_out | 43.222 | 1.511 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R19C41 | 69.44% |
R20C42 | 68.06% |
R24C46 | 65.28% |
R18C42 | 65.28% |
R19C42 | 65.28% |
R16C45 | 63.89% |
R18C44 | 63.89% |
R16C43 | 62.50% |
R20C43 | 61.11% |
R17C37 | 61.11% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk1 -period 50 -waveform {0 10} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name tck -period 50 -waveform {0 25} [get_ports {tck_pad_i}] |