Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\AHBBusArbiter\data\gowin_ahb_arbiter_top.v
D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\AHBBusArbiter\data\BusMatrix16.v
D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\AHBBusArbiter\data\InputStage.v
D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\AHBBusArbiter\data\MatrixDecodeSx.v
D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\AHBBusArbiter\data\OutputArb16.v
D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\AHBBusArbiter\data\OutputStage16.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324C2/I1
Device GW5A-25
Device Version A
Created Time Mon Dec 23 16:11:53 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_AHB_Arbiter_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.397s, Peak memory usage = 118.145MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 118.145MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 118.145MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 118.145MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 118.145MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 118.145MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 118.145MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 118.145MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 118.145MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 118.145MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 118.145MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 118.145MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.536s, Peak memory usage = 140.750MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 140.750MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 140.750MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 140.750MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 240
I/O Buf 240
    IBUF 121
    OBUF 119
Register 64
    DFFPE 1
    DFFCE 63
LUT 159
    LUT2 41
    LUT3 29
    LUT4 89
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 160(160 LUT, 0 ALU) / 23040 <1%
Register 64 / 23685 <1%
  --Register as Latch 0 / 23685 0%
  --Register as FF 64 / 23685 <1%
BSRAM 0 / 56 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 HCLK Base 10.000 100.0 0.000 5.000 HCLK_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.000(MHz) 268.025(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.269
Data Arrival Time 3.782
Data Required Time 10.051
From u_busmatrix16/uInputStage0/PendTranReg_s1
To u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 64 HCLK_ibuf/O
0.300 0.300 tNET RR 1 u_busmatrix16/uInputStage0/PendTranReg_s1/CLK
0.606 0.306 tC2Q RR 68 u_busmatrix16/uInputStage0/PendTranReg_s1/Q
0.906 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/n22_s9/I0
1.327 0.421 tINS RR 2 u_busmatrix16/uOutputstage0/uOutputArb/n22_s9/F
1.627 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/n22_s8/I0
2.048 0.421 tINS RR 3 u_busmatrix16/uOutputstage0/uOutputArb/n22_s8/F
2.348 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s5/I1
2.761 0.413 tINS RR 2 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s5/F
3.061 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s4/I0
3.482 0.421 tINS RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s4/F
3.782 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 64 HCLK_ibuf/O
10.300 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CLK
10.051 -0.249 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.676, 48.133%; route: 1.500, 43.079%; tC2Q: 0.306, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack 6.269
Data Arrival Time 3.782
Data Required Time 10.051
From u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
To u_busmatrix16/uOutputstage0/HselLock_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 64 HCLK_ibuf/O
0.300 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CLK
0.606 0.306 tC2Q RR 5 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/Q
0.906 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/SHTRANSM0_d_0_s0/I0
1.327 0.421 tINS RR 7 u_busmatrix16/uOutputstage0/SHTRANSM0_d_0_s0/F
1.627 0.300 tNET RR 1 u_busmatrix16/uInputStage0/n115_s1/I1
2.040 0.413 tINS RR 50 u_busmatrix16/uInputStage0/n115_s1/F
2.340 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/SHMASTLOCKM0_d_s0/I0
2.761 0.421 tINS RR 2 u_busmatrix16/uOutputstage0/SHMASTLOCKM0_d_s0/F
3.061 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/HselLock_s3/I0
3.482 0.421 tINS RR 1 u_busmatrix16/uOutputstage0/HselLock_s3/F
3.782 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/HselLock_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 64 HCLK_ibuf/O
10.300 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/HselLock_s0/CLK
10.051 -0.249 tSu 1 u_busmatrix16/uOutputstage0/HselLock_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.676, 48.133%; route: 1.500, 43.079%; tC2Q: 0.306, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack 6.285
Data Arrival Time 3.766
Data Required Time 10.051
From u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
To u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 64 HCLK_ibuf/O
0.300 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CLK
0.606 0.306 tC2Q RR 5 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/Q
0.906 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/SHTRANSM0_d_0_s0/I0
1.327 0.421 tINS RR 7 u_busmatrix16/uOutputstage0/SHTRANSM0_d_0_s0/F
1.627 0.300 tNET RR 1 u_busmatrix16/uInputStage0/n115_s1/I1
2.040 0.413 tINS RR 50 u_busmatrix16/uInputStage0/n115_s1/F
2.340 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s/I1
2.753 0.413 tINS RR 5 u_busmatrix16/uOutputstage0/SHSELM0_d_s/F
3.053 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I1
3.466 0.413 tINS RR 4 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F
3.766 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 64 HCLK_ibuf/O
10.300 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0/CLK
10.051 -0.249 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.660, 47.893%; route: 1.500, 43.278%; tC2Q: 0.306, 8.829%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack 6.285
Data Arrival Time 3.766
Data Required Time 10.051
From u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
To u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 64 HCLK_ibuf/O
0.300 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CLK
0.606 0.306 tC2Q RR 5 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/Q
0.906 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/SHTRANSM0_d_0_s0/I0
1.327 0.421 tINS RR 7 u_busmatrix16/uOutputstage0/SHTRANSM0_d_0_s0/F
1.627 0.300 tNET RR 1 u_busmatrix16/uInputStage0/n115_s1/I1
2.040 0.413 tINS RR 50 u_busmatrix16/uInputStage0/n115_s1/F
2.340 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s/I1
2.753 0.413 tINS RR 5 u_busmatrix16/uOutputstage0/SHSELM0_d_s/F
3.053 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I1
3.466 0.413 tINS RR 4 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F
3.766 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 64 HCLK_ibuf/O
10.300 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0/CLK
10.051 -0.249 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.660, 47.893%; route: 1.500, 43.278%; tC2Q: 0.306, 8.829%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack 6.285
Data Arrival Time 3.766
Data Required Time 10.051
From u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0
To u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 64 HCLK_ibuf/O
0.300 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/CLK
0.606 0.306 tC2Q RR 5 u_busmatrix16/uOutputstage0/uOutputArb/iAddrInPort_3_s0/Q
0.906 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/SHTRANSM0_d_0_s0/I0
1.327 0.421 tINS RR 7 u_busmatrix16/uOutputstage0/SHTRANSM0_d_0_s0/F
1.627 0.300 tNET RR 1 u_busmatrix16/uInputStage0/n115_s1/I1
2.040 0.413 tINS RR 50 u_busmatrix16/uInputStage0/n115_s1/F
2.340 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/SHSELM0_d_s/I1
2.753 0.413 tINS RR 5 u_busmatrix16/uOutputstage0/SHSELM0_d_s/F
3.053 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/I1
3.466 0.413 tINS RR 4 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_2_s2/F
3.766 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 64 HCLK_ibuf/O
10.300 0.300 tNET RR 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0/CLK
10.051 -0.249 tSu 1 u_busmatrix16/uOutputstage0/uOutputArb/BurstCount_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 1.660, 47.893%; route: 1.500, 43.278%; tC2Q: 0.306, 8.829%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%