Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v D:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v D:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v D:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v D:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_interface.v D:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_rdfifo.v D:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_wrfifo.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-4 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue Sep 12 13:54:02 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | RiscV_AE350_SOC_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 80.477MB Running netlist conversion: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 80.477MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.374s, Peak memory usage = 80.477MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.141s, Peak memory usage = 80.477MB Optimizing Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.32s, Peak memory usage = 80.477MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.113s, Peak memory usage = 80.477MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 80.477MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 80.477MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 80.477MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.379s, Peak memory usage = 80.477MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.222s, Peak memory usage = 80.477MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 80.477MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 81.156MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.311s, Peak memory usage = 81.156MB Generate output files: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.476s, Peak memory usage = 86.391MB |
Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 7s, Peak memory usage = 86.391MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 195 |
I/O Buf | 192 |
    IBUF | 52 |
    OBUF | 113 |
    TBUF | 2 |
    IOBUF | 22 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 2 |
Register | 3436 |
    DFFSE | 1 |
    DFFRE | 686 |
    DFFPE | 82 |
    DFFCE | 2666 |
    DLCE | 1 |
LUT | 2880 |
    LUT2 | 683 |
    LUT3 | 1265 |
    LUT4 | 932 |
ALU | 248 |
    ALU | 248 |
SSRAM | 64 |
    RAM16SDP4 | 64 |
INV | 132 |
    INV | 132 |
IOLOGIC | 76 |
    IDES8_MEM | 16 |
    OSER8 | 24 |
    OSER8_MEM | 20 |
    IODELAY | 16 |
BSRAM | 22 |
    SDPB | 14 |
    SDPX9B | 8 |
CLOCK | 4 |
    CLKDIV | 1 |
    DQS | 2 |
    DDRDLL | 1 |
AE350_SOC | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 3644(3012 LUT, 248 ALU, 64 RAM16) / 138240 | 3% |
Register | 3436 / 139140 | 3% |
  --Register as Latch | 1 / 139140 | <1% |
  --Register as FF | 3435 / 139140 | 3% |
BSRAM | 22 / 340 | 7% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
DDR3_CLK_IN | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR3_CLK_IN_ibuf/I | ||
DDR3_MEMORY_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR3_MEMORY_CLK_ibuf/I | ||
DDR_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR_CLK_ibuf/I | ||
AHB_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | AHB_CLK_ibuf/I | ||
FLASH_SPI_CLK_iobuf/I | Base | 10.000 | 100.0 | 0.000 | 5.000 | FLASH_SPI_CLK_iobuf/I | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1782_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1782_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_clock_inv_9 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_clock_inv_s6/O | ||
FLASH_SPI_CLK_in | Base | 10.000 | 100.0 | 0.000 | 5.000 | FLASH_SPI_CLK_iobuf/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | DDR3_MEMORY_CLK_ibuf/I | DDR3_MEMORY_CLK | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | DDR3_CLK_IN | 100.0(MHz) | 265.1(MHz) | 6 | TOP |
2 | DDR3_MEMORY_CLK | 100.0(MHz) | 1506.0(MHz) | 1 | TOP |
3 | DDR_CLK | 100.0(MHz) | 235.8(MHz) | 7 | TOP |
4 | AHB_CLK | 100.0(MHz) | 126.0(MHz) | 13 | TOP |
5 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
6 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
7 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
8 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
9 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
10 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
11 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.0(MHz) | 148.5(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 2.063 |
Data Arrival Time | 8.738 |
Data Required Time | 10.801 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 24 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/I0 |
1.915 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/I2 |
2.538 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/F |
2.718 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/I0 |
3.223 | 0.505 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I0 |
3.908 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F |
4.088 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/I0 |
4.593 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/F |
4.773 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/I2 |
5.216 | 0.443 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/F |
5.396 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
5.901 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
6.081 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
6.621 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
6.621 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
6.669 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
6.669 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
6.717 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
6.717 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
6.765 | 0.048 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
6.945 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
7.450 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
7.630 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
7.882 | 0.252 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
8.062 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s2/I1 |
8.558 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s2/F |
8.738 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/CLK |
10.801 | -0.061 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.348, 67.911%; route: 2.160, 27.426%; tC2Q: 0.367, 4.663% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 2.069 |
Data Arrival Time | 8.494 |
Data Required Time | 10.564 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 24 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/I0 |
1.915 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/I2 |
2.538 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/F |
2.718 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/I0 |
3.223 | 0.505 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I0 |
3.908 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F |
4.088 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/I0 |
4.593 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/F |
4.773 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/I2 |
5.216 | 0.443 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/F |
5.396 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
5.901 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
6.081 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
6.621 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
6.621 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
6.669 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
6.669 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
6.717 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
6.717 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
6.765 | 0.048 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
6.945 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
7.450 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
7.630 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
7.882 | 0.252 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
8.062 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I3 |
8.314 | 0.252 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
8.494 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/CLK |
10.564 | -0.299 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.105, 66.887%; route: 2.160, 28.302%; tC2Q: 0.367, 4.811% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 2.069 |
Data Arrival Time | 8.494 |
Data Required Time | 10.564 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 24 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/I0 |
1.915 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/I2 |
2.538 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/F |
2.718 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/I0 |
3.223 | 0.505 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I0 |
3.908 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F |
4.088 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/I0 |
4.593 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/F |
4.773 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/I2 |
5.216 | 0.443 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/F |
5.396 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
5.901 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
6.081 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
6.621 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
6.621 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
6.669 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
6.669 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
6.717 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
6.717 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
6.765 | 0.048 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
6.945 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
7.450 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
7.630 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
7.882 | 0.252 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
8.062 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I3 |
8.314 | 0.252 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
8.494 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CLK |
10.564 | -0.299 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.105, 66.887%; route: 2.160, 28.302%; tC2Q: 0.367, 4.811% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 2.069 |
Data Arrival Time | 8.494 |
Data Required Time | 10.564 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 24 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/I0 |
1.915 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/I2 |
2.538 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/F |
2.718 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/I0 |
3.223 | 0.505 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I0 |
3.908 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F |
4.088 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/I0 |
4.593 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/F |
4.773 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/I2 |
5.216 | 0.443 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/F |
5.396 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
5.901 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
6.081 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
6.621 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
6.621 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
6.669 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
6.669 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
6.717 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
6.717 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
6.765 | 0.048 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
6.945 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
7.450 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
7.630 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
7.882 | 0.252 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
8.062 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I3 |
8.314 | 0.252 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
8.494 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CLK |
10.564 | -0.299 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.105, 66.887%; route: 2.160, 28.302%; tC2Q: 0.367, 4.811% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 2.069 |
Data Arrival Time | 8.494 |
Data Required Time | 10.564 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/CLK |
1.230 | 0.367 | tC2Q | RR | 24 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_1_s0/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/I0 |
1.915 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_clk_en_s5/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/I2 |
2.538 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s22/F |
2.718 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/I0 |
3.223 | 0.505 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s11/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I0 |
3.908 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F |
4.088 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/I0 |
4.593 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s6/F |
4.773 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/I2 |
5.216 | 0.443 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_addr_latched_sclk_Z_s1/F |
5.396 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
5.901 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
6.081 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
6.621 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
6.621 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
6.669 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
6.669 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
6.717 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
6.717 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
6.765 | 0.048 | tINS | RR | 12 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
6.945 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/I0 |
7.450 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s4/F |
7.630 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/I3 |
7.882 | 0.252 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s6/F |
8.062 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I3 |
8.314 | 0.252 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
8.494 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1/CLK |
10.564 | -0.299 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_3_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 5.105, 66.887%; route: 2.160, 28.302%; tC2Q: 0.367, 4.811% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |