Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\AHB2AHB16Bridge\data\AHB_to_AHB_16_Bridge_Top.v
D:\Gowin\Gowin_V1.9.9Beta-4\IDE\ipcore\AHB2AHB16Bridge\data\AHB_to_AHB_16_Bridge.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-4
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Tue Sep 12 13:53:22 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module AHB_to_AHB_16_Bridge_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.298s, Peak memory usage = 43.152MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 43.152MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 43.152MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 43.152MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 43.152MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 43.152MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.152MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.152MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.152MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 43.152MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.152MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.152MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.206s, Peak memory usage = 53.789MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 53.789MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 53.789MB
Total Time and Memory Usage CPU time = 0h 0m 0.497s, Elapsed time = 0h 0m 0.527s, Peak memory usage = 53.789MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 143
I/O Buf 120
    IBUF 83
    OBUF 37
Register 4
    DFFPE 1
    DFFCE 3
LUT 47
    LUT3 4
    LUT4 43
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 48(48 LUT, 0 ALU) / 138240 <1%
Register 4 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 4 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
hclk Base 10.000 100.0 0.000 5.000 hclk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 hclk 100.0(MHz) 416.5(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 7.599
Data Arrival Time 3.203
Data Required Time 10.801
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/default_hreadyout_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.683 0.683 tINS RR 4 hclk_ibuf/O
0.863 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
1.230 0.367 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.410 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
1.915 0.505 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.095 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.347 0.252 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.527 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/n54_s1/I1
3.023 0.496 tINS RR 1 u_AHB_to_AHB_16_Bridge/n54_s1/F
3.203 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hreadyout_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.682 0.683 tINS RR 4 hclk_ibuf/O
10.863 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hreadyout_s0/CLK
10.801 -0.061 tSu 1 u_AHB_to_AHB_16_Bridge/default_hreadyout_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.253, 53.539%; route: 0.720, 30.769%; tC2Q: 0.367, 15.692%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 7.652
Data Arrival Time 3.150
Data Required Time 10.801
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/default_hresp_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.683 0.683 tINS RR 4 hclk_ibuf/O
0.863 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
1.230 0.367 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.410 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
1.915 0.505 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.095 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.347 0.252 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.527 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/n55_s1/I2
2.970 0.443 tINS RR 1 u_AHB_to_AHB_16_Bridge/n55_s1/F
3.150 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hresp_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.682 0.683 tINS RR 4 hclk_ibuf/O
10.863 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hresp_s0/CLK
10.801 -0.061 tSu 1 u_AHB_to_AHB_16_Bridge/default_hresp_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 1.200, 52.465%; route: 0.720, 31.480%; tC2Q: 0.367, 16.055%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 8.037
Data Arrival Time 2.527
Data Required Time 10.564
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.683 0.683 tINS RR 4 hclk_ibuf/O
0.863 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
1.230 0.367 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.410 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
1.915 0.505 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.095 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.347 0.252 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.527 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.682 0.683 tINS RR 4 hclk_ibuf/O
10.863 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0/CLK
10.564 -0.299 tSu 1 u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.757, 45.494%; route: 0.540, 32.444%; tC2Q: 0.367, 22.062%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 8.037
Data Arrival Time 2.527
Data Required Time 10.564
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.683 0.683 tINS RR 4 hclk_ibuf/O
0.863 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
1.230 0.367 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.410 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
1.915 0.505 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.095 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.347 0.252 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.527 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.682 0.683 tINS RR 4 hclk_ibuf/O
10.863 0.180 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
10.564 -0.299 tSu 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 0.757, 45.494%; route: 0.540, 32.444%; tC2Q: 0.367, 22.062%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%