Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\AHB2AHB16Bridge\data\AHB_to_AHB_16_Bridge_Top.v
D:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\AHB2AHB16Bridge\data\AHB_to_AHB_16_Bridge.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Mon Nov 27 17:53:36 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module AHB_to_AHB_16_Bridge_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 47.945MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 47.945MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 47.945MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 47.945MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 47.945MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 47.945MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 47.945MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 47.945MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 47.945MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 47.945MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 47.945MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 47.945MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.194s, Peak memory usage = 70.488MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 70.488MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 70.488MB
Total Time and Memory Usage CPU time = 0h 0m 0.295s, Elapsed time = 0h 0m 0.365s, Peak memory usage = 70.488MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 143
I/O Buf 120
    IBUF 83
    OBUF 37
Register 4
    DFFPE 1
    DFFCE 3
LUT 47
    LUT3 4
    LUT4 43
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 48(48 LUT, 0 ALU) / 138240 <1%
Register 4 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 4 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
hclk Base 10.000 100.0 0.000 5.000 hclk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 hclk 100.0(MHz) 369.5(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 7.294
Data Arrival Time 3.531
Data Required Time 10.825
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/default_hreadyout_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.683 0.683 tINS RR 4 hclk_ibuf/O
0.889 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
1.271 0.382 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.477 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
2.056 0.579 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.263 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.551 0.289 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.757 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/n54_s1/I1
3.325 0.567 tINS RR 1 u_AHB_to_AHB_16_Bridge/n54_s1/F
3.531 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hreadyout_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.682 0.683 tINS RR 4 hclk_ibuf/O
10.889 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hreadyout_s0/CLK
10.825 -0.064 tSu 1 u_AHB_to_AHB_16_Bridge/default_hreadyout_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 1.435, 54.305%; route: 0.825, 31.220%; tC2Q: 0.382, 14.475%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 2

Path Summary:
Slack 7.354
Data Arrival Time 3.471
Data Required Time 10.825
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/default_hresp_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.683 0.683 tINS RR 4 hclk_ibuf/O
0.889 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
1.271 0.382 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.477 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
2.056 0.579 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.263 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.551 0.289 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.757 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/n55_s1/I2
3.265 0.507 tINS RR 1 u_AHB_to_AHB_16_Bridge/n55_s1/F
3.471 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hresp_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.682 0.683 tINS RR 4 hclk_ibuf/O
10.889 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hresp_s0/CLK
10.825 -0.064 tSu 1 u_AHB_to_AHB_16_Bridge/default_hresp_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 1.375, 53.243%; route: 0.825, 31.946%; tC2Q: 0.382, 14.811%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 3

Path Summary:
Slack 7.820
Data Arrival Time 2.757
Data Required Time 10.578
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.683 0.683 tINS RR 4 hclk_ibuf/O
0.889 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
1.271 0.382 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.477 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
2.056 0.579 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.263 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.551 0.289 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.757 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.682 0.683 tINS RR 4 hclk_ibuf/O
10.889 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0/CLK
10.578 -0.311 tSu 1 u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 0.868, 46.422%; route: 0.619, 33.110%; tC2Q: 0.382, 20.468%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%

Path 4

Path Summary:
Slack 7.820
Data Arrival Time 2.757
Data Required Time 10.578
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.683 0.683 tINS RR 4 hclk_ibuf/O
0.889 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
1.271 0.382 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.477 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
2.056 0.579 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.263 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.551 0.289 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.757 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.682 0.683 tINS RR 4 hclk_ibuf/O
10.889 0.206 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
10.578 -0.311 tSu 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%
Arrival Data Path Delay: cell: 0.868, 46.422%; route: 0.619, 33.110%; tC2Q: 0.382, 20.468%
Required Clock Path Delay: cell: 0.683, 76.793%; route: 0.206, 23.207%