Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\AHB2AHB16Bridge\data\AHB_to_AHB_16_Bridge_Top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\AHB2AHB16Bridge\data\AHB_to_AHB_16_Bridge.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Tue Feb 25 17:09:10 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module AHB_to_AHB_16_Bridge_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.373s, Peak memory usage = 107.098MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 107.098MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 107.098MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 107.098MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 107.098MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 107.098MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 107.098MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 107.098MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 107.098MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 107.098MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 107.098MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 107.098MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.225s, Peak memory usage = 128.102MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 128.102MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.094s, Peak memory usage = 128.102MB
Total Time and Memory Usage CPU time = 0h 0m 0.388s, Elapsed time = 0h 0m 0.718s, Peak memory usage = 128.102MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 143
I/O Buf 120
    IBUF 83
    OBUF 37
Register 4
    DFFPE 1
    DFFCE 3
LUT 47
    LUT3 4
    LUT4 43
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 48(48 LUT, 0 ALU) / 138240 <1%
Register 4 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 4 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 hclk Base 10.000 100.000 0.000 5.000 hclk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 hclk 100.000(MHz) 283.186(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.469
Data Arrival Time 3.880
Data Required Time 10.349
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/default_hreadyout_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.000 0.000 tINS RR 4 hclk_ibuf/O
0.413 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
0.795 0.382 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.207 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
1.786 0.579 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.199 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.487 0.289 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.900 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/n54_s1/I1
3.468 0.567 tINS RR 1 u_AHB_to_AHB_16_Bridge/n54_s1/F
3.880 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hreadyout_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.000 0.000 tINS RR 4 hclk_ibuf/O
10.413 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hreadyout_s0/CLK
10.349 -0.064 tSu 1 u_AHB_to_AHB_16_Bridge/default_hreadyout_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.435, 41.384%; route: 1.650, 47.585%; tC2Q: 0.382, 11.031%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 6.529
Data Arrival Time 3.820
Data Required Time 10.349
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/default_hresp_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.000 0.000 tINS RR 4 hclk_ibuf/O
0.413 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
0.795 0.382 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.207 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
1.786 0.579 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.199 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.487 0.289 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.900 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/n55_s1/I2
3.408 0.507 tINS RR 1 u_AHB_to_AHB_16_Bridge/n55_s1/F
3.820 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hresp_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.000 0.000 tINS RR 4 hclk_ibuf/O
10.413 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/default_hresp_s0/CLK
10.349 -0.064 tSu 1 u_AHB_to_AHB_16_Bridge/default_hresp_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.375, 40.352%; route: 1.650, 48.423%; tC2Q: 0.382, 11.225%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 7.201
Data Arrival Time 2.900
Data Required Time 10.101
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.000 0.000 tINS RR 4 hclk_ibuf/O
0.413 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
0.795 0.382 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.207 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
1.786 0.579 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.199 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.487 0.289 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.900 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.000 0.000 tINS RR 4 hclk_ibuf/O
10.413 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0/CLK
10.101 -0.311 tSu 1 u_AHB_to_AHB_16_Bridge/ds1_hsel_d1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.868, 34.874%; route: 1.238, 49.749%; tC2Q: 0.382, 15.377%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 7.201
Data Arrival Time 2.900
Data Required Time 10.101
From u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
To u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.000 0.000 tINS RR 4 hclk_ibuf/O
0.413 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
0.795 0.382 tC2Q RR 36 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/Q
1.207 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/I0
1.786 0.579 tINS RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s0/F
2.199 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/I3
2.487 0.289 tINS RR 6 u_AHB_to_AHB_16_Bridge/ds_hready_d_s/F
2.900 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.000 0.000 tINS RR 4 hclk_ibuf/O
10.413 0.413 tNET RR 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0/CLK
10.101 -0.311 tSu 1 u_AHB_to_AHB_16_Bridge/ds2_hsel_d1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 0.868, 34.874%; route: 1.238, 49.749%; tC2Q: 0.382, 15.377%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%