Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBGPIO\data\apb_gpio_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBGPIO\data\apb_gpio.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Tue May 6 10:49:18 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module APB_GPIO_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.341s, Peak memory usage = 70.180MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 70.180MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 70.180MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 70.180MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 70.180MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 70.180MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 70.180MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 70.180MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 70.180MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 70.180MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 70.180MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 70.180MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.471s, Peak memory usage = 93.543MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 93.543MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 93.543MB
Total Time and Memory Usage CPU time = 0h 0m 0.67s, Elapsed time = 0h 0m 1s, Peak memory usage = 93.543MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 90
I/O Buf 68
    IBUF 27
    OBUF 41
Register 64
    DFFCE 64
LUT 114
    LUT2 13
    LUT3 26
    LUT4 75
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 115(115 LUT, 0 ALU) / 138240 <1%
Register 64 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 64 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 pclk Base 10.000 100.000 0.000 5.000 pclk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 pclk 100.000(MHz) 202.891(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.071
Data Arrival Time 5.030
Data Required Time 10.101
From u_apb_gpio/u_apb_gpio_apbslv/gpio_intr_mode_b0_1_s0
To u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s1
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 64 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_intr_mode_b0_1_s0/CLK
0.795 0.382 tC2Q RR 3 u_apb_gpio/u_apb_gpio_apbslv/gpio_intr_mode_b0_1_s0/Q
1.207 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s6/I0
1.786 0.579 tINS RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s6/F
2.199 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s5/I0
2.778 0.579 tINS RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s5/F
3.190 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s4/I2
3.697 0.507 tINS RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s4/F
4.110 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s3/I2
4.618 0.507 tINS RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s3/F
5.030 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 64 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s1/CLK
10.101 -0.311 tSu 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.172, 47.049%; route: 2.063, 44.667%; tC2Q: 0.382, 8.284%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 5.071
Data Arrival Time 5.030
Data Required Time 10.101
From u_apb_gpio/u_apb_gpio_apbslv/gpio_intr_mode_b0_2_s0
To u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s1
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 64 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_intr_mode_b0_2_s0/CLK
0.795 0.382 tC2Q RR 3 u_apb_gpio/u_apb_gpio_apbslv/gpio_intr_mode_b0_2_s0/Q
1.207 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s6/I0
1.786 0.579 tINS RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s6/F
2.199 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s5/I0
2.778 0.579 tINS RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s5/F
3.190 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s4/I2
3.697 0.507 tINS RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s4/F
4.110 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s3/I2
4.618 0.507 tINS RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s3/F
5.030 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 64 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s1/CLK
10.101 -0.311 tSu 1 u_apb_gpio/u_apb_gpio_apbslv/gpio_ch_intr_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.172, 47.049%; route: 2.063, 44.667%; tC2Q: 0.382, 8.284%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 5.290
Data Arrival Time 4.811
Data Required Time 10.101
From u_apb_gpio/u_apb_gpio_gpio/db_cntr_0_s1
To u_apb_gpio/u_apb_gpio_gpio/debounce_1_0_s1
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 64 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/db_cntr_0_s1/CLK
0.795 0.382 tC2Q RR 5 u_apb_gpio/u_apb_gpio_gpio/db_cntr_0_s1/Q
1.207 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/n336_s1/I0
1.786 0.579 tINS RR 4 u_apb_gpio/u_apb_gpio_gpio/n336_s1/F
2.199 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/n333_s2/I3
2.487 0.289 tINS RR 2 u_apb_gpio/u_apb_gpio_gpio/n333_s2/F
2.900 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/n421_s1/I2
3.408 0.507 tINS RR 11 u_apb_gpio/u_apb_gpio_gpio/n421_s1/F
3.820 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_0_s3/I0
4.399 0.579 tINS RR 2 u_apb_gpio/u_apb_gpio_gpio/debounce_1_0_s3/F
4.811 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 64 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_0_s1/CLK
10.101 -0.311 tSu 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.954, 44.416%; route: 2.063, 46.888%; tC2Q: 0.382, 8.696%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 5.290
Data Arrival Time 4.811
Data Required Time 10.101
From u_apb_gpio/u_apb_gpio_gpio/db_cntr_0_s1
To u_apb_gpio/u_apb_gpio_gpio/debounce_1_1_s1
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 64 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/db_cntr_0_s1/CLK
0.795 0.382 tC2Q RR 5 u_apb_gpio/u_apb_gpio_gpio/db_cntr_0_s1/Q
1.207 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/n336_s1/I0
1.786 0.579 tINS RR 4 u_apb_gpio/u_apb_gpio_gpio/n336_s1/F
2.199 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/n333_s2/I3
2.487 0.289 tINS RR 2 u_apb_gpio/u_apb_gpio_gpio/n333_s2/F
2.900 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/n421_s1/I2
3.408 0.507 tINS RR 11 u_apb_gpio/u_apb_gpio_gpio/n421_s1/F
3.820 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_1_s3/I0
4.399 0.579 tINS RR 2 u_apb_gpio/u_apb_gpio_gpio/debounce_1_1_s3/F
4.811 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 64 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_1_s1/CLK
10.101 -0.311 tSu 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.954, 44.416%; route: 2.063, 46.888%; tC2Q: 0.382, 8.696%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 5.290
Data Arrival Time 4.811
Data Required Time 10.101
From u_apb_gpio/u_apb_gpio_gpio/db_cntr_0_s1
To u_apb_gpio/u_apb_gpio_gpio/debounce_1_2_s1
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 64 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/db_cntr_0_s1/CLK
0.795 0.382 tC2Q RR 5 u_apb_gpio/u_apb_gpio_gpio/db_cntr_0_s1/Q
1.207 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/n336_s1/I0
1.786 0.579 tINS RR 4 u_apb_gpio/u_apb_gpio_gpio/n336_s1/F
2.199 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/n333_s2/I3
2.487 0.289 tINS RR 2 u_apb_gpio/u_apb_gpio_gpio/n333_s2/F
2.900 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/n421_s1/I2
3.408 0.507 tINS RR 11 u_apb_gpio/u_apb_gpio_gpio/n421_s1/F
3.820 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_2_s3/I0
4.399 0.579 tINS RR 2 u_apb_gpio/u_apb_gpio_gpio/debounce_1_2_s3/F
4.811 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 64 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_2_s1/CLK
10.101 -0.311 tSu 1 u_apb_gpio/u_apb_gpio_gpio/debounce_1_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 1.954, 44.416%; route: 2.063, 46.888%; tC2Q: 0.382, 8.696%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%