Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBI2C\data\apb_i2c_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBI2C\data\apb_i2c.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Tue May 6 14:18:50 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module APB_I2C_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.269s, Peak memory usage = 70.953MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 70.953MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 70.953MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 70.953MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 70.953MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 70.953MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 70.953MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 70.953MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 70.953MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 70.953MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 70.953MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 70.953MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 95.914MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 95.914MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 95.914MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 95.914MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 82
I/O Buf 77
    IBUF 39
    OBUF 38
Register 170
    DFFRE 32
    DFFPE 26
    DFFCE 112
LUT 552
    LUT2 76
    LUT3 165
    LUT4 311
ALU 52
    ALU 52
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 605(553 LUT, 52 ALU) / 138240 <1%
Register 170 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 170 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 pclk Base 10.000 100.000 0.000 5.000 pclk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 pclk 100.000(MHz) 84.379(MHz) 14 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.851
Data Arrival Time 12.200
Data Required Time 10.349
From u_apb_i2c/u_apbslv/t_sp_0_s0
To u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/empty_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 170 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_i2c/u_apbslv/t_sp_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_apb_i2c/u_apbslv/t_sp_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_i2c/u_sda_gsf/n4_s0/I1
1.807 0.600 tINS RF 1 u_apb_i2c/u_sda_gsf/n4_s0/COUT
1.807 0.000 tNET FF 2 u_apb_i2c/u_sda_gsf/n5_s0/CIN
1.857 0.050 tINS FR 1 u_apb_i2c/u_sda_gsf/n5_s0/COUT
1.857 0.000 tNET RR 2 u_apb_i2c/u_sda_gsf/n6_s0/CIN
1.907 0.050 tINS RR 3 u_apb_i2c/u_sda_gsf/n6_s0/COUT
2.320 0.413 tNET RR 1 u_apb_i2c/u_apbslv/int_st_start_s5/I0
2.899 0.579 tINS RR 4 u_apb_i2c/u_apbslv/int_st_start_s5/F
3.311 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n558_s12/I2
3.819 0.507 tINS RR 10 u_apb_i2c/u_ctrl/n558_s12/F
4.231 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s7/I0
4.810 0.579 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s7/F
5.222 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s3/I2
5.730 0.507 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s3/F
6.142 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s2/I0
6.721 0.579 tINS RR 9 u_apb_i2c/u_ctrl/ns_0_s2/F
7.134 0.413 tNET RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s3/I0
7.713 0.579 tINS RR 2 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s3/F
8.125 0.413 tNET RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s6/I0
8.704 0.579 tINS RR 7 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s6/F
9.116 0.413 tNET RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_0_s0/I1
9.684 0.567 tINS RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_0_s0/F
10.096 0.413 tNET RR 2 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/n28_s0/I1
10.696 0.600 tINS RF 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/n28_s0/COUT
10.696 0.000 tNET FF 2 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/n29_s0/CIN
10.746 0.050 tINS FR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/n29_s0/COUT
10.746 0.000 tNET RR 2 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/n31_s0/CIN
10.796 0.050 tINS RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/n31_s0/COUT
11.209 0.413 tNET RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/n58_s2/I0
11.788 0.579 tINS RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/n58_s2/F
12.200 0.413 tNET RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 170 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/empty_s0/CLK
10.349 -0.064 tSu 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 6.455, 54.761%; route: 4.950, 41.994%; tC2Q: 0.382, 3.245%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack -0.915
Data Arrival Time 11.016
Data Required Time 10.101
From u_apb_i2c/u_apbslv/t_sp_0_s0
To u_apb_i2c/u_ctrl/sr_ready_s1
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 170 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_i2c/u_apbslv/t_sp_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_apb_i2c/u_apbslv/t_sp_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_i2c/u_sda_gsf/n4_s0/I1
1.807 0.600 tINS RF 1 u_apb_i2c/u_sda_gsf/n4_s0/COUT
1.807 0.000 tNET FF 2 u_apb_i2c/u_sda_gsf/n5_s0/CIN
1.857 0.050 tINS FR 1 u_apb_i2c/u_sda_gsf/n5_s0/COUT
1.857 0.000 tNET RR 2 u_apb_i2c/u_sda_gsf/n6_s0/CIN
1.907 0.050 tINS RR 3 u_apb_i2c/u_sda_gsf/n6_s0/COUT
2.320 0.413 tNET RR 1 u_apb_i2c/u_apbslv/int_st_start_s5/I0
2.899 0.579 tINS RR 4 u_apb_i2c/u_apbslv/int_st_start_s5/F
3.311 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n558_s12/I2
3.819 0.507 tINS RR 10 u_apb_i2c/u_ctrl/n558_s12/F
4.231 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s7/I0
4.810 0.579 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s7/F
5.222 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s3/I2
5.730 0.507 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s3/F
6.142 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s2/I0
6.721 0.579 tINS RR 9 u_apb_i2c/u_ctrl/ns_0_s2/F
7.134 0.413 tNET RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s3/I0
7.713 0.579 tINS RR 2 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s3/F
8.125 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n605_s7/I2
8.632 0.507 tINS RR 2 u_apb_i2c/u_ctrl/n605_s7/F
9.045 0.413 tNET RR 1 u_apb_i2c/u_ctrl/sr_ready_s4/I0
9.624 0.579 tINS RR 1 u_apb_i2c/u_ctrl/sr_ready_s4/F
10.036 0.413 tNET RR 1 u_apb_i2c/u_ctrl/sr_ready_s3/I1
10.604 0.567 tINS RR 1 u_apb_i2c/u_ctrl/sr_ready_s3/F
11.016 0.413 tNET RR 1 u_apb_i2c/u_ctrl/sr_ready_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 170 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_i2c/u_ctrl/sr_ready_s1/CLK
10.101 -0.311 tSu 1 u_apb_i2c/u_ctrl/sr_ready_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.684, 53.602%; route: 4.537, 42.791%; tC2Q: 0.382, 3.607%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack -0.855
Data Arrival Time 10.956
Data Required Time 10.101
From u_apb_i2c/u_apbslv/t_sp_0_s0
To u_apb_i2c/u_ctrl/ack_ready_s1
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 170 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_i2c/u_apbslv/t_sp_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_apb_i2c/u_apbslv/t_sp_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_i2c/u_sda_gsf/n4_s0/I1
1.807 0.600 tINS RF 1 u_apb_i2c/u_sda_gsf/n4_s0/COUT
1.807 0.000 tNET FF 2 u_apb_i2c/u_sda_gsf/n5_s0/CIN
1.857 0.050 tINS FR 1 u_apb_i2c/u_sda_gsf/n5_s0/COUT
1.857 0.000 tNET RR 2 u_apb_i2c/u_sda_gsf/n6_s0/CIN
1.907 0.050 tINS RR 3 u_apb_i2c/u_sda_gsf/n6_s0/COUT
2.320 0.413 tNET RR 1 u_apb_i2c/u_apbslv/int_st_start_s5/I0
2.899 0.579 tINS RR 4 u_apb_i2c/u_apbslv/int_st_start_s5/F
3.311 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n558_s12/I2
3.819 0.507 tINS RR 10 u_apb_i2c/u_ctrl/n558_s12/F
4.231 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s7/I0
4.810 0.579 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s7/F
5.222 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s3/I2
5.730 0.507 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s3/F
6.142 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s2/I0
6.721 0.579 tINS RR 9 u_apb_i2c/u_ctrl/ns_0_s2/F
7.134 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n1377_s3/I2
7.641 0.507 tINS RR 9 u_apb_i2c/u_ctrl/n1377_s3/F
8.054 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n1377_s6/I0
8.632 0.579 tINS RR 1 u_apb_i2c/u_ctrl/n1377_s6/F
9.045 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n722_s2/I0
9.624 0.579 tINS RR 2 u_apb_i2c/u_ctrl/n722_s2/F
10.036 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ack_ready_s3/I2
10.544 0.507 tINS RR 1 u_apb_i2c/u_ctrl/ack_ready_s3/F
10.956 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ack_ready_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 170 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ack_ready_s1/CLK
10.101 -0.311 tSu 1 u_apb_i2c/u_ctrl/ack_ready_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.624, 53.337%; route: 4.537, 43.035%; tC2Q: 0.382, 3.628%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack -0.855
Data Arrival Time 10.956
Data Required Time 10.101
From u_apb_i2c/u_apbslv/t_sp_0_s0
To u_apb_i2c/u_apbslv/datacnt_0_s1
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 170 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_i2c/u_apbslv/t_sp_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_apb_i2c/u_apbslv/t_sp_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_i2c/u_sda_gsf/n4_s0/I1
1.807 0.600 tINS RF 1 u_apb_i2c/u_sda_gsf/n4_s0/COUT
1.807 0.000 tNET FF 2 u_apb_i2c/u_sda_gsf/n5_s0/CIN
1.857 0.050 tINS FR 1 u_apb_i2c/u_sda_gsf/n5_s0/COUT
1.857 0.000 tNET RR 2 u_apb_i2c/u_sda_gsf/n6_s0/CIN
1.907 0.050 tINS RR 3 u_apb_i2c/u_sda_gsf/n6_s0/COUT
2.320 0.413 tNET RR 1 u_apb_i2c/u_apbslv/int_st_start_s5/I0
2.899 0.579 tINS RR 4 u_apb_i2c/u_apbslv/int_st_start_s5/F
3.311 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n558_s12/I2
3.819 0.507 tINS RR 10 u_apb_i2c/u_ctrl/n558_s12/F
4.231 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s7/I0
4.810 0.579 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s7/F
5.222 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s3/I2
5.730 0.507 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s3/F
6.142 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s2/I0
6.721 0.579 tINS RR 9 u_apb_i2c/u_ctrl/ns_0_s2/F
7.134 0.413 tNET RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s3/I0
7.713 0.579 tINS RR 2 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s3/F
8.125 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n605_s7/I2
8.632 0.507 tINS RR 2 u_apb_i2c/u_ctrl/n605_s7/F
9.045 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n605_s3/I2
9.552 0.507 tINS RR 10 u_apb_i2c/u_ctrl/n605_s3/F
9.965 0.413 tNET RR 1 u_apb_i2c/u_apbslv/datacnt_8_s3/I0
10.544 0.579 tINS RR 9 u_apb_i2c/u_apbslv/datacnt_8_s3/F
10.956 0.413 tNET RR 1 u_apb_i2c/u_apbslv/datacnt_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 170 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_i2c/u_apbslv/datacnt_0_s1/CLK
10.101 -0.311 tSu 1 u_apb_i2c/u_apbslv/datacnt_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.624, 53.337%; route: 4.537, 43.035%; tC2Q: 0.382, 3.628%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack -0.855
Data Arrival Time 10.956
Data Required Time 10.101
From u_apb_i2c/u_apbslv/t_sp_0_s0
To u_apb_i2c/u_apbslv/datacnt_1_s1
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 170 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_i2c/u_apbslv/t_sp_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_apb_i2c/u_apbslv/t_sp_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_i2c/u_sda_gsf/n4_s0/I1
1.807 0.600 tINS RF 1 u_apb_i2c/u_sda_gsf/n4_s0/COUT
1.807 0.000 tNET FF 2 u_apb_i2c/u_sda_gsf/n5_s0/CIN
1.857 0.050 tINS FR 1 u_apb_i2c/u_sda_gsf/n5_s0/COUT
1.857 0.000 tNET RR 2 u_apb_i2c/u_sda_gsf/n6_s0/CIN
1.907 0.050 tINS RR 3 u_apb_i2c/u_sda_gsf/n6_s0/COUT
2.320 0.413 tNET RR 1 u_apb_i2c/u_apbslv/int_st_start_s5/I0
2.899 0.579 tINS RR 4 u_apb_i2c/u_apbslv/int_st_start_s5/F
3.311 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n558_s12/I2
3.819 0.507 tINS RR 10 u_apb_i2c/u_ctrl/n558_s12/F
4.231 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s7/I0
4.810 0.579 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s7/F
5.222 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s3/I2
5.730 0.507 tINS RR 1 u_apb_i2c/u_ctrl/ns_0_s3/F
6.142 0.413 tNET RR 1 u_apb_i2c/u_ctrl/ns_0_s2/I0
6.721 0.579 tINS RR 9 u_apb_i2c/u_ctrl/ns_0_s2/F
7.134 0.413 tNET RR 1 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s3/I0
7.713 0.579 tINS RR 2 u_apb_i2c/u_fifo/u_apb_i2c_sync_fifo/next_rd_ptr_2_s3/F
8.125 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n605_s7/I2
8.632 0.507 tINS RR 2 u_apb_i2c/u_ctrl/n605_s7/F
9.045 0.413 tNET RR 1 u_apb_i2c/u_ctrl/n605_s3/I2
9.552 0.507 tINS RR 10 u_apb_i2c/u_ctrl/n605_s3/F
9.965 0.413 tNET RR 1 u_apb_i2c/u_apbslv/datacnt_8_s3/I0
10.544 0.579 tINS RR 9 u_apb_i2c/u_apbslv/datacnt_8_s3/F
10.956 0.413 tNET RR 1 u_apb_i2c/u_apbslv/datacnt_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 170 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_i2c/u_apbslv/datacnt_1_s1/CLK
10.101 -0.311 tSu 1 u_apb_i2c/u_apbslv/datacnt_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.624, 53.337%; route: 4.537, 43.035%; tC2Q: 0.382, 3.628%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%