Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBPIT\data\apb_pit_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBPIT\data\apb_pit.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Tue May 6 15:20:49 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module APB_PIT_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.283s, Peak memory usage = 70.695MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 70.695MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 70.695MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 70.695MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 70.695MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 70.695MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 70.695MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 70.695MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 70.695MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 70.695MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 70.695MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 70.695MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 98.500MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 98.500MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 98.500MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 98.500MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 87
I/O Buf 87
    IBUF 44
    OBUF 43
Register 333
    DFFCE 333
LUT 763
    LUT2 113
    LUT3 122
    LUT4 528
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 764(764 LUT, 0 ALU) / 138240 <1%
Register 333 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 333 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 pclk Base 10.000 100.000 0.000 5.000 pclk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 pclk 100.000(MHz) 164.948(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.938
Data Arrival Time 6.164
Data Required Time 10.101
From u_apb_pit/u_ch0/u_cntr0/cntr_0_s0
To u_apb_pit/u_ch0/u_cntr3/cntr_7_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 333 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/Q
1.207 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/I0
1.786 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/F
2.199 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s6/I0
2.778 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr2/en_s6/F
3.190 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s10/I0
3.769 0.579 tINS RR 2 u_apb_pit/u_ch0/u_cntr2/en_s10/F
4.181 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/I0
4.760 0.579 tINS RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/F
5.173 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s1/I0
5.751 0.579 tINS RR 8 u_apb_pit/u_ch0/u_cntr3/en_s1/F
6.164 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_7_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 333 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_7_s0/CLK
10.101 -0.311 tSu 1 u_apb_pit/u_ch0/u_cntr3/cntr_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.894, 50.315%; route: 2.475, 43.034%; tC2Q: 0.382, 6.651%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 3.938
Data Arrival Time 6.164
Data Required Time 10.101
From u_apb_pit/u_ch0/u_cntr0/cntr_0_s0
To u_apb_pit/u_ch0/u_cntr3/cntr_0_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 333 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/Q
1.207 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/I0
1.786 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/F
2.199 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s6/I0
2.778 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr2/en_s6/F
3.190 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s10/I0
3.769 0.579 tINS RR 2 u_apb_pit/u_ch0/u_cntr2/en_s10/F
4.181 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/I0
4.760 0.579 tINS RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/F
5.173 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s1/I0
5.751 0.579 tINS RR 8 u_apb_pit/u_ch0/u_cntr3/en_s1/F
6.164 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 333 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_0_s0/CLK
10.101 -0.311 tSu 1 u_apb_pit/u_ch0/u_cntr3/cntr_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.894, 50.315%; route: 2.475, 43.034%; tC2Q: 0.382, 6.651%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 3.938
Data Arrival Time 6.164
Data Required Time 10.101
From u_apb_pit/u_ch0/u_cntr0/cntr_0_s0
To u_apb_pit/u_ch0/u_cntr3/cntr_1_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 333 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/Q
1.207 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/I0
1.786 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/F
2.199 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s6/I0
2.778 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr2/en_s6/F
3.190 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s10/I0
3.769 0.579 tINS RR 2 u_apb_pit/u_ch0/u_cntr2/en_s10/F
4.181 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/I0
4.760 0.579 tINS RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/F
5.173 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s1/I0
5.751 0.579 tINS RR 8 u_apb_pit/u_ch0/u_cntr3/en_s1/F
6.164 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 333 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_1_s0/CLK
10.101 -0.311 tSu 1 u_apb_pit/u_ch0/u_cntr3/cntr_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.894, 50.315%; route: 2.475, 43.034%; tC2Q: 0.382, 6.651%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 3.938
Data Arrival Time 6.164
Data Required Time 10.101
From u_apb_pit/u_ch0/u_cntr0/cntr_0_s0
To u_apb_pit/u_ch0/u_cntr3/cntr_2_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 333 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/Q
1.207 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/I0
1.786 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/F
2.199 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s6/I0
2.778 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr2/en_s6/F
3.190 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s10/I0
3.769 0.579 tINS RR 2 u_apb_pit/u_ch0/u_cntr2/en_s10/F
4.181 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/I0
4.760 0.579 tINS RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/F
5.173 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s1/I0
5.751 0.579 tINS RR 8 u_apb_pit/u_ch0/u_cntr3/en_s1/F
6.164 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 333 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_2_s0/CLK
10.101 -0.311 tSu 1 u_apb_pit/u_ch0/u_cntr3/cntr_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.894, 50.315%; route: 2.475, 43.034%; tC2Q: 0.382, 6.651%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 3.938
Data Arrival Time 6.164
Data Required Time 10.101
From u_apb_pit/u_ch0/u_cntr0/cntr_0_s0
To u_apb_pit/u_ch0/u_cntr3/cntr_3_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 333 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_0_s0/Q
1.207 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/I0
1.786 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr0/cntr_nx_4_s1/F
2.199 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s6/I0
2.778 0.579 tINS RR 6 u_apb_pit/u_ch0/u_cntr2/en_s6/F
3.190 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr2/en_s10/I0
3.769 0.579 tINS RR 2 u_apb_pit/u_ch0/u_cntr2/en_s10/F
4.181 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/I0
4.760 0.579 tINS RR 1 u_apb_pit/u_ch0/u_cntr3/en_s6/F
5.173 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/en_s1/I0
5.751 0.579 tINS RR 8 u_apb_pit/u_ch0/u_cntr3/en_s1/F
6.164 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 333 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_pit/u_ch0/u_cntr3/cntr_3_s0/CLK
10.101 -0.311 tSu 1 u_apb_pit/u_ch0/u_cntr3/cntr_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.894, 50.315%; route: 2.475, 43.034%; tC2Q: 0.382, 6.651%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%