Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBRTC\data\apb_rtc_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBRTC\data\apb_rtc.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC1/I0 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue May 6 16:09:08 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | APB_RTC_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.262s, Peak memory usage = 70.801MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 70.801MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 70.801MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 70.801MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 70.801MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 70.801MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 70.801MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 70.801MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 70.801MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 70.801MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 70.801MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 70.801MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 95.496MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 95.496MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 95.496MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 95.496MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 86 |
| I/O Buf | 84 |
| IBUF | 41 |
| OBUF | 43 |
| Register | 196 |
| DFFPE | 1 |
| DFFCE | 195 |
| LUT | 461 |
| LUT2 | 48 |
| LUT3 | 76 |
| LUT4 | 337 |
| INV | 3 |
| INV | 3 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 464(464 LUT, 0 ALU) / 138240 | <1% |
| Register | 196 / 139140 | <1% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 196 / 139140 | <1% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | rtc_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | rtc_clk_ibuf/I | ||
| 2 | pclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | pclk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | rtc_clk | 100.000(MHz) | 93.327(MHz) | 11 | TOP |
| 2 | pclk | 100.000(MHz) | 163.599(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.715 |
| Data Arrival Time | 11.064 |
| Data Required Time | 10.349 |
| From | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0 |
| To | u_apb_rtc/u_pulsegen/counter_5_s0 |
| Launch Clk | rtc_clk[R] |
| Latch Clk | rtc_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | rtc_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n391_s14/I0 |
| 2.778 | 0.579 | tINS | RR | 17 | u_apb_rtc/u_pulsegen/n391_s14/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/I1 |
| 3.758 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s5/I1 |
| 4.738 | 0.567 | tINS | RR | 8 | u_apb_rtc/u_pulsegen/n392_s5/F |
| 5.150 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n390_s14/I1 |
| 5.718 | 0.567 | tINS | RR | 5 | u_apb_rtc/u_pulsegen/n390_s14/F |
| 6.130 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s14/I0 |
| 6.709 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/n388_s14/F |
| 7.121 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s7/I0 |
| 7.700 | 0.579 | tINS | RR | 2 | u_apb_rtc/u_pulsegen/n388_s7/F |
| 8.113 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s4/I0 |
| 8.691 | 0.579 | tINS | RR | 10 | u_apb_rtc/u_pulsegen/n388_s4/F |
| 9.104 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n387_s2/I1 |
| 9.671 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n387_s2/F |
| 10.084 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n387_s1/I1 |
| 10.651 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n387_s1/F |
| 11.064 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | rtc_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_5_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | u_apb_rtc/u_pulsegen/counter_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 5.731, 53.808%; route: 4.537, 42.601%; tC2Q: 0.382, 3.591% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | -0.715 |
| Data Arrival Time | 11.064 |
| Data Required Time | 10.349 |
| From | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0 |
| To | u_apb_rtc/u_pulsegen/counter_7_s0 |
| Launch Clk | rtc_clk[R] |
| Latch Clk | rtc_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | rtc_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n391_s14/I0 |
| 2.778 | 0.579 | tINS | RR | 17 | u_apb_rtc/u_pulsegen/n391_s14/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/I1 |
| 3.758 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s5/I1 |
| 4.738 | 0.567 | tINS | RR | 8 | u_apb_rtc/u_pulsegen/n392_s5/F |
| 5.150 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n390_s14/I1 |
| 5.718 | 0.567 | tINS | RR | 5 | u_apb_rtc/u_pulsegen/n390_s14/F |
| 6.130 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s14/I0 |
| 6.709 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/n388_s14/F |
| 7.121 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s7/I0 |
| 7.700 | 0.579 | tINS | RR | 2 | u_apb_rtc/u_pulsegen/n388_s7/F |
| 8.113 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s4/I0 |
| 8.691 | 0.579 | tINS | RR | 10 | u_apb_rtc/u_pulsegen/n388_s4/F |
| 9.104 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n385_s2/I1 |
| 9.671 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n385_s2/F |
| 10.084 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n385_s1/I1 |
| 10.651 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n385_s1/F |
| 11.064 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | rtc_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_7_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | u_apb_rtc/u_pulsegen/counter_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 5.731, 53.808%; route: 4.537, 42.601%; tC2Q: 0.382, 3.591% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | -0.715 |
| Data Arrival Time | 11.064 |
| Data Required Time | 10.349 |
| From | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0 |
| To | u_apb_rtc/u_pulsegen/counter_9_s0 |
| Launch Clk | rtc_clk[R] |
| Latch Clk | rtc_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | rtc_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n391_s14/I0 |
| 2.778 | 0.579 | tINS | RR | 17 | u_apb_rtc/u_pulsegen/n391_s14/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/I1 |
| 3.758 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s5/I1 |
| 4.738 | 0.567 | tINS | RR | 8 | u_apb_rtc/u_pulsegen/n392_s5/F |
| 5.150 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n390_s14/I1 |
| 5.718 | 0.567 | tINS | RR | 5 | u_apb_rtc/u_pulsegen/n390_s14/F |
| 6.130 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s14/I0 |
| 6.709 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/n388_s14/F |
| 7.121 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s7/I0 |
| 7.700 | 0.579 | tINS | RR | 2 | u_apb_rtc/u_pulsegen/n388_s7/F |
| 8.113 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s4/I0 |
| 8.691 | 0.579 | tINS | RR | 10 | u_apb_rtc/u_pulsegen/n388_s4/F |
| 9.104 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n383_s2/I1 |
| 9.671 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n383_s2/F |
| 10.084 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n383_s1/I1 |
| 10.651 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n383_s1/F |
| 11.064 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_9_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | rtc_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_9_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | u_apb_rtc/u_pulsegen/counter_9_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 5.731, 53.808%; route: 4.537, 42.601%; tC2Q: 0.382, 3.591% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | -0.715 |
| Data Arrival Time | 11.064 |
| Data Required Time | 10.349 |
| From | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0 |
| To | u_apb_rtc/u_pulsegen/counter_10_s0 |
| Launch Clk | rtc_clk[R] |
| Latch Clk | rtc_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | rtc_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n391_s14/I0 |
| 2.778 | 0.579 | tINS | RR | 17 | u_apb_rtc/u_pulsegen/n391_s14/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/I1 |
| 3.758 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s5/I1 |
| 4.738 | 0.567 | tINS | RR | 8 | u_apb_rtc/u_pulsegen/n392_s5/F |
| 5.150 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n390_s14/I1 |
| 5.718 | 0.567 | tINS | RR | 5 | u_apb_rtc/u_pulsegen/n390_s14/F |
| 6.130 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s14/I0 |
| 6.709 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/n388_s14/F |
| 7.121 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s7/I0 |
| 7.700 | 0.579 | tINS | RR | 2 | u_apb_rtc/u_pulsegen/n388_s7/F |
| 8.113 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s4/I0 |
| 8.691 | 0.579 | tINS | RR | 10 | u_apb_rtc/u_pulsegen/n388_s4/F |
| 9.104 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n382_s2/I1 |
| 9.671 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n382_s2/F |
| 10.084 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n382_s1/I1 |
| 10.651 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n382_s1/F |
| 11.064 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | rtc_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_10_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | u_apb_rtc/u_pulsegen/counter_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 5.731, 53.808%; route: 4.537, 42.601%; tC2Q: 0.382, 3.591% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | -0.715 |
| Data Arrival Time | 11.064 |
| Data Required Time | 10.349 |
| From | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0 |
| To | u_apb_rtc/u_pulsegen/counter_4_s0 |
| Launch Clk | rtc_clk[R] |
| Latch Clk | rtc_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | rtc_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_apb_rtc/u_apbif/reg_min_trim_rtclk_1_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/trim_ns_1_s17/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n391_s14/I0 |
| 2.778 | 0.579 | tINS | RR | 17 | u_apb_rtc/u_pulsegen/n391_s14/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/I1 |
| 3.758 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n392_s14/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n392_s5/I1 |
| 4.738 | 0.567 | tINS | RR | 8 | u_apb_rtc/u_pulsegen/n392_s5/F |
| 5.150 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n387_s7/I1 |
| 5.718 | 0.567 | tINS | RR | 7 | u_apb_rtc/u_pulsegen/n387_s7/F |
| 6.130 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n389_s15/I0 |
| 6.709 | 0.579 | tINS | RR | 3 | u_apb_rtc/u_pulsegen/n389_s15/F |
| 7.121 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n389_s7/I1 |
| 7.689 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n389_s7/F |
| 8.101 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n389_s4/I0 |
| 8.680 | 0.579 | tINS | RR | 11 | u_apb_rtc/u_pulsegen/n389_s4/F |
| 9.093 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s21/I0 |
| 9.671 | 0.579 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n388_s21/F |
| 10.084 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/n388_s1/I1 |
| 10.651 | 0.567 | tINS | RR | 1 | u_apb_rtc/u_pulsegen/n388_s1/F |
| 11.064 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | rtc_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | rtc_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 99 | rtc_clk_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_apb_rtc/u_pulsegen/counter_4_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | u_apb_rtc/u_pulsegen/counter_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 5.731, 53.808%; route: 4.537, 42.601%; tC2Q: 0.382, 3.591% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |