Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ahb_def_slave.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\BusMatrix.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_adder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_alu_dec.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_core.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl_add3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_dec.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_bp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_define.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_dw.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_dbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_sys.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_rom_tb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_sys.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_tcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_decoder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_excpt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fetch.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fns.vh D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_matrix_check_fns.vh D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mem_ctl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiplier.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiply_shift.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mux4.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb_os.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_main.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_lvl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_num.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_tree.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_reg_bank.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_shifter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_undefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_miim_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_to_buffer.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_tx_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_arbiter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_async_fifo_clr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_config.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_const.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_fifo.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_gck.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_pad_lib.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_reg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif_ctrl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_spiif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_l2l.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_p2p.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_to_iop.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_frc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_spi.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_timer.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_autocorrelation.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_balancefilter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_collector.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_crngt_to_trng.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_inv_chain.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_trng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_ff.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_interrupt_low.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux_clk.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_ehr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_entropy_gen.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_gtech_models.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_lfsr_new.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_line.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_noise_gen.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_pmf_table.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_prng_top_wrap.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_reg_file.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_engine.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_misc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rosc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rst_logic.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sample_cntr.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_slave_bus_ifc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_tests_misc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_uart.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_defs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_frc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_iop_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1Dbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegration.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegrationWrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapahbap.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApAhbSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDapSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApMst.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSlv.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSyn.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDecMux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpEnSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpIMux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpProtocol.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpApbIf.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpProtocol.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpSync.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapswjdp.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjDpDefs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjWatcher.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_to_ahb_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dtcmdbg.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\eth_mac_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Gowin_EMPU_M1_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinAhbExt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExtWrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_ahb_psram.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_i2c.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_int_wrapper.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_sd.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_gpio.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\InputStage.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\itcmdbg_2ac.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS0.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage1.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage2.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_ahb_to_apb.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_apb_slave_mux.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_code.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\PSRAM_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_addr_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_cc_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_params.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Rtc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcApbif.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcControl.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcCounter.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcInterrupt.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcParams.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcRevAnd.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcSynctoPCLK.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcUpdate.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_int_apb_decoder.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_integration_peripherals.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sync_p2p.v F:\EMB_pub\embedded\peripherals\APB_SD_Host\ref_design\1.0\FPGA_RefDesign\DK_START_GW2A18_V2.0\apb_sd_host\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v F:\EMB_pub\embedded\peripherals\APB_SD_Host\ref_design\1.0\FPGA_RefDesign\DK_START_GW2A18_V2.0\apb_sd_host\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v F:\EMB_pub\embedded\peripherals\APB_SD_Host\ref_design\1.0\FPGA_RefDesign\DK_START_GW2A18_V2.0\apb_sd_host\src\gowin_empu_m1\temp\gw_empu_m1\parameter.vh F:\EMB_pub\embedded\peripherals\APB_SD_Host\ref_design\1.0\FPGA_RefDesign\DK_START_GW2A18_V2.0\apb_sd_host\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v F:\EMB_pub\embedded\peripherals\APB_SD_Host\ref_design\1.0\FPGA_RefDesign\DK_START_GW2A18_V2.0\apb_sd_host\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v F:\EMB_pub\embedded\peripherals\APB_SD_Host\ref_design\1.0\FPGA_RefDesign\DK_START_GW2A18_V2.0\apb_sd_host\src\gowin_empu_m1\temp\gw_empu_m1\DDR3_define.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Tue Apr 29 11:02:09 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_M1_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 7s, Peak memory usage = 173.871MB Running netlist conversion: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 173.871MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 173.871MB Optimizing Phase 1: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.373s, Peak memory usage = 173.871MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 173.871MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.722s, Peak memory usage = 173.871MB Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.094s, Peak memory usage = 173.871MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 173.871MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 173.871MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 173.871MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.257s, Peak memory usage = 173.871MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.463s, Peak memory usage = 173.871MB Tech-Mapping Phase 3: CPU time = 0h 0m 29s, Elapsed time = 0h 0m 29s, Peak memory usage = 173.871MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 1s, Peak memory usage = 173.871MB Generate output files: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.815s, Peak memory usage = 174.066MB |
Total Time and Memory Usage | CPU time = 0h 0m 40s, Elapsed time = 0h 0m 42s, Peak memory usage = 174.066MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 128 |
I/O Buf | 128 |
    IBUF | 42 |
    OBUF | 79 |
    IOBUF | 7 |
Register | 2966 |
    DFF | 94 |
    DFFE | 32 |
    DFFSE | 1 |
    DFFR | 3 |
    DFFRE | 1 |
    DFFP | 35 |
    DFFPE | 100 |
    DFFC | 585 |
    DFFCE | 2106 |
    DFFNPE | 7 |
    DL | 1 |
    DLN | 1 |
LUT | 6513 |
    LUT2 | 569 |
    LUT3 | 1916 |
    LUT4 | 4028 |
ALU | 275 |
    ALU | 275 |
SSRAM | 32 |
    RAM16SDP4 | 32 |
INV | 9 |
    INV | 9 |
DSP | |
    MULT36X36 | 1 |
BSRAM | 16 |
    DPB | 16 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 6989(6522 LUT, 275 ALU, 32 RAM16) / 20736 | 34% |
Register | 2966 / 16173 | 19% |
  --Register as Latch | 2 / 16173 | <1% |
  --Register as FF | 2964 / 16173 | 19% |
BSRAM | 16 / 46 | 35% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | HCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | HCLK_ibuf/I | ||
2 | JTAG_9 | Base | 10.000 | 100.000 | 0.000 | 5.000 | JTAG_9_ibuf/I | ||
3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | Base | 10.000 | 100.000 | 0.000 | 5.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | HCLK | 100.000(MHz) | 60.906(MHz) | 20 | TOP |
2 | JTAG_9 | 100.000(MHz) | 106.940(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -7.829 |
Data Arrival Time | 13.233 |
Data Required Time | 5.404 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s1 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2 |
Launch Clk | HCLK[F] |
Latch Clk | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 2833 | HCLK_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s1/CLK |
0.592 | 0.232 | tC2Q | RF | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s1/Q |
1.066 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s2/I1 |
1.621 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s2/F |
2.095 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s0/I1 |
2.650 | 0.555 | tINS | FF | 15 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s0/F |
3.124 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/I2 |
3.577 | 0.453 | tINS | FF | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/F |
4.051 | 0.474 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0 |
4.600 | 0.549 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT |
4.600 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN |
5.070 | 0.470 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM |
5.544 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0 |
6.061 | 0.517 | tINS | FF | 24 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F |
6.535 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/I2 |
6.988 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/F |
7.462 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/I1 |
7.565 | 0.103 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/O |
8.039 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/I1 |
8.142 | 0.103 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/O |
8.616 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/I1 |
8.719 | 0.103 | tINS | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/O |
9.193 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I1 |
9.748 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F |
10.222 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s8/I1 |
10.777 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s8/F |
11.251 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s10/I0 |
11.768 | 0.517 | tINS | FF | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s10/F |
12.242 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s3/I0 |
12.759 | 0.517 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n366_s3/F |
13.233 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | |||
5.000 | 0.000 | tCL | FF | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F |
5.474 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2/CLK |
5.439 | -0.035 | tUnc | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2 | ||
5.404 | -0.035 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_0_s2 |
Clock Skew: | 0.114 |
Setup Relationship: | 5.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 6.005, 46.648%; route: 6.636, 51.550%; tC2Q: 0.232, 1.802% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:Slack | -7.829 |
Data Arrival Time | 13.233 |
Data Required Time | 5.404 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s1 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2 |
Launch Clk | HCLK[F] |
Latch Clk | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 2833 | HCLK_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s1/CLK |
0.592 | 0.232 | tC2Q | RF | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_5_s1/Q |
1.066 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s2/I1 |
1.621 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s2/F |
2.095 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s0/I1 |
2.650 | 0.555 | tINS | FF | 15 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_trans_end_sclk_Z_s0/F |
3.124 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/I2 |
3.577 | 0.453 | tINS | FF | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_word_len_0_s5/F |
4.051 | 0.474 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/I0 |
4.600 | 0.549 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1232_s/COUT |
4.600 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/CIN |
5.070 | 0.470 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1231_s/SUM |
5.544 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/I0 |
6.061 | 0.517 | tINS | FF | 24 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ptr_1_s0/F |
6.535 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/I2 |
6.988 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s43/F |
7.462 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/I1 |
7.565 | 0.103 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s35/O |
8.039 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/I1 |
8.142 | 0.103 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s31/O |
8.616 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/I1 |
8.719 | 0.103 | tINS | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n1251_s29/O |
9.193 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/I1 |
9.748 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s7/F |
10.222 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s8/I1 |
10.777 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s8/F |
11.251 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s10/I0 |
11.768 | 0.517 | tINS | FF | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s10/F |
12.242 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s0/I0 |
12.759 | 0.517 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/n363_s0/F |
13.233 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_20 | |||
5.000 | 0.000 | tCL | FF | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_w_clk_slv_s9/F |
5.474 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2/CLK |
5.439 | -0.035 | tUnc | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2 | ||
5.404 | -0.035 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_spiif/spi_out_slv_r_1_s2 |
Clock Skew: | 0.114 |
Setup Relationship: | 5.000 |
Logic Level: | 13 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 6.005, 46.648%; route: 6.636, 51.550%; tC2Q: 0.232, 1.802% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:Slack | -6.419 |
Data Arrival Time | 16.744 |
Data Required Time | 10.325 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s1 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 2833 | HCLK_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s1/CLK |
0.592 | 0.232 | tC2Q | RF | 6 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s1/Q |
1.066 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I1 |
1.621 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F |
2.095 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I0 |
2.612 | 0.517 | tINS | FF | 13 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F |
3.086 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.539 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F |
4.013 | 0.474 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1 |
4.583 | 0.570 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT |
4.583 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN |
4.618 | 0.035 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT |
4.618 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN |
4.653 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT |
4.653 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN |
4.689 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT |
4.689 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN |
4.724 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT |
4.724 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN |
4.759 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT |
4.759 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN |
4.794 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT |
4.794 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN |
4.829 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT |
4.829 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN |
4.865 | 0.035 | tINS | FF | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT |
5.339 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s15/I0 |
5.856 | 0.517 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s15/F |
6.330 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s12/I2 |
6.783 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s12/F |
7.257 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/I1 |
7.812 | 0.555 | tINS | FF | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/F |
8.286 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ready_s6/I2 |
8.739 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ready_s6/F |
9.213 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ready_s4/I3 |
9.584 | 0.371 | tINS | FF | 3 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/tx_ready_s4/F |
10.058 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_2_s3/I0 |
10.575 | 0.517 | tINS | FF | 4 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_2_s3/F |
11.049 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_2_s2/I0 |
11.566 | 0.517 | tINS | FF | 8 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_2_s2/F |
12.040 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s3/I3 |
12.411 | 0.371 | tINS | FF | 24 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s3/F |
12.885 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s1/I2 |
13.338 | 0.453 | tINS | FF | 15 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s1/F |
13.812 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s5/I3 |
14.183 | 0.371 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s5/F |
14.657 | 0.474 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n328_s0/I0 |
15.206 | 0.549 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n328_s0/COUT |
15.206 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n329_s0/CIN |
15.241 | 0.035 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n329_s0/COUT |
15.715 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n332_s2/I1 |
16.270 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/n332_s2/F |
16.744 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 2833 | HCLK_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0/CLK |
10.325 | -0.035 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_fifo/u_spi_txfifo/empty_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 20 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 8.094, 49.401%; route: 8.058, 49.183%; tC2Q: 0.232, 1.416% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:Slack | -5.977 |
Data Arrival Time | 16.302 |
Data Required Time | 10.325 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s1 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 2833 | HCLK_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s1/CLK |
0.592 | 0.232 | tC2Q | RF | 6 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s1/Q |
1.066 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I1 |
1.621 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F |
2.095 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I0 |
2.612 | 0.517 | tINS | FF | 13 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F |
3.086 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.539 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F |
4.013 | 0.474 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1 |
4.583 | 0.570 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT |
4.583 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN |
4.618 | 0.035 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT |
4.618 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN |
4.653 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT |
4.653 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN |
4.689 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT |
4.689 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN |
4.724 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT |
4.724 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN |
4.759 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT |
4.759 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN |
4.794 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT |
4.794 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN |
4.829 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT |
4.829 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN |
4.865 | 0.035 | tINS | FF | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT |
5.339 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s15/I0 |
5.856 | 0.517 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s15/F |
6.330 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s12/I2 |
6.783 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s12/F |
7.257 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/I1 |
7.812 | 0.555 | tINS | FF | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/F |
8.286 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s11/I0 |
8.803 | 0.517 | tINS | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s11/F |
9.277 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s6/I0 |
9.794 | 0.517 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s6/F |
10.268 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s3/I0 |
10.785 | 0.517 | tINS | FF | 9 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s3/F |
11.259 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/I0 |
11.776 | 0.517 | tINS | FF | 21 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/F |
12.250 | 0.474 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/I1 |
12.820 | 0.570 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/COUT |
12.820 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/CIN |
12.855 | 0.035 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT |
12.855 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN |
12.890 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT |
12.890 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN |
12.925 | 0.035 | tINS | FF | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT |
13.399 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/I1 |
13.954 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/F |
14.428 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
14.799 | 0.371 | tINS | FF | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/F |
15.273 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n497_s2/I1 |
15.828 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n497_s2/F |
16.302 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 2833 | HCLK_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1/CLK |
10.325 | -0.035 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 19 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 8.126, 50.973%; route: 7.584, 47.572%; tC2Q: 0.232, 1.455% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:Slack | -5.875 |
Data Arrival Time | 16.200 |
Data Required Time | 10.325 |
From | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s1 |
To | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1 |
Launch Clk | HCLK[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 2833 | HCLK_ibuf/O |
0.360 | 0.360 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s1/CLK |
0.592 | 0.232 | tC2Q | RF | 6 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/slave_cmd_1_s1/Q |
1.066 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/I1 |
1.621 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s3/F |
2.095 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/I0 |
2.612 | 0.517 | tINS | FF | 13 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s2/F |
3.086 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.539 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/arb_wr_num_0_s1/F |
4.013 | 0.474 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/I1 |
4.583 | 0.570 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n388_s0/COUT |
4.583 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/CIN |
4.618 | 0.035 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n389_s0/COUT |
4.618 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/CIN |
4.653 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n390_s0/COUT |
4.653 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/CIN |
4.689 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n391_s0/COUT |
4.689 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/CIN |
4.724 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n392_s0/COUT |
4.724 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/CIN |
4.759 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n393_s0/COUT |
4.759 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/CIN |
4.794 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n394_s0/COUT |
4.794 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/CIN |
4.829 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n395_s0/COUT |
4.829 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/CIN |
4.865 | 0.035 | tINS | FF | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n396_s0/COUT |
5.339 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s15/I0 |
5.856 | 0.517 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s15/F |
6.330 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s12/I2 |
6.783 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s12/F |
7.257 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/I1 |
7.812 | 0.555 | tINS | FF | 5 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n583_s8/F |
8.286 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s11/I0 |
8.803 | 0.517 | tINS | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_3_s11/F |
9.277 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s6/I0 |
9.794 | 0.517 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s6/F |
10.268 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s3/I0 |
10.785 | 0.517 | tINS | FF | 9 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s3/F |
11.259 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/I0 |
11.776 | 0.517 | tINS | FF | 21 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/ctrl_ns_0_s2/F |
12.250 | 0.474 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/I1 |
12.820 | 0.570 | tINS | FR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n9_s0/COUT |
12.820 | 0.000 | tNET | RR | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/CIN |
12.855 | 0.035 | tINS | RF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n10_s0/COUT |
12.855 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/CIN |
12.890 | 0.035 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n11_s0/COUT |
12.890 | 0.000 | tNET | FF | 2 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/CIN |
12.925 | 0.035 | tINS | FF | 11 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n12_s0/COUT |
13.399 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/I1 |
13.954 | 0.555 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s9/F |
14.428 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/I3 |
14.799 | 0.371 | tINS | FF | 10 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_8_s6/F |
15.273 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n496_s2/I2 |
15.726 | 0.453 | tINS | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/n496_s2/F |
16.200 | 0.474 | tNET | FF | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 2833 | HCLK_ibuf/O |
10.360 | 0.360 | tNET | RR | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1/CLK |
10.325 | -0.035 | tSu | 1 | u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_spi1/u_spi_ctrl/data_cnt_r_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 19 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Arrival Data Path Delay: | cell: 8.024, 50.657%; route: 7.584, 47.878%; tC2Q: 0.232, 1.465% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |