Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBSDHost\data\apb_sd_host_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBSDHost\data\apb_sd_host.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Tue Apr 29 11:22:13 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module APB_SD_Host_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.26s, Peak memory usage = 75.230MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 75.230MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 75.230MB
    Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 75.230MB
    Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.228s, Peak memory usage = 75.230MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 75.230MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 75.230MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 75.230MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 75.230MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.302s, Peak memory usage = 75.230MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 75.230MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 75.230MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 104.746MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.393s, Peak memory usage = 104.746MB
Generate output files:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.318s, Peak memory usage = 104.746MB
Total Time and Memory Usage CPU time = 0h 0m 10s, Elapsed time = 0h 0m 11s, Peak memory usage = 104.746MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 99
I/O Buf 99
    IBUF 55
    OBUF 44
Register 1319
    DFF 29
    DFFS 3
    DFFR 12
    DFFRE 32
    DFFP 1
    DFFPE 16
    DFFC 205
    DFFCE 1021
LUT 1947
    LUT2 165
    LUT3 553
    LUT4 1229
ALU 204
    ALU 204
SSRAM 69
    RAM16S4 53
    RAM16SDP4 16
INV 14
    INV 14

Resource Utilization Summary

Resource Usage Utilization
Logic 2579(1961 LUT, 204 ALU, 69 RAM16) / 20736 13%
Register 1319 / 16173 9%
  --Register as Latch 0 / 16173 0%
  --Register as FF 1319 / 16173 9%
BSRAM 0 / 46 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 sd_clk_i_pad Base 10.000 100.000 0.000 5.000 sd_clk_i_pad_ibuf/I
2 pclk Base 10.000 100.000 0.000 5.000 pclk_ibuf/I
3 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d Base 10.000 100.000 0.000 5.000 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 sd_clk_i_pad 100.000(MHz) 198.318(MHz) 7 TOP
2 pclk 100.000(MHz) 157.505(MHz) 7 TOP
3 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d 100.000(MHz) 102.999(MHz) 13 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.291
Data Arrival Time 10.034
Data Required Time 10.325
From u_apb_sd_host/cmd_serial_host0/resp_len_5_s0
To u_apb_sd_host/cmd_serial_host0/crc_in_0_s0
Launch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Latch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
0.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
0.360 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/resp_len_5_s0/CLK
0.592 0.232 tC2Q RF 12 u_apb_sd_host/cmd_serial_host0/resp_len_5_s0/Q
1.066 0.474 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2167_s/I0
1.615 0.549 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n2167_s/COUT
1.615 0.000 tNET RR 2 u_apb_sd_host/cmd_serial_host0/n2166_s/CIN
2.085 0.470 tINS RF 1 u_apb_sd_host/cmd_serial_host0/n2166_s/SUM
2.559 0.474 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2166_s2/I0
3.108 0.549 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n2166_s2/COUT
3.108 0.000 tNET RR 2 u_apb_sd_host/cmd_serial_host0/n2165_s2/CIN
3.143 0.035 tINS RF 1 u_apb_sd_host/cmd_serial_host0/n2165_s2/COUT
3.143 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2164_s2/CIN
3.178 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2164_s2/COUT
3.178 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2163_s2/CIN
3.214 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2163_s2/COUT
3.214 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2162_s2/CIN
3.249 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2162_s2/COUT
3.249 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2161_s2/CIN
3.284 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2161_s2/COUT
3.284 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2160_s2/CIN
3.319 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2160_s2/COUT
3.319 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2159_s2/CIN
3.354 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2159_s2/COUT
3.354 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2158_s2/CIN
3.390 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2158_s2/COUT
3.390 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2157_s2/CIN
3.425 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2157_s2/COUT
3.425 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2156_s2/CIN
3.460 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2156_s2/COUT
3.460 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2155_s2/CIN
3.495 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2155_s2/COUT
3.495 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2154_s2/CIN
3.530 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2154_s2/COUT
3.530 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2153_s2/CIN
3.566 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2153_s2/COUT
3.566 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2152_s2/CIN
3.601 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2152_s2/COUT
3.601 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2151_s2/CIN
3.636 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2151_s2/COUT
3.636 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2150_s2/CIN
3.671 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2150_s2/COUT
3.671 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2149_s2/CIN
3.706 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2149_s2/COUT
3.706 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2148_s2/CIN
3.742 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2148_s2/COUT
3.742 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2147_s2/CIN
3.777 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2147_s2/COUT
3.777 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2146_s2/CIN
4.247 0.470 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2146_s2/SUM
4.721 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s12/I1
5.276 0.555 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s12/F
5.750 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s11/I3
6.121 0.371 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s11/F
6.595 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s5/I3
6.966 0.371 tINS FF 2 u_apb_sd_host/cmd_serial_host0/n4606_s5/F
7.440 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s3/I2
7.893 0.453 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s3/F
8.367 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4609_s1/I3
8.738 0.371 tINS FF 4 u_apb_sd_host/cmd_serial_host0/n4609_s1/F
9.212 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4612_s0/I2
9.674 0.462 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n4612_s0/F
10.034 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/crc_in_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
10.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
10.360 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/crc_in_0_s0/CLK
10.325 -0.035 tSu 1 u_apb_sd_host/cmd_serial_host0/crc_in_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 5.290, 54.682%; route: 4.152, 42.920%; tC2Q: 0.232, 2.398%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack 0.291
Data Arrival Time 10.034
Data Required Time 10.325
From u_apb_sd_host/cmd_serial_host0/resp_len_5_s0
To u_apb_sd_host/cmd_serial_host0/crc_in_1_s0
Launch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Latch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
0.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
0.360 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/resp_len_5_s0/CLK
0.592 0.232 tC2Q RF 12 u_apb_sd_host/cmd_serial_host0/resp_len_5_s0/Q
1.066 0.474 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2167_s/I0
1.615 0.549 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n2167_s/COUT
1.615 0.000 tNET RR 2 u_apb_sd_host/cmd_serial_host0/n2166_s/CIN
2.085 0.470 tINS RF 1 u_apb_sd_host/cmd_serial_host0/n2166_s/SUM
2.559 0.474 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2166_s2/I0
3.108 0.549 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n2166_s2/COUT
3.108 0.000 tNET RR 2 u_apb_sd_host/cmd_serial_host0/n2165_s2/CIN
3.143 0.035 tINS RF 1 u_apb_sd_host/cmd_serial_host0/n2165_s2/COUT
3.143 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2164_s2/CIN
3.178 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2164_s2/COUT
3.178 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2163_s2/CIN
3.214 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2163_s2/COUT
3.214 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2162_s2/CIN
3.249 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2162_s2/COUT
3.249 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2161_s2/CIN
3.284 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2161_s2/COUT
3.284 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2160_s2/CIN
3.319 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2160_s2/COUT
3.319 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2159_s2/CIN
3.354 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2159_s2/COUT
3.354 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2158_s2/CIN
3.390 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2158_s2/COUT
3.390 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2157_s2/CIN
3.425 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2157_s2/COUT
3.425 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2156_s2/CIN
3.460 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2156_s2/COUT
3.460 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2155_s2/CIN
3.495 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2155_s2/COUT
3.495 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2154_s2/CIN
3.530 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2154_s2/COUT
3.530 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2153_s2/CIN
3.566 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2153_s2/COUT
3.566 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2152_s2/CIN
3.601 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2152_s2/COUT
3.601 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2151_s2/CIN
3.636 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2151_s2/COUT
3.636 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2150_s2/CIN
3.671 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2150_s2/COUT
3.671 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2149_s2/CIN
3.706 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2149_s2/COUT
3.706 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2148_s2/CIN
3.742 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2148_s2/COUT
3.742 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2147_s2/CIN
3.777 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2147_s2/COUT
3.777 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2146_s2/CIN
4.247 0.470 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2146_s2/SUM
4.721 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s12/I1
5.276 0.555 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s12/F
5.750 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s11/I3
6.121 0.371 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s11/F
6.595 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s5/I3
6.966 0.371 tINS FF 2 u_apb_sd_host/cmd_serial_host0/n4606_s5/F
7.440 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s3/I2
7.893 0.453 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s3/F
8.367 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4609_s1/I3
8.738 0.371 tINS FF 4 u_apb_sd_host/cmd_serial_host0/n4609_s1/F
9.212 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4611_s0/I2
9.674 0.462 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n4611_s0/F
10.034 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/crc_in_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
10.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
10.360 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/crc_in_1_s0/CLK
10.325 -0.035 tSu 1 u_apb_sd_host/cmd_serial_host0/crc_in_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 5.290, 54.682%; route: 4.152, 42.920%; tC2Q: 0.232, 2.398%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack 0.291
Data Arrival Time 10.034
Data Required Time 10.325
From u_apb_sd_host/cmd_serial_host0/resp_len_5_s0
To u_apb_sd_host/cmd_serial_host0/crc_in_2_s0
Launch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Latch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
0.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
0.360 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/resp_len_5_s0/CLK
0.592 0.232 tC2Q RF 12 u_apb_sd_host/cmd_serial_host0/resp_len_5_s0/Q
1.066 0.474 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2167_s/I0
1.615 0.549 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n2167_s/COUT
1.615 0.000 tNET RR 2 u_apb_sd_host/cmd_serial_host0/n2166_s/CIN
2.085 0.470 tINS RF 1 u_apb_sd_host/cmd_serial_host0/n2166_s/SUM
2.559 0.474 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2166_s2/I0
3.108 0.549 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n2166_s2/COUT
3.108 0.000 tNET RR 2 u_apb_sd_host/cmd_serial_host0/n2165_s2/CIN
3.143 0.035 tINS RF 1 u_apb_sd_host/cmd_serial_host0/n2165_s2/COUT
3.143 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2164_s2/CIN
3.178 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2164_s2/COUT
3.178 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2163_s2/CIN
3.214 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2163_s2/COUT
3.214 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2162_s2/CIN
3.249 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2162_s2/COUT
3.249 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2161_s2/CIN
3.284 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2161_s2/COUT
3.284 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2160_s2/CIN
3.319 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2160_s2/COUT
3.319 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2159_s2/CIN
3.354 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2159_s2/COUT
3.354 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2158_s2/CIN
3.390 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2158_s2/COUT
3.390 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2157_s2/CIN
3.425 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2157_s2/COUT
3.425 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2156_s2/CIN
3.460 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2156_s2/COUT
3.460 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2155_s2/CIN
3.495 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2155_s2/COUT
3.495 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2154_s2/CIN
3.530 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2154_s2/COUT
3.530 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2153_s2/CIN
3.566 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2153_s2/COUT
3.566 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2152_s2/CIN
3.601 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2152_s2/COUT
3.601 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2151_s2/CIN
3.636 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2151_s2/COUT
3.636 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2150_s2/CIN
3.671 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2150_s2/COUT
3.671 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2149_s2/CIN
3.706 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2149_s2/COUT
3.706 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2148_s2/CIN
3.742 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2148_s2/COUT
3.742 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2147_s2/CIN
3.777 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2147_s2/COUT
3.777 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2146_s2/CIN
4.247 0.470 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2146_s2/SUM
4.721 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s12/I1
5.276 0.555 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s12/F
5.750 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s11/I3
6.121 0.371 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s11/F
6.595 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s5/I3
6.966 0.371 tINS FF 2 u_apb_sd_host/cmd_serial_host0/n4606_s5/F
7.440 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s3/I2
7.893 0.453 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s3/F
8.367 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4609_s1/I3
8.738 0.371 tINS FF 4 u_apb_sd_host/cmd_serial_host0/n4609_s1/F
9.212 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4610_s0/I2
9.674 0.462 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n4610_s0/F
10.034 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/crc_in_2_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
10.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
10.360 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/crc_in_2_s0/CLK
10.325 -0.035 tSu 1 u_apb_sd_host/cmd_serial_host0/crc_in_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 5.290, 54.682%; route: 4.152, 42.920%; tC2Q: 0.232, 2.398%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack 0.291
Data Arrival Time 10.034
Data Required Time 10.325
From u_apb_sd_host/cmd_serial_host0/resp_len_5_s0
To u_apb_sd_host/cmd_serial_host0/crc_in_3_s0
Launch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Latch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
0.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
0.360 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/resp_len_5_s0/CLK
0.592 0.232 tC2Q RF 12 u_apb_sd_host/cmd_serial_host0/resp_len_5_s0/Q
1.066 0.474 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2167_s/I0
1.615 0.549 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n2167_s/COUT
1.615 0.000 tNET RR 2 u_apb_sd_host/cmd_serial_host0/n2166_s/CIN
2.085 0.470 tINS RF 1 u_apb_sd_host/cmd_serial_host0/n2166_s/SUM
2.559 0.474 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2166_s2/I0
3.108 0.549 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n2166_s2/COUT
3.108 0.000 tNET RR 2 u_apb_sd_host/cmd_serial_host0/n2165_s2/CIN
3.143 0.035 tINS RF 1 u_apb_sd_host/cmd_serial_host0/n2165_s2/COUT
3.143 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2164_s2/CIN
3.178 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2164_s2/COUT
3.178 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2163_s2/CIN
3.214 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2163_s2/COUT
3.214 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2162_s2/CIN
3.249 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2162_s2/COUT
3.249 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2161_s2/CIN
3.284 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2161_s2/COUT
3.284 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2160_s2/CIN
3.319 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2160_s2/COUT
3.319 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2159_s2/CIN
3.354 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2159_s2/COUT
3.354 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2158_s2/CIN
3.390 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2158_s2/COUT
3.390 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2157_s2/CIN
3.425 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2157_s2/COUT
3.425 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2156_s2/CIN
3.460 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2156_s2/COUT
3.460 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2155_s2/CIN
3.495 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2155_s2/COUT
3.495 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2154_s2/CIN
3.530 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2154_s2/COUT
3.530 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2153_s2/CIN
3.566 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2153_s2/COUT
3.566 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2152_s2/CIN
3.601 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2152_s2/COUT
3.601 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2151_s2/CIN
3.636 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2151_s2/COUT
3.636 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2150_s2/CIN
3.671 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2150_s2/COUT
3.671 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2149_s2/CIN
3.706 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2149_s2/COUT
3.706 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2148_s2/CIN
3.742 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2148_s2/COUT
3.742 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2147_s2/CIN
3.777 0.035 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2147_s2/COUT
3.777 0.000 tNET FF 2 u_apb_sd_host/cmd_serial_host0/n2146_s2/CIN
4.247 0.470 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n2146_s2/SUM
4.721 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s12/I1
5.276 0.555 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s12/F
5.750 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s11/I3
6.121 0.371 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s11/F
6.595 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s5/I3
6.966 0.371 tINS FF 2 u_apb_sd_host/cmd_serial_host0/n4606_s5/F
7.440 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s3/I2
7.893 0.453 tINS FF 1 u_apb_sd_host/cmd_serial_host0/n4606_s3/F
8.367 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4609_s1/I3
8.738 0.371 tINS FF 4 u_apb_sd_host/cmd_serial_host0/n4609_s1/F
9.212 0.474 tNET FF 1 u_apb_sd_host/cmd_serial_host0/n4609_s0/I2
9.674 0.462 tINS FR 1 u_apb_sd_host/cmd_serial_host0/n4609_s0/F
10.034 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/crc_in_3_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
10.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
10.360 0.360 tNET RR 1 u_apb_sd_host/cmd_serial_host0/crc_in_3_s0/CLK
10.325 -0.035 tSu 1 u_apb_sd_host/cmd_serial_host0/crc_in_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 5.290, 54.682%; route: 4.152, 42.920%; tC2Q: 0.232, 2.398%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack 1.184
Data Arrival Time 9.141
Data Required Time 10.325
From u_apb_sd_host/sd_data_serial_host0/transf_cnt_1_s2
To u_apb_sd_host/sd_data_serial_host0/blkcnt_reg_0_s4
Launch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Latch Clk u_apb_sd_host/clock_divider0/sd_clk_o_pad_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
0.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
0.360 0.360 tNET RR 1 u_apb_sd_host/sd_data_serial_host0/transf_cnt_1_s2/CLK
0.592 0.232 tC2Q RF 16 u_apb_sd_host/sd_data_serial_host0/transf_cnt_1_s2/Q
1.066 0.474 tNET FF 2 u_apb_sd_host/sd_data_serial_host0/n1214_s32/I1
1.636 0.570 tINS FR 1 u_apb_sd_host/sd_data_serial_host0/n1214_s32/COUT
1.636 0.000 tNET RR 2 u_apb_sd_host/sd_data_serial_host0/n1214_s33/CIN
1.671 0.035 tINS RF 1 u_apb_sd_host/sd_data_serial_host0/n1214_s33/COUT
1.671 0.000 tNET FF 2 u_apb_sd_host/sd_data_serial_host0/n1214_s34/CIN
1.706 0.035 tINS FF 2 u_apb_sd_host/sd_data_serial_host0/n1214_s34/COUT
2.180 0.474 tNET FF 1 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s27/I0
2.697 0.517 tINS FF 1 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s27/F
3.171 0.474 tNET FF 1 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s22/I2
3.624 0.453 tINS FF 2 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s22/F
4.098 0.474 tNET FF 1 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s17/I1
4.653 0.555 tINS FF 1 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s17/F
5.127 0.474 tNET FF 1 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s8/I2
5.580 0.453 tINS FF 4 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s8/F
6.054 0.474 tNET FF 1 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s5/I1
6.609 0.555 tINS FF 16 u_apb_sd_host/sd_data_serial_host0/transf_cnt_15_s5/F
7.083 0.474 tNET FF 1 u_apb_sd_host/sd_data_serial_host0/n1607_s11/I1
7.638 0.555 tINS FF 1 u_apb_sd_host/sd_data_serial_host0/n1607_s11/F
8.112 0.474 tNET FF 1 u_apb_sd_host/sd_data_serial_host0/n1607_s9/I1
8.667 0.555 tINS FF 1 u_apb_sd_host/sd_data_serial_host0/n1607_s9/F
9.141 0.474 tNET FF 1 u_apb_sd_host/sd_data_serial_host0/blkcnt_reg_0_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u_apb_sd_host/clock_divider0/sd_clk_o_pad_d
10.000 0.000 tCL RR 978 u_apb_sd_host/clock_divider0/SD_CLK_O_s2/Q
10.360 0.360 tNET RR 1 u_apb_sd_host/sd_data_serial_host0/blkcnt_reg_0_s4/CLK
10.325 -0.035 tSu 1 u_apb_sd_host/sd_data_serial_host0/blkcnt_reg_0_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.283, 48.778%; route: 4.266, 48.580%; tC2Q: 0.232, 2.642%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%