Top Level Module |
APB_SPI_Top |
Synthesis Process |
Running parser: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.355s, Peak memory usage = 76.457MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 76.457MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 76.457MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 76.457MB Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 76.457MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 76.457MB Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 76.457MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 76.457MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 76.457MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 76.457MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 76.457MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 76.457MB Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 7s, Peak memory usage = 103.652MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.299s, Peak memory usage = 103.652MB Generate output files: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.219s, Peak memory usage = 103.652MB
|
Total Time and Memory Usage |
CPU time = 0h 0m 7s, Elapsed time = 0h 0m 8s, Peak memory usage = 103.652MB |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
spi_clock |
0.000 |
0.000 |
tCL |
RR |
1 |
spi_clock_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
312 |
spi_clock_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/CLK |
0.795 |
0.382 |
tC2Q |
RR |
7 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/Q |
1.207 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.786 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/F |
2.199 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/I2 |
2.706 |
0.507 |
tINS |
RR |
20 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/F |
3.119 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.626 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/F |
4.039 |
0.413 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n394_s0/I1 |
4.639 |
0.600 |
tINS |
RF |
1 |
u_apb_spi/u_spi_ctrl/n394_s0/COUT |
4.639 |
0.000 |
tNET |
FF |
2 |
u_apb_spi/u_spi_ctrl/n395_s0/CIN |
4.689 |
0.050 |
tINS |
FR |
1 |
u_apb_spi/u_spi_ctrl/n395_s0/COUT |
4.689 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n396_s0/CIN |
4.739 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n396_s0/COUT |
4.739 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n397_s0/CIN |
4.789 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n397_s0/COUT |
4.789 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n398_s0/CIN |
4.839 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n398_s0/COUT |
4.839 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n399_s0/CIN |
4.889 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n399_s0/COUT |
4.889 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n400_s0/CIN |
4.939 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n400_s0/COUT |
4.939 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n401_s0/CIN |
4.989 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n401_s0/COUT |
4.989 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n402_s0/CIN |
5.039 |
0.050 |
tINS |
RR |
4 |
u_apb_spi/u_spi_ctrl/n402_s0/COUT |
5.451 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/I0 |
6.030 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/F |
6.443 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/I1 |
7.010 |
0.567 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/F |
7.423 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/I2 |
7.930 |
0.507 |
tINS |
RR |
5 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/F |
8.343 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/I0 |
8.921 |
0.579 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/F |
9.334 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_0_s7/I2 |
9.841 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_0_s7/F |
10.254 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_0_s3/I3 |
10.543 |
0.289 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_0_s3/F |
10.955 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_0_s2/I0 |
11.534 |
0.579 |
tINS |
RR |
28 |
u_apb_spi/u_spi_ctrl/ctrl_ns_0_s2/F |
11.946 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/I2 |
12.454 |
0.507 |
tINS |
RR |
21 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/F |
12.866 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s1/I0 |
13.445 |
0.579 |
tINS |
RR |
20 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s1/F |
13.858 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s7/I3 |
14.146 |
0.289 |
tINS |
RR |
1 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s7/F |
14.559 |
0.413 |
tNET |
RR |
2 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/n327_s0/I0 |
15.154 |
0.595 |
tINS |
RF |
1 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/n327_s0/COUT |
15.154 |
0.000 |
tNET |
FF |
2 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/n328_s0/CIN |
15.204 |
0.050 |
tINS |
FR |
1 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/n328_s0/COUT |
15.616 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/n331_s2/I1 |
16.184 |
0.567 |
tINS |
RR |
1 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/n331_s2/F |
16.596 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_fifo/u_spi_txfifo/empty_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
spi_clock |
0.000 |
0.000 |
tCL |
RR |
1 |
spi_clock_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
312 |
spi_clock_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/CLK |
0.795 |
0.382 |
tC2Q |
RR |
7 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/Q |
1.207 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.786 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/F |
2.199 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/I2 |
2.706 |
0.507 |
tINS |
RR |
20 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/F |
3.119 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.626 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/F |
4.039 |
0.413 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n394_s0/I1 |
4.639 |
0.600 |
tINS |
RF |
1 |
u_apb_spi/u_spi_ctrl/n394_s0/COUT |
4.639 |
0.000 |
tNET |
FF |
2 |
u_apb_spi/u_spi_ctrl/n395_s0/CIN |
4.689 |
0.050 |
tINS |
FR |
1 |
u_apb_spi/u_spi_ctrl/n395_s0/COUT |
4.689 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n396_s0/CIN |
4.739 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n396_s0/COUT |
4.739 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n397_s0/CIN |
4.789 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n397_s0/COUT |
4.789 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n398_s0/CIN |
4.839 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n398_s0/COUT |
4.839 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n399_s0/CIN |
4.889 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n399_s0/COUT |
4.889 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n400_s0/CIN |
4.939 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n400_s0/COUT |
4.939 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n401_s0/CIN |
4.989 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n401_s0/COUT |
4.989 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n402_s0/CIN |
5.039 |
0.050 |
tINS |
RR |
4 |
u_apb_spi/u_spi_ctrl/n402_s0/COUT |
5.451 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/I0 |
6.030 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/F |
6.443 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/I1 |
7.010 |
0.567 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/F |
7.423 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/I2 |
7.930 |
0.507 |
tINS |
RR |
5 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/F |
8.343 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/I0 |
8.921 |
0.579 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/F |
9.334 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s3/I0 |
9.913 |
0.579 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s3/F |
10.325 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1152_s8/I3 |
10.614 |
0.289 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/n1152_s8/F |
11.026 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1168_s6/I2 |
11.534 |
0.507 |
tINS |
RR |
7 |
u_apb_spi/u_spi_ctrl/n1168_s6/F |
11.946 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1183_s9/I1 |
12.514 |
0.567 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1183_s9/F |
12.926 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1183_s5/I2 |
13.434 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1183_s5/F |
13.846 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1183_s2/I1 |
14.414 |
0.567 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1183_s2/F |
14.826 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1183_s0/I1 |
15.394 |
0.567 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1183_s0/F |
15.806 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_mux_r_0_s1/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
spi_clock |
0.000 |
0.000 |
tCL |
RR |
1 |
spi_clock_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
312 |
spi_clock_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/CLK |
0.795 |
0.382 |
tC2Q |
RR |
7 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/Q |
1.207 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.786 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/F |
2.199 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/I2 |
2.706 |
0.507 |
tINS |
RR |
20 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/F |
3.119 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.626 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/F |
4.039 |
0.413 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n394_s0/I1 |
4.639 |
0.600 |
tINS |
RF |
1 |
u_apb_spi/u_spi_ctrl/n394_s0/COUT |
4.639 |
0.000 |
tNET |
FF |
2 |
u_apb_spi/u_spi_ctrl/n395_s0/CIN |
4.689 |
0.050 |
tINS |
FR |
1 |
u_apb_spi/u_spi_ctrl/n395_s0/COUT |
4.689 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n396_s0/CIN |
4.739 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n396_s0/COUT |
4.739 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n397_s0/CIN |
4.789 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n397_s0/COUT |
4.789 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n398_s0/CIN |
4.839 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n398_s0/COUT |
4.839 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n399_s0/CIN |
4.889 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n399_s0/COUT |
4.889 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n400_s0/CIN |
4.939 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n400_s0/COUT |
4.939 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n401_s0/CIN |
4.989 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n401_s0/COUT |
4.989 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n402_s0/CIN |
5.039 |
0.050 |
tINS |
RR |
4 |
u_apb_spi/u_spi_ctrl/n402_s0/COUT |
5.451 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/I0 |
6.030 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/F |
6.443 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/I1 |
7.010 |
0.567 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/F |
7.423 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/I2 |
7.930 |
0.507 |
tINS |
RR |
5 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/F |
8.343 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/I0 |
8.921 |
0.579 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/F |
9.334 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s3/I0 |
9.913 |
0.579 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s3/F |
10.325 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1152_s8/I3 |
10.614 |
0.289 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/n1152_s8/F |
11.026 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1152_s5/I2 |
11.534 |
0.507 |
tINS |
RR |
20 |
u_apb_spi/u_spi_ctrl/n1152_s5/F |
11.946 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1154_s11/I0 |
12.525 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1154_s11/F |
12.938 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1154_s2/I2 |
13.445 |
0.507 |
tINS |
RR |
5 |
u_apb_spi/u_spi_ctrl/n1154_s2/F |
13.858 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1156_s2/I1 |
14.425 |
0.567 |
tINS |
RR |
3 |
u_apb_spi/u_spi_ctrl/n1156_s2/F |
14.838 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1161_s0/I2 |
15.345 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1161_s0/F |
15.758 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_mux_r_22_s1/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
spi_clock |
0.000 |
0.000 |
tCL |
RR |
1 |
spi_clock_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
312 |
spi_clock_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/CLK |
0.795 |
0.382 |
tC2Q |
RR |
7 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/Q |
1.207 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.786 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/F |
2.199 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/I2 |
2.706 |
0.507 |
tINS |
RR |
20 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/F |
3.119 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.626 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/F |
4.039 |
0.413 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n394_s0/I1 |
4.639 |
0.600 |
tINS |
RF |
1 |
u_apb_spi/u_spi_ctrl/n394_s0/COUT |
4.639 |
0.000 |
tNET |
FF |
2 |
u_apb_spi/u_spi_ctrl/n395_s0/CIN |
4.689 |
0.050 |
tINS |
FR |
1 |
u_apb_spi/u_spi_ctrl/n395_s0/COUT |
4.689 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n396_s0/CIN |
4.739 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n396_s0/COUT |
4.739 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n397_s0/CIN |
4.789 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n397_s0/COUT |
4.789 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n398_s0/CIN |
4.839 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n398_s0/COUT |
4.839 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n399_s0/CIN |
4.889 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n399_s0/COUT |
4.889 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n400_s0/CIN |
4.939 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n400_s0/COUT |
4.939 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n401_s0/CIN |
4.989 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n401_s0/COUT |
4.989 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n402_s0/CIN |
5.039 |
0.050 |
tINS |
RR |
4 |
u_apb_spi/u_spi_ctrl/n402_s0/COUT |
5.451 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/I0 |
6.030 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/F |
6.443 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/I1 |
7.010 |
0.567 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/F |
7.423 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/I2 |
7.930 |
0.507 |
tINS |
RR |
5 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/F |
8.343 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/I0 |
8.921 |
0.579 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/F |
9.334 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s3/I0 |
9.913 |
0.579 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s3/F |
10.325 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1152_s8/I3 |
10.614 |
0.289 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/n1152_s8/F |
11.026 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1152_s5/I2 |
11.534 |
0.507 |
tINS |
RR |
20 |
u_apb_spi/u_spi_ctrl/n1152_s5/F |
11.946 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1154_s11/I0 |
12.525 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1154_s11/F |
12.938 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1154_s2/I2 |
13.445 |
0.507 |
tINS |
RR |
5 |
u_apb_spi/u_spi_ctrl/n1154_s2/F |
13.858 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1156_s2/I1 |
14.425 |
0.567 |
tINS |
RR |
3 |
u_apb_spi/u_spi_ctrl/n1156_s2/F |
14.838 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1159_s0/I2 |
15.345 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1159_s0/F |
15.758 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_mux_r_24_s1/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
spi_clock |
0.000 |
0.000 |
tCL |
RR |
1 |
spi_clock_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
312 |
spi_clock_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/CLK |
0.795 |
0.382 |
tC2Q |
RR |
7 |
u_apb_spi/u_spi_ctrl/slave_cmd_2_s1/Q |
1.207 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.786 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s3/F |
2.199 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/I2 |
2.706 |
0.507 |
tINS |
RR |
20 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s2/F |
3.119 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.626 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/arb_wr_num_0_s1/F |
4.039 |
0.413 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n394_s0/I1 |
4.639 |
0.600 |
tINS |
RF |
1 |
u_apb_spi/u_spi_ctrl/n394_s0/COUT |
4.639 |
0.000 |
tNET |
FF |
2 |
u_apb_spi/u_spi_ctrl/n395_s0/CIN |
4.689 |
0.050 |
tINS |
FR |
1 |
u_apb_spi/u_spi_ctrl/n395_s0/COUT |
4.689 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n396_s0/CIN |
4.739 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n396_s0/COUT |
4.739 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n397_s0/CIN |
4.789 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n397_s0/COUT |
4.789 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n398_s0/CIN |
4.839 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n398_s0/COUT |
4.839 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n399_s0/CIN |
4.889 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n399_s0/COUT |
4.889 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n400_s0/CIN |
4.939 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n400_s0/COUT |
4.939 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n401_s0/CIN |
4.989 |
0.050 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n401_s0/COUT |
4.989 |
0.000 |
tNET |
RR |
2 |
u_apb_spi/u_spi_ctrl/n402_s0/CIN |
5.039 |
0.050 |
tINS |
RR |
4 |
u_apb_spi/u_spi_ctrl/n402_s0/COUT |
5.451 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/I0 |
6.030 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s10/F |
6.443 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/I1 |
7.010 |
0.567 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s8/F |
7.423 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/I2 |
7.930 |
0.507 |
tINS |
RR |
5 |
u_apb_spi/u_spi_ctrl/tx_ready_s5/F |
8.343 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/I0 |
8.921 |
0.579 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s7/F |
9.334 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s3/I0 |
9.913 |
0.579 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/ctrl_ns_3_s3/F |
10.325 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1152_s8/I3 |
10.614 |
0.289 |
tINS |
RR |
2 |
u_apb_spi/u_spi_ctrl/n1152_s8/F |
11.026 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1152_s5/I2 |
11.534 |
0.507 |
tINS |
RR |
20 |
u_apb_spi/u_spi_ctrl/n1152_s5/F |
11.946 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1154_s11/I0 |
12.525 |
0.579 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1154_s11/F |
12.938 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1154_s2/I2 |
13.445 |
0.507 |
tINS |
RR |
5 |
u_apb_spi/u_spi_ctrl/n1154_s2/F |
13.858 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1156_s2/I1 |
14.425 |
0.567 |
tINS |
RR |
3 |
u_apb_spi/u_spi_ctrl/n1156_s2/F |
14.838 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1156_s0/I2 |
15.345 |
0.507 |
tINS |
RR |
1 |
u_apb_spi/u_spi_ctrl/n1156_s0/F |
15.758 |
0.413 |
tNET |
RR |
1 |
u_apb_spi/u_spi_ctrl/tx_mux_r_27_s1/D |