Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBSPI\data\apb_spi_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBSPI\data\apb_spi.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Tue May 6 14:53:12 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module APB_SPI_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.299s, Peak memory usage = 74.289MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 74.289MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 74.289MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 74.289MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 74.289MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 74.289MB
    Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 74.289MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 74.289MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 74.289MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 74.289MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 74.289MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 74.289MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 102.094MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.291s, Peak memory usage = 102.094MB
Generate output files:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.139s, Peak memory usage = 102.094MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 102.094MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 131
I/O Buf 104
    IBUF 56
    OBUF 48
Register 735
    DFFRE 260
    DFFPE 29
    DFFCE 444
    DLCE 2
LUT 1348
    LUT2 154
    LUT3 369
    LUT4 825
ALU 85
    ALU 85
INV 7
    INV 7

Resource Utilization Summary

Resource Usage Utilization
Logic 1440(1355 LUT, 85 ALU) / 138240 2%
Register 735 / 139140 <1%
  --Register as Latch 2 / 139140 <1%
  --Register as FF 733 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 pclk Base 10.000 100.000 0.000 5.000 pclk_ibuf/I
2 spi_clock Base 10.000 100.000 0.000 5.000 spi_clock_ibuf/I
3 u_apb_spi/u_spi_spiif/spi_clock_inv Base 10.000 100.000 0.000 5.000 u_apb_spi/u_spi_spiif/spi_clock_inv_s1/F
4 u_apb_spi/u_spi_spiif/spi_w_clk_slv Base 10.000 100.000 0.000 5.000 u_apb_spi/u_spi_spiif/spi_w_clk_slv_s0/F
5 u_apb_spi/u_spi_spiif/spi_r_clk Base 10.000 100.000 0.000 5.000 u_apb_spi/u_spi_spiif/spi_r_clk_s0/F

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 pclk 100.000(MHz) 122.193(MHz) 9 TOP
2 spi_clock 100.000(MHz) 71.016(MHz) 16 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -4.171
Data Arrival Time 14.485
Data Required Time 10.314
From u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0
To u_apb_spi/u_spi_fifo/u_spi_txfifo/empty_s0
Launch Clk pclk[R]
Latch Clk spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 414 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s16/I1
1.807 0.600 tINS RF 1 u_apb_spi/u_spi_spiif/n148_s16/COUT
1.807 0.000 tNET FF 2 u_apb_spi/u_spi_spiif/n148_s17/CIN
1.857 0.050 tINS FR 1 u_apb_spi/u_spi_spiif/n148_s17/COUT
1.857 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s18/CIN
1.907 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s18/COUT
1.907 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s19/CIN
1.957 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s19/COUT
1.957 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s20/CIN
2.007 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s20/COUT
2.007 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s21/CIN
2.057 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s21/COUT
2.057 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s22/CIN
2.107 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s22/COUT
2.520 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s12/I1
3.087 0.567 tINS RR 3 u_apb_spi/u_spi_spiif/spi_ns_2_s12/F
3.500 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s15/I3
3.789 0.289 tINS RR 5 u_apb_spi/u_spi_spiif/spi_ns_2_s15/F
4.201 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/I2
4.709 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/F
5.121 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s10/I2
5.629 0.507 tINS RR 6 u_apb_spi/u_spi_spiif/spi_ns_0_s10/F
6.041 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/I2
6.549 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/F
6.961 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/I3
7.250 0.289 tINS RR 27 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/F
7.662 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s5/I1
8.230 0.567 tINS RR 5 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s5/F
8.642 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_2_s3/I0
9.221 0.579 tINS RR 3 u_apb_spi/u_spi_ctrl/ctrl_ns_2_s3/F
9.634 0.413 tNET RR 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/I0
10.212 0.579 tINS RR 26 u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/F
10.625 0.413 tNET RR 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s1/I1
11.193 0.567 tINS RR 2 u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s1/F
11.605 0.413 tNET RR 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/I2
12.113 0.507 tINS RR 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/F
12.525 0.413 tNET RR 2 u_apb_spi/u_spi_fifo/u_spi_txfifo/n328_s0/I0
13.120 0.595 tINS RF 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/n328_s0/COUT
13.505 0.385 tNET FF 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/n331_s2/I1
14.073 0.567 tINS FR 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/n331_s2/F
14.485 0.413 tNET RR 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 spi_clock
10.000 0.000 tCL RR 1 spi_clock_ibuf/I
10.000 0.000 tINS RR 309 spi_clock_ibuf/O
10.413 0.413 tNET RR 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/empty_s0/CLK
10.378 -0.035 tUnc u_apb_spi/u_spi_fifo/u_spi_txfifo/empty_s0
10.314 -0.064 tSu 1 u_apb_spi/u_spi_fifo/u_spi_txfifo/empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.530, 53.509%; route: 6.160, 43.773%; tC2Q: 0.382, 2.718%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack -4.005
Data Arrival Time 14.071
Data Required Time 10.066
From u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0
To u_apb_spi/u_spi_ctrl/data_cnt_r_0_s1
Launch Clk pclk[R]
Latch Clk spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 414 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s16/I1
1.807 0.600 tINS RF 1 u_apb_spi/u_spi_spiif/n148_s16/COUT
1.807 0.000 tNET FF 2 u_apb_spi/u_spi_spiif/n148_s17/CIN
1.857 0.050 tINS FR 1 u_apb_spi/u_spi_spiif/n148_s17/COUT
1.857 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s18/CIN
1.907 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s18/COUT
1.907 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s19/CIN
1.957 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s19/COUT
1.957 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s20/CIN
2.007 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s20/COUT
2.007 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s21/CIN
2.057 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s21/COUT
2.057 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s22/CIN
2.107 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s22/COUT
2.520 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s12/I1
3.087 0.567 tINS RR 3 u_apb_spi/u_spi_spiif/spi_ns_2_s12/F
3.500 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s15/I3
3.789 0.289 tINS RR 5 u_apb_spi/u_spi_spiif/spi_ns_2_s15/F
4.201 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/I2
4.709 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/F
5.121 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s10/I2
5.629 0.507 tINS RR 6 u_apb_spi/u_spi_spiif/spi_ns_0_s10/F
6.041 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/I2
6.549 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/F
6.961 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/I3
7.250 0.289 tINS RR 27 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/F
7.662 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s5/I0
8.241 0.579 tINS RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s5/F
8.654 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s3/I0
9.233 0.579 tINS RR 7 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s3/F
9.645 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s2/I0
10.224 0.579 tINS RR 7 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s2/F
10.636 0.413 tNET RR 2 u_apb_spi/u_spi_ctrl/n11_s0/I1
11.236 0.600 tINS RF 1 u_apb_spi/u_spi_ctrl/n11_s0/COUT
11.236 0.000 tNET FF 2 u_apb_spi/u_spi_ctrl/n12_s0/CIN
11.286 0.050 tINS FR 1 u_apb_spi/u_spi_ctrl/n12_s0/COUT
11.286 0.000 tNET RR 2 u_apb_spi/u_spi_ctrl/n13_s0/CIN
11.336 0.050 tINS RR 10 u_apb_spi/u_spi_ctrl/n13_s0/COUT
11.749 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s10/I3
12.038 0.289 tINS RR 2 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s10/F
12.450 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s6/I2
12.958 0.507 tINS RR 9 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s6/F
13.370 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s3/I3
13.659 0.289 tINS RR 9 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s3/F
14.071 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 spi_clock
10.000 0.000 tCL RR 1 spi_clock_ibuf/I
10.000 0.000 tINS RR 309 spi_clock_ibuf/O
10.413 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_0_s1/CLK
10.378 -0.035 tUnc u_apb_spi/u_spi_ctrl/data_cnt_r_0_s1
10.066 -0.311 tSu 1 u_apb_spi/u_spi_ctrl/data_cnt_r_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.089, 51.899%; route: 6.187, 45.301%; tC2Q: 0.382, 2.800%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack -4.005
Data Arrival Time 14.071
Data Required Time 10.066
From u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0
To u_apb_spi/u_spi_ctrl/data_cnt_r_1_s1
Launch Clk pclk[R]
Latch Clk spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 414 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s16/I1
1.807 0.600 tINS RF 1 u_apb_spi/u_spi_spiif/n148_s16/COUT
1.807 0.000 tNET FF 2 u_apb_spi/u_spi_spiif/n148_s17/CIN
1.857 0.050 tINS FR 1 u_apb_spi/u_spi_spiif/n148_s17/COUT
1.857 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s18/CIN
1.907 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s18/COUT
1.907 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s19/CIN
1.957 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s19/COUT
1.957 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s20/CIN
2.007 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s20/COUT
2.007 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s21/CIN
2.057 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s21/COUT
2.057 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s22/CIN
2.107 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s22/COUT
2.520 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s12/I1
3.087 0.567 tINS RR 3 u_apb_spi/u_spi_spiif/spi_ns_2_s12/F
3.500 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s15/I3
3.789 0.289 tINS RR 5 u_apb_spi/u_spi_spiif/spi_ns_2_s15/F
4.201 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/I2
4.709 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/F
5.121 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s10/I2
5.629 0.507 tINS RR 6 u_apb_spi/u_spi_spiif/spi_ns_0_s10/F
6.041 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/I2
6.549 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/F
6.961 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/I3
7.250 0.289 tINS RR 27 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/F
7.662 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s5/I0
8.241 0.579 tINS RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s5/F
8.654 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s3/I0
9.233 0.579 tINS RR 7 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s3/F
9.645 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s2/I0
10.224 0.579 tINS RR 7 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s2/F
10.636 0.413 tNET RR 2 u_apb_spi/u_spi_ctrl/n11_s0/I1
11.236 0.600 tINS RF 1 u_apb_spi/u_spi_ctrl/n11_s0/COUT
11.236 0.000 tNET FF 2 u_apb_spi/u_spi_ctrl/n12_s0/CIN
11.286 0.050 tINS FR 1 u_apb_spi/u_spi_ctrl/n12_s0/COUT
11.286 0.000 tNET RR 2 u_apb_spi/u_spi_ctrl/n13_s0/CIN
11.336 0.050 tINS RR 10 u_apb_spi/u_spi_ctrl/n13_s0/COUT
11.749 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s10/I3
12.038 0.289 tINS RR 2 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s10/F
12.450 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s6/I2
12.958 0.507 tINS RR 9 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s6/F
13.370 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s3/I3
13.659 0.289 tINS RR 9 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s3/F
14.071 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 spi_clock
10.000 0.000 tCL RR 1 spi_clock_ibuf/I
10.000 0.000 tINS RR 309 spi_clock_ibuf/O
10.413 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_1_s1/CLK
10.378 -0.035 tUnc u_apb_spi/u_spi_ctrl/data_cnt_r_1_s1
10.066 -0.311 tSu 1 u_apb_spi/u_spi_ctrl/data_cnt_r_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.089, 51.899%; route: 6.187, 45.301%; tC2Q: 0.382, 2.800%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack -4.005
Data Arrival Time 14.071
Data Required Time 10.066
From u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0
To u_apb_spi/u_spi_ctrl/data_cnt_r_2_s1
Launch Clk pclk[R]
Latch Clk spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 414 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s16/I1
1.807 0.600 tINS RF 1 u_apb_spi/u_spi_spiif/n148_s16/COUT
1.807 0.000 tNET FF 2 u_apb_spi/u_spi_spiif/n148_s17/CIN
1.857 0.050 tINS FR 1 u_apb_spi/u_spi_spiif/n148_s17/COUT
1.857 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s18/CIN
1.907 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s18/COUT
1.907 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s19/CIN
1.957 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s19/COUT
1.957 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s20/CIN
2.007 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s20/COUT
2.007 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s21/CIN
2.057 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s21/COUT
2.057 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s22/CIN
2.107 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s22/COUT
2.520 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s12/I1
3.087 0.567 tINS RR 3 u_apb_spi/u_spi_spiif/spi_ns_2_s12/F
3.500 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s15/I3
3.789 0.289 tINS RR 5 u_apb_spi/u_spi_spiif/spi_ns_2_s15/F
4.201 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/I2
4.709 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/F
5.121 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s10/I2
5.629 0.507 tINS RR 6 u_apb_spi/u_spi_spiif/spi_ns_0_s10/F
6.041 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/I2
6.549 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/F
6.961 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/I3
7.250 0.289 tINS RR 27 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/F
7.662 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s5/I0
8.241 0.579 tINS RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s5/F
8.654 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s3/I0
9.233 0.579 tINS RR 7 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s3/F
9.645 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s2/I0
10.224 0.579 tINS RR 7 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s2/F
10.636 0.413 tNET RR 2 u_apb_spi/u_spi_ctrl/n11_s0/I1
11.236 0.600 tINS RF 1 u_apb_spi/u_spi_ctrl/n11_s0/COUT
11.236 0.000 tNET FF 2 u_apb_spi/u_spi_ctrl/n12_s0/CIN
11.286 0.050 tINS FR 1 u_apb_spi/u_spi_ctrl/n12_s0/COUT
11.286 0.000 tNET RR 2 u_apb_spi/u_spi_ctrl/n13_s0/CIN
11.336 0.050 tINS RR 10 u_apb_spi/u_spi_ctrl/n13_s0/COUT
11.749 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s10/I3
12.038 0.289 tINS RR 2 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s10/F
12.450 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s6/I2
12.958 0.507 tINS RR 9 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s6/F
13.370 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s3/I3
13.659 0.289 tINS RR 9 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s3/F
14.071 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 spi_clock
10.000 0.000 tCL RR 1 spi_clock_ibuf/I
10.000 0.000 tINS RR 309 spi_clock_ibuf/O
10.413 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_2_s1/CLK
10.378 -0.035 tUnc u_apb_spi/u_spi_ctrl/data_cnt_r_2_s1
10.066 -0.311 tSu 1 u_apb_spi/u_spi_ctrl/data_cnt_r_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.089, 51.899%; route: 6.187, 45.301%; tC2Q: 0.382, 2.800%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack -4.005
Data Arrival Time 14.071
Data Required Time 10.066
From u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0
To u_apb_spi/u_spi_ctrl/data_cnt_r_3_s1
Launch Clk pclk[R]
Latch Clk spi_clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 414 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
0.795 0.382 tC2Q RR 6 u_apb_spi/u_spi_reg/reg_spiif_timing_r_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s16/I1
1.807 0.600 tINS RF 1 u_apb_spi/u_spi_spiif/n148_s16/COUT
1.807 0.000 tNET FF 2 u_apb_spi/u_spi_spiif/n148_s17/CIN
1.857 0.050 tINS FR 1 u_apb_spi/u_spi_spiif/n148_s17/COUT
1.857 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s18/CIN
1.907 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s18/COUT
1.907 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s19/CIN
1.957 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s19/COUT
1.957 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s20/CIN
2.007 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s20/COUT
2.007 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s21/CIN
2.057 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s21/COUT
2.057 0.000 tNET RR 2 u_apb_spi/u_spi_spiif/n148_s22/CIN
2.107 0.050 tINS RR 1 u_apb_spi/u_spi_spiif/n148_s22/COUT
2.520 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s12/I1
3.087 0.567 tINS RR 3 u_apb_spi/u_spi_spiif/spi_ns_2_s12/F
3.500 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_2_s15/I3
3.789 0.289 tINS RR 5 u_apb_spi/u_spi_spiif/spi_ns_2_s15/F
4.201 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/I2
4.709 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s12/F
5.121 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_ns_0_s10/I2
5.629 0.507 tINS RR 6 u_apb_spi/u_spi_spiif/spi_ns_0_s10/F
6.041 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/I2
6.549 0.507 tINS RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s0/F
6.961 0.413 tNET RR 1 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/I3
7.250 0.289 tINS RR 27 u_apb_spi/u_spi_spiif/spi_txdata_rd_Z_s/F
7.662 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s5/I0
8.241 0.579 tINS RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s5/F
8.654 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s3/I0
9.233 0.579 tINS RR 7 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s3/F
9.645 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s2/I0
10.224 0.579 tINS RR 7 u_apb_spi/u_spi_ctrl/ctrl_ns_1_s2/F
10.636 0.413 tNET RR 2 u_apb_spi/u_spi_ctrl/n11_s0/I1
11.236 0.600 tINS RF 1 u_apb_spi/u_spi_ctrl/n11_s0/COUT
11.236 0.000 tNET FF 2 u_apb_spi/u_spi_ctrl/n12_s0/CIN
11.286 0.050 tINS FR 1 u_apb_spi/u_spi_ctrl/n12_s0/COUT
11.286 0.000 tNET RR 2 u_apb_spi/u_spi_ctrl/n13_s0/CIN
11.336 0.050 tINS RR 10 u_apb_spi/u_spi_ctrl/n13_s0/COUT
11.749 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s10/I3
12.038 0.289 tINS RR 2 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s10/F
12.450 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s6/I2
12.958 0.507 tINS RR 9 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s6/F
13.370 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s3/I3
13.659 0.289 tINS RR 9 u_apb_spi/u_spi_ctrl/data_cnt_r_8_s3/F
14.071 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_3_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 spi_clock
10.000 0.000 tCL RR 1 spi_clock_ibuf/I
10.000 0.000 tINS RR 309 spi_clock_ibuf/O
10.413 0.413 tNET RR 1 u_apb_spi/u_spi_ctrl/data_cnt_r_3_s1/CLK
10.378 -0.035 tUnc u_apb_spi/u_spi_ctrl/data_cnt_r_3_s1
10.066 -0.311 tSu 1 u_apb_spi/u_spi_ctrl/data_cnt_r_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 18
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.089, 51.899%; route: 6.187, 45.301%; tC2Q: 0.382, 2.800%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%