Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\DDR3_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_32to128.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_128to32.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_dtcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_itcm.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue May 6 14:37:03 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | RiscV_AE350_SOC_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.906s, Peak memory usage = 81.055MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 81.055MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 81.055MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 81.055MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 81.055MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 81.055MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 81.055MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 81.055MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 81.055MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 81.055MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 81.055MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 81.055MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.265s, Peak memory usage = 97.898MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 97.898MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.153s, Peak memory usage = 97.898MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 97.898MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 165 |
I/O Buf | 165 |
    IBUF | 74 |
    OBUF | 91 |
Register | 138 |
    DFFRE | 64 |
    DFFCE | 74 |
LUT | 224 |
    LUT2 | 21 |
    LUT3 | 98 |
    LUT4 | 105 |
ALU | 59 |
    ALU | 59 |
INV | 2 |
    INV | 2 |
BSRAM | 64 |
    SP | 64 |
AE350_SOC | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 285(226 LUT, 59 ALU) / 138240 | <1% |
Register | 138 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 138 / 139140 | <1% |
BSRAM | 64 / 340 | 19% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | AHB_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | AHB_CLK_ibuf/I | ||
2 | DDR_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR_CLK_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | AHB_CLK | 100.000(MHz) | 231.884(MHz) | 7 | TOP |
2 | DDR_CLK | 100.000(MHz) | 234.604(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 5.688 |
Data Arrival Time | 4.661 |
Data Required Time | 10.349 |
From | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/buf_addr_0_s0 |
To | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/buf_hit_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 66 | AHB_CLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/buf_addr_0_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/buf_addr_0_s0/Q |
1.207 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n233_s0/I1 |
1.807 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n233_s0/COUT |
1.807 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n234_s0/CIN |
1.857 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n234_s0/COUT |
1.857 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n235_s0/CIN |
1.907 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n235_s0/COUT |
1.907 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n236_s0/CIN |
1.957 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n236_s0/COUT |
1.957 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n237_s0/CIN |
2.007 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n237_s0/COUT |
2.007 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n238_s0/CIN |
2.057 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n238_s0/COUT |
2.057 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n239_s0/CIN |
2.107 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n239_s0/COUT |
2.107 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n240_s0/CIN |
2.157 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n240_s0/COUT |
2.157 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n241_s0/CIN |
2.207 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n241_s0/COUT |
2.207 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n242_s0/CIN |
2.257 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n242_s0/COUT |
2.257 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n243_s0/CIN |
2.307 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n243_s0/COUT |
2.307 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n244_s0/CIN |
2.357 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n244_s0/COUT |
2.357 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n245_s0/CIN |
2.407 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n245_s0/COUT |
2.407 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n246_s0/CIN |
2.457 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n246_s0/COUT |
2.457 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n247_s0/CIN |
2.507 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n247_s0/COUT |
2.507 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n248_s0/CIN |
2.557 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n248_s0/COUT |
2.557 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n249_s0/CIN |
2.607 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n249_s0/COUT |
2.607 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n250_s0/CIN |
2.657 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n250_s0/COUT |
2.657 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n251_s0/CIN |
2.707 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n251_s0/COUT |
2.707 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n252_s0/CIN |
2.757 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n252_s0/COUT |
2.757 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n253_s0/CIN |
2.807 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n253_s0/COUT |
2.807 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n254_s0/CIN |
2.857 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n254_s0/COUT |
2.857 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n255_s0/CIN |
2.907 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n255_s0/COUT |
2.907 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n256_s0/CIN |
2.957 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n256_s0/COUT |
2.957 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n257_s0/CIN |
3.007 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n257_s0/COUT |
3.007 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n258_s0/CIN |
3.057 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n258_s0/COUT |
3.057 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n259_s0/CIN |
3.107 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n259_s0/COUT |
3.107 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n260_s0/CIN |
3.157 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n260_s0/COUT |
3.157 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n261_s0/CIN |
3.207 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n261_s0/COUT |
3.207 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n262_s0/CIN |
3.257 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/n262_s0/COUT |
3.670 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/buf_hit_nxt_s2/I0 |
4.249 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/buf_hit_nxt_s2/F |
4.661 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/buf_hit_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 66 | AHB_CLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/buf_hit_s1/CLK |
10.349 | -0.064 | tSu | 1 | u_RiscV_AE350_SOC/u_gw_itcm_top/u_gw_itcm/u_ahb_to_ilm/buf_hit_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.629, 61.871%; route: 1.238, 29.126%; tC2Q: 0.382, 9.003% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 5.738 |
Data Arrival Time | 4.611 |
Data Required Time | 10.349 |
From | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_addr_0_s0 |
To | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_hit_s1 |
Launch Clk | DDR_CLK[R] |
Latch Clk | DDR_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DDR_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | DDR_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 136 | DDR_CLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_addr_0_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_addr_0_s0/Q |
1.207 | 0.413 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n312_s0/I1 |
1.807 | 0.600 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n312_s0/COUT |
1.807 | 0.000 | tNET | FF | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n313_s0/CIN |
1.857 | 0.050 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n313_s0/COUT |
1.857 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n314_s0/CIN |
1.907 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n314_s0/COUT |
1.907 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n315_s0/CIN |
1.957 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n315_s0/COUT |
1.957 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n316_s0/CIN |
2.007 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n316_s0/COUT |
2.007 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n317_s0/CIN |
2.057 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n317_s0/COUT |
2.057 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n318_s0/CIN |
2.107 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n318_s0/COUT |
2.107 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n319_s0/CIN |
2.157 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n319_s0/COUT |
2.157 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n320_s0/CIN |
2.207 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n320_s0/COUT |
2.207 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n321_s0/CIN |
2.257 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n321_s0/COUT |
2.257 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n322_s0/CIN |
2.307 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n322_s0/COUT |
2.307 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n323_s0/CIN |
2.357 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n323_s0/COUT |
2.357 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n324_s0/CIN |
2.407 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n324_s0/COUT |
2.407 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n325_s0/CIN |
2.457 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n325_s0/COUT |
2.457 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n326_s0/CIN |
2.507 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n326_s0/COUT |
2.507 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n327_s0/CIN |
2.557 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n327_s0/COUT |
2.557 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n328_s0/CIN |
2.607 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n328_s0/COUT |
2.607 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n329_s0/CIN |
2.657 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n329_s0/COUT |
2.657 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n330_s0/CIN |
2.707 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n330_s0/COUT |
2.707 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n331_s0/CIN |
2.757 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n331_s0/COUT |
2.757 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n332_s0/CIN |
2.807 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n332_s0/COUT |
2.807 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n333_s0/CIN |
2.857 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n333_s0/COUT |
2.857 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n334_s0/CIN |
2.907 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n334_s0/COUT |
2.907 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n335_s0/CIN |
2.957 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n335_s0/COUT |
2.957 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n336_s0/CIN |
3.007 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n336_s0/COUT |
3.007 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n337_s0/CIN |
3.057 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n337_s0/COUT |
3.057 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n338_s0/CIN |
3.107 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n338_s0/COUT |
3.107 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n339_s0/CIN |
3.157 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n339_s0/COUT |
3.157 | 0.000 | tNET | RR | 2 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n340_s0/CIN |
3.207 | 0.050 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/n340_s0/COUT |
3.620 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_hit_nxt_s2/I0 |
4.199 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_hit_nxt_s2/F |
4.611 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_hit_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DDR_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | DDR_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 136 | DDR_CLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_hit_s1/CLK |
10.349 | -0.064 | tSu | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_hit_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.579, 61.417%; route: 1.238, 29.473%; tC2Q: 0.382, 9.110% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 7.224 |
Data Arrival Time | 3.179 |
Data Required Time | 10.403 |
From | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_pend_s0 |
To | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_3_s |
Launch Clk | DDR_CLK[R] |
Latch Clk | DDR_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DDR_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | DDR_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 136 | DDR_CLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_pend_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 66 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_pend_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_0_s0/I0 |
1.786 | 0.579 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_0_s0/F |
2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_7_s/I1 |
2.766 | 0.567 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_7_s/F |
3.179 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_3_s/WRE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DDR_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | DDR_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 136 | DDR_CLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_3_s/CLK |
10.403 | -0.010 | tSu | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_3_s |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 1.146, 41.437%; route: 1.238, 44.736%; tC2Q: 0.382, 13.827% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 7.224 |
Data Arrival Time | 3.179 |
Data Required Time | 10.403 |
From | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_pend_s0 |
To | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_2_s |
Launch Clk | DDR_CLK[R] |
Latch Clk | DDR_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DDR_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | DDR_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 136 | DDR_CLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_pend_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 66 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_pend_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_0_s0/I0 |
1.786 | 0.579 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_0_s0/F |
2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_7_s/I1 |
2.766 | 0.567 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_7_s/F |
3.179 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_2_s/WRE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DDR_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | DDR_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 136 | DDR_CLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_2_s/CLK |
10.403 | -0.010 | tSu | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_2_s |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 1.146, 41.437%; route: 1.238, 44.736%; tC2Q: 0.382, 13.827% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 7.224 |
Data Arrival Time | 3.179 |
Data Required Time | 10.403 |
From | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_pend_s0 |
To | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_1_s |
Launch Clk | DDR_CLK[R] |
Latch Clk | DDR_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DDR_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | DDR_CLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 136 | DDR_CLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_pend_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 66 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/buf_pend_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_0_s0/I0 |
1.786 | 0.579 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_0_s0/F |
2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_7_s/I1 |
2.766 | 0.567 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_ahb_to_dlm/DLMBYTEWR_7_s/F |
3.179 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_1_s/WRE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DDR_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | DDR_CLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 136 | DDR_CLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_1_s/CLK |
10.403 | -0.010 | tSu | 1 | u_RiscV_AE350_SOC/u_gw_dtcm_top/u_gw_dtcm/u_vc_dlm_ram/gen_ram_dw_64.memH_gen_ram_dw_64.memH_0_1_s |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 3 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 1.146, 41.437%; route: 1.238, 44.736%; tC2Q: 0.382, 13.827% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |