Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\DDR3_TOP.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_32to128.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\fifo_top_128to32.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_dtcm.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\RiscV_AE350_SOC\data\gw_itcm.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue May 6 14:44:55 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | RiscV_AE350_SOC_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 137.633MB Running netlist conversion: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 137.633MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.508s, Peak memory usage = 137.633MB Optimizing Phase 1: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.328s, Peak memory usage = 137.633MB Optimizing Phase 2: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.882s, Peak memory usage = 137.633MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.428s, Peak memory usage = 137.633MB Inferring Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.307s, Peak memory usage = 137.633MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 137.633MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 137.633MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.795s, Peak memory usage = 137.633MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.255s, Peak memory usage = 137.633MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.279s, Peak memory usage = 137.633MB Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 142.559MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.737s, Peak memory usage = 142.559MB Generate output files: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.689s, Peak memory usage = 148.602MB |
Total Time and Memory Usage | CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 148.602MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 290 |
I/O Buf | 287 |
    IBUF | 112 |
    OBUF | 154 |
    TBUF | 2 |
    IOBUF | 16 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 2 |
Register | 3948 |
    DFFSE | 1 |
    DFFRE | 233 |
    DFFPE | 85 |
    DFFCE | 3629 |
LUT | 2701 |
    LUT2 | 313 |
    LUT3 | 982 |
    LUT4 | 1406 |
ALU | 165 |
    ALU | 165 |
INV | 29 |
    INV | 29 |
IOLOGIC | 76 |
    IDES8_MEM | 16 |
    OSER8 | 24 |
    OSER8_MEM | 20 |
    IODELAY | 16 |
BSRAM | 12 |
    SDPB | 4 |
    SDPX9B | 8 |
CLOCK | 4 |
    CLKDIV | 1 |
    DQS | 2 |
    DDRDLL | 1 |
AE350_SOC | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2895(2730 LUT, 165 ALU) / 138240 | 3% |
Register | 3948 / 139140 | 3% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 3948 / 139140 | 3% |
BSRAM | 12 / 340 | 4% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | DDR3_MEMORY_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR3_MEMORY_CLK_ibuf/I | ||
2 | DDR3_CLK_IN | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR3_CLK_IN_ibuf/I | ||
3 | DDR_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | DDR_CLK_ibuf/I | ||
4 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | DDR3_MEMORY_CLK_ibuf/I | DDR3_MEMORY_CLK | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | DDR3_MEMORY_CLK | 100.000(MHz) | 1115.449(MHz) | 1 | TOP |
2 | DDR3_CLK_IN | 100.000(MHz) | 173.310(MHz) | 6 | TOP |
3 | DDR_CLK | 100.000(MHz) | 307.456(MHz) | 4 | TOP |
4 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 161.225(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 2.287 |
Data Arrival Time | 2.579 |
Data Required Time | 4.866 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | DDR3_MEMORY_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.381 | 0.381 | tCL | RR | 3707 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.793 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
1.176 | 0.382 | tC2Q | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
1.588 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
2.167 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
2.579 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | DDR3_MEMORY_CLK | |||
5.000 | 0.000 | tCL | FF | 1 | DDR3_MEMORY_CLK_ibuf/I |
5.000 | 0.000 | tINS | FF | 64 | DDR3_MEMORY_CLK_ibuf/O |
5.385 | 0.385 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.350 | -0.035 | tUnc | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.866 | -0.484 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.408 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 2.287 |
Data Arrival Time | 2.579 |
Data Required Time | 4.866 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | DDR3_MEMORY_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.381 | 0.381 | tCL | RR | 3707 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.793 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
1.176 | 0.382 | tC2Q | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
1.588 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
2.167 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
2.579 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | DDR3_MEMORY_CLK | |||
5.000 | 0.000 | tCL | FF | 1 | DDR3_MEMORY_CLK_ibuf/I |
5.000 | 0.000 | tINS | FF | 64 | DDR3_MEMORY_CLK_ibuf/O |
5.385 | 0.385 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.350 | -0.035 | tUnc | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.866 | -0.484 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.408 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 4.230 |
Data Arrival Time | 6.119 |
Data Required Time | 10.349 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1 |
Launch Clk | DDR3_CLK_IN[R] |
Latch Clk | DDR3_CLK_IN[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DDR3_CLK_IN | |||
0.000 | 0.000 | tCL | RR | 1 | DDR3_CLK_IN_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | DDR3_CLK_IN_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK |
0.795 | 0.382 | tC2Q | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q |
1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0 |
1.786 | 0.579 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F |
2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1 |
2.766 | 0.567 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F |
3.179 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n49_s2/I1 |
3.746 | 0.567 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n49_s2/F |
4.159 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n46_s3/I1 |
4.726 | 0.567 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n46_s3/F |
5.139 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n46_s4/I1 |
5.706 | 0.567 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n46_s4/F |
6.119 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DDR3_CLK_IN | |||
10.000 | 0.000 | tCL | RR | 1 | DDR3_CLK_IN_ibuf/I |
10.000 | 0.000 | tINS | RR | 40 | DDR3_CLK_IN_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1/CLK |
10.349 | -0.064 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_11_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.849, 49.924%; route: 2.475, 43.373%; tC2Q: 0.382, 6.703% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 4.230 |
Data Arrival Time | 6.119 |
Data Required Time | 10.349 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1 |
Launch Clk | DDR3_CLK_IN[R] |
Latch Clk | DDR3_CLK_IN[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | DDR3_CLK_IN | |||
0.000 | 0.000 | tCL | RR | 1 | DDR3_CLK_IN_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | DDR3_CLK_IN_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK |
0.795 | 0.382 | tC2Q | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q |
1.207 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0 |
1.786 | 0.579 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F |
2.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/I1 |
2.766 | 0.567 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n50_s3/F |
3.179 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n49_s2/I1 |
3.746 | 0.567 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n49_s2/F |
4.159 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n46_s3/I1 |
4.726 | 0.567 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n46_s3/F |
5.139 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n45_s1/I1 |
5.706 | 0.567 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/n45_s1/F |
6.119 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | DDR3_CLK_IN | |||
10.000 | 0.000 | tCL | RR | 1 | DDR3_CLK_IN_ibuf/I |
10.000 | 0.000 | tINS | RR | 40 | DDR3_CLK_IN_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/CLK |
10.349 | -0.064 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.849, 49.924%; route: 2.475, 43.373%; tC2Q: 0.382, 6.703% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 4.684 |
Data Arrival Time | 36.010 |
Data Required Time | 40.694 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_lpddr_to_ahb_top/ahb_mask_word_7_s0 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_140_s0 |
Launch Clk | DDR_CLK[R] |
Latch Clk | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
30.000 | 0.000 | DDR_CLK | |||
30.000 | 0.000 | tCL | RR | 1 | DDR_CLK_ibuf/I |
30.000 | 0.000 | tINS | RR | 211 | DDR_CLK_ibuf/O |
30.413 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_lpddr_to_ahb_top/ahb_mask_word_7_s0/CLK |
30.795 | 0.382 | tC2Q | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_lpddr_to_ahb_top/ahb_mask_word_7_s0/Q |
31.208 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n722_s8/I0 |
31.786 | 0.579 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n722_s8/F |
32.199 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n722_s7/I0 |
32.778 | 0.579 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n722_s7/F |
33.190 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n724_s5/I2 |
33.697 | 0.507 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n724_s5/F |
34.110 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n725_s3/I1 |
34.678 | 0.567 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n725_s3/F |
35.090 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n725_s2/I2 |
35.597 | 0.507 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/n725_s2/F |
36.010 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_140_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
40.000 | 0.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
40.381 | 0.381 | tCL | RR | 3707 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
40.793 | 0.413 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_140_s0/CLK |
40.758 | -0.035 | tUnc | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_140_s0 | ||
40.694 | -0.064 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_gwmc_top/gw_wr_data0/wr_buf_din_140_s0 |
Clock Skew: | 0.381 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.740, 48.951%; route: 2.475, 44.216%; tC2Q: 0.382, 6.833% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |