Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBTimer\data\apb_timer_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBTimer\data\apb_timer.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue May 6 13:56:19 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | APB_Timer_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.218s, Peak memory usage = 69.137MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.137MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 69.137MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 69.137MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 69.137MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.137MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.137MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 69.137MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 69.137MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 69.137MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.137MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.137MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.941s, Peak memory usage = 92.953MB Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 92.953MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 92.953MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 92.953MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 84 |
I/O Buf | 84 |
    IBUF | 49 |
    OBUF | 35 |
Register | 80 |
    DFFCE | 80 |
LUT | 204 |
    LUT2 | 27 |
    LUT3 | 38 |
    LUT4 | 139 |
INV | 1 |
    INV | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 205(205 LUT, 0 ALU) / 138240 | <1% |
Register | 80 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 80 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | PCLKG | Base | 10.000 | 100.000 | 0.000 | 5.000 | PCLKG_ibuf/I | ||
2 | PCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | PCLK_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | PCLKG | 100.000(MHz) | 271.003(MHz) | 4 | TOP |
2 | PCLK | 100.000(MHz) | 207.792(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 5.188 |
Data Arrival Time | 5.161 |
Data Required Time | 10.349 |
From | u_apb_timer/reg_curr_val_13_s0 |
To | u_apb_timer/reg_curr_val_2_s0 |
Launch Clk | PCLK[R] |
Latch Clk | PCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | PCLK | |||
0.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_13_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_timer/reg_curr_val_13_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_timer/n426_s3/I0 |
1.786 | 0.579 | tINS | RR | 9 | u_apb_timer/n426_s3/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_timer/n414_s6/I0 |
2.778 | 0.579 | tINS | RR | 12 | u_apb_timer/n414_s6/F |
3.190 | 0.413 | tNET | RR | 1 | u_apb_timer/n423_s3/I1 |
3.758 | 0.567 | tINS | RR | 16 | u_apb_timer/n423_s3/F |
4.170 | 0.413 | tNET | RR | 1 | u_apb_timer/n441_s0/I0 |
4.749 | 0.579 | tINS | RR | 1 | u_apb_timer/n441_s0/F |
5.161 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | PCLK | |||
10.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_2_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_apb_timer/reg_curr_val_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 5.188 |
Data Arrival Time | 5.161 |
Data Required Time | 10.349 |
From | u_apb_timer/reg_curr_val_13_s0 |
To | u_apb_timer/reg_curr_val_3_s0 |
Launch Clk | PCLK[R] |
Latch Clk | PCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | PCLK | |||
0.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_13_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_timer/reg_curr_val_13_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_timer/n426_s3/I0 |
1.786 | 0.579 | tINS | RR | 9 | u_apb_timer/n426_s3/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_timer/n414_s6/I0 |
2.778 | 0.579 | tINS | RR | 12 | u_apb_timer/n414_s6/F |
3.190 | 0.413 | tNET | RR | 1 | u_apb_timer/n423_s3/I1 |
3.758 | 0.567 | tINS | RR | 16 | u_apb_timer/n423_s3/F |
4.170 | 0.413 | tNET | RR | 1 | u_apb_timer/n440_s0/I0 |
4.749 | 0.579 | tINS | RR | 1 | u_apb_timer/n440_s0/F |
5.161 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | PCLK | |||
10.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_3_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_apb_timer/reg_curr_val_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 5.188 |
Data Arrival Time | 5.161 |
Data Required Time | 10.349 |
From | u_apb_timer/reg_curr_val_13_s0 |
To | u_apb_timer/reg_curr_val_4_s0 |
Launch Clk | PCLK[R] |
Latch Clk | PCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | PCLK | |||
0.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_13_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_timer/reg_curr_val_13_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_timer/n426_s3/I0 |
1.786 | 0.579 | tINS | RR | 9 | u_apb_timer/n426_s3/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_timer/n414_s6/I0 |
2.778 | 0.579 | tINS | RR | 12 | u_apb_timer/n414_s6/F |
3.190 | 0.413 | tNET | RR | 1 | u_apb_timer/n423_s3/I1 |
3.758 | 0.567 | tINS | RR | 16 | u_apb_timer/n423_s3/F |
4.170 | 0.413 | tNET | RR | 1 | u_apb_timer/n439_s0/I0 |
4.749 | 0.579 | tINS | RR | 1 | u_apb_timer/n439_s0/F |
5.161 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_4_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | PCLK | |||
10.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_4_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_apb_timer/reg_curr_val_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 5.188 |
Data Arrival Time | 5.161 |
Data Required Time | 10.349 |
From | u_apb_timer/reg_curr_val_13_s0 |
To | u_apb_timer/reg_curr_val_5_s0 |
Launch Clk | PCLK[R] |
Latch Clk | PCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | PCLK | |||
0.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_13_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_timer/reg_curr_val_13_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_timer/n426_s3/I0 |
1.786 | 0.579 | tINS | RR | 9 | u_apb_timer/n426_s3/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_timer/n414_s6/I0 |
2.778 | 0.579 | tINS | RR | 12 | u_apb_timer/n414_s6/F |
3.190 | 0.413 | tNET | RR | 1 | u_apb_timer/n423_s3/I1 |
3.758 | 0.567 | tINS | RR | 16 | u_apb_timer/n423_s3/F |
4.170 | 0.413 | tNET | RR | 1 | u_apb_timer/n438_s0/I0 |
4.749 | 0.579 | tINS | RR | 1 | u_apb_timer/n438_s0/F |
5.161 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_5_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | PCLK | |||
10.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_5_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_apb_timer/reg_curr_val_5_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 5.188 |
Data Arrival Time | 5.161 |
Data Required Time | 10.349 |
From | u_apb_timer/reg_curr_val_13_s0 |
To | u_apb_timer/reg_curr_val_6_s0 |
Launch Clk | PCLK[R] |
Latch Clk | PCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | PCLK | |||
0.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_13_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_timer/reg_curr_val_13_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_timer/n426_s3/I0 |
1.786 | 0.579 | tINS | RR | 9 | u_apb_timer/n426_s3/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_timer/n414_s6/I0 |
2.778 | 0.579 | tINS | RR | 12 | u_apb_timer/n414_s6/F |
3.190 | 0.413 | tNET | RR | 1 | u_apb_timer/n423_s3/I1 |
3.758 | 0.567 | tINS | RR | 16 | u_apb_timer/n423_s3/F |
4.170 | 0.413 | tNET | RR | 1 | u_apb_timer/n437_s0/I0 |
4.749 | 0.579 | tINS | RR | 1 | u_apb_timer/n437_s0/F |
5.161 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_6_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | PCLK | |||
10.000 | 0.000 | tCL | RR | 1 | PCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 36 | PCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_timer/reg_curr_val_6_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_apb_timer/reg_curr_val_6_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |