Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBUART\data\apb_uart_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBUART\data\apb_uart.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Tue May 6 11:19:59 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module APB_UART_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.292s, Peak memory usage = 71.324MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 71.324MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 71.324MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 71.324MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 71.324MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 71.324MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 71.324MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 71.324MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 71.324MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 71.324MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 71.324MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 71.324MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 96.027MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.215s, Peak memory usage = 96.027MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 96.027MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 96.027MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 90
I/O Buf 66
    IBUF 24
    OBUF 42
Register 475
    DFFRE 304
    DFFPE 22
    DFFCE 149
LUT 640
    LUT2 74
    LUT3 283
    LUT4 283
ALU 36
    ALU 36
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 677(641 LUT, 36 ALU) / 138240 <1%
Register 475 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 475 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 pclk Base 10.000 100.000 0.000 5.000 pclk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 pclk 100.000(MHz) 91.554(MHz) 13 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.923
Data Arrival Time 11.271
Data Required Time 10.349
From u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0
To u_apb_uart/u_txctrl/uart_txfifo/full_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 475 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK
0.795 0.382 tC2Q RR 18 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1
1.807 0.600 tINS RF 1 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT
1.807 0.000 tNET FF 2 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN
1.857 0.050 tINS FR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT
1.857 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN
1.907 0.050 tINS RR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT
1.907 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN
2.151 0.244 tINS RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM
2.564 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s5/I0
3.142 0.579 tINS RR 1 u_apb_uart/u_modem/msr_cts_s5/F
3.555 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s3/I1
4.122 0.567 tINS RR 5 u_apb_uart/u_modem/msr_cts_s3/F
4.535 0.413 tNET RR 1 u_apb_uart/u_baud/baud_active_s1/I0
5.114 0.579 tINS RR 5 u_apb_uart/u_baud/baud_active_s1/F
5.526 0.413 tNET RR 1 u_apb_uart/u_uart_tx/n322_s2/I1
6.094 0.567 tINS RR 2 u_apb_uart/u_uart_tx/n322_s2/F
6.506 0.413 tNET RR 1 u_apb_uart/u_uart_tx/n322_s0/I1
7.074 0.567 tINS RR 7 u_apb_uart/u_uart_tx/n322_s0/F
7.486 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_0_s0/I1
8.054 0.567 tINS RR 2 u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_0_s0/F
8.466 0.413 tNET RR 2 u_apb_uart/u_txctrl/uart_txfifo/n38_s0/I1
9.066 0.600 tINS RF 1 u_apb_uart/u_txctrl/uart_txfifo/n38_s0/COUT
9.066 0.000 tNET FF 2 u_apb_uart/u_txctrl/uart_txfifo/n39_s0/CIN
9.116 0.050 tINS FR 1 u_apb_uart/u_txctrl/uart_txfifo/n39_s0/COUT
9.116 0.000 tNET RR 2 u_apb_uart/u_txctrl/uart_txfifo/n40_s0/CIN
9.166 0.050 tINS RR 1 u_apb_uart/u_txctrl/uart_txfifo/n40_s0/COUT
9.579 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/n45_s6/I0
10.158 0.579 tINS RR 1 u_apb_uart/u_txctrl/uart_txfifo/n45_s6/F
10.570 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/n45_s2/I3
10.859 0.289 tINS RR 1 u_apb_uart/u_txctrl/uart_txfifo/n45_s2/F
11.271 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 475 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/full_s0/CLK
10.349 -0.064 tSu 1 u_apb_uart/u_txctrl/uart_txfifo/full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.939, 54.690%; route: 4.537, 41.787%; tC2Q: 0.382, 3.523%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack -0.784
Data Arrival Time 11.133
Data Required Time 10.349
From u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0
To u_apb_uart/u_txctrl/uart_txfifo/empty_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 475 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK
0.795 0.382 tC2Q RR 18 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1
1.807 0.600 tINS RF 1 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT
1.807 0.000 tNET FF 2 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN
1.857 0.050 tINS FR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT
1.857 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN
1.907 0.050 tINS RR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT
1.907 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN
2.151 0.244 tINS RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM
2.564 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s5/I0
3.142 0.579 tINS RR 1 u_apb_uart/u_modem/msr_cts_s5/F
3.555 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s3/I1
4.122 0.567 tINS RR 5 u_apb_uart/u_modem/msr_cts_s3/F
4.535 0.413 tNET RR 1 u_apb_uart/u_baud/baud_active_s1/I0
5.114 0.579 tINS RR 5 u_apb_uart/u_baud/baud_active_s1/F
5.526 0.413 tNET RR 1 u_apb_uart/u_uart_tx/n322_s2/I1
6.094 0.567 tINS RR 2 u_apb_uart/u_uart_tx/n322_s2/F
6.506 0.413 tNET RR 1 u_apb_uart/u_uart_tx/n322_s0/I1
7.074 0.567 tINS RR 7 u_apb_uart/u_uart_tx/n322_s0/F
7.486 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_4_s1/I3
7.775 0.289 tINS RR 5 u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_4_s1/F
8.188 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_3_s0/I1
8.755 0.567 tINS RR 2 u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_3_s0/F
9.168 0.413 tNET RR 2 u_apb_uart/u_txctrl/uart_txfifo/n41_s2/I1
9.768 0.600 tINS RF 1 u_apb_uart/u_txctrl/uart_txfifo/n41_s2/COUT
10.153 0.385 tNET FF 1 u_apb_uart/u_txctrl/uart_txfifo/n80_s2/I1
10.720 0.567 tINS FR 1 u_apb_uart/u_txctrl/uart_txfifo/n80_s2/F
11.133 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 475 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/empty_s0/CLK
10.349 -0.064 tSu 1 u_apb_uart/u_txctrl/uart_txfifo/empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.828, 54.361%; route: 4.510, 42.071%; tC2Q: 0.382, 3.568%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 0.869
Data Arrival Time 9.480
Data Required Time 10.349
From u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0
To u_apb_uart/u_rxctrl/dma_rx_req_r_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 475 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK
0.795 0.382 tC2Q RR 18 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1
1.807 0.600 tINS RF 1 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT
1.807 0.000 tNET FF 2 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN
1.857 0.050 tINS FR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT
1.857 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN
1.907 0.050 tINS RR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT
1.907 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN
2.151 0.244 tINS RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM
2.564 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s5/I0
3.142 0.579 tINS RR 1 u_apb_uart/u_modem/msr_cts_s5/F
3.555 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s3/I1
4.122 0.567 tINS RR 5 u_apb_uart/u_modem/msr_cts_s3/F
4.535 0.413 tNET RR 1 u_apb_uart/u_baud/baud_active_s1/I0
5.114 0.579 tINS RR 5 u_apb_uart/u_baud/baud_active_s1/F
5.526 0.413 tNET RR 1 u_apb_uart/u_baud/baud_active_s0/I0
6.105 0.579 tINS RR 6 u_apb_uart/u_baud/baud_active_s0/F
6.517 0.413 tNET RR 1 u_apb_uart/u_rxctrl/rx_timeout_r_s4/I0
7.096 0.579 tINS RR 1 u_apb_uart/u_rxctrl/rx_timeout_r_s4/F
7.509 0.413 tNET RR 1 u_apb_uart/u_rxctrl/n178_s2/I0
8.087 0.579 tINS RR 2 u_apb_uart/u_rxctrl/n178_s2/F
8.500 0.413 tNET RR 1 u_apb_uart/u_rxctrl/n178_s1/I1
9.068 0.567 tINS RR 1 u_apb_uart/u_rxctrl/n178_s1/F
9.480 0.413 tNET RR 1 u_apb_uart/u_rxctrl/dma_rx_req_r_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 475 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_uart/u_rxctrl/dma_rx_req_r_s0/CLK
10.349 -0.064 tSu 1 u_apb_uart/u_rxctrl/dma_rx_req_r_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.973, 54.839%; route: 3.712, 40.943%; tC2Q: 0.382, 4.218%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 0.929
Data Arrival Time 9.420
Data Required Time 10.349
From u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0
To u_apb_uart/u_rxctrl/triggerred_r_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 475 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK
0.795 0.382 tC2Q RR 18 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1
1.807 0.600 tINS RF 1 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT
1.807 0.000 tNET FF 2 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN
1.857 0.050 tINS FR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT
1.857 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN
1.907 0.050 tINS RR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT
1.907 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN
2.151 0.244 tINS RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM
2.564 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s5/I0
3.142 0.579 tINS RR 1 u_apb_uart/u_modem/msr_cts_s5/F
3.555 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s3/I1
4.122 0.567 tINS RR 5 u_apb_uart/u_modem/msr_cts_s3/F
4.535 0.413 tNET RR 1 u_apb_uart/u_baud/baud_active_s1/I0
5.114 0.579 tINS RR 5 u_apb_uart/u_baud/baud_active_s1/F
5.526 0.413 tNET RR 1 u_apb_uart/u_baud/baud_active_s0/I0
6.105 0.579 tINS RR 6 u_apb_uart/u_baud/baud_active_s0/F
6.517 0.413 tNET RR 1 u_apb_uart/u_rxctrl/rx_timeout_r_s4/I0
7.096 0.579 tINS RR 1 u_apb_uart/u_rxctrl/rx_timeout_r_s4/F
7.509 0.413 tNET RR 1 u_apb_uart/u_rxctrl/n178_s2/I0
8.087 0.579 tINS RR 2 u_apb_uart/u_rxctrl/n178_s2/F
8.500 0.413 tNET RR 1 u_apb_uart/u_rxctrl/n164_s1/I2
9.007 0.507 tINS RR 1 u_apb_uart/u_rxctrl/n164_s1/F
9.420 0.413 tNET RR 1 u_apb_uart/u_rxctrl/triggerred_r_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 475 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_uart/u_rxctrl/triggerred_r_s0/CLK
10.349 -0.064 tSu 1 u_apb_uart/u_rxctrl/triggerred_r_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.913, 54.538%; route: 3.712, 41.216%; tC2Q: 0.382, 4.246%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 0.962
Data Arrival Time 9.386
Data Required Time 10.349
From u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0
To u_apb_uart/u_txctrl/uart_txfifo/rd_ptr_2_s0
Launch Clk pclk[R]
Latch Clk pclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pclk
0.000 0.000 tCL RR 1 pclk_ibuf/I
0.000 0.000 tINS RR 475 pclk_ibuf/O
0.413 0.413 tNET RR 1 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK
0.795 0.382 tC2Q RR 18 u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q
1.207 0.413 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1
1.807 0.600 tINS RF 1 u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT
1.807 0.000 tNET FF 2 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN
1.857 0.050 tINS FR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT
1.857 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN
1.907 0.050 tINS RR 1 u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT
1.907 0.000 tNET RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN
2.151 0.244 tINS RR 2 u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM
2.564 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s5/I0
3.142 0.579 tINS RR 1 u_apb_uart/u_modem/msr_cts_s5/F
3.555 0.413 tNET RR 1 u_apb_uart/u_modem/msr_cts_s3/I1
4.122 0.567 tINS RR 5 u_apb_uart/u_modem/msr_cts_s3/F
4.535 0.413 tNET RR 1 u_apb_uart/u_baud/baud_active_s1/I0
5.114 0.579 tINS RR 5 u_apb_uart/u_baud/baud_active_s1/F
5.526 0.413 tNET RR 1 u_apb_uart/u_uart_tx/n322_s2/I1
6.094 0.567 tINS RR 2 u_apb_uart/u_uart_tx/n322_s2/F
6.506 0.413 tNET RR 1 u_apb_uart/u_uart_tx/n322_s0/I1
7.074 0.567 tINS RR 7 u_apb_uart/u_uart_tx/n322_s0/F
7.486 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_2_s0/I2
7.994 0.507 tINS RR 3 u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_2_s0/F
8.406 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/n63_s2/I1
8.974 0.567 tINS RR 1 u_apb_uart/u_txctrl/uart_txfifo/n63_s2/F
9.386 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/rd_ptr_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 pclk
10.000 0.000 tCL RR 1 pclk_ibuf/I
10.000 0.000 tINS RR 475 pclk_ibuf/O
10.413 0.413 tNET RR 1 u_apb_uart/u_txctrl/uart_txfifo/rd_ptr_2_s0/CLK
10.349 -0.064 tSu 1 u_apb_uart/u_txctrl/uart_txfifo/rd_ptr_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.879, 54.367%; route: 3.712, 41.371%; tC2Q: 0.382, 4.262%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%