Top Level Module |
APB_UART_Top |
Synthesis Process |
Running parser: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.292s, Peak memory usage = 71.324MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 71.324MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 71.324MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 71.324MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 71.324MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 71.324MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 71.324MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 71.324MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 71.324MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 71.324MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 71.324MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 71.324MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 96.027MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.215s, Peak memory usage = 96.027MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 96.027MB
|
Total Time and Memory Usage |
CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 96.027MB |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
pclk |
0.000 |
0.000 |
tCL |
RR |
1 |
pclk_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
475 |
pclk_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK |
0.795 |
0.382 |
tC2Q |
RR |
18 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q |
1.207 |
0.413 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1 |
1.807 |
0.600 |
tINS |
RF |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT |
1.807 |
0.000 |
tNET |
FF |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN |
1.857 |
0.050 |
tINS |
FR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT |
1.857 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN |
1.907 |
0.050 |
tINS |
RR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT |
1.907 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN |
2.151 |
0.244 |
tINS |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM |
2.564 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/I0 |
3.142 |
0.579 |
tINS |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/F |
3.555 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s3/I1 |
4.122 |
0.567 |
tINS |
RR |
5 |
u_apb_uart/u_modem/msr_cts_s3/F |
4.535 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_baud/baud_active_s1/I0 |
5.114 |
0.579 |
tINS |
RR |
5 |
u_apb_uart/u_baud/baud_active_s1/F |
5.526 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_uart_tx/n322_s2/I1 |
6.094 |
0.567 |
tINS |
RR |
2 |
u_apb_uart/u_uart_tx/n322_s2/F |
6.506 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_uart_tx/n322_s0/I1 |
7.074 |
0.567 |
tINS |
RR |
7 |
u_apb_uart/u_uart_tx/n322_s0/F |
7.486 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_0_s0/I1 |
8.054 |
0.567 |
tINS |
RR |
2 |
u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_0_s0/F |
8.466 |
0.413 |
tNET |
RR |
2 |
u_apb_uart/u_txctrl/uart_txfifo/n38_s0/I1 |
9.066 |
0.600 |
tINS |
RF |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n38_s0/COUT |
9.066 |
0.000 |
tNET |
FF |
2 |
u_apb_uart/u_txctrl/uart_txfifo/n39_s0/CIN |
9.116 |
0.050 |
tINS |
FR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n39_s0/COUT |
9.116 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_txctrl/uart_txfifo/n40_s0/CIN |
9.166 |
0.050 |
tINS |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n40_s0/COUT |
9.579 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n45_s6/I0 |
10.158 |
0.579 |
tINS |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n45_s6/F |
10.570 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n45_s2/I3 |
10.859 |
0.289 |
tINS |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n45_s2/F |
11.271 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/full_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
pclk |
0.000 |
0.000 |
tCL |
RR |
1 |
pclk_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
475 |
pclk_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK |
0.795 |
0.382 |
tC2Q |
RR |
18 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q |
1.207 |
0.413 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1 |
1.807 |
0.600 |
tINS |
RF |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT |
1.807 |
0.000 |
tNET |
FF |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN |
1.857 |
0.050 |
tINS |
FR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT |
1.857 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN |
1.907 |
0.050 |
tINS |
RR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT |
1.907 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN |
2.151 |
0.244 |
tINS |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM |
2.564 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/I0 |
3.142 |
0.579 |
tINS |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/F |
3.555 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s3/I1 |
4.122 |
0.567 |
tINS |
RR |
5 |
u_apb_uart/u_modem/msr_cts_s3/F |
4.535 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_baud/baud_active_s1/I0 |
5.114 |
0.579 |
tINS |
RR |
5 |
u_apb_uart/u_baud/baud_active_s1/F |
5.526 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_uart_tx/n322_s2/I1 |
6.094 |
0.567 |
tINS |
RR |
2 |
u_apb_uart/u_uart_tx/n322_s2/F |
6.506 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_uart_tx/n322_s0/I1 |
7.074 |
0.567 |
tINS |
RR |
7 |
u_apb_uart/u_uart_tx/n322_s0/F |
7.486 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_4_s1/I3 |
7.775 |
0.289 |
tINS |
RR |
5 |
u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_4_s1/F |
8.188 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_3_s0/I1 |
8.755 |
0.567 |
tINS |
RR |
2 |
u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_3_s0/F |
9.168 |
0.413 |
tNET |
RR |
2 |
u_apb_uart/u_txctrl/uart_txfifo/n41_s2/I1 |
9.768 |
0.600 |
tINS |
RF |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n41_s2/COUT |
10.153 |
0.385 |
tNET |
FF |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n80_s2/I1 |
10.720 |
0.567 |
tINS |
FR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n80_s2/F |
11.133 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/empty_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
pclk |
0.000 |
0.000 |
tCL |
RR |
1 |
pclk_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
475 |
pclk_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK |
0.795 |
0.382 |
tC2Q |
RR |
18 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q |
1.207 |
0.413 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1 |
1.807 |
0.600 |
tINS |
RF |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT |
1.807 |
0.000 |
tNET |
FF |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN |
1.857 |
0.050 |
tINS |
FR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT |
1.857 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN |
1.907 |
0.050 |
tINS |
RR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT |
1.907 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN |
2.151 |
0.244 |
tINS |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM |
2.564 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/I0 |
3.142 |
0.579 |
tINS |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/F |
3.555 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s3/I1 |
4.122 |
0.567 |
tINS |
RR |
5 |
u_apb_uart/u_modem/msr_cts_s3/F |
4.535 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_baud/baud_active_s1/I0 |
5.114 |
0.579 |
tINS |
RR |
5 |
u_apb_uart/u_baud/baud_active_s1/F |
5.526 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_baud/baud_active_s0/I0 |
6.105 |
0.579 |
tINS |
RR |
6 |
u_apb_uart/u_baud/baud_active_s0/F |
6.517 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/rx_timeout_r_s4/I0 |
7.096 |
0.579 |
tINS |
RR |
1 |
u_apb_uart/u_rxctrl/rx_timeout_r_s4/F |
7.509 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/n178_s2/I0 |
8.087 |
0.579 |
tINS |
RR |
2 |
u_apb_uart/u_rxctrl/n178_s2/F |
8.500 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/n178_s1/I1 |
9.068 |
0.567 |
tINS |
RR |
1 |
u_apb_uart/u_rxctrl/n178_s1/F |
9.480 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/dma_rx_req_r_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
pclk |
0.000 |
0.000 |
tCL |
RR |
1 |
pclk_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
475 |
pclk_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK |
0.795 |
0.382 |
tC2Q |
RR |
18 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q |
1.207 |
0.413 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1 |
1.807 |
0.600 |
tINS |
RF |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT |
1.807 |
0.000 |
tNET |
FF |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN |
1.857 |
0.050 |
tINS |
FR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT |
1.857 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN |
1.907 |
0.050 |
tINS |
RR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT |
1.907 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN |
2.151 |
0.244 |
tINS |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM |
2.564 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/I0 |
3.142 |
0.579 |
tINS |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/F |
3.555 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s3/I1 |
4.122 |
0.567 |
tINS |
RR |
5 |
u_apb_uart/u_modem/msr_cts_s3/F |
4.535 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_baud/baud_active_s1/I0 |
5.114 |
0.579 |
tINS |
RR |
5 |
u_apb_uart/u_baud/baud_active_s1/F |
5.526 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_baud/baud_active_s0/I0 |
6.105 |
0.579 |
tINS |
RR |
6 |
u_apb_uart/u_baud/baud_active_s0/F |
6.517 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/rx_timeout_r_s4/I0 |
7.096 |
0.579 |
tINS |
RR |
1 |
u_apb_uart/u_rxctrl/rx_timeout_r_s4/F |
7.509 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/n178_s2/I0 |
8.087 |
0.579 |
tINS |
RR |
2 |
u_apb_uart/u_rxctrl/n178_s2/F |
8.500 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/n164_s1/I2 |
9.007 |
0.507 |
tINS |
RR |
1 |
u_apb_uart/u_rxctrl/n164_s1/F |
9.420 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/triggerred_r_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
pclk |
0.000 |
0.000 |
tCL |
RR |
1 |
pclk_ibuf/I |
0.000 |
0.000 |
tINS |
RR |
475 |
pclk_ibuf/O |
0.413 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/CLK |
0.795 |
0.382 |
tC2Q |
RR |
18 |
u_apb_uart/u_rxctrl/uart_rxfifo/rd_ptr_0_s0/Q |
1.207 |
0.413 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/I1 |
1.807 |
0.600 |
tINS |
RF |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_0_s/COUT |
1.807 |
0.000 |
tNET |
FF |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/CIN |
1.857 |
0.050 |
tINS |
FR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_1_s/COUT |
1.857 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/CIN |
1.907 |
0.050 |
tINS |
RR |
1 |
u_apb_uart/u_rxctrl/rxfifo_data_num_2_s/COUT |
1.907 |
0.000 |
tNET |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/CIN |
2.151 |
0.244 |
tINS |
RR |
2 |
u_apb_uart/u_rxctrl/rxfifo_data_num_3_s/SUM |
2.564 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/I0 |
3.142 |
0.579 |
tINS |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s5/F |
3.555 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_modem/msr_cts_s3/I1 |
4.122 |
0.567 |
tINS |
RR |
5 |
u_apb_uart/u_modem/msr_cts_s3/F |
4.535 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_baud/baud_active_s1/I0 |
5.114 |
0.579 |
tINS |
RR |
5 |
u_apb_uart/u_baud/baud_active_s1/F |
5.526 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_uart_tx/n322_s2/I1 |
6.094 |
0.567 |
tINS |
RR |
2 |
u_apb_uart/u_uart_tx/n322_s2/F |
6.506 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_uart_tx/n322_s0/I1 |
7.074 |
0.567 |
tINS |
RR |
7 |
u_apb_uart/u_uart_tx/n322_s0/F |
7.486 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_2_s0/I2 |
7.994 |
0.507 |
tINS |
RR |
3 |
u_apb_uart/u_txctrl/uart_txfifo/next_rd_ptr_2_s0/F |
8.406 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n63_s2/I1 |
8.974 |
0.567 |
tINS |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/n63_s2/F |
9.386 |
0.413 |
tNET |
RR |
1 |
u_apb_uart/u_txctrl/uart_txfifo/rd_ptr_2_s0/D |