Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBWatchdog\data\apb_wdt_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\APBWatchdog\data\apb_wdt.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue May 6 11:06:41 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | APB_WDT_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.247s, Peak memory usage = 69.129MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.129MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.129MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.129MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.129MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.129MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 69.129MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 69.129MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 69.129MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 69.129MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.129MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 69.129MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.446s, Peak memory usage = 91.383MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 91.383MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 91.383MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.639s, Elapsed time = 0h 0m 0.757s, Peak memory usage = 91.383MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 78 |
I/O Buf | 62 |
    IBUF | 26 |
    OBUF | 36 |
Register | 56 |
    DFFCE | 56 |
LUT | 115 |
    LUT2 | 11 |
    LUT3 | 37 |
    LUT4 | 67 |
INV | 1 |
    INV | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 116(116 LUT, 0 ALU) / 138240 | <1% |
Register | 56 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 56 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | pclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | pclk_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | pclk | 100.000(MHz) | 147.738(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.231 |
Data Arrival Time | 6.870 |
Data Required Time | 10.101 |
From | u_apb_wdt/counter_29_s0 |
To | u_apb_wdt/counter_0_s0 |
Launch Clk | pclk[R] |
Latch Clk | pclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_29_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_wdt/counter_29_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s30/I0 |
1.786 | 0.579 | tINS | RR | 1 | u_apb_wdt/time_end_s30/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s14/I1 |
2.349 | 0.150 | tINS | RR | 1 | u_apb_wdt/time_end_s14/O |
2.761 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s6/I1 |
2.848 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s6/O |
3.260 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s2/I1 |
3.346 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s2/O |
3.759 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s0/I1 |
3.845 | 0.086 | tINS | RR | 6 | u_apb_wdt/time_end_s0/O |
4.258 | 0.413 | tNET | RR | 1 | u_apb_wdt/set_sr_intzero_reg_s2/I2 |
4.765 | 0.507 | tINS | RR | 2 | u_apb_wdt/set_sr_intzero_reg_s2/F |
5.178 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s2/I3 |
5.466 | 0.289 | tINS | RR | 1 | u_apb_wdt/counter_en_s2/F |
5.879 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s1/I0 |
6.458 | 0.579 | tINS | RR | 32 | u_apb_wdt/counter_en_s1/F |
6.870 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_0_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pclk | |||
10.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_0_s0/CLK |
10.101 | -0.311 | tSu | 1 | u_apb_wdt/counter_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.363, 36.585%; route: 3.712, 57.492%; tC2Q: 0.382, 5.923% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 3.231 |
Data Arrival Time | 6.870 |
Data Required Time | 10.101 |
From | u_apb_wdt/counter_29_s0 |
To | u_apb_wdt/counter_1_s0 |
Launch Clk | pclk[R] |
Latch Clk | pclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_29_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_wdt/counter_29_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s30/I0 |
1.786 | 0.579 | tINS | RR | 1 | u_apb_wdt/time_end_s30/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s14/I1 |
2.349 | 0.150 | tINS | RR | 1 | u_apb_wdt/time_end_s14/O |
2.761 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s6/I1 |
2.848 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s6/O |
3.260 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s2/I1 |
3.346 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s2/O |
3.759 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s0/I1 |
3.845 | 0.086 | tINS | RR | 6 | u_apb_wdt/time_end_s0/O |
4.258 | 0.413 | tNET | RR | 1 | u_apb_wdt/set_sr_intzero_reg_s2/I2 |
4.765 | 0.507 | tINS | RR | 2 | u_apb_wdt/set_sr_intzero_reg_s2/F |
5.178 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s2/I3 |
5.466 | 0.289 | tINS | RR | 1 | u_apb_wdt/counter_en_s2/F |
5.879 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s1/I0 |
6.458 | 0.579 | tINS | RR | 32 | u_apb_wdt/counter_en_s1/F |
6.870 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pclk | |||
10.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_1_s0/CLK |
10.101 | -0.311 | tSu | 1 | u_apb_wdt/counter_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.363, 36.585%; route: 3.712, 57.492%; tC2Q: 0.382, 5.923% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 3.231 |
Data Arrival Time | 6.870 |
Data Required Time | 10.101 |
From | u_apb_wdt/counter_29_s0 |
To | u_apb_wdt/counter_2_s0 |
Launch Clk | pclk[R] |
Latch Clk | pclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_29_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_wdt/counter_29_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s30/I0 |
1.786 | 0.579 | tINS | RR | 1 | u_apb_wdt/time_end_s30/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s14/I1 |
2.349 | 0.150 | tINS | RR | 1 | u_apb_wdt/time_end_s14/O |
2.761 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s6/I1 |
2.848 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s6/O |
3.260 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s2/I1 |
3.346 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s2/O |
3.759 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s0/I1 |
3.845 | 0.086 | tINS | RR | 6 | u_apb_wdt/time_end_s0/O |
4.258 | 0.413 | tNET | RR | 1 | u_apb_wdt/set_sr_intzero_reg_s2/I2 |
4.765 | 0.507 | tINS | RR | 2 | u_apb_wdt/set_sr_intzero_reg_s2/F |
5.178 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s2/I3 |
5.466 | 0.289 | tINS | RR | 1 | u_apb_wdt/counter_en_s2/F |
5.879 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s1/I0 |
6.458 | 0.579 | tINS | RR | 32 | u_apb_wdt/counter_en_s1/F |
6.870 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_2_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pclk | |||
10.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_2_s0/CLK |
10.101 | -0.311 | tSu | 1 | u_apb_wdt/counter_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.363, 36.585%; route: 3.712, 57.492%; tC2Q: 0.382, 5.923% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 3.231 |
Data Arrival Time | 6.870 |
Data Required Time | 10.101 |
From | u_apb_wdt/counter_29_s0 |
To | u_apb_wdt/counter_3_s0 |
Launch Clk | pclk[R] |
Latch Clk | pclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_29_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_wdt/counter_29_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s30/I0 |
1.786 | 0.579 | tINS | RR | 1 | u_apb_wdt/time_end_s30/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s14/I1 |
2.349 | 0.150 | tINS | RR | 1 | u_apb_wdt/time_end_s14/O |
2.761 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s6/I1 |
2.848 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s6/O |
3.260 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s2/I1 |
3.346 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s2/O |
3.759 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s0/I1 |
3.845 | 0.086 | tINS | RR | 6 | u_apb_wdt/time_end_s0/O |
4.258 | 0.413 | tNET | RR | 1 | u_apb_wdt/set_sr_intzero_reg_s2/I2 |
4.765 | 0.507 | tINS | RR | 2 | u_apb_wdt/set_sr_intzero_reg_s2/F |
5.178 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s2/I3 |
5.466 | 0.289 | tINS | RR | 1 | u_apb_wdt/counter_en_s2/F |
5.879 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s1/I0 |
6.458 | 0.579 | tINS | RR | 32 | u_apb_wdt/counter_en_s1/F |
6.870 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_3_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pclk | |||
10.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_3_s0/CLK |
10.101 | -0.311 | tSu | 1 | u_apb_wdt/counter_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.363, 36.585%; route: 3.712, 57.492%; tC2Q: 0.382, 5.923% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 3.231 |
Data Arrival Time | 6.870 |
Data Required Time | 10.101 |
From | u_apb_wdt/counter_29_s0 |
To | u_apb_wdt/counter_4_s0 |
Launch Clk | pclk[R] |
Latch Clk | pclk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | pclk | |||
0.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
0.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_29_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | u_apb_wdt/counter_29_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s30/I0 |
1.786 | 0.579 | tINS | RR | 1 | u_apb_wdt/time_end_s30/F |
2.199 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s14/I1 |
2.349 | 0.150 | tINS | RR | 1 | u_apb_wdt/time_end_s14/O |
2.761 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s6/I1 |
2.848 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s6/O |
3.260 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s2/I1 |
3.346 | 0.086 | tINS | RR | 1 | u_apb_wdt/time_end_s2/O |
3.759 | 0.413 | tNET | RR | 1 | u_apb_wdt/time_end_s0/I1 |
3.845 | 0.086 | tINS | RR | 6 | u_apb_wdt/time_end_s0/O |
4.258 | 0.413 | tNET | RR | 1 | u_apb_wdt/set_sr_intzero_reg_s2/I2 |
4.765 | 0.507 | tINS | RR | 2 | u_apb_wdt/set_sr_intzero_reg_s2/F |
5.178 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s2/I3 |
5.466 | 0.289 | tINS | RR | 1 | u_apb_wdt/counter_en_s2/F |
5.879 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_en_s1/I0 |
6.458 | 0.579 | tINS | RR | 32 | u_apb_wdt/counter_en_s1/F |
6.870 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_4_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | pclk | |||
10.000 | 0.000 | tCL | RR | 1 | pclk_ibuf/I |
10.000 | 0.000 | tINS | RR | 56 | pclk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_apb_wdt/counter_4_s0/CLK |
10.101 | -0.311 | tSu | 1 | u_apb_wdt/counter_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.363, 36.585%; route: 3.712, 57.492%; tC2Q: 0.382, 5.923% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |