Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AXI_STREAM_FIFO\data\AXI_Stream_FIFO_Top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AXI_STREAM_FIFO\data\AXI_Stream_FIFO.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Thu Aug 03 10:57:18 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module AXI_Stream_FIFO_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.427s, Peak memory usage = 49.082MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 49.082MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 49.082MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 49.082MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 49.082MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 49.082MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 49.082MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 49.082MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 49.082MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 49.082MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 49.082MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 49.082MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 61.234MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.17s, Peak memory usage = 61.234MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 61.234MB
Total Time and Memory Usage CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 61.234MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 209
I/O Buf 170
    IBUF 90
    OBUF 80
Register 845
    DFF 19
    DFFE 131
    DFFR 3
    DFFP 6
    DFFPE 9
    DFFC 87
    DFFCE 590
LUT 1859
    LUT2 141
    LUT3 880
    LUT4 838
ALU 28
    ALU 28
INV 4
    INV 4
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 1891(1863 LUTs, 28 ALUs) / 54720 4%
Register 845 / 41997 3%
  --Register as Latch 0 / 41997 0%
  --Register as FF 845 / 41997 3%
BSRAM 2 / 140 2%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
S_axi_aclk Base 10.000 100.0 0.000 5.000 S_axi_aclk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 S_axi_aclk 100.0(MHz) 149.0(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.291
Data Arrival Time 7.537
Data Required Time 10.828
From AXI_Stream_FIFO_inst/tlr_mem_data[1]_1_s1
To AXI_Stream_FIFO_inst/isr_tse_reg_s4
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 849 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/tlr_mem_data[1]_1_s1/CLK
1.095 0.232 tC2Q RF 2 AXI_Stream_FIFO_inst/tlr_mem_data[1]_1_s1/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n2306_s36/I1
1.887 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n2306_s36/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n2306_s32/I0
2.227 0.103 tINS FF 1 AXI_Stream_FIFO_inst/n2306_s32/O
2.464 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n2306_s30/I0
2.566 0.103 tINS FF 1 AXI_Stream_FIFO_inst/n2306_s30/O
2.803 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n2306_s29/I0
2.906 0.103 tINS FF 19 AXI_Stream_FIFO_inst/n2306_s29/O
3.143 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4062_s4/I1
3.698 0.555 tINS FF 4 AXI_Stream_FIFO_inst/n4062_s4/F
3.935 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4059_s4/I3
4.306 0.371 tINS FF 4 AXI_Stream_FIFO_inst/n4059_s4/F
4.543 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4057_s4/I2
4.997 0.453 tINS FF 2 AXI_Stream_FIFO_inst/n4057_s4/F
5.234 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4056_s3/I1
5.788 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n4056_s3/F
6.025 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4075_s0/I0
6.575 0.549 tINS FR 1 AXI_Stream_FIFO_inst/n4075_s0/COUT
6.575 0.000 tNET RR 1 AXI_Stream_FIFO_inst/n4076_s0/CIN
6.610 0.035 tINS RF 1 AXI_Stream_FIFO_inst/n4076_s0/COUT
6.847 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4080_s6/I2
7.300 0.453 tINS FF 1 AXI_Stream_FIFO_inst/n4080_s6/F
7.537 0.237 tNET FF 1 AXI_Stream_FIFO_inst/isr_tse_reg_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 849 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/isr_tse_reg_s4/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/isr_tse_reg_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.835, 57.463%; route: 2.607, 39.061%; tC2Q: 0.232, 3.476%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.606
Data Arrival Time 6.222
Data Required Time 10.828
From AXI_Stream_FIFO_inst/S_axi_araddr_reg_3_s1
To AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/Empty_s0
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 849 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/S_axi_araddr_reg_3_s1/CLK
1.095 0.232 tC2Q RF 3 AXI_Stream_FIFO_inst/S_axi_araddr_reg_3_s1/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n43_s5/I1
1.887 0.555 tINS FF 9 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n43_s5/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n43_s2/I1
2.679 0.555 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n43_s2/F
2.916 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rbin_next_1_s5/I1
3.471 0.555 tINS FF 3 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rbin_next_1_s5/F
3.708 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rbin_next_1_s3/I1
4.263 0.555 tINS FF 2 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rbin_next_1_s3/F
4.500 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n260_s0/I0
5.049 0.549 tINS FR 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n260_s0/COUT
5.049 0.000 tNET RR 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n261_s0/CIN
5.084 0.035 tINS RF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n261_s0/COUT
5.084 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n262_s0/CIN
5.119 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n262_s0/COUT
5.119 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n263_s0/CIN
5.154 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n263_s0/COUT
5.154 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n264_s0/CIN
5.189 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n264_s0/COUT
5.189 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n265_s0/CIN
5.225 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n265_s0/COUT
5.225 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n266_s0/CIN
5.260 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n266_s0/COUT
5.260 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n267_s0/CIN
5.295 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n267_s0/COUT
5.532 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rempty_val_s1/I2
5.985 0.453 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rempty_val_s1/F
6.222 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 849 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/Empty_s0/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.468, 64.716%; route: 1.659, 30.955%; tC2Q: 0.232, 4.329%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From AXI_Stream_FIFO_inst/rlr_mem_cnt_19_s1
To AXI_Stream_FIFO_inst/rlr_mem_cnt_27_s1
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 849 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_19_s1/CLK
1.095 0.232 tC2Q RF 9 AXI_Stream_FIFO_inst/rlr_mem_cnt_19_s1/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/rlr_mem_data[15]_11_s9/I1
1.887 0.555 tINS FF 2 AXI_Stream_FIFO_inst/rlr_mem_data[15]_11_s9/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4837_s12/I1
2.679 0.555 tINS FF 3 AXI_Stream_FIFO_inst/n4837_s12/F
2.916 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4842_s10/I1
3.471 0.555 tINS FF 5 AXI_Stream_FIFO_inst/n4842_s10/F
3.708 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4838_s10/I1
4.263 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n4838_s10/F
4.500 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4838_s8/I1
5.055 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n4838_s8/F
5.292 0.237 tNET FF 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_27_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 849 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_27_s1/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_27_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From AXI_Stream_FIFO_inst/rlr_mem_cnt_19_s1
To AXI_Stream_FIFO_inst/rlr_mem_cnt_29_s1
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 849 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_19_s1/CLK
1.095 0.232 tC2Q RF 9 AXI_Stream_FIFO_inst/rlr_mem_cnt_19_s1/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/rlr_mem_data[15]_11_s9/I1
1.887 0.555 tINS FF 2 AXI_Stream_FIFO_inst/rlr_mem_data[15]_11_s9/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4837_s12/I1
2.679 0.555 tINS FF 3 AXI_Stream_FIFO_inst/n4837_s12/F
2.916 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4837_s14/I1
3.471 0.555 tINS FF 5 AXI_Stream_FIFO_inst/n4837_s14/F
3.708 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4836_s10/I1
4.263 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n4836_s10/F
4.500 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4836_s8/I1
5.055 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n4836_s8/F
5.292 0.237 tNET FF 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_29_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 849 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_29_s1/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_29_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From AXI_Stream_FIFO_inst/tdfv_cnt_17_s1
To AXI_Stream_FIFO_inst/tdfv_cnt_24_s1
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 849 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/tdfv_cnt_17_s1/CLK
1.095 0.232 tC2Q RF 10 AXI_Stream_FIFO_inst/tdfv_cnt_17_s1/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n895_s13/I1
1.887 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n895_s13/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n884_s13/I1
2.679 0.555 tINS FF 10 AXI_Stream_FIFO_inst/n884_s13/F
2.916 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n1747_s12/I1
3.471 0.555 tINS FF 3 AXI_Stream_FIFO_inst/n1747_s12/F
3.708 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n1749_s10/I1
4.263 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n1749_s10/F
4.500 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n1749_s8/I1
5.055 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n1749_s8/F
5.292 0.237 tNET FF 1 AXI_Stream_FIFO_inst/tdfv_cnt_24_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 849 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/tdfv_cnt_24_s1/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/tdfv_cnt_24_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%