Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AXI_STREAM_FIFO\data\AXI_Stream_FIFO_Top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AXI_STREAM_FIFO\data\AXI_Stream_FIFO.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Fri Jul 28 16:27:25 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module AXI_Stream_FIFO_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.436s, Peak memory usage = 48.699MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 48.699MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 48.699MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 48.699MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 48.699MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 48.699MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 48.699MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 48.699MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 48.699MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.122s, Peak memory usage = 48.699MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 48.699MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 48.699MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 60.590MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.168s, Peak memory usage = 60.590MB
Generate output files:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 60.590MB
Total Time and Memory Usage CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 60.590MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 371
I/O Buf 282
    IBUF 152
    OBUF 130
Register 867
    DFF 22
    DFFE 132
    DFFR 2
    DFFRE 1
    DFFP 2
    DFFPE 15
    DFFC 87
    DFFCE 606
LUT 1764
    LUT2 143
    LUT3 578
    LUT4 1043
ALU 28
    ALU 28
INV 6
    INV 6
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 1798(1770 LUTs, 28 ALUs) / 54720 4%
Register 867 / 41997 3%
  --Register as Latch 0 / 41997 0%
  --Register as FF 867 / 41997 3%
BSRAM 2 / 140 2%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
S_axi_aclk Base 10.000 100.0 0.000 5.000 S_axi_aclk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 S_axi_aclk 100.0(MHz) 150.9(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.373
Data Arrival Time 7.455
Data Required Time 10.828
From AXI_Stream_FIFO_inst/tlr_mem_data[1]_1_s1
To AXI_Stream_FIFO_inst/isr_tse_reg_s4
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 871 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/tlr_mem_data[1]_1_s1/CLK
1.095 0.232 tC2Q RF 2 AXI_Stream_FIFO_inst/tlr_mem_data[1]_1_s1/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n3087_s36/I1
1.887 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n3087_s36/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n3087_s32/I0
2.227 0.103 tINS FF 1 AXI_Stream_FIFO_inst/n3087_s32/O
2.464 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n3087_s30/I0
2.566 0.103 tINS FF 1 AXI_Stream_FIFO_inst/n3087_s30/O
2.803 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n3087_s29/I0
2.906 0.103 tINS FF 5 AXI_Stream_FIFO_inst/n3087_s29/O
3.143 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4938_s4/I1
3.698 0.555 tINS FF 4 AXI_Stream_FIFO_inst/n4938_s4/F
3.935 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4935_s4/I3
4.306 0.371 tINS FF 4 AXI_Stream_FIFO_inst/n4935_s4/F
4.543 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4932_s4/I3
4.914 0.371 tINS FF 2 AXI_Stream_FIFO_inst/n4932_s4/F
5.151 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4932_s3/I1
5.706 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n4932_s3/F
5.943 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4951_s0/I0
6.492 0.549 tINS FR 1 AXI_Stream_FIFO_inst/n4951_s0/COUT
6.492 0.000 tNET RR 1 AXI_Stream_FIFO_inst/n4952_s0/CIN
6.528 0.035 tINS RF 1 AXI_Stream_FIFO_inst/n4952_s0/COUT
6.765 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4990_s6/I2
7.218 0.453 tINS FF 1 AXI_Stream_FIFO_inst/n4990_s6/F
7.455 0.237 tNET FF 1 AXI_Stream_FIFO_inst/isr_tse_reg_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 871 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/isr_tse_reg_s4/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/isr_tse_reg_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.753, 56.934%; route: 2.607, 39.547%; tC2Q: 0.232, 3.519%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 5.464
Data Arrival Time 5.363
Data Required Time 10.828
From AXI_Stream_FIFO_inst/S_axi4_araddr_reg_5_s0
To AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/Empty_s0
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 871 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/S_axi4_araddr_reg_5_s0/CLK
1.095 0.232 tC2Q RF 1 AXI_Stream_FIFO_inst/S_axi4_araddr_reg_5_s0/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n43_s2/I1
1.887 0.555 tINS FF 9 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n43_s2/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n43_s1/I2
2.577 0.453 tINS FF 13 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n43_s1/F
2.814 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rbin_next_0_s3/I1
3.369 0.555 tINS FF 2 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rbin_next_0_s3/F
3.606 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n259_s0/I0
4.155 0.549 tINS FR 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n259_s0/COUT
4.155 0.000 tNET RR 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n260_s0/CIN
4.190 0.035 tINS RF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n260_s0/COUT
4.190 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n261_s0/CIN
4.225 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n261_s0/COUT
4.225 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n262_s0/CIN
4.260 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n262_s0/COUT
4.260 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n263_s0/CIN
4.295 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n263_s0/COUT
4.295 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n264_s0/CIN
4.331 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n264_s0/COUT
4.331 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n265_s0/CIN
4.366 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n265_s0/COUT
4.366 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n266_s0/CIN
4.401 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n266_s0/COUT
4.401 0.000 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n267_s0/CIN
4.436 0.035 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/n267_s0/COUT
4.673 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rempty_val_s1/I2
5.126 0.453 tINS FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/rempty_val_s1/F
5.363 0.237 tNET FF 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 871 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/Empty_s0/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/FIFO_receive/fifo_sc_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.847, 63.249%; route: 1.422, 31.596%; tC2Q: 0.232, 5.155%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From AXI_Stream_FIFO_inst/tlr_1_s3
To AXI_Stream_FIFO_inst/tlr_1_s3
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 871 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/tlr_1_s3/CLK
1.095 0.232 tC2Q RF 2 AXI_Stream_FIFO_inst/tlr_1_s3/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5446_s25/I1
1.887 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n5446_s25/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5446_s23/I1
2.679 0.555 tINS FF 5 AXI_Stream_FIFO_inst/n5446_s23/F
2.916 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5481_s13/I1
3.471 0.555 tINS FF 3 AXI_Stream_FIFO_inst/n5481_s13/F
3.708 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5478_s23/I1
4.263 0.555 tINS FF 2 AXI_Stream_FIFO_inst/n5478_s23/F
4.500 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5478_s27/I1
5.055 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n5478_s27/F
5.292 0.237 tNET FF 1 AXI_Stream_FIFO_inst/tlr_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 871 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/tlr_1_s3/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/tlr_1_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From AXI_Stream_FIFO_inst/rlr_mem_cnt_5_s1
To AXI_Stream_FIFO_inst/rlr_mem_cnt_24_s1
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 871 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_5_s1/CLK
1.095 0.232 tC2Q RF 8 AXI_Stream_FIFO_inst/rlr_mem_cnt_5_s1/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5733_s11/I1
1.887 0.555 tINS FF 4 AXI_Stream_FIFO_inst/n5733_s11/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5719_s12/I1
2.679 0.555 tINS FF 12 AXI_Stream_FIFO_inst/n5719_s12/F
2.916 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5716_s11/I1
3.471 0.555 tINS FF 3 AXI_Stream_FIFO_inst/n5716_s11/F
3.708 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5717_s10/I1
4.263 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n5717_s10/F
4.500 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n5717_s8/I1
5.055 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n5717_s8/F
5.292 0.237 tNET FF 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_24_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 871 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_24_s1/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/rlr_mem_cnt_24_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.536
Data Arrival Time 5.292
Data Required Time 10.828
From AXI_Stream_FIFO_inst/tlr_mem_cnt_23_s1
To AXI_Stream_FIFO_inst/tlr_mem_cnt_18_s1
Launch Clk S_axi_aclk[R]
Latch Clk S_axi_aclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 S_axi_aclk
0.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
0.683 0.683 tINS RR 871 S_axi_aclk_ibuf/O
0.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/tlr_mem_cnt_23_s1/CLK
1.095 0.232 tC2Q RF 6 AXI_Stream_FIFO_inst/tlr_mem_cnt_23_s1/Q
1.332 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n4230_s7/I1
1.887 0.555 tINS FF 3 AXI_Stream_FIFO_inst/n4230_s7/F
2.124 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n2747_s16/I1
2.679 0.555 tINS FF 4 AXI_Stream_FIFO_inst/n2747_s16/F
2.916 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n2747_s12/I1
3.471 0.555 tINS FF 40 AXI_Stream_FIFO_inst/n2747_s12/F
3.708 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n2748_s10/I1
4.263 0.555 tINS FF 13 AXI_Stream_FIFO_inst/n2748_s10/F
4.500 0.237 tNET FF 1 AXI_Stream_FIFO_inst/n2760_s8/I1
5.055 0.555 tINS FF 1 AXI_Stream_FIFO_inst/n2760_s8/F
5.292 0.237 tNET FF 1 AXI_Stream_FIFO_inst/tlr_mem_cnt_18_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 S_axi_aclk
10.000 0.000 tCL RR 1 S_axi_aclk_ibuf/I
10.682 0.683 tINS RR 871 S_axi_aclk_ibuf/O
10.863 0.180 tNET RR 1 AXI_Stream_FIFO_inst/tlr_mem_cnt_18_s1/CLK
10.828 -0.035 tSu 1 AXI_Stream_FIFO_inst/tlr_mem_cnt_18_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.775, 62.655%; route: 1.422, 32.107%; tC2Q: 0.232, 5.238%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%