Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\AXI2AHB_Async\data\axi_to_ahb_async_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\AXI2AHB_Async\data\axi_to_ahb_async.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Tue May 6 09:04:26 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module AXI_to_AHB_Async_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.323s, Peak memory usage = 72.551MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 72.551MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 72.551MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 72.551MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 72.551MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 72.551MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 72.551MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 72.551MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 72.551MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 72.551MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 72.551MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 72.551MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 100.719MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.349s, Peak memory usage = 100.719MB
Generate output files:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.127s, Peak memory usage = 100.719MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 4s, Peak memory usage = 100.719MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 321
I/O Buf 312
    IBUF 185
    OBUF 127
Register 1006
    DFFRE 740
    DFFPE 6
    DFFCE 260
LUT 892
    LUT2 49
    LUT3 553
    LUT4 290
ALU 41
    ALU 41
INV 7
    INV 7

Resource Utilization Summary

Resource Usage Utilization
Logic 940(899 LUT, 41 ALU) / 138240 <1%
Register 1006 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 1006 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 hclk Base 10.000 100.000 0.000 5.000 hclk_ibuf/I
2 aclk Base 10.000 100.000 0.000 5.000 aclk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 hclk 100.000(MHz) 90.610(MHz) 12 TOP
2 aclk 100.000(MHz) 174.787(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.068
Data Arrival Time 11.381
Data Required Time 10.314
From u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0
To u_axi_to_ahb_async/fifo2ahb/haddr_0_s1
Launch Clk aclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 aclk
0.000 0.000 tCL RR 1 aclk_ibuf/I
0.000 0.000 tINS RR 628 aclk_ibuf/O
0.413 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0/CLK
0.795 0.382 tC2Q RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0/Q
1.207 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s2/I0
1.786 0.579 tINS RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s2/F
2.199 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s0/I1
2.349 0.150 tINS RR 11 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s0/O
2.761 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n2176_s13/I0
3.340 0.579 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/n2176_s13/F
3.753 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s28/I1
4.320 0.567 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s28/F
4.733 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s18/I0
5.311 0.579 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s18/F
5.724 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s7/I0
6.303 0.579 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s7/F
6.715 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s1/I3
7.004 0.289 tINS RR 7 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s1/F
7.416 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s2/I0
7.995 0.579 tINS RR 7 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s2/F
8.408 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_3_s1/I0
8.986 0.579 tINS RR 6 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_3_s1/F
9.399 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n1321_s3/I0
9.977 0.579 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/n1321_s3/F
10.390 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n1321_s2/I0
10.969 0.579 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/n1321_s2/F
11.381 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/haddr_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.000 0.000 tINS RR 378 hclk_ibuf/O
10.413 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/haddr_0_s1/CLK
10.378 -0.035 tUnc u_axi_to_ahb_async/fifo2ahb/haddr_0_s1
10.314 -0.064 tSu 1 u_axi_to_ahb_async/fifo2ahb/haddr_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.636, 51.385%; route: 4.950, 45.128%; tC2Q: 0.382, 3.487%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack -1.056
Data Arrival Time 11.370
Data Required Time 10.314
From u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0
To u_axi_to_ahb_async/fifo2ahb/hsize_0_s1
Launch Clk aclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 aclk
0.000 0.000 tCL RR 1 aclk_ibuf/I
0.000 0.000 tINS RR 628 aclk_ibuf/O
0.413 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0/CLK
0.795 0.382 tC2Q RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0/Q
1.207 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s2/I0
1.786 0.579 tINS RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s2/F
2.199 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s0/I1
2.349 0.150 tINS RR 11 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s0/O
2.761 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n2176_s13/I0
3.340 0.579 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/n2176_s13/F
3.753 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s28/I1
4.320 0.567 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s28/F
4.733 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s18/I0
5.311 0.579 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s18/F
5.724 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s7/I0
6.303 0.579 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s7/F
6.715 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s1/I3
7.004 0.289 tINS RR 7 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s1/F
7.416 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s2/I0
7.995 0.579 tINS RR 7 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s2/F
8.408 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_3_s2/I1
8.975 0.567 tINS RR 4 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_3_s2/F
9.388 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n1400_s2/I0
9.966 0.579 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/n1400_s2/F
10.379 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n1400_s1/I0
10.958 0.579 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/n1400_s1/F
11.370 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.000 0.000 tINS RR 378 hclk_ibuf/O
10.413 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/CLK
10.378 -0.035 tUnc u_axi_to_ahb_async/fifo2ahb/hsize_0_s1
10.314 -0.064 tSu 1 u_axi_to_ahb_async/fifo2ahb/hsize_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.625, 51.334%; route: 4.950, 45.175%; tC2Q: 0.382, 3.491%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack -1.045
Data Arrival Time 11.359
Data Required Time 10.314
From u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0
To u_axi_to_ahb_async/fifo2ahb/hsize_1_s1
Launch Clk aclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 aclk
0.000 0.000 tCL RR 1 aclk_ibuf/I
0.000 0.000 tINS RR 628 aclk_ibuf/O
0.413 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0/CLK
0.795 0.382 tC2Q RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0/Q
1.207 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s2/I0
1.786 0.579 tINS RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s2/F
2.199 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s0/I1
2.349 0.150 tINS RR 11 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s0/O
2.761 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n2176_s13/I0
3.340 0.579 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/n2176_s13/F
3.753 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s28/I1
4.320 0.567 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s28/F
4.733 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s18/I0
5.311 0.579 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s18/F
5.724 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s7/I0
6.303 0.579 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s7/F
6.715 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s1/I3
7.004 0.289 tINS RR 7 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s1/F
7.416 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s2/I0
7.995 0.579 tINS RR 7 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s2/F
8.408 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_3_s1/I0
8.986 0.579 tINS RR 6 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_3_s1/F
9.399 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n1399_s2/I1
9.966 0.567 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/n1399_s2/F
10.379 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n1399_s1/I1
10.946 0.567 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/n1399_s1/F
11.359 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/hsize_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.000 0.000 tINS RR 378 hclk_ibuf/O
10.413 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/hsize_1_s1/CLK
10.378 -0.035 tUnc u_axi_to_ahb_async/fifo2ahb/hsize_1_s1
10.314 -0.064 tSu 1 u_axi_to_ahb_async/fifo2ahb/hsize_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.614, 51.285%; route: 4.950, 45.221%; tC2Q: 0.382, 3.494%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack -1.045
Data Arrival Time 11.359
Data Required Time 10.314
From u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0
To u_axi_to_ahb_async/fifo2ahb/wstrb_ap_6_s0
Launch Clk aclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 aclk
0.000 0.000 tCL RR 1 aclk_ibuf/I
0.000 0.000 tINS RR 628 aclk_ibuf/O
0.413 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0/CLK
0.795 0.382 tC2Q RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_mem_RAMREG_1_G[1]_s0/Q
1.207 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s2/I0
1.786 0.579 tINS RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s2/F
2.199 0.413 tNET RR 1 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s0/I1
2.349 0.150 tINS RR 11 u_axi_to_ahb_async/wcmdq_fifo/mem_RAMOUT_3_G[0]_s0/O
2.761 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n2176_s13/I0
3.340 0.579 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/n2176_s13/F
3.753 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s28/I1
4.320 0.567 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s28/F
4.733 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s18/I0
5.311 0.579 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s18/F
5.724 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s7/I0
6.303 0.579 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s7/F
6.715 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s1/I3
7.004 0.289 tINS RR 7 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s1/F
7.416 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s2/I0
7.995 0.579 tINS RR 7 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s2/F
8.408 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_3_s2/I1
8.975 0.567 tINS RR 4 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_3_s2/F
9.388 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s3/I0
9.966 0.579 tINS RR 4 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_4_s3/F
10.379 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_6_s0/I1
10.946 0.567 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_6_s0/F
11.359 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.000 0.000 tINS RR 378 hclk_ibuf/O
10.413 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_6_s0/CLK
10.378 -0.035 tUnc u_axi_to_ahb_async/fifo2ahb/wstrb_ap_6_s0
10.314 -0.064 tSu 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.614, 51.285%; route: 4.950, 45.221%; tC2Q: 0.382, 3.494%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack -1.036
Data Arrival Time 11.138
Data Required Time 10.101
From u_axi_to_ahb_async/fifo2ahb/hsize_0_s1
To u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1
Launch Clk hclk[R]
Latch Clk hclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 hclk
0.000 0.000 tCL RR 1 hclk_ibuf/I
0.000 0.000 tINS RR 378 hclk_ibuf/O
0.413 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/CLK
0.795 0.382 tC2Q RR 28 u_axi_to_ahb_async/fifo2ahb/hsize_0_s1/Q
1.207 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/I0
1.786 0.579 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/haddr_adder_0_s/F
2.199 0.413 tNET RR 2 u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/I1
2.799 0.600 tINS RF 1 u_axi_to_ahb_async/fifo2ahb/haddr_inc_0_s/COUT
2.799 0.000 tNET FF 2 u_axi_to_ahb_async/fifo2ahb/haddr_inc_1_s/CIN
3.043 0.244 tINS FR 3 u_axi_to_ahb_async/fifo2ahb/haddr_inc_1_s/SUM
3.455 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s30/I2
3.962 0.507 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s30/F
4.375 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s20/I1
4.943 0.567 tINS RR 3 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s20/F
5.355 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s12/I1
5.923 0.567 tINS RR 2 u_axi_to_ahb_async/fifo2ahb/wstrb_ap_part_wr_nxt_2_s12/F
6.335 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n2176_s5/I2
6.843 0.507 tINS RR 3 u_axi_to_ahb_async/fifo2ahb/n2176_s5/F
7.255 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n495_s14/I2
7.763 0.507 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/n495_s14/F
8.175 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n495_s5/I1
8.743 0.567 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/n495_s5/F
9.155 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/n495_s1/I0
9.734 0.579 tINS RR 3 u_axi_to_ahb_async/fifo2ahb/n495_s1/F
10.146 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s3/I0
10.725 0.579 tINS RR 1 u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s3/F
11.138 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 hclk
10.000 0.000 tCL RR 1 hclk_ibuf/I
10.000 0.000 tINS RR 378 hclk_ibuf/O
10.413 0.413 tNET RR 1 u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1/CLK
10.101 -0.311 tSu 1 u_axi_to_ahb_async/fifo2ahb/error_wstrb_ap_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.805, 54.126%; route: 4.537, 42.308%; tC2Q: 0.382, 3.566%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%