Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\AXI2AHB_Sync\data\axi_to_ahb_sync_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\AXI2AHB_Sync\data\axi_to_ahb_sync.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue May 6 09:30:51 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | AXI_to_AHB_Sync_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.304s, Peak memory usage = 71.891MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 71.891MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 71.891MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 71.891MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 71.891MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 71.891MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 71.891MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 71.891MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 71.891MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 71.891MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 71.891MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 71.891MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 5s, Peak memory usage = 98.840MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.214s, Peak memory usage = 98.840MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 98.840MB |
Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 5s, Peak memory usage = 98.840MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 319 |
I/O Buf | 310 |
    IBUF | 183 |
    OBUF | 127 |
Register | 289 |
    DFFRE | 76 |
    DFFPE | 3 |
    DFFCE | 210 |
LUT | 671 |
    LUT2 | 57 |
    LUT3 | 283 |
    LUT4 | 331 |
ALU | 31 |
    ALU | 31 |
INV | 2 |
    INV | 2 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 704(673 LUT, 31 ALU) / 138240 | <1% |
Register | 289 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 289 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.000(MHz) | 71.988(MHz) | 14 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -3.891 |
Data Arrival Time | 14.240 |
Data Required Time | 10.349 |
From | u_axi_to_ahb_sync/hsize_0_s1 |
To | u_axi_to_ahb_sync/ahb_non_cmd_phase_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/hsize_0_s1/CLK |
0.795 | 0.382 | tC2Q | RR | 25 | u_axi_to_ahb_sync/hsize_0_s1/Q |
1.207 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/haddr_adder_0_s0/I0 |
1.786 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_adder_0_s0/F |
2.199 | 0.413 | tNET | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/I1 |
2.980 | 0.781 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/SUM |
3.392 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/I0 |
3.971 | 0.579 | tINS | RR | 3 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/F |
4.384 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/I1 |
4.951 | 0.567 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/F |
5.364 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/I0 |
5.943 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/F |
6.355 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/I1 |
6.923 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/F |
7.335 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/I0 |
7.914 | 0.579 | tINS | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/F |
8.326 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/I0 |
8.905 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/F |
9.318 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_3_s30/I1 |
9.885 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/ahb_ns_3_s30/F |
10.298 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_0_s31/I0 |
10.876 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/ahb_ns_0_s31/F |
11.289 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s30/I1 |
11.856 | 0.567 | tINS | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s30/F |
12.269 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s28/I1 |
12.836 | 0.567 | tINS | RR | 7 | u_axi_to_ahb_sync/ahb_ns_1_s28/F |
13.249 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/n67_s2/I0 |
13.828 | 0.579 | tINS | RR | 1 | u_axi_to_ahb_sync/n67_s2/F |
14.240 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_non_cmd_phase_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_non_cmd_phase_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_axi_to_ahb_sync/ahb_non_cmd_phase_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 7.670, 55.469%; route: 5.775, 41.765%; tC2Q: 0.382, 2.766% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | -3.880 |
Data Arrival Time | 14.229 |
Data Required Time | 10.349 |
From | u_axi_to_ahb_sync/hsize_0_s1 |
To | u_axi_to_ahb_sync/htrans_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/hsize_0_s1/CLK |
0.795 | 0.382 | tC2Q | RR | 25 | u_axi_to_ahb_sync/hsize_0_s1/Q |
1.207 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/haddr_adder_0_s0/I0 |
1.786 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_adder_0_s0/F |
2.199 | 0.413 | tNET | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/I1 |
2.980 | 0.781 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/SUM |
3.392 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/I0 |
3.971 | 0.579 | tINS | RR | 3 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/F |
4.384 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/I1 |
4.951 | 0.567 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/F |
5.364 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/I0 |
5.943 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/F |
6.355 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/I1 |
6.923 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/F |
7.335 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/I0 |
7.914 | 0.579 | tINS | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/F |
8.326 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/I0 |
8.905 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/F |
9.318 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_3_s30/I1 |
9.885 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/ahb_ns_3_s30/F |
10.298 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_0_s31/I0 |
10.876 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/ahb_ns_0_s31/F |
11.289 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s30/I1 |
11.856 | 0.567 | tINS | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s30/F |
12.269 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s28/I1 |
12.836 | 0.567 | tINS | RR | 7 | u_axi_to_ahb_sync/ahb_ns_1_s28/F |
13.249 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/n706_s1/I1 |
13.816 | 0.567 | tINS | RR | 1 | u_axi_to_ahb_sync/n706_s1/F |
14.229 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/htrans_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/htrans_0_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_axi_to_ahb_sync/htrans_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 7.659, 55.433%; route: 5.775, 41.799%; tC2Q: 0.382, 2.768% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | -3.880 |
Data Arrival Time | 14.229 |
Data Required Time | 10.349 |
From | u_axi_to_ahb_sync/hsize_0_s1 |
To | u_axi_to_ahb_sync/ahb_idle_wdata_dp_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/hsize_0_s1/CLK |
0.795 | 0.382 | tC2Q | RR | 25 | u_axi_to_ahb_sync/hsize_0_s1/Q |
1.207 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/haddr_adder_0_s0/I0 |
1.786 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_adder_0_s0/F |
2.199 | 0.413 | tNET | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/I1 |
2.980 | 0.781 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/SUM |
3.392 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/I0 |
3.971 | 0.579 | tINS | RR | 3 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/F |
4.384 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/I1 |
4.951 | 0.567 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/F |
5.364 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/I0 |
5.943 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/F |
6.355 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/I1 |
6.923 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/F |
7.335 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/I0 |
7.914 | 0.579 | tINS | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/F |
8.326 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/I0 |
8.905 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/F |
9.318 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_3_s30/I1 |
9.885 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/ahb_ns_3_s30/F |
10.298 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_0_s31/I0 |
10.876 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/ahb_ns_0_s31/F |
11.289 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s30/I1 |
11.856 | 0.567 | tINS | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s30/F |
12.269 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s28/I1 |
12.836 | 0.567 | tINS | RR | 7 | u_axi_to_ahb_sync/ahb_ns_1_s28/F |
13.249 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/n81_s2/I1 |
13.816 | 0.567 | tINS | RR | 1 | u_axi_to_ahb_sync/n81_s2/F |
14.229 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_idle_wdata_dp_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_idle_wdata_dp_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_axi_to_ahb_sync/ahb_idle_wdata_dp_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 7.659, 55.433%; route: 5.775, 41.799%; tC2Q: 0.382, 2.768% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | -3.880 |
Data Arrival Time | 14.229 |
Data Required Time | 10.349 |
From | u_axi_to_ahb_sync/hsize_0_s1 |
To | u_axi_to_ahb_sync/ahb_wait_wvalid_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/hsize_0_s1/CLK |
0.795 | 0.382 | tC2Q | RR | 25 | u_axi_to_ahb_sync/hsize_0_s1/Q |
1.207 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/haddr_adder_0_s0/I0 |
1.786 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_adder_0_s0/F |
2.199 | 0.413 | tNET | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/I1 |
2.980 | 0.781 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/SUM |
3.392 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/I0 |
3.971 | 0.579 | tINS | RR | 3 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/F |
4.384 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/I1 |
4.951 | 0.567 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/F |
5.364 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/I0 |
5.943 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/F |
6.355 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/I1 |
6.923 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/F |
7.335 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/I0 |
7.914 | 0.579 | tINS | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/F |
8.326 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/I0 |
8.905 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/F |
9.318 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_3_s30/I1 |
9.885 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/ahb_ns_3_s30/F |
10.298 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_0_s31/I0 |
10.876 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/ahb_ns_0_s31/F |
11.289 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s30/I1 |
11.856 | 0.567 | tINS | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s30/F |
12.269 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_1_s28/I1 |
12.836 | 0.567 | tINS | RR | 7 | u_axi_to_ahb_sync/ahb_ns_1_s28/F |
13.249 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/n79_s0/I1 |
13.816 | 0.567 | tINS | RR | 1 | u_axi_to_ahb_sync/n79_s0/F |
14.229 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_wait_wvalid_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_wait_wvalid_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_axi_to_ahb_sync/ahb_wait_wvalid_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 7.659, 55.433%; route: 5.775, 41.799%; tC2Q: 0.382, 2.768% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | -3.629 |
Data Arrival Time | 13.978 |
Data Required Time | 10.349 |
From | u_axi_to_ahb_sync/hsize_0_s1 |
To | u_axi_to_ahb_sync/ahb_addr_phase_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/hsize_0_s1/CLK |
0.795 | 0.382 | tC2Q | RR | 25 | u_axi_to_ahb_sync/hsize_0_s1/Q |
1.207 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/haddr_adder_0_s0/I0 |
1.786 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_adder_0_s0/F |
2.199 | 0.413 | tNET | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/I1 |
2.980 | 0.781 | tINS | RR | 2 | u_axi_to_ahb_sync/haddr_inc_0_s/SUM |
3.392 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/I0 |
3.971 | 0.579 | tINS | RR | 3 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s37/F |
4.384 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/I1 |
4.951 | 0.567 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s47/F |
5.364 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/I0 |
5.943 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s22/F |
6.355 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/I1 |
6.923 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/zero_wstrb_ap_nxt_s9/F |
7.335 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/I0 |
7.914 | 0.579 | tINS | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s18/F |
8.326 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/I0 |
8.905 | 0.579 | tINS | RR | 2 | u_axi_to_ahb_sync/error_wstrb_ap_nxt_s15/F |
9.318 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_3_s30/I1 |
9.885 | 0.567 | tINS | RR | 9 | u_axi_to_ahb_sync/ahb_ns_3_s30/F |
10.298 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_0_s37/I2 |
10.805 | 0.507 | tINS | RR | 1 | u_axi_to_ahb_sync/ahb_ns_0_s37/F |
11.218 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_0_s65/I2 |
11.725 | 0.507 | tINS | RR | 1 | u_axi_to_ahb_sync/ahb_ns_0_s65/F |
12.138 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_ns_0_s29/I2 |
12.645 | 0.507 | tINS | RR | 6 | u_axi_to_ahb_sync/ahb_ns_0_s29/F |
13.058 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/n61_s3/I2 |
13.565 | 0.507 | tINS | RR | 1 | u_axi_to_ahb_sync/n61_s3/F |
13.978 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_addr_phase_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 289 | clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | u_axi_to_ahb_sync/ahb_addr_phase_s0/CLK |
10.349 | -0.064 | tSu | 1 | u_axi_to_ahb_sync/ahb_addr_phase_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 14 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 7.408, 54.607%; route: 5.775, 42.573%; tC2Q: 0.382, 2.820% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |