Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\AHB_to_AXI_Bridge\data\ahb2axi_top.v D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\AHB_to_AXI_Bridge\data\ahb2axi_encrypt.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Tue May 6 09:30:38 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | AHB_to_AXI_Bridge_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.429s, Peak memory usage = 70.945MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 70.945MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 70.945MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 70.945MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 70.945MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 70.945MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 70.945MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 70.945MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 70.945MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 70.945MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 70.945MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 70.945MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.555s, Peak memory usage = 93.875MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.19s, Peak memory usage = 93.875MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.121s, Peak memory usage = 93.875MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.947s, Elapsed time = 0h 0m 1s, Peak memory usage = 93.875MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 307 |
I/O Buf | 305 |
    IBUF | 123 |
    OBUF | 182 |
Register | 446 |
    DFFRE | 284 |
    DFFPE | 3 |
    DFFCE | 159 |
LUT | 243 |
    LUT2 | 13 |
    LUT3 | 178 |
    LUT4 | 52 |
ALU | 4 |
    ALU | 4 |
INV | 8 |
    INV | 8 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 255(251 LUT, 4 ALU) / 138240 | <1% |
Register | 446 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 446 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | AHB_HCLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | AHB_HCLK_ibuf/I | ||
2 | AXI_ACLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | AXI_ACLK_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | AHB_HCLK | 100.000(MHz) | 152.178(MHz) | 8 | TOP |
2 | AXI_ACLK | 100.000(MHz) | 204.499(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 3.429 |
Data Arrival Time | 6.920 |
Data Required Time | 10.349 |
From | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_drop_rdata_s0 |
To | ahb2axi_inst/u_rdata_fifo/empty_s0 |
Launch Clk | AHB_HCLK[R] |
Latch Clk | AHB_HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 279 | AHB_HCLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_drop_rdata_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 8 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_drop_rdata_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/n117_s0/I0 |
1.786 | 0.579 | tINS | RR | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/n117_s0/F |
2.199 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/I3 |
2.487 | 0.289 | tINS | RR | 7 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/F |
2.900 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_1_s3/I1 |
3.468 | 0.567 | tINS | RR | 2 | ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_1_s3/F |
3.880 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/next_gray_rd_ptr_0_s1/I0 |
4.459 | 0.579 | tINS | RR | 2 | ahb2axi_inst/u_rdata_fifo/next_gray_rd_ptr_0_s1/F |
4.871 | 0.413 | tNET | RR | 2 | ahb2axi_inst/u_rdata_fifo/n146_s0/I0 |
5.466 | 0.595 | tINS | RF | 1 | ahb2axi_inst/u_rdata_fifo/n146_s0/COUT |
5.466 | 0.000 | tNET | FF | 2 | ahb2axi_inst/u_rdata_fifo/n147_s0/CIN |
5.516 | 0.050 | tINS | FR | 1 | ahb2axi_inst/u_rdata_fifo/n147_s0/COUT |
5.929 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/next_empty_s1/I0 |
6.508 | 0.579 | tINS | RR | 1 | ahb2axi_inst/u_rdata_fifo/next_empty_s1/F |
6.920 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/empty_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 279 | AHB_HCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/empty_s0/CLK |
10.349 | -0.064 | tSu | 1 | ahb2axi_inst/u_rdata_fifo/empty_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 3.238, 49.750%; route: 2.887, 44.372%; tC2Q: 0.382, 5.878% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 3.724 |
Data Arrival Time | 6.343 |
Data Required Time | 10.066 |
From | ahb2axi_inst/u_rdata_fifo/mem_mem_RAMREG_1_G[32]_s0 |
To | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s1 |
Launch Clk | AXI_ACLK[R] |
Latch Clk | AHB_HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AXI_ACLK | |||
0.000 | 0.000 | tCL | RR | 1 | AXI_ACLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 167 | AXI_ACLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_RAMREG_1_G[32]_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_RAMREG_1_G[32]_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s2/I0 |
1.786 | 0.579 | tINS | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s2/F |
2.199 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s0/I1 |
2.349 | 0.150 | tINS | RR | 2 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s0/O |
2.761 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s3/I1 |
3.329 | 0.567 | tINS | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s3/F |
3.741 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s2/I3 |
4.030 | 0.289 | tINS | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s2/F |
4.443 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s0/I2 |
4.950 | 0.507 | tINS | RR | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s0/F |
5.363 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s3/I1 |
5.930 | 0.567 | tINS | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s3/F |
6.343 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 279 | AHB_HCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s1/CLK |
10.378 | -0.035 | tUnc | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s1 | ||
10.066 | -0.311 | tSu | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.660, 44.857%; route: 2.887, 48.693%; tC2Q: 0.382, 6.450% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 3.960 |
Data Arrival Time | 6.354 |
Data Required Time | 10.314 |
From | ahb2axi_inst/u_rdata_fifo/mem_mem_RAMREG_1_G[32]_s0 |
To | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_s0 |
Launch Clk | AXI_ACLK[R] |
Latch Clk | AHB_HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AXI_ACLK | |||
0.000 | 0.000 | tCL | RR | 1 | AXI_ACLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 167 | AXI_ACLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_RAMREG_1_G[32]_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_RAMREG_1_G[32]_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s2/I0 |
1.786 | 0.579 | tINS | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s2/F |
2.199 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s0/I1 |
2.349 | 0.150 | tINS | RR | 2 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s0/O |
2.761 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s3/I1 |
3.329 | 0.567 | tINS | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s3/F |
3.741 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s2/I3 |
4.030 | 0.289 | tINS | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s2/F |
4.443 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s0/I2 |
4.950 | 0.507 | tINS | RR | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s0/F |
5.363 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_nx_s0/I0 |
5.941 | 0.579 | tINS | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_nx_s0/F |
6.354 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 279 | AHB_HCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_s0/CLK |
10.378 | -0.035 | tUnc | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_s0 | ||
10.314 | -0.064 | tSu | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.671, 44.961%; route: 2.887, 48.601%; tC2Q: 0.382, 6.438% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 3.971 |
Data Arrival Time | 6.343 |
Data Required Time | 10.314 |
From | ahb2axi_inst/u_rdata_fifo/mem_mem_RAMREG_1_G[32]_s0 |
To | ahb2axi_inst/u_ahb2axi_ahb2fifo/hresp_s0 |
Launch Clk | AXI_ACLK[R] |
Latch Clk | AHB_HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AXI_ACLK | |||
0.000 | 0.000 | tCL | RR | 1 | AXI_ACLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 167 | AXI_ACLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_RAMREG_1_G[32]_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_RAMREG_1_G[32]_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s2/I0 |
1.786 | 0.579 | tINS | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s2/F |
2.199 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s0/I1 |
2.349 | 0.150 | tINS | RR | 2 | ahb2axi_inst/u_rdata_fifo/mem_RAMOUT_96_G[0]_s0/O |
2.761 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s3/I1 |
3.329 | 0.567 | tINS | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s3/F |
3.741 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s2/I3 |
4.030 | 0.289 | tINS | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s2/F |
4.443 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s0/I2 |
4.950 | 0.507 | tINS | RR | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s0/F |
5.363 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_2cycle_nx_s0/I1 |
5.930 | 0.567 | tINS | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_2cycle_nx_s0/F |
6.343 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hresp_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 279 | AHB_HCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hresp_s0/CLK |
10.378 | -0.035 | tUnc | ahb2axi_inst/u_ahb2axi_ahb2fifo/hresp_s0 | ||
10.314 | -0.064 | tSu | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hresp_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.660, 44.857%; route: 2.887, 48.693%; tC2Q: 0.382, 6.450% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 4.279 |
Data Arrival Time | 6.070 |
Data Required Time | 10.349 |
From | ahb2axi_inst/u_ahb2axi_ahb2fifo/wr_cnt_2_s0 |
To | ahb2axi_inst/u_wdata_fifo/full_s0 |
Launch Clk | AHB_HCLK[R] |
Latch Clk | AHB_HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_HCLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
0.000 | 0.000 | tINS | RR | 279 | AHB_HCLK_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/wr_cnt_2_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/wr_cnt_2_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/wlast_nx_s2/I0 |
1.786 | 0.579 | tINS | RR | 5 | ahb2axi_inst/u_ahb2axi_ahb2fifo/wlast_nx_s2/F |
2.199 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_wdata_fifo/mem_s177/I2 |
2.706 | 0.507 | tINS | RR | 12 | ahb2axi_inst/u_wdata_fifo/mem_s177/F |
3.119 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_wdata_fifo/next_gray_wr_ptr_1_s1/I1 |
3.686 | 0.567 | tINS | RR | 2 | ahb2axi_inst/u_wdata_fifo/next_gray_wr_ptr_1_s1/F |
4.099 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_wdata_fifo/n40_s1/I1 |
4.666 | 0.567 | tINS | RR | 1 | ahb2axi_inst/u_wdata_fifo/n40_s1/F |
5.079 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_wdata_fifo/n40_s0/I0 |
5.658 | 0.579 | tINS | RR | 1 | ahb2axi_inst/u_wdata_fifo/n40_s0/F |
6.070 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_wdata_fifo/full_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_HCLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
10.000 | 0.000 | tINS | RR | 279 | AHB_HCLK_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | ahb2axi_inst/u_wdata_fifo/full_s0/CLK |
10.349 | -0.064 | tSu | 1 | ahb2axi_inst/u_wdata_fifo/full_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.800, 49.492%; route: 2.475, 43.747%; tC2Q: 0.382, 6.761% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |