Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\advanced_fir_filter.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\advanced_fir_filter_wrap.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\static_macro_define.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Dec 25 12:42:04 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Advanced_FIR_Filter_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.569s, Peak memory usage = 149.898MB
Running netlist conversion:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 149.898MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.409s, Peak memory usage = 149.898MB
    Optimizing Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.192s, Peak memory usage = 149.898MB
    Optimizing Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.341s, Peak memory usage = 149.898MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.344s, Peak memory usage = 149.898MB
    Inferring Phase 1: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.819s, Peak memory usage = 149.898MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 149.898MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 149.898MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.734s, Peak memory usage = 149.898MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 149.898MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 149.898MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 169.871MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 169.871MB
Generate output files:
    CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.65s, Peak memory usage = 218.914MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 218.914MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 39
I/O Buf 39
    IBUF 20
    OBUF 19
Register 6043
    DFFPE 40
    DFFCE 6003
LUT 2060
    LUT2 31
    LUT3 1781
    LUT4 248
ALU 906
    ALU 906
INV 3
    INV 3
DSP
    MULTALU27X18 21
BSRAM 1
    pROM 1

Resource Utilization Summary

Resource Usage Utilization
Logic 2969(2063 LUT, 906 ALU) / 23040 13%
Register 6043 / 23685 26%
  --Register as Latch 0 / 23685 0%
  --Register as FF 6043 / 23685 26%
BSRAM 1 / 56 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 244.709(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.914
Data Arrival Time 4.404
Data Required Time 10.318
From advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/n47_s1
To advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/mult_dsp_o_29_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6065 clk_ibuf/O
0.375 0.375 tNET RR 32 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/n47_s1/CLK[0]
4.054 3.679 tC2Q RF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/n47_s1/DOUT[29]
4.404 0.350 tNET FF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/mult_dsp_o_29_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6065 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/mult_dsp_o_29_s0/CLK
10.318 -0.058 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/mult_dsp_o_29_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.350, 8.687%; tC2Q: 3.679, 91.313%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 5.914
Data Arrival Time 4.404
Data Required Time 10.318
From advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[18].mult_dsp_inst/n47_s1
To advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[18].mult_dsp_inst/mult_dsp_o_29_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6065 clk_ibuf/O
0.375 0.375 tNET RR 32 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[18].mult_dsp_inst/n47_s1/CLK[0]
4.054 3.679 tC2Q RF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[18].mult_dsp_inst/n47_s1/DOUT[29]
4.404 0.350 tNET FF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[18].mult_dsp_inst/mult_dsp_o_29_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6065 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[18].mult_dsp_inst/mult_dsp_o_29_s0/CLK
10.318 -0.058 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[18].mult_dsp_inst/mult_dsp_o_29_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.350, 8.687%; tC2Q: 3.679, 91.313%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 5.914
Data Arrival Time 4.404
Data Required Time 10.318
From advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/n47_s1
To advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/mult_dsp_o_29_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6065 clk_ibuf/O
0.375 0.375 tNET RR 32 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/n47_s1/CLK[0]
4.054 3.679 tC2Q RF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/n47_s1/DOUT[29]
4.404 0.350 tNET FF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/mult_dsp_o_29_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6065 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/mult_dsp_o_29_s0/CLK
10.318 -0.058 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/mult_dsp_o_29_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.350, 8.687%; tC2Q: 3.679, 91.313%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 5.914
Data Arrival Time 4.404
Data Required Time 10.318
From advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[16].mult_dsp_inst/n47_s1
To advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[16].mult_dsp_inst/mult_dsp_o_29_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6065 clk_ibuf/O
0.375 0.375 tNET RR 32 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[16].mult_dsp_inst/n47_s1/CLK[0]
4.054 3.679 tC2Q RF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[16].mult_dsp_inst/n47_s1/DOUT[29]
4.404 0.350 tNET FF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[16].mult_dsp_inst/mult_dsp_o_29_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6065 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[16].mult_dsp_inst/mult_dsp_o_29_s0/CLK
10.318 -0.058 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[16].mult_dsp_inst/mult_dsp_o_29_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.350, 8.687%; tC2Q: 3.679, 91.313%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 5.914
Data Arrival Time 4.404
Data Required Time 10.318
From advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[15].mult_dsp_inst/n47_s1
To advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[15].mult_dsp_inst/mult_dsp_o_29_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6065 clk_ibuf/O
0.375 0.375 tNET RR 32 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[15].mult_dsp_inst/n47_s1/CLK[0]
4.054 3.679 tC2Q RF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[15].mult_dsp_inst/n47_s1/DOUT[29]
4.404 0.350 tNET FF 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[15].mult_dsp_inst/mult_dsp_o_29_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6065 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[15].mult_dsp_inst/mult_dsp_o_29_s0/CLK
10.318 -0.058 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[15].mult_dsp_inst/mult_dsp_o_29_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.350, 8.687%; tC2Q: 3.679, 91.313%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%