Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\advanced_fir_filter.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\advanced_fir_filter_wrap.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\static_macro_define.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Dec 25 10:48:31 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Advanced_FIR_Filter_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.357s, Peak memory usage = 118.660MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 118.660MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 118.660MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 118.660MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 118.660MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 118.660MB
    Inferring Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 118.660MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 118.660MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 118.660MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.161s, Peak memory usage = 118.660MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 118.660MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 118.660MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.65s, Peak memory usage = 143.043MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 143.043MB
Generate output files:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.175s, Peak memory usage = 143.043MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 143.043MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 54
I/O Buf 54
    IBUF 20
    OBUF 34
Register 1671
    DFFPE 31
    DFFCE 1640
LUT 879
    LUT2 76
    LUT3 707
    LUT4 96
ALU 44
    ALU 44
INV 5
    INV 5
DSP
    MULTALU27X18 1
    MULT12X12 1
BSRAM 1
    pROM 1

Resource Utilization Summary

Resource Usage Utilization
Logic 928(884 LUT, 44 ALU) / 23040 5%
Register 1671 / 23685 8%
  --Register as Latch 0 / 23685 0%
  --Register as FF 1671 / 23685 8%
BSRAM 1 / 56 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 156.252(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.600
Data Arrival Time 6.711
Data Required Time 10.311
From advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1673 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.270 2.236 tINS RR 2 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[5]
4.645 0.375 tNET RR 2 advanced_fir_filter_inst/fir_interpolator_inst/n842_s/I0
5.201 0.556 tINS RF 1 advanced_fir_filter_inst/fir_interpolator_inst/n842_s/COUT
5.201 0.000 tNET FF 2 advanced_fir_filter_inst/fir_interpolator_inst/n841_s/CIN
5.445 0.244 tINS FR 1 advanced_fir_filter_inst/fir_interpolator_inst/n841_s/SUM
5.820 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n848_s0/I1
6.336 0.516 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n848_s0/F
6.711 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1673 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.079, 64.371%; route: 1.875, 29.592%; tC2Q: 0.382, 6.037%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 3.669
Data Arrival Time 6.642
Data Required Time 10.311
From advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1673 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.270 2.236 tINS RR 2 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[5]
4.645 0.375 tNET RR 2 advanced_fir_filter_inst/fir_interpolator_inst/n842_s/I0
5.376 0.731 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n842_s/SUM
5.751 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n849_s0/I1
6.267 0.516 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n849_s0/F
6.642 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1673 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.010, 63.980%; route: 1.875, 29.917%; tC2Q: 0.382, 6.103%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 3.734
Data Arrival Time 6.578
Data Required Time 10.311
From advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1673 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.136 2.103 tINS RR 2 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[3]
4.511 0.375 tNET RR 2 advanced_fir_filter_inst/fir_interpolator_inst/n844_s/I0
5.068 0.556 tINS RF 1 advanced_fir_filter_inst/fir_interpolator_inst/n844_s/COUT
5.068 0.000 tNET FF 2 advanced_fir_filter_inst/fir_interpolator_inst/n843_s/CIN
5.311 0.244 tINS FR 1 advanced_fir_filter_inst/fir_interpolator_inst/n843_s/SUM
5.686 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n850_s0/I1
6.203 0.516 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n850_s0/F
6.578 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1673 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.945, 63.603%; route: 1.875, 30.230%; tC2Q: 0.382, 6.167%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 3.786
Data Arrival Time 6.525
Data Required Time 10.311
From advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1673 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.109 2.075 tINS RF 2 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[2]
4.459 0.350 tNET FF 2 advanced_fir_filter_inst/fir_interpolator_inst/n845_s/I0
5.015 0.556 tINS FF 1 advanced_fir_filter_inst/fir_interpolator_inst/n845_s/COUT
5.015 0.000 tNET FF 2 advanced_fir_filter_inst/fir_interpolator_inst/n844_s/CIN
5.259 0.244 tINS FR 1 advanced_fir_filter_inst/fir_interpolator_inst/n844_s/SUM
5.634 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n851_s0/I1
6.150 0.516 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n851_s0/F
6.525 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1673 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.918, 63.700%; route: 1.850, 30.081%; tC2Q: 0.382, 6.219%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 3.855
Data Arrival Time 6.456
Data Required Time 10.311
From advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1673 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.109 2.075 tINS RF 2 advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[2]
4.459 0.350 tNET FF 2 advanced_fir_filter_inst/fir_interpolator_inst/n845_s/I0
5.190 0.731 tINS FR 1 advanced_fir_filter_inst/fir_interpolator_inst/n845_s/SUM
5.565 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n852_s0/I1
6.081 0.516 tINS RR 1 advanced_fir_filter_inst/fir_interpolator_inst/n852_s0/F
6.456 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1673 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.849, 63.289%; route: 1.850, 30.421%; tC2Q: 0.382, 6.290%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%