Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\1_fir_singlerate\32taps_8chn_32tdm_16bit\proj\src\advanced_fir_filter\advanced_fir_filter.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\1_fir_singlerate\32taps_8chn_32tdm_16bit\proj\src\sim_input_gen.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\1_fir_singlerate\32taps_8chn_32tdm_16bit\proj\src\sim_output_storage.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\1_fir_singlerate\32taps_8chn_32tdm_16bit\proj\src\spram.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\1_fir_singlerate\32taps_8chn_32tdm_16bit\proj\src\tb_gw5a.v
C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\1_fir_singlerate\32taps_8chn_32tdm_16bit\proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Dec 24 17:57:53 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module tb_gw5a
Synthesis Process Running parser:
    CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.685s, Peak memory usage = 629.586MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 629.586MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 629.586MB
    Optimizing Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.18s, Peak memory usage = 629.586MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 629.586MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 629.586MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 629.586MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 629.586MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 629.586MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 629.586MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 629.586MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 629.586MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.138s, Peak memory usage = 629.586MB
Generate output files:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.198s, Peak memory usage = 629.586MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 629.586MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 49
I/O Buf 49
    IBUF 5
    OBUF 44
Register 1823
    DFFRE 1
    DFFPE 118
    DFFCE 1704
LUT 1480
    LUT2 355
    LUT3 665
    LUT4 460
MUX 1
    MUX16 1
ALU 76
    ALU 76
INV 15
    INV 15
DSP
    MULTALU27X18 1
BSRAM 4
    SDPB 4
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1579(1503 LUT, 76 ALU) / 23040 7%
Register 1823 / 23685 8%
  --Register as Latch 0 / 23685 0%
  --Register as FF 1823 / 23685 8%
BSRAM 4 / 56 8%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 139.714(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.843
Data Arrival Time 7.469
Data Required Time 10.311
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s667
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_s48
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1607 clk_ibuf/O
0.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s667/CLK
0.757 0.382 tC2Q RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s667/Q
1.132 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1933/I0
1.659 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1933/F
2.034 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1829/I1
2.170 0.136 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1829/O
2.545 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1777/I1
2.631 0.086 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1777/O
3.006 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1751/I1
3.093 0.086 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1751/O
3.468 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1382/I1
3.554 0.086 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1382/O
3.929 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1700/I0
4.455 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1700/F
4.830 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1685/I0
5.356 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1685/F
5.731 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1642/I2
6.193 0.461 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1642/F
6.568 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_init_s10/I0
7.094 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_init_s10/F
7.469 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_s48/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1607 clk_ibuf/O
10.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_s48/CLK
10.311 -0.064 tSu 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_s48
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.961, 41.744%; route: 3.750, 52.864%; tC2Q: 0.382, 5.392%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 4.812
Data Arrival Time 5.499
Data Required Time 10.311
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1607 clk_ibuf/O
0.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
0.757 0.382 tC2Q RR 8 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
1.132 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n330_s2/I0
1.659 0.526 tINS RR 3 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n330_s2/F
2.034 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n328_s2/I2
2.495 0.461 tINS RR 3 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n328_s2/F
2.870 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n326_s2/I2
3.331 0.461 tINS RR 2 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n326_s2/F
3.706 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s3/I1
4.223 0.516 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s3/F
4.598 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s2/I0
5.124 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s2/F
5.499 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1607 clk_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.311 -0.064 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.491, 48.622%; route: 2.250, 43.913%; tC2Q: 0.382, 7.465%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 5.109
Data Arrival Time 5.202
Data Required Time 10.311
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_6_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1607 clk_ibuf/O
0.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/CLK
0.757 0.382 tC2Q RR 5 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/Q
1.132 0.375 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/I1
1.695 0.563 tINS RF 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/COUT
1.695 0.000 tNET FF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/CIN
1.745 0.050 tINS FR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/COUT
1.745 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/CIN
1.795 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/COUT
1.795 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/CIN
1.845 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/COUT
1.845 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/CIN
1.895 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/COUT
1.895 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/CIN
1.945 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/COUT
1.945 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/CIN
2.189 0.244 tINS RR 3 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/SUM
2.564 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/I0
3.090 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/F
3.465 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/I2
3.926 0.461 tINS RR 3 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/F
4.301 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n527_s0/I0
4.827 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n527_s0/F
5.202 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1607 clk_ibuf/O
10.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_6_s0/CLK
10.311 -0.064 tSu 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.570, 53.237%; route: 1.875, 38.840%; tC2Q: 0.382, 7.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 5.119
Data Arrival Time 5.192
Data Required Time 10.311
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_7_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1607 clk_ibuf/O
0.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/CLK
0.757 0.382 tC2Q RR 5 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/Q
1.132 0.375 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/I1
1.695 0.563 tINS RF 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/COUT
1.695 0.000 tNET FF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/CIN
1.745 0.050 tINS FR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/COUT
1.745 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/CIN
1.795 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/COUT
1.795 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/CIN
1.845 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/COUT
1.845 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/CIN
1.895 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/COUT
1.895 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/CIN
1.945 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/COUT
1.945 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/CIN
2.189 0.244 tINS RR 3 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/SUM
2.564 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/I0
3.090 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/F
3.465 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/I2
3.926 0.461 tINS RR 3 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/F
4.301 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s0/I1
4.817 0.516 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s0/F
5.192 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1607 clk_ibuf/O
10.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_7_s0/CLK
10.311 -0.064 tSu 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.560, 53.139%; route: 1.875, 38.921%; tC2Q: 0.382, 7.940%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 5.174
Data Arrival Time 5.137
Data Required Time 10.311
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_5_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1607 clk_ibuf/O
0.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/CLK
0.757 0.382 tC2Q RR 5 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/Q
1.132 0.375 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/I1
1.695 0.563 tINS RF 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/COUT
1.695 0.000 tNET FF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/CIN
1.745 0.050 tINS FR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/COUT
1.745 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/CIN
1.795 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/COUT
1.795 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/CIN
1.845 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/COUT
1.845 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/CIN
1.895 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/COUT
1.895 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/CIN
1.945 0.050 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/COUT
1.945 0.000 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/CIN
2.189 0.244 tINS RR 3 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/SUM
2.564 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/I0
3.090 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/F
3.465 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/I2
3.926 0.461 tINS RR 3 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/F
4.301 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n528_s0/I2
4.762 0.461 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/n528_s0/F
5.137 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1607 clk_ibuf/O
10.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_5_s0/CLK
10.311 -0.064 tSu 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.505, 52.599%; route: 1.875, 39.370%; tC2Q: 0.382, 8.031%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%