Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\2_fir_symmetry\33taps_3chn_4tdm_31bit\proj\src\advanced_fir_filter\advanced_fir_filter.v E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\2_fir_symmetry\33taps_3chn_4tdm_31bit\proj\src\sim_input_gen.v E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\2_fir_symmetry\33taps_3chn_4tdm_31bit\proj\src\sim_output_storage.v E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\2_fir_symmetry\33taps_3chn_4tdm_31bit\proj\src\spram.v E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\2_fir_symmetry\33taps_3chn_4tdm_31bit\proj\src\tb_gw5a.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\2_fir_symmetry\33taps_3chn_4tdm_31bit\proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Tue Dec 24 18:27:08 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | tb_gw5a |
Synthesis Process | Running parser: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 0.993s, Peak memory usage = 629.586MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.162s, Peak memory usage = 629.586MB Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 629.586MB Optimizing Phase 2: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.292s, Peak memory usage = 629.586MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 629.586MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 629.586MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 629.586MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 629.586MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 629.586MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 629.586MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 629.586MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 629.586MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.192s, Peak memory usage = 629.586MB Generate output files: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.375s, Peak memory usage = 629.586MB |
Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 629.586MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 79 |
I/O Buf | 79 |
    IBUF | 5 |
    OBUF | 74 |
Register | 3589 |
    DFFRE | 1 |
    DFFPE | 82 |
    DFFCE | 3506 |
LUT | 1961 |
    LUT2 | 100 |
    LUT3 | 1276 |
    LUT4 | 585 |
MUX | 1 |
    MUX16 | 1 |
ALU | 334 |
    ALU | 334 |
INV | 12 |
    INV | 12 |
DSP | |
    MULTALU27X18 | 5 |
BSRAM | 4 |
    SDPB | 4 |
Black Box | 1 |
    GW_JTAG | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2315(1981 LUT, 334 ALU) / 23040 | 11% |
Register | 3589 / 23685 | 16% |
  --Register as Latch | 0 / 23685 | 0% |
  --Register as FF | 3589 / 23685 | 16% |
BSRAM | 4 / 56 | 8% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.000(MHz) | 192.771(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.812 |
Data Arrival Time | 5.499 |
Data Required Time | 10.311 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
0.757 | 0.382 | tC2Q | RR | 9 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q |
1.132 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n410_s2/I0 |
1.659 | 0.526 | tINS | RR | 3 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n410_s2/F |
2.034 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n408_s2/I2 |
2.495 | 0.461 | tINS | RR | 3 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n408_s2/F |
2.870 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n406_s2/I2 |
3.331 | 0.461 | tINS | RR | 2 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n406_s2/F |
3.706 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s3/I1 |
4.223 | 0.516 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s3/F |
4.598 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s2/I0 |
5.124 | 0.526 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s2/F |
5.499 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
10.311 | -0.064 | tSu | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.491, 48.622%; route: 2.250, 43.913%; tC2Q: 0.382, 7.465% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 4.946 |
Data Arrival Time | 5.365 |
Data Required Time | 10.311 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
0.757 | 0.382 | tC2Q | RR | 14 | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q |
1.132 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I1 |
1.649 | 0.516 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F |
2.024 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/I0 |
2.550 | 0.526 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s16/F |
2.925 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/I3 |
3.187 | 0.262 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/F |
3.562 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s11/I0 |
4.089 | 0.526 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s11/F |
4.464 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I0 |
4.990 | 0.526 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F |
5.365 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK |
10.311 | -0.064 | tSu | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.358, 47.245%; route: 2.250, 45.090%; tC2Q: 0.382, 7.665% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 5.336 |
Data Arrival Time | 4.727 |
Data Required Time | 10.064 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
0.757 | 0.382 | tC2Q | RR | 7 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q |
1.132 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s8/I0 |
1.659 | 0.526 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s8/F |
2.034 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s5/I1 |
2.550 | 0.516 | tINS | RR | 2 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s5/F |
2.925 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s4/I0 |
3.451 | 0.526 | tINS | RR | 10 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s4/F |
3.826 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
4.352 | 0.526 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
4.727 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
10.064 | -0.311 | tSu | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 5.396 |
Data Arrival Time | 4.915 |
Data Required Time | 10.311 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/acc_out_0_s1 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/acc_out_35_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/acc_out_0_s1/CLK |
0.757 | 0.382 | tC2Q | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/acc_out_0_s1/Q |
1.132 | 0.375 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2716_s/I1 |
1.695 | 0.563 | tINS | RF | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2716_s/COUT |
1.695 | 0.000 | tNET | FF | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2715_s/CIN |
1.745 | 0.050 | tINS | FR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2715_s/COUT |
1.745 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2714_s/CIN |
1.795 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2714_s/COUT |
1.795 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2713_s/CIN |
1.845 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2713_s/COUT |
1.845 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2712_s/CIN |
1.895 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2712_s/COUT |
1.895 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2711_s/CIN |
1.945 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2711_s/COUT |
1.945 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2710_s/CIN |
1.995 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2710_s/COUT |
1.995 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2709_s/CIN |
2.045 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2709_s/COUT |
2.045 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2708_s/CIN |
2.095 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2708_s/COUT |
2.095 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2707_s/CIN |
2.145 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2707_s/COUT |
2.145 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2706_s/CIN |
2.195 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2706_s/COUT |
2.195 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2705_s/CIN |
2.245 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2705_s/COUT |
2.245 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2704_s/CIN |
2.295 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2704_s/COUT |
2.295 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2703_s/CIN |
2.345 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2703_s/COUT |
2.345 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2702_s/CIN |
2.395 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2702_s/COUT |
2.395 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2701_s/CIN |
2.445 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2701_s/COUT |
2.445 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2700_s/CIN |
2.495 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2700_s/COUT |
2.495 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2699_s/CIN |
2.545 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2699_s/COUT |
2.545 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2698_s/CIN |
2.595 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2698_s/COUT |
2.595 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2697_s/CIN |
2.645 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2697_s/COUT |
2.645 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2696_s/CIN |
2.695 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2696_s/COUT |
2.695 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2695_s/CIN |
2.745 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2695_s/COUT |
2.745 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2694_s/CIN |
2.795 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2694_s/COUT |
2.795 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2693_s/CIN |
2.845 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2693_s/COUT |
2.845 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2692_s/CIN |
2.895 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2692_s/COUT |
2.895 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2691_s/CIN |
2.945 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2691_s/COUT |
2.945 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2690_s/CIN |
2.995 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2690_s/COUT |
2.995 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2689_s/CIN |
3.045 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2689_s/COUT |
3.045 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2688_s/CIN |
3.095 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2688_s/COUT |
3.095 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2687_s/CIN |
3.145 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2687_s/COUT |
3.145 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2686_s/CIN |
3.195 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2686_s/COUT |
3.195 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2685_s/CIN |
3.245 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2685_s/COUT |
3.245 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2684_s/CIN |
3.295 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2684_s/COUT |
3.295 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2683_s/CIN |
3.345 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2683_s/COUT |
3.345 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2682_s/CIN |
3.395 | 0.050 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2682_s/COUT |
3.395 | 0.000 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2681_s/CIN |
3.639 | 0.244 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2681_s/SUM |
4.014 | 0.375 | tNET | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2717_s1/I0 |
4.540 | 0.526 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2717_s1/F |
4.915 | 0.375 | tNET | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/acc_out_35_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/acc_out_35_s1/CLK |
10.311 | -0.064 | tSu | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/acc_out_35_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 3.032, 66.795%; route: 1.125, 24.780%; tC2Q: 0.382, 8.425% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 5.439 |
Data Arrival Time | 4.872 |
Data Required Time | 10.311 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/ram_shift_addrb_max_2_s1 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/ram_shift_addrb_precal_4_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/ram_shift_addrb_max_2_s1/CLK |
0.757 | 0.382 | tC2Q | RR | 6 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/ram_shift_addrb_max_2_s1/Q |
1.132 | 0.375 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n554_s/I0 |
1.864 | 0.731 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n554_s/SUM |
2.239 | 0.375 | tNET | RR | 2 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n554_s2/I0 |
2.795 | 0.556 | tINS | RF | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n554_s2/COUT |
3.145 | 0.350 | tNET | FF | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n557_s4/I2 |
3.606 | 0.461 | tINS | FR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n557_s4/F |
3.981 | 0.375 | tNET | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n557_s2/I1 |
4.497 | 0.516 | tINS | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n557_s2/F |
4.872 | 0.375 | tNET | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/ram_shift_addrb_precal_4_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 3343 | clk_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/ram_shift_addrb_precal_4_s0/CLK |
10.311 | -0.064 | tSu | 1 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/ram_shift_addrb_precal_4_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 2.265, 50.361%; route: 1.850, 41.134%; tC2Q: 0.382, 8.505% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |