Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\4_fir_interpolator\68taps_2chn_2tdm_34factor_31bit\proj\impl\gwsynthesis\fir_proj.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\4_fir_interpolator\68taps_2chn_2tdm_34factor_31bit\proj\src\fir_proj.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\4_fir_interpolator\68taps_2chn_2tdm_34factor_31bit\proj\src\fir_proj.sdc |
Tool Version | V1.9.11 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Dec 25 10:49:08 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C ES |
Hold Delay Model | Fast 0.945V 85C ES |
Numbers of Paths Analyzed | 6281 |
Numbers of Endpoints Analyzed | 6964 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk | ||
2 | tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.000(MHz) | 123.830(MHz) | 6 | TOP |
2 | tck_pad_i | 20.000(MHz) | 150.002(MHz) | 6 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.924 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0/D | clk:[R] | clk:[R] | 10.000 | -0.009 | 8.021 |
2 | 2.029 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0/D | clk:[R] | clk:[R] | 10.000 | -0.009 | 7.916 |
3 | 2.156 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_1_s0/D | clk:[R] | clk:[R] | 10.000 | -0.009 | 7.790 |
4 | 2.223 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0/D | clk:[R] | clk:[R] | 10.000 | -0.009 | 7.722 |
5 | 2.268 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_0_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.031 | 7.453 |
6 | 2.329 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0/D | clk:[R] | clk:[R] | 10.000 | -0.017 | 7.624 |
7 | 2.351 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0/D | clk:[R] | clk:[R] | 10.000 | -0.026 | 7.611 |
8 | 2.394 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_7_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.039 | 7.334 |
9 | 2.394 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_4_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.039 | 7.334 |
10 | 2.448 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_10_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.011 | 7.230 |
11 | 2.548 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_0_s0/D | clk:[R] | clk:[R] | 10.000 | -0.009 | 7.397 |
12 | 2.655 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[59]_7_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.016 | 7.050 |
13 | 2.758 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_1_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.031 | 6.963 |
14 | 2.758 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_0_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.031 | 6.963 |
15 | 2.787 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_1_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.041 | 6.943 |
16 | 2.787 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_0_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.041 | 6.943 |
17 | 2.816 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_0_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.041 | 6.914 |
18 | 2.816 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_3_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.041 | 6.914 |
19 | 2.831 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_5_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.041 | 6.899 |
20 | 2.840 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_7_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.001 | 6.850 |
21 | 2.852 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_9_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.046 | 6.883 |
22 | 2.879 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_0_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.048 | 6.858 |
23 | 2.879 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_1_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.048 | 6.858 |
24 | 2.879 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_9_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.048 | 6.858 |
25 | 2.975 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_2_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.001 | 6.715 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.166 | sim_output_storage_inst/ram_dout_addrb_5_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[10] | clk:[R] | clk:[R] | 0.000 | -0.010 | 0.211 |
2 | 0.193 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3] | clk:[R] | clk:[R] | 0.000 | -0.005 | 0.235 |
3 | 0.193 | sim_output_storage_inst/ram_din_data_0_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/DI[0] | clk:[R] | clk:[R] | 0.000 | -0.005 | 0.235 |
4 | 0.207 | sim_output_storage_inst/ram_din_addra_8_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[13] | clk:[R] | clk:[R] | 0.000 | -0.009 | 0.253 |
5 | 0.212 | sim_output_storage_inst/ram_din_addra_0_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[5] | clk:[R] | clk:[R] | 0.000 | -0.018 | 0.267 |
6 | 0.217 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_6_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/AD[10] | clk:[R] | clk:[R] | 0.000 | 0.009 | 0.243 |
7 | 0.226 | sim_output_storage_inst/ram_dout_addrb_3_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[8] | clk:[R] | clk:[R] | 0.000 | -0.010 | 0.271 |
8 | 0.253 | sim_output_storage_inst/ram_din_addra_3_s0/Q | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/ADA[8] | clk:[R] | clk:[R] | 0.000 | -0.018 | 0.308 |
9 | 0.256 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_1_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/AD[5] | clk:[R] | clk:[R] | 0.000 | 0.005 | 0.286 |
10 | 0.257 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] | clk:[R] | clk:[R] | 0.000 | 0.009 | 0.285 |
11 | 0.260 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/AD[6] | clk:[R] | clk:[R] | 0.000 | 0.005 | 0.290 |
12 | 0.262 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[13] | clk:[R] | clk:[R] | 0.000 | 0.011 | 0.288 |
13 | 0.264 | sim_output_storage_inst/ram_din_addra_7_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[12] | clk:[R] | clk:[R] | 0.000 | -0.018 | 0.319 |
14 | 0.271 | sim_output_storage_inst/ram_din_data_21_s0/Q | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/DI[5] | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.307 |
15 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[11] | clk:[R] | clk:[R] | 0.000 | 0.015 | 0.297 |
16 | 0.275 | sim_output_storage_inst/cnt_chn_0_s0/Q | sim_output_storage_inst/cnt_chn_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
17 | 0.275 | sim_output_storage_inst/ram_din_addra_6_s0/Q | sim_output_storage_inst/ram_din_addra_6_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
18 | 0.275 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/ram_data_addra_0_s4/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/ram_data_addra_0_s4/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
19 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
20 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
21 | 0.275 | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
22 | 0.275 | gw_gao_inst_0/u_la0_top/word_count_5_s0/Q | gw_gao_inst_0/u_la0_top/word_count_5_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
23 | 0.275 | gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q | gw_gao_inst_0/u_la0_top/address_counter_3_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
24 | 0.277 | sim_output_storage_inst/ram_dout_addrb_6_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[11] | clk:[R] | clk:[R] | 0.000 | -0.005 | 0.317 |
25 | 0.278 | gw_gao_inst_0/u_la0_top/word_count_2_s0/Q | gw_gao_inst_0/u_la0_top/word_count_2_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.303 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 2.962 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.040 | 1.731 |
2 | 2.962 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.040 | 1.731 |
3 | 2.962 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.040 | 1.731 |
4 | 2.973 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.043 | 1.723 |
5 | 3.127 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.040 | 1.566 |
6 | 3.127 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.040 | 1.566 |
7 | 3.319 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.022 | 1.355 |
8 | 3.319 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.022 | 1.355 |
9 | 3.319 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.022 | 1.355 |
10 | 3.319 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.022 | 1.355 |
11 | 3.322 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.024 | 1.355 |
12 | 3.322 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.024 | 1.355 |
13 | 3.338 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk:[F] | clk:[R] | 5.000 | -0.031 | 1.345 |
14 | 3.338 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.031 | 1.345 |
15 | 3.338 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.031 | 1.345 |
16 | 3.341 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.033 | 1.345 |
17 | 3.341 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.033 | 1.345 |
18 | 3.741 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.024 | 0.935 |
19 | 3.741 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.024 | 0.935 |
20 | 3.741 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.024 | 0.935 |
21 | 3.756 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.031 | 0.928 |
22 | 3.756 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.031 | 0.928 |
23 | 3.768 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.038 | 0.922 |
24 | 3.768 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.038 | 0.922 |
25 | 3.768 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.038 | 0.922 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 5.347 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.016 | 0.310 |
2 | 5.347 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.016 | 0.310 |
3 | 5.352 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | clk:[F] | clk:[R] | -5.000 | -0.011 | 0.310 |
4 | 5.358 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.022 | 0.327 |
5 | 5.358 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.022 | 0.327 |
6 | 5.358 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.022 | 0.327 |
7 | 5.419 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.361 |
8 | 5.419 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.361 |
9 | 5.419 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.361 |
10 | 5.419 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.361 |
11 | 5.419 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.361 |
12 | 5.423 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.009 | 0.361 |
13 | 5.423 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.009 | 0.361 |
14 | 5.423 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.009 | 0.361 |
15 | 5.423 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.009 | 0.361 |
16 | 5.430 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.376 |
17 | 5.430 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.376 |
18 | 5.430 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.376 |
19 | 5.430 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.376 |
20 | 5.430 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.376 |
21 | 5.430 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.376 |
22 | 5.430 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.376 |
23 | 5.445 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.016 | 0.408 |
24 | 5.445 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.016 | 0.408 |
25 | 5.447 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.025 | 0.419 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.751 | 3.751 | 1.000 | Low Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
2 | 2.751 | 3.751 | 1.000 | Low Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
3 | 2.757 | 3.757 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
4 | 2.757 | 3.757 | 1.000 | Low Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
5 | 2.757 | 3.757 | 1.000 | Low Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
6 | 2.757 | 3.757 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
7 | 2.759 | 3.759 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1 |
8 | 2.762 | 3.762 | 1.000 | High Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
9 | 2.762 | 3.762 | 1.000 | High Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
10 | 2.762 | 3.762 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.924 |
Data Arrival Time | 10.640 |
Data Required Time | 12.565 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 2 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q |
3.352 | 0.350 | tNET | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0 |
3.878 | 0.526 | tINS | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F |
4.278 | 0.400 | tNET | RR | 24 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0] |
8.497 | 4.219 | tINS | RF | 2 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[0] |
8.867 | 0.370 | tNET | FF | 2 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/I0 |
9.429 | 0.563 | tINS | FF | 1 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/COUT |
9.429 | 0.000 | tNET | FF | 2 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/CIN |
9.479 | 0.050 | tINS | FR | 1 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/COUT |
9.479 | 0.000 | tNET | RR | 2 | R25C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/CIN |
9.529 | 0.050 | tINS | RR | 1 | R25C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/COUT |
9.529 | 0.000 | tNET | RR | 2 | R25C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/CIN |
9.579 | 0.050 | tINS | RR | 1 | R25C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/COUT |
9.579 | 0.000 | tNET | RR | 2 | R25C40[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n843_s/CIN |
9.629 | 0.050 | tINS | RR | 1 | R25C40[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n843_s/COUT |
9.629 | 0.000 | tNET | RR | 2 | R25C40[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n842_s/CIN |
9.930 | 0.301 | tINS | RF | 1 | R25C40[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n842_s/SUM |
10.119 | 0.189 | tNET | FF | 1 | R26C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n849_s0/I1 |
10.640 | 0.521 | tINS | FR | 1 | R26C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n849_s0/F |
10.640 | 0.000 | tNET | RR | 1 | R26C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R26C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0/CLK |
12.565 | -0.064 | tSu | 1 | R26C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 26.059%; route: 1.937, 73.941% |
Arrival Data Path Delay | cell: 6.330, 78.915%; route: 1.309, 16.316%; tC2Q: 0.382, 4.769% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path2
Path Summary:
Slack | 2.029 |
Data Arrival Time | 10.535 |
Data Required Time | 12.565 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 2 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q |
3.352 | 0.350 | tNET | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0 |
3.878 | 0.526 | tINS | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F |
4.278 | 0.400 | tNET | RR | 24 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0] |
8.497 | 4.219 | tINS | RF | 2 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[0] |
8.867 | 0.370 | tNET | FF | 2 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/I0 |
9.429 | 0.563 | tINS | FF | 1 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/COUT |
9.429 | 0.000 | tNET | FF | 2 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/CIN |
9.479 | 0.050 | tINS | FR | 1 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/COUT |
9.479 | 0.000 | tNET | RR | 2 | R25C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/CIN |
9.529 | 0.050 | tINS | RR | 1 | R25C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/COUT |
9.529 | 0.000 | tNET | RR | 2 | R25C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/CIN |
9.830 | 0.301 | tINS | RF | 1 | R25C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/SUM |
10.019 | 0.189 | tNET | FF | 1 | R26C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n851_s0/I1 |
10.535 | 0.516 | tINS | FR | 1 | R26C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n851_s0/F |
10.535 | 0.000 | tNET | RR | 1 | R26C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R26C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0/CLK |
12.565 | -0.064 | tSu | 1 | R26C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 26.059%; route: 1.937, 73.941% |
Arrival Data Path Delay | cell: 6.225, 78.636%; route: 1.309, 16.533%; tC2Q: 0.382, 4.832% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path3
Path Summary:
Slack | 2.156 |
Data Arrival Time | 10.409 |
Data Required Time | 12.565 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 2 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q |
3.352 | 0.350 | tNET | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0 |
3.878 | 0.526 | tINS | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F |
4.278 | 0.400 | tNET | RR | 24 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0] |
8.497 | 4.219 | tINS | RF | 2 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[0] |
8.867 | 0.370 | tNET | FF | 2 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/I0 |
9.429 | 0.563 | tINS | FF | 1 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/COUT |
9.429 | 0.000 | tNET | FF | 2 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/CIN |
9.725 | 0.296 | tINS | FR | 1 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/SUM |
9.883 | 0.157 | tNET | RR | 1 | R26C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n853_s0/I1 |
10.409 | 0.526 | tINS | RR | 1 | R26C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n853_s0/F |
10.409 | 0.000 | tNET | RR | 1 | R26C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R26C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_1_s0/CLK |
12.565 | -0.064 | tSu | 1 | R26C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_1_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 26.059%; route: 1.937, 73.941% |
Arrival Data Path Delay | cell: 6.130, 78.691%; route: 1.278, 16.399%; tC2Q: 0.382, 4.910% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path4
Path Summary:
Slack | 2.223 |
Data Arrival Time | 10.342 |
Data Required Time | 12.565 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 2 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q |
3.352 | 0.350 | tNET | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0 |
3.878 | 0.526 | tINS | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F |
4.278 | 0.400 | tNET | RR | 24 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0] |
8.497 | 4.219 | tINS | RF | 2 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[0] |
8.867 | 0.370 | tNET | FF | 2 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/I0 |
9.429 | 0.563 | tINS | FF | 1 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/COUT |
9.429 | 0.000 | tNET | FF | 2 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/CIN |
9.479 | 0.050 | tINS | FR | 1 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/COUT |
9.479 | 0.000 | tNET | RR | 2 | R25C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/CIN |
9.723 | 0.244 | tINS | RR | 1 | R25C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/SUM |
9.880 | 0.157 | tNET | RR | 1 | R26C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n852_s0/I1 |
10.342 | 0.461 | tINS | RR | 1 | R26C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n852_s0/F |
10.342 | 0.000 | tNET | RR | 1 | R26C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R26C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0/CLK |
12.565 | -0.064 | tSu | 1 | R26C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 26.059%; route: 1.937, 73.941% |
Arrival Data Path Delay | cell: 6.062, 78.504%; route: 1.278, 16.543%; tC2Q: 0.382, 4.953% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path5
Path Summary:
Slack | 2.268 |
Data Arrival Time | 10.059 |
Data Required Time | 12.327 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/I3 |
5.343 | 0.461 | tINS | RR | 9 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/F |
7.262 | 1.919 | tNET | RR | 1 | R5C36[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5307_s0/I0 |
7.778 | 0.516 | tINS | RR | 16 | R5C36[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5307_s0/F |
10.059 | 2.281 | tNET | RR | 1 | R24C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.638 | 1.956 | tNET | RR | 1 | R24C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_0_s0/CLK |
12.327 | -0.311 | tSu | 1 | R24C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_0_s0 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.392, 18.685%; route: 5.678, 76.182%; tC2Q: 0.382, 5.133% |
Required Clock Path Delay | cell: 0.683, 25.871%; route: 1.956, 74.129% |
Path6
Path Summary:
Slack | 2.329 |
Data Arrival Time | 10.243 |
Data Required Time | 12.572 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 2 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q |
3.352 | 0.350 | tNET | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0 |
3.878 | 0.526 | tINS | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F |
4.278 | 0.400 | tNET | RR | 24 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0] |
8.497 | 4.219 | tINS | RF | 2 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[0] |
8.867 | 0.370 | tNET | FF | 2 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/I0 |
9.429 | 0.563 | tINS | FF | 1 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/COUT |
9.429 | 0.000 | tNET | FF | 2 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/CIN |
9.479 | 0.050 | tINS | FR | 1 | R25C40[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n846_s/COUT |
9.479 | 0.000 | tNET | RR | 2 | R25C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/CIN |
9.529 | 0.050 | tINS | RR | 1 | R25C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/COUT |
9.529 | 0.000 | tNET | RR | 2 | R25C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/CIN |
9.579 | 0.050 | tINS | RR | 1 | R25C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/COUT |
9.579 | 0.000 | tNET | RR | 2 | R25C40[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n843_s/CIN |
9.823 | 0.244 | tINS | RF | 1 | R25C40[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n843_s/SUM |
9.828 | 0.005 | tNET | FF | 1 | R25C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n850_s0/I1 |
10.243 | 0.415 | tINS | FR | 1 | R25C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n850_s0/F |
10.243 | 0.000 | tNET | RR | 1 | R25C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.636 | 1.953 | tNET | RR | 1 | R25C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0/CLK |
12.572 | -0.064 | tSu | 1 | R25C40[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0 |
Path Statistics:
Clock Skew | 0.017 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 26.059%; route: 1.937, 73.941% |
Arrival Data Path Delay | cell: 6.116, 80.226%; route: 1.125, 14.757%; tC2Q: 0.382, 5.017% |
Required Clock Path Delay | cell: 0.683, 25.895%; route: 1.953, 74.105% |
Path7
Path Summary:
Slack | 2.351 |
Data Arrival Time | 10.230 |
Data Required Time | 12.581 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 2 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q |
3.352 | 0.350 | tNET | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0 |
3.878 | 0.526 | tINS | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F |
4.278 | 0.400 | tNET | RR | 24 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0] |
8.494 | 4.216 | tINS | RR | 2 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[6] |
9.235 | 0.741 | tNET | RR | 2 | R25C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n841_s/I0 |
9.965 | 0.730 | tINS | RR | 1 | R25C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n841_s/SUM |
9.967 | 0.003 | tNET | RR | 1 | R25C41[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n848_s0/I1 |
10.230 | 0.262 | tINS | RR | 1 | R25C41[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n848_s0/F |
10.230 | 0.000 | tNET | RR | 1 | R25C41[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.645 | 1.962 | tNET | RR | 1 | R25C41[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0/CLK |
12.581 | -0.064 | tSu | 1 | R25C41[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0 |
Path Statistics:
Clock Skew | 0.026 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 26.059%; route: 1.937, 73.941% |
Arrival Data Path Delay | cell: 5.735, 75.348%; route: 1.494, 19.627%; tC2Q: 0.382, 5.026% |
Required Clock Path Delay | cell: 0.683, 25.803%; route: 1.962, 74.197% |
Path8
Path Summary:
Slack | 2.394 |
Data Arrival Time | 9.941 |
Data Required Time | 12.334 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_7_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.136 | 0.839 | tNET | RR | 1 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/I0 |
6.597 | 0.461 | tINS | RR | 16 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/F |
9.941 | 3.344 | tNET | RR | 1 | R21C32[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.646 | 1.963 | tNET | RR | 1 | R21C32[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_7_s0/CLK |
12.334 | -0.311 | tSu | 1 | R21C32[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_7_s0 |
Path Statistics:
Clock Skew | 0.039 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.291, 17.607%; route: 5.660, 77.177%; tC2Q: 0.382, 5.216% |
Required Clock Path Delay | cell: 0.683, 25.797%; route: 1.963, 74.203% |
Path9
Path Summary:
Slack | 2.394 |
Data Arrival Time | 9.941 |
Data Required Time | 12.334 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.136 | 0.839 | tNET | RR | 1 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/I0 |
6.597 | 0.461 | tINS | RR | 16 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/F |
9.941 | 3.344 | tNET | RR | 1 | R21C32[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.646 | 1.963 | tNET | RR | 1 | R21C32[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_4_s0/CLK |
12.334 | -0.311 | tSu | 1 | R21C32[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_4_s0 |
Path Statistics:
Clock Skew | 0.039 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.291, 17.607%; route: 5.660, 77.177%; tC2Q: 0.382, 5.216% |
Required Clock Path Delay | cell: 0.683, 25.797%; route: 1.963, 74.203% |
Path10
Path Summary:
Slack | 2.448 |
Data Arrival Time | 9.837 |
Data Required Time | 12.285 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_10_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.903 | 1.606 | tNET | RR | 1 | R5C42[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4907_s0/I0 |
7.424 | 0.521 | tINS | RR | 16 | R5C42[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4907_s0/F |
9.837 | 2.412 | tNET | RR | 1 | R13C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.596 | 1.914 | tNET | RR | 1 | R13C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_10_s0/CLK |
12.285 | -0.311 | tSu | 1 | R13C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_10_s0 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.351, 18.689%; route: 5.496, 76.020%; tC2Q: 0.382, 5.290% |
Required Clock Path Delay | cell: 0.683, 26.288%; route: 1.914, 73.712% |
Path11
Path Summary:
Slack | 2.548 |
Data Arrival Time | 10.017 |
Data Required Time | 12.565 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.619 | 1.937 | tNET | RR | 1 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK |
3.002 | 0.382 | tC2Q | RR | 2 | R26C39[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q |
3.352 | 0.350 | tNET | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0 |
3.878 | 0.526 | tINS | RR | 1 | R25C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F |
4.278 | 0.400 | tNET | RR | 24 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0] |
8.497 | 4.219 | tINS | RF | 2 | DSP_R19[12][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[0] |
8.867 | 0.370 | tNET | FF | 2 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/I0 |
9.597 | 0.730 | tINS | FR | 1 | R25C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n847_s/SUM |
9.754 | 0.157 | tNET | RR | 1 | R26C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n854_s0/I1 |
10.017 | 0.262 | tINS | RR | 1 | R26C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n854_s0/F |
10.017 | 0.000 | tNET | RR | 1 | R26C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R26C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_0_s0/CLK |
12.565 | -0.064 | tSu | 1 | R26C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_0_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 26.059%; route: 1.937, 73.941% |
Arrival Data Path Delay | cell: 5.737, 77.560%; route: 1.278, 17.269%; tC2Q: 0.382, 5.171% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path12
Path Summary:
Slack | 2.655 |
Data Arrival Time | 9.657 |
Data Required Time | 12.312 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[59]_7_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/I3 |
5.343 | 0.461 | tINS | RR | 9 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/F |
7.262 | 1.919 | tNET | RR | 1 | R5C36[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5563_s0/I0 |
7.778 | 0.516 | tINS | RR | 16 | R5C36[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5563_s0/F |
9.657 | 1.879 | tNET | RR | 1 | R18C33[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[59]_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.623 | 1.941 | tNET | RR | 1 | R18C33[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[59]_7_s0/CLK |
12.312 | -0.311 | tSu | 1 | R18C33[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[59]_7_s0 |
Path Statistics:
Clock Skew | 0.016 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.392, 19.752%; route: 5.275, 74.823%; tC2Q: 0.382, 5.426% |
Required Clock Path Delay | cell: 0.683, 26.019%; route: 1.941, 73.981% |
Path13
Path Summary:
Slack | 2.758 |
Data Arrival Time | 9.569 |
Data Required Time | 12.327 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4715_s1/I3 |
5.343 | 0.461 | tINS | RR | 8 | R21C43[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4715_s1/F |
6.451 | 1.107 | tNET | RR | 1 | R7C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5483_s0/I0 |
6.967 | 0.516 | tINS | RR | 16 | R7C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5483_s0/F |
9.569 | 2.602 | tNET | RR | 1 | R24C36[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.638 | 1.956 | tNET | RR | 1 | R24C36[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_1_s0/CLK |
12.327 | -0.311 | tSu | 1 | R24C36[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_1_s0 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.392, 20.000%; route: 5.188, 74.506%; tC2Q: 0.382, 5.494% |
Required Clock Path Delay | cell: 0.683, 25.871%; route: 1.956, 74.129% |
Path14
Path Summary:
Slack | 2.758 |
Data Arrival Time | 9.569 |
Data Required Time | 12.327 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4715_s1/I3 |
5.343 | 0.461 | tINS | RR | 8 | R21C43[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4715_s1/F |
6.451 | 1.107 | tNET | RR | 1 | R7C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5483_s0/I0 |
6.967 | 0.516 | tINS | RR | 16 | R7C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5483_s0/F |
9.569 | 2.602 | tNET | RR | 1 | R24C36[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.638 | 1.956 | tNET | RR | 1 | R24C36[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_0_s0/CLK |
12.327 | -0.311 | tSu | 1 | R24C36[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[54]_0_s0 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.392, 20.000%; route: 5.188, 74.506%; tC2Q: 0.382, 5.494% |
Required Clock Path Delay | cell: 0.683, 25.871%; route: 1.956, 74.129% |
Path15
Path Summary:
Slack | 2.787 |
Data Arrival Time | 9.549 |
Data Required Time | 12.336 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/I3 |
5.343 | 0.461 | tINS | RR | 9 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/F |
7.449 | 2.106 | tNET | RR | 1 | R7C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5435_s0/I0 |
7.714 | 0.265 | tINS | RR | 16 | R7C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5435_s0/F |
9.549 | 1.835 | tNET | RR | 1 | R24C37[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.648 | 1.965 | tNET | RR | 1 | R24C37[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_1_s0/CLK |
12.336 | -0.311 | tSu | 1 | R24C37[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_1_s0 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.141, 16.439%; route: 5.419, 78.052%; tC2Q: 0.382, 5.510% |
Required Clock Path Delay | cell: 0.683, 25.779%; route: 1.965, 74.221% |
Path16
Path Summary:
Slack | 2.787 |
Data Arrival Time | 9.549 |
Data Required Time | 12.336 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/I3 |
5.343 | 0.461 | tINS | RR | 9 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/F |
7.449 | 2.106 | tNET | RR | 1 | R7C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5435_s0/I0 |
7.714 | 0.265 | tINS | RR | 16 | R7C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5435_s0/F |
9.549 | 1.835 | tNET | RR | 1 | R24C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.648 | 1.965 | tNET | RR | 1 | R24C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_0_s0/CLK |
12.336 | -0.311 | tSu | 1 | R24C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[51]_0_s0 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.141, 16.439%; route: 5.419, 78.052%; tC2Q: 0.382, 5.510% |
Required Clock Path Delay | cell: 0.683, 25.779%; route: 1.965, 74.221% |
Path17
Path Summary:
Slack | 2.816 |
Data Arrival Time | 9.521 |
Data Required Time | 12.336 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.903 | 1.606 | tNET | RR | 1 | R5C42[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4907_s0/I0 |
7.424 | 0.521 | tINS | RR | 16 | R5C42[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4907_s0/F |
9.521 | 2.096 | tNET | RR | 1 | R24C49[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.648 | 1.965 | tNET | RR | 1 | R24C49[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_0_s0/CLK |
12.336 | -0.311 | tSu | 1 | R24C49[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_0_s0 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.351, 19.544%; route: 5.180, 74.923%; tC2Q: 0.382, 5.532% |
Required Clock Path Delay | cell: 0.683, 25.779%; route: 1.965, 74.221% |
Path18
Path Summary:
Slack | 2.816 |
Data Arrival Time | 9.521 |
Data Required Time | 12.336 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.903 | 1.606 | tNET | RR | 1 | R5C42[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4907_s0/I0 |
7.424 | 0.521 | tINS | RR | 16 | R5C42[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4907_s0/F |
9.521 | 2.096 | tNET | RR | 1 | R24C49[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.648 | 1.965 | tNET | RR | 1 | R24C49[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_3_s0/CLK |
12.336 | -0.311 | tSu | 1 | R24C49[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_3_s0 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.351, 19.544%; route: 5.180, 74.923%; tC2Q: 0.382, 5.532% |
Required Clock Path Delay | cell: 0.683, 25.779%; route: 1.965, 74.221% |
Path19
Path Summary:
Slack | 2.831 |
Data Arrival Time | 9.506 |
Data Required Time | 12.337 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_5_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.136 | 0.839 | tNET | RR | 1 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/I0 |
6.597 | 0.461 | tINS | RR | 16 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/F |
9.506 | 2.909 | tNET | RR | 1 | R20C36[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_5_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.648 | 1.966 | tNET | RR | 1 | R20C36[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_5_s0/CLK |
12.337 | -0.311 | tSu | 1 | R20C36[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_5_s0 |
Path Statistics:
Clock Skew | 0.041 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.291, 18.717%; route: 5.225, 75.738%; tC2Q: 0.382, 5.544% |
Required Clock Path Delay | cell: 0.683, 25.773%; route: 1.966, 74.227% |
Path20
Path Summary:
Slack | 2.840 |
Data Arrival Time | 9.457 |
Data Required Time | 12.297 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_7_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.903 | 1.606 | tNET | RR | 1 | R5C42[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4907_s0/I0 |
7.424 | 0.521 | tINS | RR | 16 | R5C42[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4907_s0/F |
9.457 | 2.033 | tNET | RR | 1 | R15C48[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.608 | 1.926 | tNET | RR | 1 | R15C48[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_7_s0/CLK |
12.297 | -0.311 | tSu | 1 | R15C48[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[18]_7_s0 |
Path Statistics:
Clock Skew | 0.001 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.351, 19.726%; route: 5.116, 74.690%; tC2Q: 0.382, 5.584% |
Required Clock Path Delay | cell: 0.683, 26.168%; route: 1.926, 73.832% |
Path21
Path Summary:
Slack | 2.852 |
Data Arrival Time | 9.489 |
Data Required Time | 12.341 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_9_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/I3 |
5.343 | 0.461 | tINS | RR | 9 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/F |
7.262 | 1.919 | tNET | RR | 1 | R5C36[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5307_s0/I0 |
7.778 | 0.516 | tINS | RR | 16 | R5C36[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5307_s0/F |
9.489 | 1.711 | tNET | RR | 1 | R22C41[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_9_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.653 | 1.970 | tNET | RR | 1 | R22C41[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_9_s0/CLK |
12.341 | -0.311 | tSu | 1 | R22C41[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_9_s0 |
Path Statistics:
Clock Skew | 0.046 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.392, 20.232%; route: 5.108, 74.210%; tC2Q: 0.382, 5.558% |
Required Clock Path Delay | cell: 0.683, 25.730%; route: 1.970, 74.270% |
Path22
Path Summary:
Slack | 2.879 |
Data Arrival Time | 9.464 |
Data Required Time | 12.344 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.136 | 0.839 | tNET | RR | 1 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/I0 |
6.597 | 0.461 | tINS | RR | 16 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/F |
9.464 | 2.868 | tNET | RR | 1 | R21C37[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.655 | 1.972 | tNET | RR | 1 | R21C37[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_0_s0/CLK |
12.344 | -0.311 | tSu | 1 | R21C37[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_0_s0 |
Path Statistics:
Clock Skew | 0.048 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.291, 18.830%; route: 5.184, 75.592%; tC2Q: 0.382, 5.578% |
Required Clock Path Delay | cell: 0.683, 25.706%; route: 1.972, 74.294% |
Path23
Path Summary:
Slack | 2.879 |
Data Arrival Time | 9.464 |
Data Required Time | 12.344 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.136 | 0.839 | tNET | RR | 1 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/I0 |
6.597 | 0.461 | tINS | RR | 16 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/F |
9.464 | 2.868 | tNET | RR | 1 | R21C37[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.655 | 1.972 | tNET | RR | 1 | R21C37[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_1_s0/CLK |
12.344 | -0.311 | tSu | 1 | R21C37[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_1_s0 |
Path Statistics:
Clock Skew | 0.048 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.291, 18.830%; route: 5.184, 75.592%; tC2Q: 0.382, 5.578% |
Required Clock Path Delay | cell: 0.683, 25.706%; route: 1.972, 74.294% |
Path24
Path Summary:
Slack | 2.879 |
Data Arrival Time | 9.464 |
Data Required Time | 12.344 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_9_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/I3 |
5.297 | 0.415 | tINS | RR | 9 | R21C43[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4651_s1/F |
6.136 | 0.839 | tNET | RR | 1 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/I0 |
6.597 | 0.461 | tINS | RR | 16 | R9C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5419_s0/F |
9.464 | 2.868 | tNET | RR | 1 | R21C37[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_9_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.655 | 1.972 | tNET | RR | 1 | R21C37[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_9_s0/CLK |
12.344 | -0.311 | tSu | 1 | R21C37[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[50]_9_s0 |
Path Statistics:
Clock Skew | 0.048 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.291, 18.830%; route: 5.184, 75.592%; tC2Q: 0.382, 5.578% |
Required Clock Path Delay | cell: 0.683, 25.706%; route: 1.972, 74.294% |
Path25
Path Summary:
Slack | 2.975 |
Data Arrival Time | 9.322 |
Data Required Time | 12.297 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_2_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 16 | R29C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_load_flag_s0/Q |
4.288 | 1.299 | tNET | RR | 1 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/I1 |
4.703 | 0.415 | tINS | RR | 7 | R21C42[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4731_s1/F |
4.882 | 0.179 | tNET | RR | 1 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/I3 |
5.343 | 0.461 | tINS | RR | 9 | R21C43[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n4667_s1/F |
7.262 | 1.919 | tNET | RR | 1 | R5C36[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5307_s0/I0 |
7.778 | 0.516 | tINS | RR | 16 | R5C36[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5307_s0/F |
9.322 | 1.544 | tNET | RR | 1 | R15C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.608 | 1.926 | tNET | RR | 1 | R15C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_2_s0/CLK |
12.297 | -0.311 | tSu | 1 | R15C40[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[43]_2_s0 |
Path Statistics:
Clock Skew | 0.001 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.392, 20.737%; route: 4.940, 73.567%; tC2Q: 0.382, 5.696% |
Required Clock Path Delay | cell: 0.683, 26.168%; route: 1.926, 73.832% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.166 |
Data Arrival Time | 1.576 |
Data Required Time | 1.410 |
From | sim_output_storage_inst/ram_dout_addrb_5_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.365 | 0.689 | tNET | RR | 1 | R12C29[0][B] | sim_output_storage_inst/ram_dout_addrb_5_s0/CLK |
1.506 | 0.141 | tC2Q | RF | 6 | R12C29[0][B] | sim_output_storage_inst/ram_dout_addrb_5_s0/Q |
1.576 | 0.070 | tNET | FF | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
1.410 | 0.035 | tHld | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.505%; route: 0.689, 50.495% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.070, 33.175%; tC2Q: 0.141, 66.825% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path2
Path Summary:
Slack | 0.193 |
Data Arrival Time | 1.600 |
Data Required Time | 1.408 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.365 | 0.690 | tNET | RR | 1 | R11C23[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK |
1.507 | 0.141 | tC2Q | RF | 1 | R11C23[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q |
1.600 | 0.094 | tNET | FF | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.469%; route: 0.690, 50.531% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path3
Path Summary:
Slack | 0.193 |
Data Arrival Time | 1.609 |
Data Required Time | 1.415 |
From | sim_output_storage_inst/ram_din_data_0_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.374 | 0.698 | tNET | RR | 1 | R11C29[1][B] | sim_output_storage_inst/ram_din_data_0_s0/CLK |
1.515 | 0.141 | tC2Q | RF | 1 | R11C29[1][B] | sim_output_storage_inst/ram_din_data_0_s0/Q |
1.609 | 0.094 | tNET | FF | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.181%; route: 0.698, 50.819% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path4
Path Summary:
Slack | 0.207 |
Data Arrival Time | 1.622 |
Data Required Time | 1.415 |
From | sim_output_storage_inst/ram_din_addra_8_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C30[0][B] | sim_output_storage_inst/ram_din_addra_8_s0/CLK |
1.513 | 0.144 | tC2Q | RR | 7 | R11C30[0][B] | sim_output_storage_inst/ram_din_addra_8_s0/Q |
1.622 | 0.109 | tNET | RR | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.109, 43.083%; tC2Q: 0.144, 56.917% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path5
Path Summary:
Slack | 0.212 |
Data Arrival Time | 1.628 |
Data Required Time | 1.415 |
From | sim_output_storage_inst/ram_din_addra_0_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.361 | 0.685 | tNET | RR | 1 | R12C30[2][B] | sim_output_storage_inst/ram_din_addra_0_s0/CLK |
1.502 | 0.141 | tC2Q | RF | 7 | R12C30[2][B] | sim_output_storage_inst/ram_din_addra_0_s0/Q |
1.628 | 0.126 | tNET | FF | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.651%; route: 0.685, 50.349% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 47.191%; tC2Q: 0.141, 52.809% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path6
Path Summary:
Slack | 0.217 |
Data Arrival Time | 1.622 |
Data Required Time | 1.406 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_6_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R27C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_6_s0/CLK |
1.523 | 0.144 | tC2Q | RR | 5 | R27C38[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_6_s0/Q |
1.622 | 0.099 | tNET | RR | 1 | BSRAM_R28[11] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/AD[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[11] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK |
1.406 | 0.035 | tHld | 1 | BSRAM_R28[11] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path7
Path Summary:
Slack | 0.226 |
Data Arrival Time | 1.636 |
Data Required Time | 1.410 |
From | sim_output_storage_inst/ram_dout_addrb_3_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.365 | 0.689 | tNET | RR | 1 | R12C29[1][A] | sim_output_storage_inst/ram_dout_addrb_3_s0/CLK |
1.506 | 0.141 | tC2Q | RF | 5 | R12C29[1][A] | sim_output_storage_inst/ram_dout_addrb_3_s0/Q |
1.636 | 0.130 | tNET | FF | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
1.410 | 0.035 | tHld | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.505%; route: 0.689, 50.495% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 47.970%; tC2Q: 0.141, 52.030% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path8
Path Summary:
Slack | 0.253 |
Data Arrival Time | 1.664 |
Data Required Time | 1.411 |
From | sim_output_storage_inst/ram_din_addra_3_s0 |
To | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.356 | 0.681 | tNET | RR | 1 | R12C31[1][A] | sim_output_storage_inst/ram_din_addra_3_s0/CLK |
1.497 | 0.141 | tC2Q | RF | 4 | R12C31[1][A] | sim_output_storage_inst/ram_din_addra_3_s0/Q |
1.664 | 0.167 | tNET | FF | 1 | BSRAM_R10[9] | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/ADA[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[9] | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[9] | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.167, 54.221%; tC2Q: 0.141, 45.779% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path9
Path Summary:
Slack | 0.256 |
Data Arrival Time | 1.661 |
Data Required Time | 1.406 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_1_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C39[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_1_s0/CLK |
1.520 | 0.144 | tC2Q | RR | 9 | R27C39[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_1_s0/Q |
1.661 | 0.142 | tNET | RR | 1 | BSRAM_R28[11] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/AD[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[11] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK |
1.406 | 0.035 | tHld | 1 | BSRAM_R28[11] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.142, 49.650%; tC2Q: 0.144, 50.350% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path10
Path Summary:
Slack | 0.257 |
Data Arrival Time | 1.664 |
Data Required Time | 1.408 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R9C26[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK |
1.523 | 0.144 | tC2Q | RR | 1 | R9C26[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q |
1.664 | 0.141 | tNET | RR | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.408 | 0.037 | tHld | 1 | BSRAM_R10[6] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.141, 49.474%; tC2Q: 0.144, 50.526% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path11
Path Summary:
Slack | 0.260 |
Data Arrival Time | 1.666 |
Data Required Time | 1.406 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C39[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_2_s0/CLK |
1.520 | 0.144 | tC2Q | RR | 8 | R27C39[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_mem_addr_2_s0/Q |
1.666 | 0.146 | tNET | RR | 1 | BSRAM_R28[11] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/AD[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.371 | 0.695 | tNET | RR | 1 | BSRAM_R28[11] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK |
1.406 | 0.035 | tHld | 1 | BSRAM_R28[11] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.146, 50.345%; tC2Q: 0.144, 49.655% |
Required Clock Path Delay | cell: 0.675, 49.289%; route: 0.695, 50.711% |
Path12
Path Summary:
Slack | 0.262 |
Data Arrival Time | 1.674 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.385 | 0.710 | tNET | RR | 1 | R7C27[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.530 | 0.144 | tC2Q | RR | 5 | R7C27[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
1.674 | 0.144 | tNET | RR | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.755%; route: 0.710, 51.245% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.144, 50.000%; tC2Q: 0.144, 50.000% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path13
Path Summary:
Slack | 0.264 |
Data Arrival Time | 1.680 |
Data Required Time | 1.415 |
From | sim_output_storage_inst/ram_din_addra_7_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.361 | 0.685 | tNET | RR | 1 | R12C30[0][A] | sim_output_storage_inst/ram_din_addra_7_s0/CLK |
1.502 | 0.141 | tC2Q | RF | 7 | R12C30[0][A] | sim_output_storage_inst/ram_din_addra_7_s0/Q |
1.680 | 0.178 | tNET | FF | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.651%; route: 0.685, 50.349% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.178, 55.799%; tC2Q: 0.141, 44.201% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path14
Path Summary:
Slack | 0.271 |
Data Arrival Time | 1.682 |
Data Required Time | 1.411 |
From | sim_output_storage_inst/ram_din_data_21_s0 |
To | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R17C32[1][B] | sim_output_storage_inst/ram_din_data_21_s0/CLK |
1.516 | 0.141 | tC2Q | RF | 1 | R17C32[1][B] | sim_output_storage_inst/ram_din_data_21_s0/Q |
1.682 | 0.166 | tNET | FF | 1 | BSRAM_R10[9] | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[9] | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[9] | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.127%; route: 0.700, 50.873% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.166, 54.072%; tC2Q: 0.141, 45.928% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path15
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.686 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C26[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
1.533 | 0.144 | tC2Q | RR | 7 | R7C26[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q |
1.686 | 0.153 | tNET | RR | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[7] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.153, 51.515%; tC2Q: 0.144, 48.485% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path16
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.674 |
Data Required Time | 1.399 |
From | sim_output_storage_inst/cnt_chn_0_s0 |
To | sim_output_storage_inst/cnt_chn_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.374 | 0.698 | tNET | RR | 1 | R16C30[0][A] | sim_output_storage_inst/cnt_chn_0_s0/CLK |
1.515 | 0.141 | tC2Q | RF | 5 | R16C30[0][A] | sim_output_storage_inst/cnt_chn_0_s0/Q |
1.521 | 0.006 | tNET | FF | 1 | R16C30[0][A] | sim_output_storage_inst/n77_s3/I0 |
1.674 | 0.153 | tINS | FF | 1 | R16C30[0][A] | sim_output_storage_inst/n77_s3/F |
1.674 | 0.000 | tNET | FF | 1 | R16C30[0][A] | sim_output_storage_inst/cnt_chn_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.374 | 0.698 | tNET | RR | 1 | R16C30[0][A] | sim_output_storage_inst/cnt_chn_0_s0/CLK |
1.399 | 0.025 | tHld | 1 | R16C30[0][A] | sim_output_storage_inst/cnt_chn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.172%; route: 0.698, 50.828% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 49.172%; route: 0.698, 50.828% |
Path17
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.656 |
Data Required Time | 1.381 |
From | sim_output_storage_inst/ram_din_addra_6_s0 |
To | sim_output_storage_inst/ram_din_addra_6_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.356 | 0.681 | tNET | RR | 1 | R12C31[0][A] | sim_output_storage_inst/ram_din_addra_6_s0/CLK |
1.497 | 0.141 | tC2Q | RF | 4 | R12C31[0][A] | sim_output_storage_inst/ram_din_addra_6_s0/Q |
1.503 | 0.006 | tNET | FF | 1 | R12C31[0][A] | sim_output_storage_inst/n125_s1/I1 |
1.656 | 0.153 | tINS | FF | 1 | R12C31[0][A] | sim_output_storage_inst/n125_s1/F |
1.656 | 0.000 | tNET | FF | 1 | R12C31[0][A] | sim_output_storage_inst/ram_din_addra_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.356 | 0.681 | tNET | RR | 1 | R12C31[0][A] | sim_output_storage_inst/ram_din_addra_6_s0/CLK |
1.381 | 0.025 | tHld | 1 | R12C31[0][A] | sim_output_storage_inst/ram_din_addra_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 49.797%; route: 0.681, 50.203% |
Path18
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.676 |
Data Required Time | 1.400 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/ram_data_addra_0_s4 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/ram_data_addra_0_s4 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C43[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/ram_data_addra_0_s4/CLK |
1.516 | 0.141 | tC2Q | RF | 6 | R27C43[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/ram_data_addra_0_s4/Q |
1.523 | 0.006 | tNET | FF | 1 | R27C43[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n237_s5/I1 |
1.676 | 0.153 | tINS | FF | 1 | R27C43[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n237_s5/F |
1.676 | 0.000 | tNET | FF | 1 | R27C43[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/ram_data_addra_0_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R27C43[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/ram_data_addra_0_s4/CLK |
1.400 | 0.025 | tHld | 1 | R27C43[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/ram_data_addra_0_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 49.109%; route: 0.700, 50.891% |
Path19
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.687 |
Data Required Time | 1.412 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.387 | 0.712 | tNET | RR | 1 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
1.528 | 0.141 | tC2Q | RF | 9 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/Q |
1.534 | 0.006 | tNET | FF | 1 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n414_s3/I3 |
1.687 | 0.153 | tINS | FF | 1 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n414_s3/F |
1.687 | 0.000 | tNET | FF | 1 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.387 | 0.712 | tNET | RR | 1 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
1.412 | 0.025 | tHld | 1 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.693%; route: 0.712, 51.307% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.693%; route: 0.712, 51.307% |
Path20
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.689 |
Data Required Time | 1.414 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
1.530 | 0.141 | tC2Q | RF | 2 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q |
1.536 | 0.006 | tNET | FF | 1 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n312_s0/I2 |
1.689 | 0.153 | tINS | FF | 1 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n312_s0/F |
1.689 | 0.000 | tNET | FF | 1 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
1.414 | 0.025 | tHld | 1 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Path21
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.669 |
Data Required Time | 1.393 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
1.510 | 0.141 | tC2Q | RF | 3 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q |
1.516 | 0.006 | tNET | FF | 1 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/n2076_s1/I1 |
1.669 | 0.153 | tINS | FF | 1 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/n2076_s1/F |
1.669 | 0.000 | tNET | FF | 1 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
1.393 | 0.025 | tHld | 1 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Path22
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.707 |
Data Required Time | 2.432 |
From | gw_gao_inst_0/u_la0_top/word_count_5_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_5_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 259 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.407 | 1.056 | tNET | RR | 1 | R31C28[0][A] | gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK |
2.548 | 0.141 | tC2Q | RF | 2 | R31C28[0][A] | gw_gao_inst_0/u_la0_top/word_count_5_s0/Q |
2.554 | 0.006 | tNET | FF | 1 | R31C28[0][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_5_s0/I2 |
2.707 | 0.153 | tINS | FF | 1 | R31C28[0][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_5_s0/F |
2.707 | 0.000 | tNET | FF | 1 | R31C28[0][A] | gw_gao_inst_0/u_la0_top/word_count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 259 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.407 | 1.056 | tNET | RR | 1 | R31C28[0][A] | gw_gao_inst_0/u_la0_top/word_count_5_s0/CLK |
2.432 | 0.025 | tHld | 1 | R31C28[0][A] | gw_gao_inst_0/u_la0_top/word_count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 56.128%; route: 1.056, 43.872% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 56.128%; route: 1.056, 43.872% |
Path23
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.736 |
Data Required Time | 2.461 |
From | gw_gao_inst_0/u_la0_top/address_counter_3_s0 |
To | gw_gao_inst_0/u_la0_top/address_counter_3_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 259 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.436 | 1.085 | tNET | RR | 1 | R23C28[1][A] | gw_gao_inst_0/u_la0_top/address_counter_3_s0/CLK |
2.577 | 0.141 | tC2Q | RF | 5 | R23C28[1][A] | gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q |
2.583 | 0.006 | tNET | FF | 1 | R23C28[1][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_3_s0/I2 |
2.736 | 0.153 | tINS | FF | 1 | R23C28[1][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_3_s0/F |
2.736 | 0.000 | tNET | FF | 1 | R23C28[1][A] | gw_gao_inst_0/u_la0_top/address_counter_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 259 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.436 | 1.085 | tNET | RR | 1 | R23C28[1][A] | gw_gao_inst_0/u_la0_top/address_counter_3_s0/CLK |
2.461 | 0.025 | tHld | 1 | R23C28[1][A] | gw_gao_inst_0/u_la0_top/address_counter_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 55.471%; route: 1.085, 44.529% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 55.471%; route: 1.085, 44.529% |
Path24
Path Summary:
Slack | 0.277 |
Data Arrival Time | 1.686 |
Data Required Time | 1.410 |
From | sim_output_storage_inst/ram_dout_addrb_6_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C30[0][A] | sim_output_storage_inst/ram_dout_addrb_6_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 6 | R11C30[0][A] | sim_output_storage_inst/ram_dout_addrb_6_s0/Q |
1.686 | 0.176 | tNET | FF | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
1.410 | 0.035 | tHld | 1 | BSRAM_R10[8] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.176, 55.521%; tC2Q: 0.141, 44.479% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path25
Path Summary:
Slack | 0.278 |
Data Arrival Time | 2.702 |
Data Required Time | 2.424 |
From | gw_gao_inst_0/u_la0_top/word_count_2_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_2_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 259 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.399 | 1.048 | tNET | RR | 1 | R31C26[0][A] | gw_gao_inst_0/u_la0_top/word_count_2_s0/CLK |
2.540 | 0.141 | tC2Q | RF | 5 | R31C26[0][A] | gw_gao_inst_0/u_la0_top/word_count_2_s0/Q |
2.549 | 0.009 | tNET | FF | 1 | R31C26[0][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_2_s0/I1 |
2.702 | 0.153 | tINS | FF | 1 | R31C26[0][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_2_s0/F |
2.702 | 0.000 | tNET | FF | 1 | R31C26[0][A] | gw_gao_inst_0/u_la0_top/word_count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 259 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.399 | 1.048 | tNET | RR | 1 | R31C26[0][A] | gw_gao_inst_0/u_la0_top/word_count_2_s0/CLK |
2.424 | 0.025 | tHld | 1 | R31C26[0][A] | gw_gao_inst_0/u_la0_top/word_count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 56.315%; route: 1.048, 43.685% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 1.351, 56.315%; route: 1.048, 43.685% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 2.962 |
Data Arrival Time | 9.336 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.336 | 1.289 | tNET | FF | 1 | R7C25[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.645 | 1.962 | tNET | RR | 1 | R7C25[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
12.298 | -0.347 | tSu | 1 | R7C25[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | 0.040 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.289, 74.440%; tC2Q: 0.442, 25.560% |
Required Clock Path Delay | cell: 0.683, 25.803%; route: 1.962, 74.197% |
Path2
Path Summary:
Slack | 2.962 |
Data Arrival Time | 9.336 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.336 | 1.289 | tNET | FF | 1 | R7C25[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.645 | 1.962 | tNET | RR | 1 | R7C25[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
12.298 | -0.347 | tSu | 1 | R7C25[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | 0.040 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.289, 74.440%; tC2Q: 0.442, 25.560% |
Required Clock Path Delay | cell: 0.683, 25.803%; route: 1.962, 74.197% |
Path3
Path Summary:
Slack | 2.962 |
Data Arrival Time | 9.336 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.336 | 1.289 | tNET | FF | 1 | R7C25[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.645 | 1.962 | tNET | RR | 1 | R7C25[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
12.298 | -0.347 | tSu | 1 | R7C25[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | 0.040 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.289, 74.440%; tC2Q: 0.442, 25.560% |
Required Clock Path Delay | cell: 0.683, 25.803%; route: 1.962, 74.197% |
Path4
Path Summary:
Slack | 2.973 |
Data Arrival Time | 9.327 |
Data Required Time | 12.300 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.327 | 1.280 | tNET | FF | 1 | R6C25[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.648 | 1.965 | tNET | RR | 1 | R6C25[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
12.300 | -0.347 | tSu | 1 | R6C25[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | 0.043 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.280, 74.311%; tC2Q: 0.442, 25.689% |
Required Clock Path Delay | cell: 0.683, 25.779%; route: 1.965, 74.221% |
Path5
Path Summary:
Slack | 3.127 |
Data Arrival Time | 9.171 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.171 | 1.124 | tNET | FF | 1 | R7C29[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.645 | 1.962 | tNET | RR | 1 | R7C29[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
12.298 | -0.347 | tSu | 1 | R7C29[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | 0.040 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.124, 71.748%; tC2Q: 0.442, 28.252% |
Required Clock Path Delay | cell: 0.683, 25.803%; route: 1.962, 74.197% |
Path6
Path Summary:
Slack | 3.127 |
Data Arrival Time | 9.171 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.171 | 1.124 | tNET | FF | 1 | R7C29[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.645 | 1.962 | tNET | RR | 1 | R7C29[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
12.298 | -0.347 | tSu | 1 | R7C29[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | 0.040 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.124, 71.748%; tC2Q: 0.442, 28.252% |
Required Clock Path Delay | cell: 0.683, 25.803%; route: 1.962, 74.197% |
Path7
Path Summary:
Slack | 3.319 |
Data Arrival Time | 8.960 |
Data Required Time | 12.279 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.960 | 0.912 | tNET | FF | 1 | R7C27[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.626 | 1.944 | tNET | RR | 1 | R7C27[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
12.279 | -0.347 | tSu | 1 | R7C27[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | 0.022 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.912, 67.343%; tC2Q: 0.442, 32.657% |
Required Clock Path Delay | cell: 0.683, 25.988%; route: 1.944, 74.012% |
Path8
Path Summary:
Slack | 3.319 |
Data Arrival Time | 8.960 |
Data Required Time | 12.279 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.960 | 0.912 | tNET | FF | 1 | R7C27[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.626 | 1.944 | tNET | RR | 1 | R7C27[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
12.279 | -0.347 | tSu | 1 | R7C27[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | 0.022 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.912, 67.343%; tC2Q: 0.442, 32.657% |
Required Clock Path Delay | cell: 0.683, 25.988%; route: 1.944, 74.012% |
Path9
Path Summary:
Slack | 3.319 |
Data Arrival Time | 8.960 |
Data Required Time | 12.279 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.960 | 0.912 | tNET | FF | 1 | R7C27[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.626 | 1.944 | tNET | RR | 1 | R7C27[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
12.279 | -0.347 | tSu | 1 | R7C27[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | 0.022 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.912, 67.343%; tC2Q: 0.442, 32.657% |
Required Clock Path Delay | cell: 0.683, 25.988%; route: 1.944, 74.012% |
Path10
Path Summary:
Slack | 3.319 |
Data Arrival Time | 8.960 |
Data Required Time | 12.279 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.960 | 0.912 | tNET | FF | 1 | R7C27[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.626 | 1.944 | tNET | RR | 1 | R7C27[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
12.279 | -0.347 | tSu | 1 | R7C27[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | 0.022 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.912, 67.343%; tC2Q: 0.442, 32.657% |
Required Clock Path Delay | cell: 0.683, 25.988%; route: 1.944, 74.012% |
Path11
Path Summary:
Slack | 3.322 |
Data Arrival Time | 8.960 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.960 | 0.912 | tNET | FF | 1 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.629 | 1.946 | tNET | RR | 1 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
12.281 | -0.347 | tSu | 1 | R6C27[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
Clock Skew | 0.024 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.912, 67.343%; tC2Q: 0.442, 32.657% |
Required Clock Path Delay | cell: 0.683, 25.963%; route: 1.946, 74.037% |
Path12
Path Summary:
Slack | 3.322 |
Data Arrival Time | 8.960 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.960 | 0.912 | tNET | FF | 1 | R6C27[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.629 | 1.946 | tNET | RR | 1 | R6C27[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
12.281 | -0.347 | tSu | 1 | R6C27[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | 0.024 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.912, 67.343%; tC2Q: 0.442, 32.657% |
Required Clock Path Delay | cell: 0.683, 25.963%; route: 1.946, 74.037% |
Path13
Path Summary:
Slack | 3.338 |
Data Arrival Time | 8.950 |
Data Required Time | 12.288 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.950 | 0.902 | tNET | FF | 1 | R7C28[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.636 | 1.953 | tNET | RR | 1 | R7C28[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
12.288 | -0.347 | tSu | 1 | R7C28[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.902, 67.100%; tC2Q: 0.442, 32.900% |
Required Clock Path Delay | cell: 0.683, 25.895%; route: 1.953, 74.105% |
Path14
Path Summary:
Slack | 3.338 |
Data Arrival Time | 8.950 |
Data Required Time | 12.288 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.950 | 0.902 | tNET | FF | 1 | R7C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.636 | 1.953 | tNET | RR | 1 | R7C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
12.288 | -0.347 | tSu | 1 | R7C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.902, 67.100%; tC2Q: 0.442, 32.900% |
Required Clock Path Delay | cell: 0.683, 25.895%; route: 1.953, 74.105% |
Path15
Path Summary:
Slack | 3.338 |
Data Arrival Time | 8.950 |
Data Required Time | 12.288 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.950 | 0.902 | tNET | FF | 1 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.636 | 1.953 | tNET | RR | 1 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
12.288 | -0.347 | tSu | 1 | R7C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.902, 67.100%; tC2Q: 0.442, 32.900% |
Required Clock Path Delay | cell: 0.683, 25.895%; route: 1.953, 74.105% |
Path16
Path Summary:
Slack | 3.341 |
Data Arrival Time | 8.950 |
Data Required Time | 12.291 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.950 | 0.902 | tNET | FF | 1 | R6C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.638 | 1.956 | tNET | RR | 1 | R6C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
12.291 | -0.347 | tSu | 1 | R6C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.902, 67.100%; tC2Q: 0.442, 32.900% |
Required Clock Path Delay | cell: 0.683, 25.871%; route: 1.956, 74.129% |
Path17
Path Summary:
Slack | 3.341 |
Data Arrival Time | 8.950 |
Data Required Time | 12.291 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.950 | 0.902 | tNET | FF | 1 | R6C28[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.638 | 1.956 | tNET | RR | 1 | R6C28[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
12.291 | -0.347 | tSu | 1 | R6C28[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | 0.033 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.902, 67.100%; tC2Q: 0.442, 32.900% |
Required Clock Path Delay | cell: 0.683, 25.871%; route: 1.956, 74.129% |
Path18
Path Summary:
Slack | 3.741 |
Data Arrival Time | 8.540 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.540 | 0.492 | tNET | FF | 1 | R26C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R26C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
12.281 | -0.347 | tSu | 1 | R26C28[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | 0.024 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.492, 52.674%; tC2Q: 0.442, 47.326% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path19
Path Summary:
Slack | 3.741 |
Data Arrival Time | 8.540 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.540 | 0.492 | tNET | FF | 1 | R26C28[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R26C28[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
12.281 | -0.347 | tSu | 1 | R26C28[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | 0.024 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.492, 52.674%; tC2Q: 0.442, 47.326% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path20
Path Summary:
Slack | 3.741 |
Data Arrival Time | 8.540 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.540 | 0.492 | tNET | FF | 1 | R26C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R26C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
12.281 | -0.347 | tSu | 1 | R26C28[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | 0.024 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.492, 52.674%; tC2Q: 0.442, 47.326% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path21
Path Summary:
Slack | 3.756 |
Data Arrival Time | 8.532 |
Data Required Time | 12.288 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.532 | 0.485 | tNET | FF | 1 | R7C26[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.636 | 1.953 | tNET | RR | 1 | R7C26[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
12.288 | -0.347 | tSu | 1 | R7C26[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.485, 52.291%; tC2Q: 0.442, 47.709% |
Required Clock Path Delay | cell: 0.683, 25.895%; route: 1.953, 74.105% |
Path22
Path Summary:
Slack | 3.756 |
Data Arrival Time | 8.532 |
Data Required Time | 12.288 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.532 | 0.485 | tNET | FF | 1 | R7C26[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.636 | 1.953 | tNET | RR | 1 | R7C26[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
12.288 | -0.347 | tSu | 1 | R7C26[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | 0.031 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.485, 52.291%; tC2Q: 0.442, 47.709% |
Required Clock Path Delay | cell: 0.683, 25.895%; route: 1.953, 74.105% |
Path23
Path Summary:
Slack | 3.768 |
Data Arrival Time | 8.527 |
Data Required Time | 12.296 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.527 | 0.480 | tNET | FF | 1 | R22C28[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.643 | 1.961 | tNET | RR | 1 | R22C28[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
12.296 | -0.347 | tSu | 1 | R22C28[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | 0.038 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.480, 52.033%; tC2Q: 0.442, 47.967% |
Required Clock Path Delay | cell: 0.683, 25.822%; route: 1.961, 74.178% |
Path24
Path Summary:
Slack | 3.768 |
Data Arrival Time | 8.527 |
Data Required Time | 12.296 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.527 | 0.480 | tNET | FF | 1 | R22C28[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.643 | 1.961 | tNET | RR | 1 | R22C28[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
12.296 | -0.347 | tSu | 1 | R22C28[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.038 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.480, 52.033%; tC2Q: 0.442, 47.967% |
Required Clock Path Delay | cell: 0.683, 25.822%; route: 1.961, 74.178% |
Path25
Path Summary:
Slack | 3.768 |
Data Arrival Time | 8.527 |
Data Required Time | 12.296 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
7.605 | 1.917 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.047 | 0.442 | tC2Q | FF | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.527 | 0.480 | tNET | FF | 1 | R22C28[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
12.643 | 1.961 | tNET | RR | 1 | R22C28[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
12.296 | -0.347 | tSu | 1 | R22C28[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | 0.038 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 26.395%; route: 1.917, 73.605% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.480, 52.033%; tC2Q: 0.442, 47.967% |
Required Clock Path Delay | cell: 0.683, 25.822%; route: 1.961, 74.178% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 5.347 |
Data Arrival Time | 6.683 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.683 | 0.152 | tNET | RR | 1 | R7C28[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C28[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
1.336 | -0.053 | tHld | 1 | R7C28[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | 0.016 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.152, 49.032%; tC2Q: 0.158, 50.968% |
Required Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Path2
Path Summary:
Slack | 5.347 |
Data Arrival Time | 6.683 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.683 | 0.152 | tNET | RR | 1 | R7C28[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C28[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
1.336 | -0.053 | tHld | 1 | R7C28[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | 0.016 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.152, 49.032%; tC2Q: 0.158, 50.968% |
Required Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Path3
Path Summary:
Slack | 5.352 |
Data Arrival Time | 6.683 |
Data Required Time | 1.332 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.683 | 0.152 | tNET | RR | 1 | R8C28[1][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R8C28[1][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
1.332 | -0.053 | tHld | 1 | R8C28[1][A] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | 0.011 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.152, 49.032%; tC2Q: 0.158, 50.968% |
Required Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Path4
Path Summary:
Slack | 5.358 |
Data Arrival Time | 6.701 |
Data Required Time | 1.342 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.701 | 0.169 | tNET | RR | 1 | R6C29[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.395 | 0.720 | tNET | RR | 1 | R6C29[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
1.342 | -0.053 | tHld | 1 | R6C29[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | 0.022 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.169, 51.682%; tC2Q: 0.158, 48.318% |
Required Clock Path Delay | cell: 0.675, 48.414%; route: 0.720, 51.586% |
Path5
Path Summary:
Slack | 5.358 |
Data Arrival Time | 6.701 |
Data Required Time | 1.342 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.701 | 0.169 | tNET | RR | 1 | R6C29[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.395 | 0.720 | tNET | RR | 1 | R6C29[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
1.342 | -0.053 | tHld | 1 | R6C29[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | 0.022 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.169, 51.682%; tC2Q: 0.158, 48.318% |
Required Clock Path Delay | cell: 0.675, 48.414%; route: 0.720, 51.586% |
Path6
Path Summary:
Slack | 5.358 |
Data Arrival Time | 6.701 |
Data Required Time | 1.342 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.701 | 0.169 | tNET | RR | 1 | R6C29[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.395 | 0.720 | tNET | RR | 1 | R6C29[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
1.342 | -0.053 | tHld | 1 | R6C29[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | 0.022 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.169, 51.682%; tC2Q: 0.158, 48.318% |
Required Clock Path Delay | cell: 0.675, 48.414%; route: 0.720, 51.586% |
Path7
Path Summary:
Slack | 5.419 |
Data Arrival Time | 6.734 |
Data Required Time | 1.315 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.734 | 0.203 | tNET | RR | 1 | R14C26[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R14C26[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
1.316 | -0.053 | tHld | 1 | R14C26[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Path8
Path Summary:
Slack | 5.419 |
Data Arrival Time | 6.734 |
Data Required Time | 1.315 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.734 | 0.203 | tNET | RR | 1 | R14C26[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R14C26[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK |
1.316 | -0.053 | tHld | 1 | R14C26[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Path9
Path Summary:
Slack | 5.419 |
Data Arrival Time | 6.734 |
Data Required Time | 1.315 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.734 | 0.203 | tNET | RR | 1 | R14C26[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R14C26[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
1.316 | -0.053 | tHld | 1 | R14C26[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Path10
Path Summary:
Slack | 5.419 |
Data Arrival Time | 6.734 |
Data Required Time | 1.315 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.734 | 0.203 | tNET | RR | 1 | R14C26[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R14C26[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK |
1.316 | -0.053 | tHld | 1 | R14C26[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Path11
Path Summary:
Slack | 5.419 |
Data Arrival Time | 6.734 |
Data Required Time | 1.315 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.734 | 0.203 | tNET | RR | 1 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
1.316 | -0.053 | tHld | 1 | R14C26[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Path12
Path Summary:
Slack | 5.423 |
Data Arrival Time | 6.734 |
Data Required Time | 1.312 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.734 | 0.203 | tNET | RR | 1 | R13C28[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.365 | 0.689 | tNET | RR | 1 | R13C28[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
1.312 | -0.053 | tHld | 1 | R13C28[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 49.505%; route: 0.689, 50.495% |
Path13
Path Summary:
Slack | 5.423 |
Data Arrival Time | 6.734 |
Data Required Time | 1.312 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.734 | 0.203 | tNET | RR | 1 | R13C28[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.365 | 0.689 | tNET | RR | 1 | R13C28[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
1.312 | -0.053 | tHld | 1 | R13C28[0][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 49.505%; route: 0.689, 50.495% |
Path14
Path Summary:
Slack | 5.423 |
Data Arrival Time | 6.734 |
Data Required Time | 1.312 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.734 | 0.203 | tNET | RR | 1 | R13C28[0][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.365 | 0.689 | tNET | RR | 1 | R13C28[0][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
1.312 | -0.053 | tHld | 1 | R13C28[0][B] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 49.505%; route: 0.689, 50.495% |
Path15
Path Summary:
Slack | 5.423 |
Data Arrival Time | 6.734 |
Data Required Time | 1.312 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.734 | 0.203 | tNET | RR | 1 | R13C28[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.365 | 0.689 | tNET | RR | 1 | R13C28[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
1.312 | -0.053 | tHld | 1 | R13C28[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 49.505%; route: 0.689, 50.495% |
Path16
Path Summary:
Slack | 5.430 |
Data Arrival Time | 6.749 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.749 | 0.218 | tNET | RR | 1 | R14C29[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C29[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
1.319 | -0.053 | tHld | 1 | R14C29[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.218, 57.979%; tC2Q: 0.158, 42.021% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path17
Path Summary:
Slack | 5.430 |
Data Arrival Time | 6.749 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.749 | 0.218 | tNET | RR | 1 | R14C29[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C29[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
1.319 | -0.053 | tHld | 1 | R14C29[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.218, 57.979%; tC2Q: 0.158, 42.021% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path18
Path Summary:
Slack | 5.430 |
Data Arrival Time | 6.749 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.749 | 0.218 | tNET | RR | 1 | R14C29[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C29[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
1.319 | -0.053 | tHld | 1 | R14C29[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.218, 57.979%; tC2Q: 0.158, 42.021% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path19
Path Summary:
Slack | 5.430 |
Data Arrival Time | 6.749 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.749 | 0.218 | tNET | RR | 1 | R14C29[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C29[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
1.319 | -0.053 | tHld | 1 | R14C29[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.218, 57.979%; tC2Q: 0.158, 42.021% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path20
Path Summary:
Slack | 5.430 |
Data Arrival Time | 6.749 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.749 | 0.218 | tNET | RR | 1 | R14C29[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C29[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C29[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.218, 57.979%; tC2Q: 0.158, 42.021% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path21
Path Summary:
Slack | 5.430 |
Data Arrival Time | 6.749 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.749 | 0.218 | tNET | RR | 1 | R14C29[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C29[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C29[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.218, 57.979%; tC2Q: 0.158, 42.021% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path22
Path Summary:
Slack | 5.430 |
Data Arrival Time | 6.749 |
Data Required Time | 1.319 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.749 | 0.218 | tNET | RR | 1 | R14C29[3][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.372 | 0.697 | tNET | RR | 1 | R14C29[3][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
1.319 | -0.053 | tHld | 1 | R14C29[3][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.218, 57.979%; tC2Q: 0.158, 42.021% |
Required Clock Path Delay | cell: 0.675, 49.217%; route: 0.697, 50.783% |
Path23
Path Summary:
Slack | 5.445 |
Data Arrival Time | 6.781 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.781 | 0.250 | tNET | RR | 1 | R7C26[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C26[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
1.336 | -0.053 | tHld | 1 | R7C26[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | 0.016 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.250, 61.275%; tC2Q: 0.158, 38.725% |
Required Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Path24
Path Summary:
Slack | 5.445 |
Data Arrival Time | 6.781 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.781 | 0.250 | tNET | RR | 1 | R7C26[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C26[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
1.336 | -0.053 | tHld | 1 | R7C26[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | 0.016 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.250, 61.275%; tC2Q: 0.158, 38.725% |
Required Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Path25
Path Summary:
Slack | 5.447 |
Data Arrival Time | 6.793 |
Data Required Time | 1.346 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 1952 | IOB29[A] | clk_ibuf/O |
6.373 | 0.696 | tNET | FF | 1 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.531 | 0.158 | tC2Q | FR | 53 | R14C28[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.793 | 0.261 | tNET | RR | 1 | R22C29[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 1952 | IOB29[A] | clk_ibuf/O |
1.399 | 0.723 | tNET | RR | 1 | R22C29[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
1.346 | -0.053 | tHld | 1 | R22C29[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.025 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 49.327%; route: 0.696, 50.673% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.261, 62.291%; tC2Q: 0.158, 37.709% |
Required Clock Path Delay | cell: 0.675, 48.293%; route: 0.723, 51.707% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.751 |
Actual Width: | 3.751 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.627 | 1.940 | tNET | FF | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.703 | tNET | RR | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
MPW2
MPW Summary:
Slack: | 2.751 |
Actual Width: | 3.751 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.627 | 1.940 | tNET | FF | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.703 | tNET | RR | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKB |
MPW3
MPW Summary:
Slack: | 2.757 |
Actual Width: | 3.757 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.930 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.375 | 0.699 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW4
MPW Summary:
Slack: | 2.757 |
Actual Width: | 3.757 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.930 | tNET | FF | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.375 | 0.699 | tNET | RR | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
MPW5
MPW Summary:
Slack: | 2.757 |
Actual Width: | 3.757 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.930 | tNET | FF | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.375 | 0.699 | tNET | RR | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKA |
MPW6
MPW Summary:
Slack: | 2.757 |
Actual Width: | 3.757 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.930 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.375 | 0.699 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
MPW7
MPW Summary:
Slack: | 2.759 |
Actual Width: | 3.759 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.931 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.702 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0] |
MPW8
MPW Summary:
Slack: | 2.762 |
Actual Width: | 3.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | clk_ibuf/O |
6.385 | 0.708 | tNET | FF | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
MPW9
MPW Summary:
Slack: | 2.762 |
Actual Width: | 3.762 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clk | ||
0.000 | 0.000 | tCL | RR | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | clk_ibuf/O |
2.623 | 1.941 | tNET | RR | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | clk_ibuf/O |
6.385 | 0.708 | tNET | FF | sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKB |
MPW10
MPW Summary:
Slack: | 2.762 |
Actual Width: | 3.762 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.608 | 1.921 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.371 | 0.695 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1952 | clk_d | 1.924 | 1.985 |
544 | coeff_ram_addrb[0] | 3.850 | 2.642 |
272 | coeff_ram_addrb[1] | 4.953 | 2.827 |
259 | control0[0] | 3.659 | 2.735 |
129 | coeff_ram_addrb[2] | 3.061 | 3.971 |
68 | coeff_mem_out[0] | 6.187 | 1.775 |
68 | coeff_mem_out[9] | 4.977 | 2.966 |
68 | coeff_mem_out[10] | 4.702 | 3.250 |
68 | coeff_mem_out[11] | 5.337 | 2.590 |
68 | coeff_mem_out[12] | 4.940 | 3.017 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R17C27 | 48.61% |
R21C43 | 48.61% |
R9C26 | 45.83% |
R10C26 | 45.83% |
R10C29 | 45.83% |
R22C42 | 44.44% |
R12C30 | 44.44% |
R17C26 | 43.06% |
R6C41 | 43.06% |
R31C44 | 41.67% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}] |