Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\341taps_4chn_4tdm_7inter_17decim_16bit\proj\impl\gwsynthesis\fir_proj.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\341taps_4chn_4tdm_7inter_17decim_16bit\proj\src\fir_proj.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\341taps_4chn_4tdm_7inter_17decim_16bit\proj\src\fir_proj.sdc |
Tool Version | V1.9.11 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Dec 25 12:57:08 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C ES |
Hold Delay Model | Fast 0.945V 85C ES |
Numbers of Paths Analyzed | 34392 |
Numbers of Endpoints Analyzed | 35303 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk | ||
2 | tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.000(MHz) | 117.086(MHz) | 6 | TOP |
2 | tck_pad_i | 20.000(MHz) | 178.044(MHz) | 7 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.459 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_4_s0/D | clk:[R] | clk:[R] | 10.000 | 0.007 | 8.470 |
2 | 1.676 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_3_s0/D | clk:[R] | clk:[R] | 10.000 | 0.033 | 8.228 |
3 | 1.711 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_1_s0/D | clk:[R] | clk:[R] | 10.000 | 0.033 | 8.193 |
4 | 1.735 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_0_s0/D | clk:[R] | clk:[R] | 10.000 | 0.033 | 8.169 |
5 | 1.977 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_2_s0/D | clk:[R] | clk:[R] | 10.000 | 0.033 | 7.926 |
6 | 2.090 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_7_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.001 | 7.600 |
7 | 2.096 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_13_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.017 | 7.576 |
8 | 2.096 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_10_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.017 | 7.576 |
9 | 2.096 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_4_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.017 | 7.576 |
10 | 2.096 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_1_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.017 | 7.576 |
11 | 2.129 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_10_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.005 | 7.555 |
12 | 2.137 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_11_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.017 | 7.535 |
13 | 2.137 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_4_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.017 | 7.535 |
14 | 2.202 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_13_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.011 | 7.476 |
15 | 2.202 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_10_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.011 | 7.476 |
16 | 2.202 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_4_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.011 | 7.476 |
17 | 2.202 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_2_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.011 | 7.476 |
18 | 2.227 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_15_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.000 | 7.461 |
19 | 2.237 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_7_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.009 | 7.461 |
20 | 2.237 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_9_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.009 | 7.461 |
21 | 2.237 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_11_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.009 | 7.461 |
22 | 2.237 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_15_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.009 | 7.461 |
23 | 2.311 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[19]_3_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.017 | 7.361 |
24 | 2.336 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_6_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.001 | 7.354 |
25 | 2.336 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_10_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.001 | 7.354 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.193 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] | clk:[R] | clk:[R] | 0.000 | -0.005 | 0.235 |
2 | 0.212 | sim_output_storage_inst/ram_din_data_11_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/DI[11] | clk:[R] | clk:[R] | 0.000 | 0.026 | 0.223 |
3 | 0.213 | sim_output_storage_inst/ram_dout_addrb_6_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[10] | clk:[R] | clk:[R] | 0.000 | 0.016 | 0.232 |
4 | 0.216 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1] | clk:[R] | clk:[R] | 0.000 | -0.005 | 0.258 |
5 | 0.216 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] | clk:[R] | clk:[R] | 0.000 | -0.005 | 0.258 |
6 | 0.252 | sim_output_storage_inst/ram_din_data_10_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/DI[10] | clk:[R] | clk:[R] | 0.000 | 0.026 | 0.263 |
7 | 0.275 | sim_input_gen_inst/cnt_chn_0_s1/Q | sim_input_gen_inst/cnt_chn_0_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
8 | 0.275 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_3_s1/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_3_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
9 | 0.275 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_1_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_1_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
10 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
11 | 0.275 | gw_gao_inst_0/u_la0_top/word_count_12_s0/Q | gw_gao_inst_0/u_la0_top/word_count_12_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
12 | 0.278 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_2_s1/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_2_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.303 |
13 | 0.278 | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.303 |
14 | 0.278 | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.303 |
15 | 0.280 | sim_output_storage_inst/ram_dout_addrb_0_s3/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[4] | clk:[R] | clk:[R] | 0.000 | 0.020 | 0.295 |
16 | 0.281 | sim_output_storage_inst/ram_dout_addrb_7_s0/Q | sim_output_storage_inst/ram_dout_addrb_7_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.306 |
17 | 0.281 | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.306 |
18 | 0.287 | sim_output_storage_inst/ram_dout_addrb_4_s0/Q | sim_output_storage_inst/ram_dout_addrb_4_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.312 |
19 | 0.287 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_data_addrb_0_s1/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_data_addrb_0_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.312 |
20 | 0.287 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_3_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_3_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.312 |
21 | 0.287 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_5_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_5_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.312 |
22 | 0.287 | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.312 |
23 | 0.287 | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.312 |
24 | 0.289 | sim_output_storage_inst/ram_dout_addrb_5_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[9] | clk:[R] | clk:[R] | 0.000 | 0.016 | 0.308 |
25 | 0.290 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.315 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 3.544 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.012 | 1.096 |
2 | 3.544 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.012 | 1.096 |
3 | 3.544 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.012 | 1.096 |
4 | 3.544 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.012 | 1.096 |
5 | 3.544 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.012 | 1.096 |
6 | 3.544 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.012 | 1.096 |
7 | 3.556 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.001 | 1.096 |
8 | 3.556 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.001 | 1.096 |
9 | 3.556 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.001 | 1.096 |
10 | 3.556 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.001 | 1.096 |
11 | 3.558 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.056 | 1.039 |
12 | 3.601 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.006 | 1.046 |
13 | 3.601 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.006 | 1.046 |
14 | 3.601 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.006 | 1.046 |
15 | 3.603 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.003 | 1.046 |
16 | 3.603 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.003 | 1.046 |
17 | 3.603 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.003 | 1.046 |
18 | 3.603 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.003 | 1.046 |
19 | 3.603 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.003 | 1.046 |
20 | 3.613 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.037 | 1.003 |
21 | 3.613 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.037 | 1.003 |
22 | 3.613 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.037 | 1.003 |
23 | 3.624 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.009 | 1.037 |
24 | 3.624 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | -0.009 | 1.037 |
25 | 3.624 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | clk:[F] | clk:[R] | 5.000 | -0.009 | 1.037 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 5.322 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.006 | 0.263 |
2 | 5.418 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.004 | 0.361 |
3 | 5.428 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.010 | 0.365 |
4 | 5.428 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.010 | 0.365 |
5 | 5.428 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.010 | 0.365 |
6 | 5.435 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.016 | 0.366 |
7 | 5.435 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.016 | 0.366 |
8 | 5.442 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.011 | 0.378 |
9 | 5.442 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.011 | 0.378 |
10 | 5.442 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.011 | 0.378 |
11 | 5.442 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.011 | 0.378 |
12 | 5.442 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk:[F] | clk:[R] | -5.000 | 0.015 | 0.374 |
13 | 5.442 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.015 | 0.374 |
14 | 5.507 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.453 |
15 | 5.507 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.035 | 0.419 |
16 | 5.510 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.008 | 0.449 |
17 | 5.510 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.008 | 0.449 |
18 | 5.515 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.001 | 0.463 |
19 | 5.526 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.026 | 0.447 |
20 | 5.526 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.026 | 0.447 |
21 | 5.526 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.026 | 0.447 |
22 | 5.528 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.003 | 0.478 |
23 | 5.528 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.003 | 0.478 |
24 | 5.528 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | clk:[F] | clk:[R] | -5.000 | -0.003 | 0.478 |
25 | 5.528 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | -0.003 | 0.478 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.751 | 3.751 | 1.000 | Low Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
2 | 2.754 | 3.754 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[2].mult_dsp_inst/n47_s1 |
3 | 2.754 | 3.754 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[10].mult_dsp_inst/n47_s1 |
4 | 2.754 | 3.754 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[11].mult_dsp_inst/n47_s1 |
5 | 2.757 | 3.757 | 1.000 | Low Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
6 | 2.757 | 3.757 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
7 | 2.759 | 3.759 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[8].mult_dsp_inst/n47_s1 |
8 | 2.759 | 3.759 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1 |
9 | 2.759 | 3.759 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[3].mult_dsp_inst/n47_s1 |
10 | 2.759 | 3.759 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[4].mult_dsp_inst/n47_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.459 |
Data Arrival Time | 11.084 |
Data Required Time | 12.543 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.614 | 1.931 | tNET | RR | 1 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK |
2.996 | 0.382 | tC2Q | RR | 2 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q |
3.136 | 0.140 | tNET | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0 |
3.658 | 0.521 | tINS | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F |
3.934 | 0.276 | tNET | RR | 24 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0] |
8.133 | 4.199 | tINS | RR | 2 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[0] |
9.264 | 1.131 | tNET | RR | 2 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/I0 |
9.826 | 0.563 | tINS | RF | 1 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/COUT |
9.826 | 0.000 | tNET | FF | 2 | R30C80[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1171_s/CIN |
9.876 | 0.050 | tINS | FR | 1 | R30C80[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1171_s/COUT |
9.876 | 0.000 | tNET | RR | 2 | R30C80[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1170_s/CIN |
9.926 | 0.050 | tINS | RR | 1 | R30C80[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1170_s/COUT |
9.926 | 0.000 | tNET | RR | 2 | R30C80[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1169_s/CIN |
9.976 | 0.050 | tINS | RR | 1 | R30C80[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1169_s/COUT |
10.568 | 0.591 | tNET | RR | 1 | R29C78[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1173_s2/I2 |
11.084 | 0.516 | tINS | RR | 1 | R29C78[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1173_s2/F |
11.084 | 0.000 | tNET | RR | 1 | R29C78[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.607 | 1.924 | tNET | RR | 1 | R29C78[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_4_s0/CLK |
12.543 | -0.064 | tSu | 1 | R29C78[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_4_s0 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Arrival Data Path Delay | cell: 5.949, 70.233%; route: 2.139, 25.251%; tC2Q: 0.382, 4.516% |
Required Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Path2
Path Summary:
Slack | 1.676 |
Data Arrival Time | 10.841 |
Data Required Time | 12.517 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.614 | 1.931 | tNET | RR | 1 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK |
2.996 | 0.382 | tC2Q | RR | 2 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q |
3.136 | 0.140 | tNET | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0 |
3.658 | 0.521 | tINS | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F |
3.934 | 0.276 | tNET | RR | 24 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0] |
8.133 | 4.199 | tINS | RR | 2 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[0] |
9.264 | 1.131 | tNET | RR | 2 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/I0 |
9.826 | 0.563 | tINS | RF | 1 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/COUT |
9.826 | 0.000 | tNET | FF | 2 | R30C80[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1171_s/CIN |
9.876 | 0.050 | tINS | FR | 1 | R30C80[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1171_s/COUT |
9.876 | 0.000 | tNET | RR | 2 | R30C80[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1170_s/CIN |
9.926 | 0.050 | tINS | RR | 1 | R30C80[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1170_s/COUT |
9.926 | 0.000 | tNET | RR | 2 | R30C80[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1169_s/CIN |
10.223 | 0.296 | tINS | RR | 1 | R30C80[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1169_s/SUM |
10.380 | 0.157 | tNET | RR | 1 | R30C79[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1174_s0/I1 |
10.841 | 0.461 | tINS | RR | 1 | R30C79[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1174_s0/F |
10.841 | 0.000 | tNET | RR | 1 | R30C79[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.581 | 1.898 | tNET | RR | 1 | R30C79[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_3_s0/CLK |
12.517 | -0.064 | tSu | 1 | R30C79[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_3_s0 |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Arrival Data Path Delay | cell: 6.140, 74.628%; route: 1.705, 20.723%; tC2Q: 0.382, 4.649% |
Required Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
Path3
Path Summary:
Slack | 1.711 |
Data Arrival Time | 10.806 |
Data Required Time | 12.517 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.614 | 1.931 | tNET | RR | 1 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK |
2.996 | 0.382 | tC2Q | RR | 2 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q |
3.136 | 0.140 | tNET | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0 |
3.658 | 0.521 | tINS | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F |
3.934 | 0.276 | tNET | RR | 24 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0] |
8.133 | 4.199 | tINS | RR | 2 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[0] |
9.264 | 1.131 | tNET | RR | 2 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/I0 |
9.826 | 0.563 | tINS | RF | 1 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/COUT |
9.826 | 0.000 | tNET | FF | 2 | R30C80[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1171_s/CIN |
10.123 | 0.296 | tINS | FR | 1 | R30C80[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1171_s/SUM |
10.280 | 0.157 | tNET | RR | 1 | R30C79[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1176_s0/I1 |
10.806 | 0.526 | tINS | RR | 1 | R30C79[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1176_s0/F |
10.806 | 0.000 | tNET | RR | 1 | R30C79[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.581 | 1.898 | tNET | RR | 1 | R30C79[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_1_s0/CLK |
12.517 | -0.064 | tSu | 1 | R30C79[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_1_s0 |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Arrival Data Path Delay | cell: 6.105, 74.520%; route: 1.705, 20.812%; tC2Q: 0.382, 4.669% |
Required Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
Path4
Path Summary:
Slack | 1.735 |
Data Arrival Time | 10.783 |
Data Required Time | 12.517 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.614 | 1.931 | tNET | RR | 1 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK |
2.996 | 0.382 | tC2Q | RR | 2 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q |
3.136 | 0.140 | tNET | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0 |
3.658 | 0.521 | tINS | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F |
3.934 | 0.276 | tNET | RR | 24 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0] |
8.133 | 4.199 | tINS | RR | 2 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[0] |
9.264 | 1.131 | tNET | RR | 2 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/I0 |
9.994 | 0.730 | tINS | RR | 1 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/SUM |
10.321 | 0.327 | tNET | RR | 1 | R30C79[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1177_s0/I1 |
10.783 | 0.461 | tINS | RR | 1 | R30C79[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1177_s0/F |
10.783 | 0.000 | tNET | RR | 1 | R30C79[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.581 | 1.898 | tNET | RR | 1 | R30C79[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_0_s0/CLK |
12.517 | -0.064 | tSu | 1 | R30C79[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_0_s0 |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 10.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Arrival Data Path Delay | cell: 5.911, 72.364%; route: 1.875, 22.953%; tC2Q: 0.382, 4.682% |
Required Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
Path5
Path Summary:
Slack | 1.977 |
Data Arrival Time | 10.540 |
Data Required Time | 12.517 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_2_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.614 | 1.931 | tNET | RR | 1 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK |
2.996 | 0.382 | tC2Q | RR | 2 | R18C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q |
3.136 | 0.140 | tNET | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0 |
3.658 | 0.521 | tINS | RR | 1 | R18C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F |
3.934 | 0.276 | tNET | RR | 24 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0] |
8.133 | 4.199 | tINS | RR | 2 | DSP_R19[23][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[0] |
9.264 | 1.131 | tNET | RR | 2 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/I0 |
9.826 | 0.563 | tINS | RF | 1 | R30C80[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1172_s/COUT |
9.826 | 0.000 | tNET | FF | 2 | R30C80[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1171_s/CIN |
9.876 | 0.050 | tINS | FR | 1 | R30C80[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1171_s/COUT |
9.876 | 0.000 | tNET | RR | 2 | R30C80[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1170_s/CIN |
10.120 | 0.244 | tINS | RR | 1 | R30C80[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1170_s/SUM |
10.278 | 0.157 | tNET | RR | 1 | R30C79[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1175_s0/I1 |
10.540 | 0.262 | tINS | RR | 1 | R30C79[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n1175_s0/F |
10.540 | 0.000 | tNET | RR | 1 | R30C79[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.581 | 1.898 | tNET | RR | 1 | R30C79[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_2_s0/CLK |
12.517 | -0.064 | tSu | 1 | R30C79[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_2_s0 |
Path Statistics:
Clock Skew | -0.033 |
Setup Relationship | 10.000 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Arrival Data Path Delay | cell: 5.839, 73.664%; route: 1.705, 21.511%; tC2Q: 0.382, 4.826% |
Required Clock Path Delay | cell: 0.683, 26.444%; route: 1.898, 73.556% |
Path6
Path Summary:
Slack | 2.090 |
Data Arrival Time | 10.207 |
Data Required Time | 12.297 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_7_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.401 | 0.559 | tNET | RR | 1 | R32C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1979_s3/I0 |
4.922 | 0.521 | tINS | RR | 13 | R32C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1979_s3/F |
7.512 | 2.590 | tNET | RR | 1 | R32C22[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1979_s0/I0 |
7.973 | 0.461 | tINS | RR | 16 | R32C22[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1979_s0/F |
10.207 | 2.234 | tNET | RR | 1 | R33C74[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.608 | 1.926 | tNET | RR | 1 | R33C74[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_7_s0/CLK |
12.297 | -0.311 | tSu | 1 | R33C74[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_7_s0 |
Path Statistics:
Clock Skew | 0.001 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.480, 19.474%; route: 5.737, 75.493%; tC2Q: 0.382, 5.033% |
Required Clock Path Delay | cell: 0.683, 26.168%; route: 1.926, 73.832% |
Path7
Path Summary:
Slack | 2.096 |
Data Arrival Time | 10.183 |
Data Required Time | 12.279 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_13_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.206 | 0.364 | tNET | RR | 1 | R30C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2027_s3/I0 |
4.621 | 0.415 | tINS | RR | 13 | R30C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2027_s3/F |
7.516 | 2.895 | tNET | RR | 1 | R33C22[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2027_s0/I0 |
8.013 | 0.498 | tINS | RR | 16 | R33C22[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2027_s0/F |
10.183 | 2.170 | tNET | RR | 1 | R30C72[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.590 | 1.908 | tNET | RR | 1 | R30C72[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_13_s0/CLK |
12.279 | -0.311 | tSu | 1 | R30C72[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_13_s0 |
Path Statistics:
Clock Skew | -0.017 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.410, 18.611%; route: 5.784, 76.341%; tC2Q: 0.382, 5.049% |
Required Clock Path Delay | cell: 0.683, 26.348%; route: 1.908, 73.652% |
Path8
Path Summary:
Slack | 2.096 |
Data Arrival Time | 10.183 |
Data Required Time | 12.279 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_10_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.206 | 0.364 | tNET | RR | 1 | R30C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2027_s3/I0 |
4.621 | 0.415 | tINS | RR | 13 | R30C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2027_s3/F |
7.516 | 2.895 | tNET | RR | 1 | R33C22[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2027_s0/I0 |
8.013 | 0.498 | tINS | RR | 16 | R33C22[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2027_s0/F |
10.183 | 2.170 | tNET | RR | 1 | R30C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.590 | 1.908 | tNET | RR | 1 | R30C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_10_s0/CLK |
12.279 | -0.311 | tSu | 1 | R30C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_10_s0 |
Path Statistics:
Clock Skew | -0.017 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.410, 18.611%; route: 5.784, 76.341%; tC2Q: 0.382, 5.049% |
Required Clock Path Delay | cell: 0.683, 26.348%; route: 1.908, 73.652% |
Path9
Path Summary:
Slack | 2.096 |
Data Arrival Time | 10.183 |
Data Required Time | 12.279 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.206 | 0.364 | tNET | RR | 1 | R30C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2027_s3/I0 |
4.621 | 0.415 | tINS | RR | 13 | R30C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2027_s3/F |
7.516 | 2.895 | tNET | RR | 1 | R33C22[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2027_s0/I0 |
8.013 | 0.498 | tINS | RR | 16 | R33C22[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2027_s0/F |
10.183 | 2.170 | tNET | RR | 1 | R30C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.590 | 1.908 | tNET | RR | 1 | R30C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_4_s0/CLK |
12.279 | -0.311 | tSu | 1 | R30C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_4_s0 |
Path Statistics:
Clock Skew | -0.017 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.410, 18.611%; route: 5.784, 76.341%; tC2Q: 0.382, 5.049% |
Required Clock Path Delay | cell: 0.683, 26.348%; route: 1.908, 73.652% |
Path10
Path Summary:
Slack | 2.096 |
Data Arrival Time | 10.183 |
Data Required Time | 12.279 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.206 | 0.364 | tNET | RR | 1 | R30C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2027_s3/I0 |
4.621 | 0.415 | tINS | RR | 13 | R30C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2027_s3/F |
7.516 | 2.895 | tNET | RR | 1 | R33C22[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2027_s0/I0 |
8.013 | 0.498 | tINS | RR | 16 | R33C22[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2027_s0/F |
10.183 | 2.170 | tNET | RR | 1 | R30C72[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.590 | 1.908 | tNET | RR | 1 | R30C72[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_1_s0/CLK |
12.279 | -0.311 | tSu | 1 | R30C72[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[4]_1_s0 |
Path Statistics:
Clock Skew | -0.017 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.410, 18.611%; route: 5.784, 76.341%; tC2Q: 0.382, 5.049% |
Required Clock Path Delay | cell: 0.683, 26.348%; route: 1.908, 73.652% |
Path11
Path Summary:
Slack | 2.129 |
Data Arrival Time | 10.162 |
Data Required Time | 12.291 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_10_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.401 | 0.559 | tNET | RR | 1 | R32C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1979_s3/I0 |
4.922 | 0.521 | tINS | RR | 13 | R32C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1979_s3/F |
7.512 | 2.590 | tNET | RR | 1 | R32C22[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1979_s0/I0 |
7.973 | 0.461 | tINS | RR | 16 | R32C22[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1979_s0/F |
10.162 | 2.189 | tNET | RR | 1 | R32C68[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.602 | 1.920 | tNET | RR | 1 | R32C68[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_10_s0/CLK |
12.291 | -0.311 | tSu | 1 | R32C68[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[1]_10_s0 |
Path Statistics:
Clock Skew | -0.005 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.480, 19.590%; route: 5.692, 75.347%; tC2Q: 0.382, 5.063% |
Required Clock Path Delay | cell: 0.683, 26.228%; route: 1.920, 73.772% |
Path12
Path Summary:
Slack | 2.137 |
Data Arrival Time | 10.142 |
Data Required Time | 12.279 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_11_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.187 | 0.197 | tNET | RR | 1 | R31C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2091_s2/I1 |
3.684 | 0.498 | tINS | RR | 8 | R31C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2091_s2/F |
3.849 | 0.165 | tNET | RR | 1 | R31C79[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2155_s2/I3 |
4.311 | 0.461 | tINS | RR | 13 | R31C79[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2155_s2/F |
7.516 | 3.205 | tNET | RR | 1 | R32C20[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2155_s0/I0 |
7.977 | 0.461 | tINS | RR | 16 | R32C20[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2155_s0/F |
10.142 | 2.165 | tNET | RR | 1 | R30C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_11_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.590 | 1.908 | tNET | RR | 1 | R30C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_11_s0/CLK |
12.279 | -0.311 | tSu | 1 | R30C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_11_s0 |
Path Statistics:
Clock Skew | -0.017 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.420, 18.845%; route: 5.732, 76.078%; tC2Q: 0.382, 5.076% |
Required Clock Path Delay | cell: 0.683, 26.348%; route: 1.908, 73.652% |
Path13
Path Summary:
Slack | 2.137 |
Data Arrival Time | 10.142 |
Data Required Time | 12.279 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.187 | 0.197 | tNET | RR | 1 | R31C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2091_s2/I1 |
3.684 | 0.498 | tINS | RR | 8 | R31C78[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2091_s2/F |
3.849 | 0.165 | tNET | RR | 1 | R31C79[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2155_s2/I3 |
4.311 | 0.461 | tINS | RR | 13 | R31C79[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2155_s2/F |
7.516 | 3.205 | tNET | RR | 1 | R32C20[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2155_s0/I0 |
7.977 | 0.461 | tINS | RR | 16 | R32C20[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2155_s0/F |
10.142 | 2.165 | tNET | RR | 1 | R30C72[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.590 | 1.908 | tNET | RR | 1 | R30C72[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_4_s0/CLK |
12.279 | -0.311 | tSu | 1 | R30C72[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[12]_4_s0 |
Path Statistics:
Clock Skew | -0.017 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.420, 18.845%; route: 5.732, 76.078%; tC2Q: 0.382, 5.076% |
Required Clock Path Delay | cell: 0.683, 26.348%; route: 1.908, 73.652% |
Path14
Path Summary:
Slack | 2.202 |
Data Arrival Time | 10.083 |
Data Required Time | 12.285 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_13_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.586 | 0.744 | tNET | RR | 1 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/I0 |
5.047 | 0.461 | tINS | RR | 13 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/F |
7.676 | 2.629 | tNET | RR | 1 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/I0 |
7.938 | 0.262 | tINS | RR | 16 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/F |
10.083 | 2.145 | tNET | RR | 1 | R31C72[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.596 | 1.914 | tNET | RR | 1 | R31C72[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_13_s0/CLK |
12.285 | -0.311 | tSu | 1 | R31C72[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_13_s0 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.221, 16.335%; route: 5.872, 78.549%; tC2Q: 0.382, 5.116% |
Required Clock Path Delay | cell: 0.683, 26.288%; route: 1.914, 73.712% |
Path15
Path Summary:
Slack | 2.202 |
Data Arrival Time | 10.083 |
Data Required Time | 12.285 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_10_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.586 | 0.744 | tNET | RR | 1 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/I0 |
5.047 | 0.461 | tINS | RR | 13 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/F |
7.676 | 2.629 | tNET | RR | 1 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/I0 |
7.938 | 0.262 | tINS | RR | 16 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/F |
10.083 | 2.145 | tNET | RR | 1 | R31C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.596 | 1.914 | tNET | RR | 1 | R31C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_10_s0/CLK |
12.285 | -0.311 | tSu | 1 | R31C72[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_10_s0 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.221, 16.335%; route: 5.872, 78.549%; tC2Q: 0.382, 5.116% |
Required Clock Path Delay | cell: 0.683, 26.288%; route: 1.914, 73.712% |
Path16
Path Summary:
Slack | 2.202 |
Data Arrival Time | 10.083 |
Data Required Time | 12.285 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.586 | 0.744 | tNET | RR | 1 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/I0 |
5.047 | 0.461 | tINS | RR | 13 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/F |
7.676 | 2.629 | tNET | RR | 1 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/I0 |
7.938 | 0.262 | tINS | RR | 16 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/F |
10.083 | 2.145 | tNET | RR | 1 | R31C72[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.596 | 1.914 | tNET | RR | 1 | R31C72[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_4_s0/CLK |
12.285 | -0.311 | tSu | 1 | R31C72[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_4_s0 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.221, 16.335%; route: 5.872, 78.549%; tC2Q: 0.382, 5.116% |
Required Clock Path Delay | cell: 0.683, 26.288%; route: 1.914, 73.712% |
Path17
Path Summary:
Slack | 2.202 |
Data Arrival Time | 10.083 |
Data Required Time | 12.285 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_2_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.586 | 0.744 | tNET | RR | 1 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/I0 |
5.047 | 0.461 | tINS | RR | 13 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/F |
7.676 | 2.629 | tNET | RR | 1 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/I0 |
7.938 | 0.262 | tINS | RR | 16 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/F |
10.083 | 2.145 | tNET | RR | 1 | R31C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.596 | 1.914 | tNET | RR | 1 | R31C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_2_s0/CLK |
12.285 | -0.311 | tSu | 1 | R31C72[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_2_s0 |
Path Statistics:
Clock Skew | -0.011 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.221, 16.335%; route: 5.872, 78.549%; tC2Q: 0.382, 5.116% |
Required Clock Path Delay | cell: 0.683, 26.288%; route: 1.914, 73.712% |
Path18
Path Summary:
Slack | 2.227 |
Data Arrival Time | 10.068 |
Data Required Time | 12.296 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_15_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_3_s0/Q |
3.344 | 0.355 | tNET | RR | 1 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/I0 |
3.842 | 0.498 | tINS | RR | 8 | R31C79[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1964_s5/F |
4.586 | 0.744 | tNET | RR | 1 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/I0 |
5.047 | 0.461 | tINS | RR | 13 | R34C76[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n1995_s3/F |
7.676 | 2.629 | tNET | RR | 1 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/I0 |
7.938 | 0.262 | tINS | RR | 16 | R33C22[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1995_s0/F |
10.068 | 2.130 | tNET | RR | 1 | R29C66[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_15_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.607 | 1.924 | tNET | RR | 1 | R29C66[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_15_s0/CLK |
12.296 | -0.311 | tSu | 1 | R29C66[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[2]_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.221, 16.368%; route: 5.858, 78.506%; tC2Q: 0.382, 5.126% |
Required Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Path19
Path Summary:
Slack | 2.237 |
Data Arrival Time | 10.068 |
Data Required Time | 12.305 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_7_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q |
3.137 | 0.147 | tNET | RR | 1 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/I1 |
3.653 | 0.516 | tINS | RR | 8 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/F |
4.011 | 0.357 | tNET | RR | 1 | R30C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2299_s2/I3 |
4.276 | 0.265 | tINS | RR | 13 | R30C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2299_s2/F |
7.044 | 2.769 | tNET | RR | 1 | R32C20[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2299_s0/I0 |
7.566 | 0.521 | tINS | RR | 16 | R32C20[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2299_s0/F |
10.068 | 2.503 | tNET | RR | 1 | R29C73[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.616 | 1.934 | tNET | RR | 1 | R29C73[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_7_s0/CLK |
12.305 | -0.311 | tSu | 1 | R29C73[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_7_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.303, 17.457%; route: 5.776, 77.417%; tC2Q: 0.382, 5.126% |
Required Clock Path Delay | cell: 0.683, 26.087%; route: 1.934, 73.913% |
Path20
Path Summary:
Slack | 2.237 |
Data Arrival Time | 10.068 |
Data Required Time | 12.305 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_9_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q |
3.137 | 0.147 | tNET | RR | 1 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/I1 |
3.653 | 0.516 | tINS | RR | 8 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/F |
4.011 | 0.357 | tNET | RR | 1 | R30C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2299_s2/I3 |
4.276 | 0.265 | tINS | RR | 13 | R30C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2299_s2/F |
7.044 | 2.769 | tNET | RR | 1 | R32C20[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2299_s0/I0 |
7.566 | 0.521 | tINS | RR | 16 | R32C20[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2299_s0/F |
10.068 | 2.503 | tNET | RR | 1 | R29C73[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_9_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.616 | 1.934 | tNET | RR | 1 | R29C73[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_9_s0/CLK |
12.305 | -0.311 | tSu | 1 | R29C73[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_9_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.303, 17.457%; route: 5.776, 77.417%; tC2Q: 0.382, 5.126% |
Required Clock Path Delay | cell: 0.683, 26.087%; route: 1.934, 73.913% |
Path21
Path Summary:
Slack | 2.237 |
Data Arrival Time | 10.068 |
Data Required Time | 12.305 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_11_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q |
3.137 | 0.147 | tNET | RR | 1 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/I1 |
3.653 | 0.516 | tINS | RR | 8 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/F |
4.011 | 0.357 | tNET | RR | 1 | R30C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2299_s2/I3 |
4.276 | 0.265 | tINS | RR | 13 | R30C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2299_s2/F |
7.044 | 2.769 | tNET | RR | 1 | R32C20[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2299_s0/I0 |
7.566 | 0.521 | tINS | RR | 16 | R32C20[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2299_s0/F |
10.068 | 2.503 | tNET | RR | 1 | R29C73[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_11_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.616 | 1.934 | tNET | RR | 1 | R29C73[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_11_s0/CLK |
12.305 | -0.311 | tSu | 1 | R29C73[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_11_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.303, 17.457%; route: 5.776, 77.417%; tC2Q: 0.382, 5.126% |
Required Clock Path Delay | cell: 0.683, 26.087%; route: 1.934, 73.913% |
Path22
Path Summary:
Slack | 2.237 |
Data Arrival Time | 10.068 |
Data Required Time | 12.305 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_15_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q |
3.137 | 0.147 | tNET | RR | 1 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/I1 |
3.653 | 0.516 | tINS | RR | 8 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/F |
4.011 | 0.357 | tNET | RR | 1 | R30C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2299_s2/I3 |
4.276 | 0.265 | tINS | RR | 13 | R30C76[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2299_s2/F |
7.044 | 2.769 | tNET | RR | 1 | R32C20[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2299_s0/I0 |
7.566 | 0.521 | tINS | RR | 16 | R32C20[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2299_s0/F |
10.068 | 2.503 | tNET | RR | 1 | R29C73[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_15_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.616 | 1.934 | tNET | RR | 1 | R29C73[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_15_s0/CLK |
12.305 | -0.311 | tSu | 1 | R29C73[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[21]_15_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.303, 17.457%; route: 5.776, 77.417%; tC2Q: 0.382, 5.126% |
Required Clock Path Delay | cell: 0.683, 26.087%; route: 1.934, 73.913% |
Path23
Path Summary:
Slack | 2.311 |
Data Arrival Time | 9.968 |
Data Required Time | 12.279 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[19]_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.607 | 1.924 | tNET | RR | 1 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/CLK |
2.989 | 0.382 | tC2Q | RR | 6 | R29C78[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_4_s0/Q |
3.137 | 0.147 | tNET | RR | 1 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/I1 |
3.653 | 0.516 | tINS | RR | 8 | R29C78[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2219_s2/F |
4.013 | 0.360 | tNET | RR | 1 | R29C76[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/I3 |
4.529 | 0.516 | tINS | RR | 13 | R29C76[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/F |
7.471 | 2.941 | tNET | RR | 1 | R32C21[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2267_s0/I0 |
7.886 | 0.415 | tINS | RR | 16 | R32C21[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2267_s0/F |
9.968 | 2.082 | tNET | RR | 1 | R30C66[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[19]_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.590 | 1.908 | tNET | RR | 1 | R30C66[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[19]_3_s0/CLK |
12.279 | -0.311 | tSu | 1 | R30C66[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[19]_3_s0 |
Path Statistics:
Clock Skew | -0.017 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Arrival Data Path Delay | cell: 1.447, 19.664%; route: 5.531, 75.140%; tC2Q: 0.382, 5.196% |
Required Clock Path Delay | cell: 0.683, 26.348%; route: 1.908, 73.652% |
Path24
Path Summary:
Slack | 2.336 |
Data Arrival Time | 9.952 |
Data Required Time | 12.288 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_6_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.599 | 1.916 | tNET | RR | 1 | R33C75[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
2.981 | 0.382 | tC2Q | RR | 7 | R33C75[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
3.586 | 0.605 | tNET | RR | 1 | R34C74[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[8].spram_coeff_inst/n1964_s2/I2 |
4.108 | 0.521 | tINS | RR | 5 | R34C74[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[8].spram_coeff_inst/n1964_s2/F |
6.055 | 1.947 | tNET | RR | 1 | R32C34[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1964_s2/I3 |
6.317 | 0.262 | tINS | RR | 28 | R32C34[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1964_s2/F |
7.367 | 1.050 | tNET | RR | 1 | R33C21[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2203_s0/I1 |
7.865 | 0.498 | tINS | RR | 16 | R33C21[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2203_s0/F |
9.952 | 2.087 | tNET | RR | 1 | R30C73[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_6_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.600 | 1.917 | tNET | RR | 1 | R30C73[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_6_s0/CLK |
12.288 | -0.311 | tSu | 1 | R30C73[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_6_s0 |
Path Statistics:
Clock Skew | 0.001 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Arrival Data Path Delay | cell: 1.281, 17.423%; route: 5.690, 77.375%; tC2Q: 0.382, 5.201% |
Required Clock Path Delay | cell: 0.683, 26.253%; route: 1.917, 73.747% |
Path25
Path Summary:
Slack | 2.336 |
Data Arrival Time | 9.952 |
Data Required Time | 12.288 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_10_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
2.599 | 1.916 | tNET | RR | 1 | R33C75[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
2.981 | 0.382 | tC2Q | RR | 7 | R33C75[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
3.586 | 0.605 | tNET | RR | 1 | R34C74[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[8].spram_coeff_inst/n1964_s2/I2 |
4.108 | 0.521 | tINS | RR | 5 | R34C74[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[8].spram_coeff_inst/n1964_s2/F |
6.055 | 1.947 | tNET | RR | 1 | R32C34[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1964_s2/I3 |
6.317 | 0.262 | tINS | RR | 28 | R32C34[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n1964_s2/F |
7.367 | 1.050 | tNET | RR | 1 | R33C21[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2203_s0/I1 |
7.865 | 0.498 | tINS | RR | 16 | R33C21[3][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/n2203_s0/F |
9.952 | 2.087 | tNET | RR | 1 | R30C73[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.600 | 1.917 | tNET | RR | 1 | R30C73[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_10_s0/CLK |
12.288 | -0.311 | tSu | 1 | R30C73[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[11].spram_coeff_inst/mem[15]_10_s0 |
Path Statistics:
Clock Skew | 0.001 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Arrival Data Path Delay | cell: 1.281, 17.423%; route: 5.690, 77.375%; tC2Q: 0.382, 5.201% |
Required Clock Path Delay | cell: 0.683, 26.253%; route: 1.917, 73.747% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.193 |
Data Arrival Time | 1.604 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C86[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 1 | R11C86[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q |
1.604 | 0.094 | tNET | FF | 1 | BSRAM_R10[27] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[27] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[27] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path2
Path Summary:
Slack | 0.212 |
Data Arrival Time | 1.624 |
Data Required Time | 1.411 |
From | sim_output_storage_inst/ram_din_data_11_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.401 | 0.725 | tNET | RR | 1 | R3C57[0][B] | sim_output_storage_inst/ram_din_data_11_s0/CLK |
1.542 | 0.141 | tC2Q | RF | 1 | R3C57[0][B] | sim_output_storage_inst/ram_din_data_11_s0/Q |
1.624 | 0.082 | tNET | FF | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/DI[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.026 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.233%; route: 0.725, 51.767% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.082, 36.771%; tC2Q: 0.141, 63.229% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path3
Path Summary:
Slack | 0.213 |
Data Arrival Time | 1.627 |
Data Required Time | 1.413 |
From | sim_output_storage_inst/ram_dout_addrb_6_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C56[0][A] | sim_output_storage_inst/ram_dout_addrb_6_s0/CLK |
1.536 | 0.141 | tC2Q | RF | 4 | R4C56[0][A] | sim_output_storage_inst/ram_dout_addrb_6_s0/Q |
1.627 | 0.091 | tNET | FF | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
1.413 | 0.035 | tHld | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.016 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.091, 39.224%; tC2Q: 0.141, 60.776% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path4
Path Summary:
Slack | 0.216 |
Data Arrival Time | 1.627 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C86[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 1 | R11C86[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q |
1.627 | 0.117 | tNET | FF | 1 | BSRAM_R10[27] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[27] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[27] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path5
Path Summary:
Slack | 0.216 |
Data Arrival Time | 1.627 |
Data Required Time | 1.411 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C86[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 1 | R11C86[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q |
1.627 | 0.117 | tNET | FF | 1 | BSRAM_R10[27] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[27] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[27] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path6
Path Summary:
Slack | 0.252 |
Data Arrival Time | 1.664 |
Data Required Time | 1.411 |
From | sim_output_storage_inst/ram_din_data_10_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.401 | 0.725 | tNET | RR | 1 | R3C57[0][A] | sim_output_storage_inst/ram_din_data_10_s0/CLK |
1.542 | 0.141 | tC2Q | RF | 1 | R3C57[0][A] | sim_output_storage_inst/ram_din_data_10_s0/Q |
1.664 | 0.122 | tNET | FF | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/DI[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.026 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.233%; route: 0.725, 51.767% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.122, 46.388%; tC2Q: 0.141, 53.612% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path7
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.702 |
Data Required Time | 1.427 |
From | sim_input_gen_inst/cnt_chn_0_s1 |
To | sim_input_gen_inst/cnt_chn_0_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R2C49[0][A] | sim_input_gen_inst/cnt_chn_0_s1/CLK |
1.543 | 0.141 | tC2Q | RF | 5 | R2C49[0][A] | sim_input_gen_inst/cnt_chn_0_s1/Q |
1.549 | 0.006 | tNET | FF | 1 | R2C49[0][A] | sim_input_gen_inst/n69_s3/I2 |
1.702 | 0.153 | tINS | FF | 1 | R2C49[0][A] | sim_input_gen_inst/n69_s3/F |
1.702 | 0.000 | tNET | FF | 1 | R2C49[0][A] | sim_input_gen_inst/cnt_chn_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R2C49[0][A] | sim_input_gen_inst/cnt_chn_0_s1/CLK |
1.427 | 0.025 | tHld | 1 | R2C49[0][A] | sim_input_gen_inst/cnt_chn_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Path8
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.695 |
Data Required Time | 1.420 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_3_s1 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_3_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C44[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_3_s1/CLK |
1.536 | 0.141 | tC2Q | RF | 2 | R4C44[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_3_s1/Q |
1.542 | 0.006 | tNET | FF | 1 | R4C44[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n429_s0/I2 |
1.695 | 0.153 | tINS | FF | 1 | R4C44[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n429_s0/F |
1.695 | 0.000 | tNET | FF | 1 | R4C44[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C44[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_3_s1/CLK |
1.420 | 0.025 | tHld | 1 | R4C44[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Path9
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.698 |
Data Required Time | 1.423 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_1_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R2C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_1_s0/CLK |
1.539 | 0.141 | tC2Q | RF | 2 | R2C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_1_s0/Q |
1.545 | 0.006 | tNET | FF | 1 | R2C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n2527_s1/I1 |
1.698 | 0.153 | tINS | FF | 1 | R2C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n2527_s1/F |
1.698 | 0.000 | tNET | FF | 1 | R2C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R2C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_1_s0/CLK |
1.423 | 0.025 | tHld | 1 | R2C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Path10
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.689 |
Data Required Time | 1.413 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.388 | 0.713 | tNET | RR | 1 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
1.530 | 0.141 | tC2Q | RF | 2 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q |
1.536 | 0.006 | tNET | FF | 1 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n232_s0/I2 |
1.689 | 0.153 | tINS | FF | 1 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n232_s0/F |
1.689 | 0.000 | tNET | FF | 1 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.388 | 0.713 | tNET | RR | 1 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
1.413 | 0.025 | tHld | 1 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.650%; route: 0.713, 51.350% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.650%; route: 0.713, 51.350% |
Path11
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.708 |
Data Required Time | 2.433 |
From | gw_gao_inst_0/u_la0_top/word_count_12_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_12_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.408 | 1.057 | tNET | RR | 1 | R29C91[0][A] | gw_gao_inst_0/u_la0_top/word_count_12_s0/CLK |
2.549 | 0.141 | tC2Q | RF | 4 | R29C91[0][A] | gw_gao_inst_0/u_la0_top/word_count_12_s0/Q |
2.555 | 0.006 | tNET | FF | 1 | R29C91[0][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_12_s0/I1 |
2.708 | 0.153 | tINS | FF | 1 | R29C91[0][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_12_s0/F |
2.708 | 0.000 | tNET | FF | 1 | R29C91[0][A] | gw_gao_inst_0/u_la0_top/word_count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.408 | 1.057 | tNET | RR | 1 | R29C91[0][A] | gw_gao_inst_0/u_la0_top/word_count_12_s0/CLK |
2.433 | 0.025 | tHld | 1 | R29C91[0][A] | gw_gao_inst_0/u_la0_top/word_count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 56.105%; route: 1.057, 43.895% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 56.105%; route: 1.057, 43.895% |
Path12
Path Summary:
Slack | 0.278 |
Data Arrival Time | 1.698 |
Data Required Time | 1.420 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_2_s1 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_2_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C44[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_2_s1/CLK |
1.536 | 0.141 | tC2Q | RF | 3 | R4C44[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_2_s1/Q |
1.545 | 0.009 | tNET | FF | 1 | R4C44[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n430_s0/I0 |
1.698 | 0.153 | tINS | FF | 1 | R4C44[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n430_s0/F |
1.698 | 0.000 | tNET | FF | 1 | R4C44[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C44[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_2_s1/CLK |
1.420 | 0.025 | tHld | 1 | R4C44[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Path13
Path Summary:
Slack | 0.278 |
Data Arrival Time | 1.700 |
Data Required Time | 1.422 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
1.538 | 0.141 | tC2Q | RF | 5 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/Q |
1.547 | 0.009 | tNET | FF | 1 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/n1642_s1/I0 |
1.700 | 0.153 | tINS | FF | 1 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/n1642_s1/F |
1.700 | 0.000 | tNET | FF | 1 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
1.422 | 0.025 | tHld | 1 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Path14
Path Summary:
Slack | 0.278 |
Data Arrival Time | 1.700 |
Data Required Time | 1.422 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
1.538 | 0.141 | tC2Q | RF | 3 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q |
1.547 | 0.009 | tNET | FF | 1 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/n1640_s1/I1 |
1.700 | 0.153 | tINS | FF | 1 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/n1640_s1/F |
1.700 | 0.000 | tNET | FF | 1 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
1.422 | 0.025 | tHld | 1 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Path15
Path Summary:
Slack | 0.280 |
Data Arrival Time | 1.694 |
Data Required Time | 1.413 |
From | sim_output_storage_inst/ram_dout_addrb_0_s3 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.399 | 0.723 | tNET | RR | 1 | R4C57[0][A] | sim_output_storage_inst/ram_dout_addrb_0_s3/CLK |
1.540 | 0.141 | tC2Q | RF | 7 | R4C57[0][A] | sim_output_storage_inst/ram_dout_addrb_0_s3/Q |
1.694 | 0.154 | tNET | FF | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
1.413 | 0.035 | tHld | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.020 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.293%; route: 0.723, 51.707% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.154, 52.203%; tC2Q: 0.141, 47.797% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path16
Path Summary:
Slack | 0.281 |
Data Arrival Time | 1.699 |
Data Required Time | 1.418 |
From | sim_output_storage_inst/ram_dout_addrb_7_s0 |
To | sim_output_storage_inst/ram_dout_addrb_7_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.393 | 0.718 | tNET | RR | 1 | R5C56[1][A] | sim_output_storage_inst/ram_dout_addrb_7_s0/CLK |
1.534 | 0.141 | tC2Q | RF | 4 | R5C56[1][A] | sim_output_storage_inst/ram_dout_addrb_7_s0/Q |
1.546 | 0.012 | tNET | FF | 1 | R5C56[1][A] | sim_output_storage_inst/n172_s2/I0 |
1.699 | 0.153 | tINS | FF | 1 | R5C56[1][A] | sim_output_storage_inst/n172_s2/F |
1.699 | 0.000 | tNET | FF | 1 | R5C56[1][A] | sim_output_storage_inst/ram_dout_addrb_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.393 | 0.718 | tNET | RR | 1 | R5C56[1][A] | sim_output_storage_inst/ram_dout_addrb_7_s0/CLK |
1.418 | 0.025 | tHld | 1 | R5C56[1][A] | sim_output_storage_inst/ram_dout_addrb_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.492%; route: 0.718, 51.508% |
Arrival Data Path Delay | cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078% |
Required Clock Path Delay | cell: 0.675, 48.492%; route: 0.718, 51.508% |
Path17
Path Summary:
Slack | 0.281 |
Data Arrival Time | 1.704 |
Data Required Time | 1.423 |
From | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
1.539 | 0.141 | tC2Q | RF | 4 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/Q |
1.551 | 0.012 | tNET | FF | 1 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/n1600_s1/I1 |
1.704 | 0.153 | tINS | FF | 1 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/n1600_s1/F |
1.704 | 0.000 | tNET | FF | 1 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
1.423 | 0.025 | tHld | 1 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Arrival Data Path Delay | cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078% |
Required Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Path18
Path Summary:
Slack | 0.287 |
Data Arrival Time | 1.707 |
Data Required Time | 1.420 |
From | sim_output_storage_inst/ram_dout_addrb_4_s0 |
To | sim_output_storage_inst/ram_dout_addrb_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C56[1][A] | sim_output_storage_inst/ram_dout_addrb_4_s0/CLK |
1.539 | 0.144 | tC2Q | RR | 6 | R4C56[1][A] | sim_output_storage_inst/ram_dout_addrb_4_s0/Q |
1.554 | 0.015 | tNET | RR | 1 | R4C56[1][A] | sim_output_storage_inst/n175_s2/I0 |
1.707 | 0.153 | tINS | RF | 1 | R4C56[1][A] | sim_output_storage_inst/n175_s2/F |
1.707 | 0.000 | tNET | FF | 1 | R4C56[1][A] | sim_output_storage_inst/ram_dout_addrb_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C56[1][A] | sim_output_storage_inst/ram_dout_addrb_4_s0/CLK |
1.420 | 0.025 | tHld | 1 | R4C56[1][A] | sim_output_storage_inst/ram_dout_addrb_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Arrival Data Path Delay | cell: 0.153, 49.038%; route: 0.015, 4.808%; tC2Q: 0.144, 46.154% |
Required Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Path19
Path Summary:
Slack | 0.287 |
Data Arrival Time | 1.697 |
Data Required Time | 1.410 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_data_addrb_0_s1 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_data_addrb_0_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R26C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_data_addrb_0_s1/CLK |
1.529 | 0.144 | tC2Q | RR | 34 | R26C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_data_addrb_0_s1/Q |
1.544 | 0.015 | tNET | RR | 1 | R26C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n257_s4/I3 |
1.697 | 0.153 | tINS | RF | 1 | R26C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n257_s4/F |
1.697 | 0.000 | tNET | FF | 1 | R26C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_data_addrb_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R26C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_data_addrb_0_s1/CLK |
1.410 | 0.025 | tHld | 1 | R26C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_data_addrb_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Arrival Data Path Delay | cell: 0.153, 49.038%; route: 0.015, 4.808%; tC2Q: 0.144, 46.154% |
Required Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Path20
Path Summary:
Slack | 0.287 |
Data Arrival Time | 1.681 |
Data Required Time | 1.394 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_3_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R29C72[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_3_s0/CLK |
1.513 | 0.144 | tC2Q | RR | 6 | R29C72[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_3_s0/Q |
1.528 | 0.015 | tNET | RR | 1 | R29C72[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n822_s1/I3 |
1.681 | 0.153 | tINS | RF | 1 | R29C72[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n822_s1/F |
1.681 | 0.000 | tNET | FF | 1 | R29C72[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R29C72[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_3_s0/CLK |
1.394 | 0.025 | tHld | 1 | R29C72[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.153, 49.038%; route: 0.015, 4.808%; tC2Q: 0.144, 46.154% |
Required Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Path21
Path Summary:
Slack | 0.287 |
Data Arrival Time | 1.681 |
Data Required Time | 1.394 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_5_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_5_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R29C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_5_s0/CLK |
1.513 | 0.144 | tC2Q | RR | 7 | R29C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_5_s0/Q |
1.528 | 0.015 | tNET | RR | 1 | R29C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n820_s1/I2 |
1.681 | 0.153 | tINS | RF | 1 | R29C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n820_s1/F |
1.681 | 0.000 | tNET | FF | 1 | R29C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R29C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_5_s0/CLK |
1.394 | 0.025 | tHld | 1 | R29C72[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_mem_addr_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.153, 49.038%; route: 0.015, 4.808%; tC2Q: 0.144, 46.154% |
Required Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Path22
Path Summary:
Slack | 0.287 |
Data Arrival Time | 1.714 |
Data Required Time | 1.427 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
1.546 | 0.144 | tC2Q | RR | 12 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q |
1.561 | 0.015 | tNET | RR | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/n1648_s1/I0 |
1.714 | 0.153 | tINS | RF | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/n1648_s1/F |
1.714 | 0.000 | tNET | FF | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
1.427 | 0.025 | tHld | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Arrival Data Path Delay | cell: 0.153, 49.038%; route: 0.015, 4.808%; tC2Q: 0.144, 46.154% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Path23
Path Summary:
Slack | 0.287 |
Data Arrival Time | 1.710 |
Data Required Time | 1.423 |
From | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
1.542 | 0.144 | tC2Q | RR | 8 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q |
1.557 | 0.015 | tNET | RR | 1 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/n1646_s1/I1 |
1.710 | 0.153 | tINS | RF | 1 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/n1646_s1/F |
1.710 | 0.000 | tNET | FF | 1 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
1.423 | 0.025 | tHld | 1 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Arrival Data Path Delay | cell: 0.153, 49.038%; route: 0.015, 4.808%; tC2Q: 0.144, 46.154% |
Required Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Path24
Path Summary:
Slack | 0.289 |
Data Arrival Time | 1.703 |
Data Required Time | 1.413 |
From | sim_output_storage_inst/ram_dout_addrb_5_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C56[0][B] | sim_output_storage_inst/ram_dout_addrb_5_s0/CLK |
1.536 | 0.141 | tC2Q | RF | 5 | R4C56[0][B] | sim_output_storage_inst/ram_dout_addrb_5_s0/Q |
1.703 | 0.167 | tNET | FF | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
1.413 | 0.035 | tHld | 1 | BSRAM_R10[17] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.016 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.167, 54.221%; tC2Q: 0.141, 45.779% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path25
Path Summary:
Slack | 0.290 |
Data Arrival Time | 1.710 |
Data Required Time | 1.420 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C14[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_0_s0/CLK |
1.539 | 0.144 | tC2Q | RR | 43 | R4C14[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_0_s0/Q |
1.557 | 0.018 | tNET | RR | 1 | R4C14[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n2508_s3/I0 |
1.710 | 0.153 | tINS | RF | 1 | R4C14[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n2508_s3/F |
1.710 | 0.000 | tNET | FF | 1 | R4C14[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.719 | tNET | RR | 1 | R4C14[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_0_s0/CLK |
1.420 | 0.025 | tHld | 1 | R4C14[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Arrival Data Path Delay | cell: 0.153, 48.571%; route: 0.018, 5.714%; tC2Q: 0.144, 45.714% |
Required Clock Path Delay | cell: 0.675, 48.432%; route: 0.719, 51.568% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 3.544 |
Data Arrival Time | 8.745 |
Data Required Time | 12.289 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R3C91[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.636 | 1.954 | tNET | RR | 1 | R3C91[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
12.289 | -0.347 | tSu | 1 | R3C91[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.889%; route: 1.954, 74.111% |
Path2
Path Summary:
Slack | 3.544 |
Data Arrival Time | 8.745 |
Data Required Time | 12.289 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R3C91[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.636 | 1.954 | tNET | RR | 1 | R3C91[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
12.289 | -0.347 | tSu | 1 | R3C91[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.889%; route: 1.954, 74.111% |
Path3
Path Summary:
Slack | 3.544 |
Data Arrival Time | 8.745 |
Data Required Time | 12.289 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R3C91[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.636 | 1.954 | tNET | RR | 1 | R3C91[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
12.289 | -0.347 | tSu | 1 | R3C91[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.889%; route: 1.954, 74.111% |
Path4
Path Summary:
Slack | 3.544 |
Data Arrival Time | 8.745 |
Data Required Time | 12.289 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R3C91[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.636 | 1.954 | tNET | RR | 1 | R3C91[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
12.289 | -0.347 | tSu | 1 | R3C91[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.889%; route: 1.954, 74.111% |
Path5
Path Summary:
Slack | 3.544 |
Data Arrival Time | 8.745 |
Data Required Time | 12.289 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R3C91[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.636 | 1.954 | tNET | RR | 1 | R3C91[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
12.289 | -0.347 | tSu | 1 | R3C91[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.889%; route: 1.954, 74.111% |
Path6
Path Summary:
Slack | 3.544 |
Data Arrival Time | 8.745 |
Data Required Time | 12.289 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R3C91[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.636 | 1.954 | tNET | RR | 1 | R3C91[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
12.289 | -0.347 | tSu | 1 | R3C91[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | -0.012 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.889%; route: 1.954, 74.111% |
Path7
Path Summary:
Slack | 3.556 |
Data Arrival Time | 8.745 |
Data Required Time | 12.301 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R2C90[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.648 | 1.966 | tNET | RR | 1 | R2C90[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
12.301 | -0.347 | tSu | 1 | R2C90[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | -0.001 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.773%; route: 1.966, 74.227% |
Path8
Path Summary:
Slack | 3.556 |
Data Arrival Time | 8.745 |
Data Required Time | 12.301 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.648 | 1.966 | tNET | RR | 1 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
12.301 | -0.347 | tSu | 1 | R2C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.001 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.773%; route: 1.966, 74.227% |
Path9
Path Summary:
Slack | 3.556 |
Data Arrival Time | 8.745 |
Data Required Time | 12.301 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R2C90[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.648 | 1.966 | tNET | RR | 1 | R2C90[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
12.301 | -0.347 | tSu | 1 | R2C90[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | -0.001 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.773%; route: 1.966, 74.227% |
Path10
Path Summary:
Slack | 3.556 |
Data Arrival Time | 8.745 |
Data Required Time | 12.301 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.745 | 0.654 | tNET | FF | 1 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.648 | 1.966 | tNET | RR | 1 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
12.301 | -0.347 | tSu | 1 | R2C90[0][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | -0.001 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.654, 59.635%; tC2Q: 0.442, 40.365% |
Required Clock Path Delay | cell: 0.683, 25.773%; route: 1.966, 74.227% |
Path11
Path Summary:
Slack | 3.558 |
Data Arrival Time | 8.687 |
Data Required Time | 12.245 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.687 | 0.596 | tNET | FF | 1 | R14C91[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.593 | 1.910 | tNET | RR | 1 | R14C91[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
12.245 | -0.347 | tSu | 1 | R14C91[1][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | -0.056 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.596, 57.401%; tC2Q: 0.442, 42.599% |
Required Clock Path Delay | cell: 0.683, 26.323%; route: 1.910, 73.677% |
Path12
Path Summary:
Slack | 3.601 |
Data Arrival Time | 8.695 |
Data Required Time | 12.296 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.695 | 0.604 | tNET | FF | 1 | R4C90[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.643 | 1.961 | tNET | RR | 1 | R4C90[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
12.296 | -0.347 | tSu | 1 | R4C90[3][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.604, 57.706%; tC2Q: 0.442, 42.294% |
Required Clock Path Delay | cell: 0.683, 25.822%; route: 1.961, 74.178% |
Path13
Path Summary:
Slack | 3.601 |
Data Arrival Time | 8.695 |
Data Required Time | 12.296 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.695 | 0.604 | tNET | FF | 1 | R4C90[2][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.643 | 1.961 | tNET | RR | 1 | R4C90[2][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
12.296 | -0.347 | tSu | 1 | R4C90[2][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.604, 57.706%; tC2Q: 0.442, 42.294% |
Required Clock Path Delay | cell: 0.683, 25.822%; route: 1.961, 74.178% |
Path14
Path Summary:
Slack | 3.601 |
Data Arrival Time | 8.695 |
Data Required Time | 12.296 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.695 | 0.604 | tNET | FF | 1 | R4C90[2][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.643 | 1.961 | tNET | RR | 1 | R4C90[2][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
12.296 | -0.347 | tSu | 1 | R4C90[2][B] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -0.006 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.604, 57.706%; tC2Q: 0.442, 42.294% |
Required Clock Path Delay | cell: 0.683, 25.822%; route: 1.961, 74.178% |
Path15
Path Summary:
Slack | 3.603 |
Data Arrival Time | 8.695 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.695 | 0.604 | tNET | FF | 1 | R3C90[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.646 | 1.963 | tNET | RR | 1 | R3C90[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK |
12.298 | -0.347 | tSu | 1 | R3C90[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.604, 57.706%; tC2Q: 0.442, 42.294% |
Required Clock Path Delay | cell: 0.683, 25.797%; route: 1.963, 74.203% |
Path16
Path Summary:
Slack | 3.603 |
Data Arrival Time | 8.695 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.695 | 0.604 | tNET | FF | 1 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.646 | 1.963 | tNET | RR | 1 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
12.298 | -0.347 | tSu | 1 | R3C90[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.604, 57.706%; tC2Q: 0.442, 42.294% |
Required Clock Path Delay | cell: 0.683, 25.797%; route: 1.963, 74.203% |
Path17
Path Summary:
Slack | 3.603 |
Data Arrival Time | 8.695 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.695 | 0.604 | tNET | FF | 1 | R3C90[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.646 | 1.963 | tNET | RR | 1 | R3C90[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK |
12.298 | -0.347 | tSu | 1 | R3C90[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.604, 57.706%; tC2Q: 0.442, 42.294% |
Required Clock Path Delay | cell: 0.683, 25.797%; route: 1.963, 74.203% |
Path18
Path Summary:
Slack | 3.603 |
Data Arrival Time | 8.695 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.695 | 0.604 | tNET | FF | 1 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.646 | 1.963 | tNET | RR | 1 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
12.298 | -0.347 | tSu | 1 | R3C90[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.604, 57.706%; tC2Q: 0.442, 42.294% |
Required Clock Path Delay | cell: 0.683, 25.797%; route: 1.963, 74.203% |
Path19
Path Summary:
Slack | 3.603 |
Data Arrival Time | 8.695 |
Data Required Time | 12.298 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.695 | 0.604 | tNET | FF | 1 | R3C90[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.646 | 1.963 | tNET | RR | 1 | R3C90[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
12.298 | -0.347 | tSu | 1 | R3C90[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -0.003 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.604, 57.706%; tC2Q: 0.442, 42.294% |
Required Clock Path Delay | cell: 0.683, 25.797%; route: 1.963, 74.203% |
Path20
Path Summary:
Slack | 3.613 |
Data Arrival Time | 8.651 |
Data Required Time | 12.264 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.651 | 0.560 | tNET | FF | 1 | R9C91[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.612 | 1.929 | tNET | RR | 1 | R9C91[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
12.264 | -0.347 | tSu | 1 | R9C91[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.560, 55.860%; tC2Q: 0.442, 44.140% |
Required Clock Path Delay | cell: 0.683, 26.131%; route: 1.929, 73.869% |
Path21
Path Summary:
Slack | 3.613 |
Data Arrival Time | 8.651 |
Data Required Time | 12.264 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.651 | 0.560 | tNET | FF | 1 | R9C91[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.612 | 1.929 | tNET | RR | 1 | R9C91[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
12.264 | -0.347 | tSu | 1 | R9C91[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.560, 55.860%; tC2Q: 0.442, 44.140% |
Required Clock Path Delay | cell: 0.683, 26.131%; route: 1.929, 73.869% |
Path22
Path Summary:
Slack | 3.613 |
Data Arrival Time | 8.651 |
Data Required Time | 12.264 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.651 | 0.560 | tNET | FF | 1 | R9C91[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.612 | 1.929 | tNET | RR | 1 | R9C91[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
12.264 | -0.347 | tSu | 1 | R9C91[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -0.037 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.560, 55.860%; tC2Q: 0.442, 44.140% |
Required Clock Path Delay | cell: 0.683, 26.131%; route: 1.929, 73.869% |
Path23
Path Summary:
Slack | 3.624 |
Data Arrival Time | 8.686 |
Data Required Time | 12.310 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.686 | 0.595 | tNET | FF | 1 | R2C89[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.658 | 1.975 | tNET | RR | 1 | R2C89[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
12.310 | -0.347 | tSu | 1 | R2C89[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.595, 57.349%; tC2Q: 0.442, 42.651% |
Required Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Path24
Path Summary:
Slack | 3.624 |
Data Arrival Time | 8.686 |
Data Required Time | 12.310 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.686 | 0.595 | tNET | FF | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.658 | 1.975 | tNET | RR | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
12.310 | -0.347 | tSu | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.595, 57.349%; tC2Q: 0.442, 42.651% |
Required Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Path25
Path Summary:
Slack | 3.624 |
Data Arrival Time | 8.686 |
Data Required Time | 12.310 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
7.649 | 1.961 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.091 | 0.442 | tC2Q | FF | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
8.686 | 0.595 | tNET | FF | 1 | R2C89[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
12.658 | 1.975 | tNET | RR | 1 | R2C89[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
12.310 | -0.347 | tSu | 1 | R2C89[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | 0.009 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.956%; route: 1.961, 74.044% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.595, 57.349%; tC2Q: 0.442, 42.651% |
Required Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 5.322 |
Data Arrival Time | 6.662 |
Data Required Time | 1.341 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.662 | 0.105 | tNET | RR | 1 | R7C89[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.394 | 0.718 | tNET | RR | 1 | R7C89[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
1.341 | -0.053 | tHld | 1 | R7C89[1][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.105, 39.924%; tC2Q: 0.158, 60.076% |
Required Clock Path Delay | cell: 0.675, 48.475%; route: 0.718, 51.525% |
Path2
Path Summary:
Slack | 5.418 |
Data Arrival Time | 6.760 |
Data Required Time | 1.342 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.760 | 0.203 | tNET | RR | 1 | R6C89[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.395 | 0.720 | tNET | RR | 1 | R6C89[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
1.342 | -0.053 | tHld | 1 | R6C89[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.004 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
Required Clock Path Delay | cell: 0.675, 48.414%; route: 0.720, 51.586% |
Path3
Path Summary:
Slack | 5.428 |
Data Arrival Time | 6.765 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.764 | 0.207 | tNET | RR | 1 | R7C90[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C90[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
1.336 | -0.053 | tHld | 1 | R7C90[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.207, 56.712%; tC2Q: 0.158, 43.288% |
Required Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Path4
Path Summary:
Slack | 5.428 |
Data Arrival Time | 6.765 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.764 | 0.207 | tNET | RR | 1 | R7C90[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C90[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
1.336 | -0.053 | tHld | 1 | R7C90[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.207, 56.712%; tC2Q: 0.158, 43.288% |
Required Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Path5
Path Summary:
Slack | 5.428 |
Data Arrival Time | 6.765 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.764 | 0.207 | tNET | RR | 1 | R7C90[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R7C90[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
1.336 | -0.053 | tHld | 1 | R7C90[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.207, 56.712%; tC2Q: 0.158, 43.288% |
Required Clock Path Delay | cell: 0.675, 48.615%; route: 0.714, 51.385% |
Path6
Path Summary:
Slack | 5.435 |
Data Arrival Time | 6.766 |
Data Required Time | 1.331 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.766 | 0.208 | tNET | RR | 1 | R9C89[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.384 | 0.708 | tNET | RR | 1 | R9C89[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
1.331 | -0.053 | tHld | 1 | R9C89[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -0.016 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169% |
Required Clock Path Delay | cell: 0.675, 48.825%; route: 0.708, 51.175% |
Path7
Path Summary:
Slack | 5.435 |
Data Arrival Time | 6.766 |
Data Required Time | 1.331 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.766 | 0.208 | tNET | RR | 1 | R9C89[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.384 | 0.708 | tNET | RR | 1 | R9C89[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
1.331 | -0.053 | tHld | 1 | R9C89[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -0.016 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.208, 56.831%; tC2Q: 0.158, 43.169% |
Required Clock Path Delay | cell: 0.675, 48.825%; route: 0.708, 51.175% |
Path8
Path Summary:
Slack | 5.442 |
Data Arrival Time | 6.777 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.777 | 0.220 | tNET | RR | 1 | R8C89[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.388 | 0.713 | tNET | RR | 1 | R8C89[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
1.336 | -0.053 | tHld | 1 | R8C89[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.220, 58.201%; tC2Q: 0.158, 41.799% |
Required Clock Path Delay | cell: 0.675, 48.650%; route: 0.713, 51.350% |
Path9
Path Summary:
Slack | 5.442 |
Data Arrival Time | 6.777 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.777 | 0.220 | tNET | RR | 1 | R8C89[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.388 | 0.713 | tNET | RR | 1 | R8C89[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
1.336 | -0.053 | tHld | 1 | R8C89[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.220, 58.201%; tC2Q: 0.158, 41.799% |
Required Clock Path Delay | cell: 0.675, 48.650%; route: 0.713, 51.350% |
Path10
Path Summary:
Slack | 5.442 |
Data Arrival Time | 6.777 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.777 | 0.220 | tNET | RR | 1 | R8C89[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.388 | 0.713 | tNET | RR | 1 | R8C89[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
1.336 | -0.053 | tHld | 1 | R8C89[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.220, 58.201%; tC2Q: 0.158, 41.799% |
Required Clock Path Delay | cell: 0.675, 48.650%; route: 0.713, 51.350% |
Path11
Path Summary:
Slack | 5.442 |
Data Arrival Time | 6.777 |
Data Required Time | 1.336 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.777 | 0.220 | tNET | RR | 1 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.388 | 0.713 | tNET | RR | 1 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
1.336 | -0.053 | tHld | 1 | R8C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.220, 58.201%; tC2Q: 0.158, 41.799% |
Required Clock Path Delay | cell: 0.675, 48.650%; route: 0.713, 51.350% |
Path12
Path Summary:
Slack | 5.442 |
Data Arrival Time | 6.773 |
Data Required Time | 1.332 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.773 | 0.216 | tNET | RR | 1 | R8C90[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R8C90[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
1.332 | -0.053 | tHld | 1 | R8C90[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.216, 57.754%; tC2Q: 0.158, 42.246% |
Required Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Path13
Path Summary:
Slack | 5.442 |
Data Arrival Time | 6.773 |
Data Required Time | 1.332 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.773 | 0.216 | tNET | RR | 1 | R8C90[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R8C90[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
1.332 | -0.053 | tHld | 1 | R8C90[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | -0.015 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.216, 57.754%; tC2Q: 0.158, 42.246% |
Required Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Path14
Path Summary:
Slack | 5.507 |
Data Arrival Time | 6.852 |
Data Required Time | 1.346 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.852 | 0.295 | tNET | RR | 1 | R4C89[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.399 | 0.723 | tNET | RR | 1 | R4C89[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
1.346 | -0.053 | tHld | 1 | R4C89[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.295, 65.121%; tC2Q: 0.158, 34.879% |
Required Clock Path Delay | cell: 0.675, 48.293%; route: 0.723, 51.707% |
Path15
Path Summary:
Slack | 5.507 |
Data Arrival Time | 6.819 |
Data Required Time | 1.312 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.819 | 0.261 | tNET | RR | 1 | R13C90[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.365 | 0.689 | tNET | RR | 1 | R13C90[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
1.312 | -0.053 | tHld | 1 | R13C90[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.035 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.261, 62.291%; tC2Q: 0.158, 37.709% |
Required Clock Path Delay | cell: 0.675, 49.505%; route: 0.689, 50.495% |
Path16
Path Summary:
Slack | 5.510 |
Data Arrival Time | 6.848 |
Data Required Time | 1.338 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.848 | 0.291 | tNET | RR | 1 | R6C90[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.391 | 0.716 | tNET | RR | 1 | R6C90[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
1.338 | -0.053 | tHld | 1 | R6C90[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.291, 64.811%; tC2Q: 0.158, 35.189% |
Required Clock Path Delay | cell: 0.675, 48.553%; route: 0.716, 51.447% |
Path17
Path Summary:
Slack | 5.510 |
Data Arrival Time | 6.848 |
Data Required Time | 1.338 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.848 | 0.291 | tNET | RR | 1 | R6C90[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.391 | 0.716 | tNET | RR | 1 | R6C90[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
1.338 | -0.053 | tHld | 1 | R6C90[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.008 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.291, 64.811%; tC2Q: 0.158, 35.189% |
Required Clock Path Delay | cell: 0.675, 48.553%; route: 0.716, 51.447% |
Path18
Path Summary:
Slack | 5.515 |
Data Arrival Time | 6.862 |
Data Required Time | 1.348 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.862 | 0.305 | tNET | RR | 1 | R3C89[1][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.401 | 0.725 | tNET | RR | 1 | R3C89[1][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
1.348 | -0.053 | tHld | 1 | R3C89[1][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | 0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.305, 65.875%; tC2Q: 0.158, 34.125% |
Required Clock Path Delay | cell: 0.675, 48.233%; route: 0.725, 51.767% |
Path19
Path Summary:
Slack | 5.526 |
Data Arrival Time | 6.846 |
Data Required Time | 1.320 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.846 | 0.289 | tNET | RR | 1 | R11C89[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.374 | 0.698 | tNET | RR | 1 | R11C89[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
1.321 | -0.053 | tHld | 1 | R11C89[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | -0.026 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.289, 64.653%; tC2Q: 0.158, 35.347% |
Required Clock Path Delay | cell: 0.675, 49.181%; route: 0.698, 50.819% |
Path20
Path Summary:
Slack | 5.526 |
Data Arrival Time | 6.846 |
Data Required Time | 1.320 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.846 | 0.289 | tNET | RR | 1 | R11C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.374 | 0.698 | tNET | RR | 1 | R11C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
1.321 | -0.053 | tHld | 1 | R11C89[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -0.026 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.289, 64.653%; tC2Q: 0.158, 35.347% |
Required Clock Path Delay | cell: 0.675, 49.181%; route: 0.698, 50.819% |
Path21
Path Summary:
Slack | 5.526 |
Data Arrival Time | 6.846 |
Data Required Time | 1.320 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.846 | 0.289 | tNET | RR | 1 | R11C89[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.374 | 0.698 | tNET | RR | 1 | R11C89[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.321 | -0.053 | tHld | 1 | R11C89[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | -0.026 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.289, 64.653%; tC2Q: 0.158, 35.347% |
Required Clock Path Delay | cell: 0.675, 49.181%; route: 0.698, 50.819% |
Path22
Path Summary:
Slack | 5.528 |
Data Arrival Time | 6.878 |
Data Required Time | 1.349 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.878 | 0.320 | tNET | RR | 1 | R2C89[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R2C89[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
1.349 | -0.053 | tHld | 1 | R2C89[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | 0.003 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.320, 66.946%; tC2Q: 0.158, 33.054% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Path23
Path Summary:
Slack | 5.528 |
Data Arrival Time | 6.878 |
Data Required Time | 1.349 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.878 | 0.320 | tNET | RR | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
1.349 | -0.053 | tHld | 1 | R2C89[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | 0.003 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.320, 66.946%; tC2Q: 0.158, 33.054% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Path24
Path Summary:
Slack | 5.528 |
Data Arrival Time | 6.878 |
Data Required Time | 1.349 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.878 | 0.320 | tNET | RR | 1 | R2C89[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R2C89[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
1.349 | -0.053 | tHld | 1 | R2C89[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | 0.003 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.320, 66.946%; tC2Q: 0.158, 33.054% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Path25
Path Summary:
Slack | 5.528 |
Data Arrival Time | 6.878 |
Data Required Time | 1.349 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 11294 | IOB29[A] | clk_ibuf/O |
6.399 | 0.722 | tNET | FF | 1 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.557 | 0.158 | tC2Q | FR | 53 | R7C89[2][B] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.878 | 0.320 | tNET | RR | 1 | R2C89[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 11294 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R2C89[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
1.349 | -0.053 | tHld | 1 | R2C89[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | 0.003 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.410%; route: 0.722, 51.590% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.320, 66.946%; tC2Q: 0.158, 33.054% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.751 |
Actual Width: | 3.751 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.627 | 1.940 | tNET | FF | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.703 | tNET | RR | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
MPW2
MPW Summary:
Slack: | 2.754 |
Actual Width: | 3.754 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[2].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.628 | 1.940 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[2].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.382 | 0.706 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[2].mult_dsp_inst/n47_s1/CLK[0] |
MPW3
MPW Summary:
Slack: | 2.754 |
Actual Width: | 3.754 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[10].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.628 | 1.940 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[10].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.382 | 0.706 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[10].mult_dsp_inst/n47_s1/CLK[0] |
MPW4
MPW Summary:
Slack: | 2.754 |
Actual Width: | 3.754 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[11].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.628 | 1.940 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[11].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.382 | 0.706 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[11].mult_dsp_inst/n47_s1/CLK[0] |
MPW5
MPW Summary:
Slack: | 2.757 |
Actual Width: | 3.757 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.930 | tNET | FF | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.375 | 0.699 | tNET | RR | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
MPW6
MPW Summary:
Slack: | 2.757 |
Actual Width: | 3.757 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.930 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.375 | 0.699 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
MPW7
MPW Summary:
Slack: | 2.759 |
Actual Width: | 3.759 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[8].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.931 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[8].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.702 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[8].mult_dsp_inst/n47_s1/CLK[0] |
MPW8
MPW Summary:
Slack: | 2.759 |
Actual Width: | 3.759 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.931 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.702 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0] |
MPW9
MPW Summary:
Slack: | 2.759 |
Actual Width: | 3.759 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[3].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.931 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[3].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.702 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[3].mult_dsp_inst/n47_s1/CLK[0] |
MPW10
MPW Summary:
Slack: | 2.759 |
Actual Width: | 3.759 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[4].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.931 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[4].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.702 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[4].mult_dsp_inst/n47_s1/CLK[0] |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
11294 | clk_d | 1.459 | 1.985 |
2912 | coeff_ram_addrb[0] | 2.954 | 4.246 |
1665 | delay_shift_addrb[0] | 6.728 | 2.036 |
1456 | coeff_ram_addrb[1] | 3.552 | 4.028 |
833 | delay_shift_addrb[1] | 6.881 | 2.259 |
832 | coeff_ram_addrb[2] | 3.477 | 4.214 |
417 | delay_shift_addrb[2] | 7.190 | 2.070 |
416 | coeff_ram_addrb[3] | 4.422 | 3.962 |
386 | mult_valid | 7.189 | 2.035 |
364 | coeff_mem_out[0] | 4.712 | 3.214 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R32C22 | 84.72% |
R30C79 | 83.33% |
R28C74 | 81.94% |
R14C71 | 77.78% |
R29C23 | 77.78% |
R20C66 | 76.39% |
R31C79 | 76.39% |
R28C75 | 75.00% |
R28C76 | 73.61% |
R6C78 | 72.22% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}] |