Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\161taps_2chn_1tdm_8inter_3decim_16bit\proj\impl\gwsynthesis\fir_proj.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\161taps_2chn_1tdm_8inter_3decim_16bit\proj\src\fir_proj.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\161taps_2chn_1tdm_8inter_3decim_16bit\proj\src\fir_proj.sdc |
Tool Version | V1.9.11 (64-bit) |
Part Number | GW5A-LV25UG324ES |
Device | GW5A-25 |
Device Version | A |
Created Time | Wed Dec 25 12:42:57 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.855V 0C ES |
Hold Delay Model | Fast 0.945V 85C ES |
Numbers of Paths Analyzed | 19426 |
Numbers of Endpoints Analyzed | 20610 |
Numbers of Falling Endpoints | 3 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk | ||
2 | tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.000(MHz) | 117.941(MHz) | 3 | TOP |
2 | tck_pad_i | 20.000(MHz) | 156.870(MHz) | 6 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
tck_pad_i | Setup | 0.000 | 0 |
tck_pad_i | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.521 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_15_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.044 | 8.124 |
2 | 1.711 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_10_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.044 | 7.934 |
3 | 1.711 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_8_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.044 | 7.934 |
4 | 1.864 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_12_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.030 | 7.795 |
5 | 1.904 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_11_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.044 | 7.741 |
6 | 2.020 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_14_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.040 | 7.629 |
7 | 2.056 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_11_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.028 | 7.605 |
8 | 2.074 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_10_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.044 | 7.571 |
9 | 2.074 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_8_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.044 | 7.571 |
10 | 2.086 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_6_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.059 | 7.544 |
11 | 2.109 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_9_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.036 | 7.544 |
12 | 2.109 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_0_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.036 | 7.544 |
13 | 2.148 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_2_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.017 | 7.557 |
14 | 2.204 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_4_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.046 | 7.439 |
15 | 2.228 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_1_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.047 | 7.414 |
16 | 2.253 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_15_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.055 | 7.381 |
17 | 2.253 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_6_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.055 | 7.381 |
18 | 2.267 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_5_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.007 | 7.415 |
19 | 2.293 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_13_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.040 | 7.356 |
20 | 2.293 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_12_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.040 | 7.356 |
21 | 2.293 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_7_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.040 | 7.356 |
22 | 2.317 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[0]_13_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.020 | 7.391 |
23 | 2.348 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_13_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.027 | 7.367 |
24 | 2.350 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_9_s0/CE | clk:[R] | clk:[R] | 10.000 | -0.029 | 7.367 |
25 | 2.384 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[1]_14_s0/CE | clk:[R] | clk:[R] | 10.000 | 0.007 | 7.298 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.205 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[10] | clk:[R] | clk:[R] | 0.000 | -0.005 | 0.247 |
2 | 0.208 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[13] | clk:[R] | clk:[R] | 0.000 | 0.001 | 0.244 |
3 | 0.212 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[8] | clk:[R] | clk:[R] | 0.000 | 0.005 | 0.244 |
4 | 0.215 | sim_output_storage_inst/ram_dout_addrb_4_s3/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[8] | clk:[R] | clk:[R] | 0.000 | 0.018 | 0.232 |
5 | 0.223 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[4] | clk:[R] | clk:[R] | 0.000 | 0.006 | 0.254 |
6 | 0.224 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[9] | clk:[R] | clk:[R] | 0.000 | 0.010 | 0.251 |
7 | 0.236 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] | clk:[R] | clk:[R] | 0.000 | 0.013 | 0.260 |
8 | 0.257 | sim_output_storage_inst/ram_din_data_9_s0/Q | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/DI[9] | clk:[R] | clk:[R] | 0.000 | -0.005 | 0.299 |
9 | 0.271 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[11] | clk:[R] | clk:[R] | 0.000 | 0.001 | 0.307 |
10 | 0.275 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/acc_out_18_s3/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/fir_acc_out_18_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.222 |
11 | 0.275 | sim_output_storage_inst/ram_din_addra_4_s0/Q | sim_output_storage_inst/ram_din_addra_4_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
12 | 0.275 | sim_input_gen_inst/cnt_chn_0_s0/Q | sim_input_gen_inst/cnt_chn_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
13 | 0.275 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_0_s1/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_0_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
14 | 0.275 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_limit_1_s1/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_limit_1_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
15 | 0.275 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
16 | 0.275 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addra_0_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addra_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
17 | 0.275 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.300 |
18 | 0.275 | gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q | gw_gao_inst_0/u_la0_top/bit_count_0_s1/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.300 |
19 | 0.278 | gw_gao_inst_0/u_la0_top/bit_count_2_s1/Q | gw_gao_inst_0/u_la0_top/bit_count_2_s1/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.303 |
20 | 0.278 | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q | gw_gao_inst_0/u_la0_top/word_count_3_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.303 |
21 | 0.278 | gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q | gw_gao_inst_0/u_la0_top/address_counter_4_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.303 |
22 | 0.278 | gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q | gw_gao_inst_0/u_la0_top/address_counter_7_s0/D | tck_pad_i:[R] | tck_pad_i:[R] | 0.000 | 0.000 | 0.303 |
23 | 0.278 | sim_output_storage_inst/cnt_chn_0_s0/Q | sim_output_storage_inst/cnt_chn_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.303 |
24 | 0.278 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_index_cnt_5_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_index_cnt_5_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.303 |
25 | 0.278 | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.303 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 2.184 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.044 | 2.425 |
2 | 2.293 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.013 | 2.346 |
3 | 2.293 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.013 | 2.346 |
4 | 2.358 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.053 | 2.241 |
5 | 2.358 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.053 | 2.241 |
6 | 2.358 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.053 | 2.241 |
7 | 2.628 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.034 | 1.990 |
8 | 2.682 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.029 | 1.941 |
9 | 2.682 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.029 | 1.941 |
10 | 2.691 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.020 | 1.941 |
11 | 2.691 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.020 | 1.941 |
12 | 2.767 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.019 | 1.866 |
13 | 3.097 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.032 | 1.524 |
14 | 3.097 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.032 | 1.524 |
15 | 3.107 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.022 | 1.524 |
16 | 3.107 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.022 | 1.524 |
17 | 3.107 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.022 | 1.524 |
18 | 3.107 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.022 | 1.524 |
19 | 3.107 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.022 | 1.524 |
20 | 3.129 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk:[F] | clk:[R] | 5.000 | 0.024 | 1.499 |
21 | 3.129 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.024 | 1.499 |
22 | 3.129 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.024 | 1.499 |
23 | 3.139 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.015 | 1.499 |
24 | 3.139 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.015 | 1.499 |
25 | 3.139 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | clk:[F] | clk:[R] | 5.000 | 0.015 | 1.499 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 5.361 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.307 |
2 | 5.361 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.307 |
3 | 5.361 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.001 | 0.307 |
4 | 5.367 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.309 |
5 | 5.367 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.309 |
6 | 5.367 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.309 |
7 | 5.367 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.309 |
8 | 5.367 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.309 |
9 | 5.422 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.007 | 0.362 |
10 | 5.422 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.007 | 0.362 |
11 | 5.422 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.007 | 0.362 |
12 | 5.422 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.007 | 0.362 |
13 | 5.422 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.007 | 0.362 |
14 | 5.426 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.011 | 0.362 |
15 | 5.426 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.011 | 0.362 |
16 | 5.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.009 | 0.415 |
17 | 5.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.009 | 0.415 |
18 | 5.477 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.009 | 0.415 |
19 | 5.516 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.003 | 0.460 |
20 | 5.516 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.003 | 0.460 |
21 | 5.527 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.029 | 0.446 |
22 | 5.577 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.005 | 0.519 |
23 | 5.676 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | clk:[F] | clk:[R] | -5.000 | 0.023 | 0.600 |
24 | 5.681 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.027 | 0.601 |
25 | 5.681 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR | clk:[F] | clk:[R] | -5.000 | 0.027 | 0.601 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.751 | 3.751 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
2 | 2.751 | 3.751 | 1.000 | Low Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
3 | 2.754 | 3.754 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[11].mult_dsp_inst/n47_s1 |
4 | 2.754 | 3.754 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[12].mult_dsp_inst/n47_s1 |
5 | 2.754 | 3.754 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[14].mult_dsp_inst/n47_s1 |
6 | 2.754 | 3.754 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/n47_s1 |
7 | 2.757 | 3.757 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
8 | 2.757 | 3.757 | 1.000 | Low Pulse Width | clk | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
9 | 2.757 | 3.757 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_rom_inst/mem_mem_0_0_s |
10 | 2.759 | 3.759 | 1.000 | Low Pulse Width | clk | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/n47_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.521 |
Data Arrival Time | 10.781 |
Data Required Time | 12.303 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_15_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.781 | 2.438 | tNET | RR | 1 | R36C42[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_15_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.614 | 1.931 | tNET | RR | 1 | R36C42[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_15_s0/CLK |
12.303 | -0.311 | tSu | 1 | R36C42[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_15_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 12.156%; route: 6.769, 83.321%; tC2Q: 0.368, 4.524% |
Required Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Path2
Path Summary:
Slack | 1.711 |
Data Arrival Time | 10.591 |
Data Required Time | 12.303 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_10_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.591 | 2.247 | tNET | RR | 1 | R36C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.614 | 1.931 | tNET | RR | 1 | R36C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_10_s0/CLK |
12.303 | -0.311 | tSu | 1 | R36C40[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_10_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 12.447%; route: 6.579, 82.921%; tC2Q: 0.368, 4.632% |
Required Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Path3
Path Summary:
Slack | 1.711 |
Data Arrival Time | 10.591 |
Data Required Time | 12.303 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_8_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.591 | 2.247 | tNET | RR | 1 | R36C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_8_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.614 | 1.931 | tNET | RR | 1 | R36C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_8_s0/CLK |
12.303 | -0.311 | tSu | 1 | R36C40[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_8_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 12.447%; route: 6.579, 82.921%; tC2Q: 0.368, 4.632% |
Required Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Path4
Path Summary:
Slack | 1.864 |
Data Arrival Time | 10.423 |
Data Required Time | 12.288 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_12_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.628 | 1.946 | tNET | RR | 1 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
3.011 | 0.382 | tC2Q | RR | 6 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
4.443 | 1.432 | tNET | RR | 1 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/I2 |
4.965 | 0.521 | tINS | RR | 22 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/F |
6.467 | 1.502 | tNET | RR | 1 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/I2 |
6.988 | 0.521 | tINS | RR | 8 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/F |
7.465 | 0.476 | tNET | RR | 1 | R20C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n723_s1/I3 |
7.926 | 0.461 | tINS | RR | 16 | R20C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n723_s1/F |
10.423 | 2.497 | tNET | RR | 1 | R15C23[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_12_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.599 | 1.916 | tNET | RR | 1 | R15C23[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_12_s0/CLK |
12.288 | -0.311 | tSu | 1 | R15C23[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_12_s0 |
Path Statistics:
Clock Skew | -0.030 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Arrival Data Path Delay | cell: 1.504, 19.291%; route: 5.909, 75.802%; tC2Q: 0.382, 4.907% |
Required Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Path5
Path Summary:
Slack | 1.904 |
Data Arrival Time | 10.399 |
Data Required Time | 12.303 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_11_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.399 | 2.055 | tNET | RR | 1 | R36C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_11_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.614 | 1.931 | tNET | RR | 1 | R36C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_11_s0/CLK |
12.303 | -0.311 | tSu | 1 | R36C38[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_11_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 12.756%; route: 6.386, 82.496%; tC2Q: 0.368, 4.747% |
Required Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Path6
Path Summary:
Slack | 2.020 |
Data Arrival Time | 10.286 |
Data Required Time | 12.306 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_14_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.286 | 1.943 | tNET | RR | 1 | R33C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_14_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.618 | 1.935 | tNET | RR | 1 | R33C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_14_s0/CLK |
12.306 | -0.311 | tSu | 1 | R33C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_14_s0 |
Path Statistics:
Clock Skew | -0.040 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 12.944%; route: 6.274, 82.238%; tC2Q: 0.368, 4.817% |
Required Clock Path Delay | cell: 0.683, 26.074%; route: 1.935, 73.925% |
Path7
Path Summary:
Slack | 2.056 |
Data Arrival Time | 10.233 |
Data Required Time | 12.289 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_11_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.628 | 1.946 | tNET | RR | 1 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
3.011 | 0.382 | tC2Q | RR | 6 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
4.443 | 1.432 | tNET | RR | 1 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/I2 |
4.965 | 0.521 | tINS | RR | 22 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/F |
6.467 | 1.502 | tNET | RR | 1 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/I2 |
6.988 | 0.521 | tINS | RR | 8 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/F |
7.465 | 0.476 | tNET | RR | 1 | R20C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n723_s1/I3 |
7.926 | 0.461 | tINS | RR | 16 | R20C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n723_s1/F |
10.233 | 2.307 | tNET | RR | 1 | R16C23[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_11_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.601 | 1.918 | tNET | RR | 1 | R16C23[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_11_s0/CLK |
12.289 | -0.311 | tSu | 1 | R16C23[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_11_s0 |
Path Statistics:
Clock Skew | -0.028 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Arrival Data Path Delay | cell: 1.504, 19.773%; route: 5.719, 75.197%; tC2Q: 0.382, 5.030% |
Required Clock Path Delay | cell: 0.683, 26.244%; route: 1.918, 73.756% |
Path8
Path Summary:
Slack | 2.074 |
Data Arrival Time | 10.229 |
Data Required Time | 12.303 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_10_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.623 | 2.598 | tNET | FF | 1 | R5C14[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n691_s1/I1 |
6.149 | 0.526 | tINS | FR | 3 | R5C14[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n691_s1/F |
7.924 | 1.775 | tNET | RR | 1 | R25C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n691_s1/I0 |
8.186 | 0.262 | tINS | RR | 16 | R25C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n691_s1/F |
10.229 | 2.043 | tNET | RR | 1 | R36C42[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.614 | 1.931 | tNET | RR | 1 | R36C42[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_10_s0/CLK |
12.303 | -0.311 | tSu | 1 | R36C42[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_10_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.789, 10.418%; route: 6.415, 84.728%; tC2Q: 0.368, 4.854% |
Required Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Path9
Path Summary:
Slack | 2.074 |
Data Arrival Time | 10.229 |
Data Required Time | 12.303 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_8_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.623 | 2.598 | tNET | FF | 1 | R5C14[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n691_s1/I1 |
6.149 | 0.526 | tINS | FR | 3 | R5C14[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n691_s1/F |
7.924 | 1.775 | tNET | RR | 1 | R25C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n691_s1/I0 |
8.186 | 0.262 | tINS | RR | 16 | R25C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n691_s1/F |
10.229 | 2.043 | tNET | RR | 1 | R36C42[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_8_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.614 | 1.931 | tNET | RR | 1 | R36C42[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_8_s0/CLK |
12.303 | -0.311 | tSu | 1 | R36C42[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_8_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.789, 10.418%; route: 6.415, 84.728%; tC2Q: 0.368, 4.854% |
Required Clock Path Delay | cell: 0.683, 26.112%; route: 1.931, 73.888% |
Path10
Path Summary:
Slack | 2.086 |
Data Arrival Time | 10.201 |
Data Required Time | 12.288 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_6_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.201 | 1.858 | tNET | RR | 1 | R33C43[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_6_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.599 | 1.916 | tNET | RR | 1 | R33C43[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_6_s0/CLK |
12.288 | -0.311 | tSu | 1 | R33C43[2][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_6_s0 |
Path Statistics:
Clock Skew | -0.059 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 13.090%; route: 6.189, 82.038%; tC2Q: 0.368, 4.872% |
Required Clock Path Delay | cell: 0.683, 26.263%; route: 1.916, 73.737% |
Path11
Path Summary:
Slack | 2.109 |
Data Arrival Time | 10.201 |
Data Required Time | 12.310 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_9_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.201 | 1.858 | tNET | RR | 1 | R35C41[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_9_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.621 | 1.939 | tNET | RR | 1 | R35C41[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_9_s0/CLK |
12.310 | -0.311 | tSu | 1 | R35C41[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_9_s0 |
Path Statistics:
Clock Skew | -0.036 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 13.090%; route: 6.189, 82.038%; tC2Q: 0.368, 4.872% |
Required Clock Path Delay | cell: 0.683, 26.037%; route: 1.939, 73.963% |
Path12
Path Summary:
Slack | 2.109 |
Data Arrival Time | 10.201 |
Data Required Time | 12.310 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.201 | 1.858 | tNET | RR | 1 | R35C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.621 | 1.939 | tNET | RR | 1 | R35C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_0_s0/CLK |
12.310 | -0.311 | tSu | 1 | R35C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_0_s0 |
Path Statistics:
Clock Skew | -0.036 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 13.090%; route: 6.189, 82.038%; tC2Q: 0.368, 4.872% |
Required Clock Path Delay | cell: 0.683, 26.037%; route: 1.939, 73.963% |
Path13
Path Summary:
Slack | 2.148 |
Data Arrival Time | 10.186 |
Data Required Time | 12.334 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_2_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.628 | 1.946 | tNET | RR | 1 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
3.011 | 0.382 | tC2Q | RR | 6 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
4.443 | 1.432 | tNET | RR | 1 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/I2 |
4.965 | 0.521 | tINS | RR | 22 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/F |
6.467 | 1.502 | tNET | RR | 1 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/I2 |
6.988 | 0.521 | tINS | RR | 8 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/F |
8.016 | 1.028 | tNET | RR | 1 | R16C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n739_s1/I3 |
8.477 | 0.461 | tINS | RR | 16 | R16C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n739_s1/F |
10.186 | 1.709 | tNET | RR | 1 | R21C22[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.646 | 1.963 | tNET | RR | 1 | R21C22[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_2_s0/CLK |
12.334 | -0.311 | tSu | 1 | R21C22[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_2_s0 |
Path Statistics:
Clock Skew | 0.017 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Arrival Data Path Delay | cell: 1.504, 19.897%; route: 5.671, 75.041%; tC2Q: 0.382, 5.061% |
Required Clock Path Delay | cell: 0.683, 25.797%; route: 1.963, 74.203% |
Path14
Path Summary:
Slack | 2.204 |
Data Arrival Time | 10.096 |
Data Required Time | 12.300 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.096 | 1.753 | tNET | RR | 1 | R32C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.612 | 1.929 | tNET | RR | 1 | R32C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_4_s0/CLK |
12.300 | -0.311 | tSu | 1 | R32C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_4_s0 |
Path Statistics:
Clock Skew | -0.046 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 13.275%; route: 6.084, 81.785%; tC2Q: 0.368, 4.940% |
Required Clock Path Delay | cell: 0.683, 26.134%; route: 1.929, 73.866% |
Path15
Path Summary:
Slack | 2.228 |
Data Arrival Time | 10.071 |
Data Required Time | 12.299 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.071 | 1.728 | tNET | RR | 1 | R34C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.610 | 1.928 | tNET | RR | 1 | R34C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_1_s0/CLK |
12.299 | -0.311 | tSu | 1 | R34C38[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_1_s0 |
Path Statistics:
Clock Skew | -0.047 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 13.320%; route: 6.059, 81.723%; tC2Q: 0.368, 4.957% |
Required Clock Path Delay | cell: 0.683, 26.149%; route: 1.928, 73.851% |
Path16
Path Summary:
Slack | 2.253 |
Data Arrival Time | 10.039 |
Data Required Time | 12.291 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_15_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.623 | 2.598 | tNET | FF | 1 | R5C14[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n691_s1/I1 |
6.149 | 0.526 | tINS | FR | 3 | R5C14[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n691_s1/F |
7.924 | 1.775 | tNET | RR | 1 | R25C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n691_s1/I0 |
8.186 | 0.262 | tINS | RR | 16 | R25C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n691_s1/F |
10.039 | 1.852 | tNET | RR | 1 | R35C43[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_15_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.602 | 1.920 | tNET | RR | 1 | R35C43[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_15_s0/CLK |
12.291 | -0.311 | tSu | 1 | R35C43[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_15_s0 |
Path Statistics:
Clock Skew | -0.055 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.789, 10.686%; route: 6.225, 84.335%; tC2Q: 0.368, 4.979% |
Required Clock Path Delay | cell: 0.683, 26.225%; route: 1.920, 73.775% |
Path17
Path Summary:
Slack | 2.253 |
Data Arrival Time | 10.039 |
Data Required Time | 12.291 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_6_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.623 | 2.598 | tNET | FF | 1 | R5C14[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n691_s1/I1 |
6.149 | 0.526 | tINS | FR | 3 | R5C14[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n691_s1/F |
7.924 | 1.775 | tNET | RR | 1 | R25C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n691_s1/I0 |
8.186 | 0.262 | tINS | RR | 16 | R25C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n691_s1/F |
10.039 | 1.852 | tNET | RR | 1 | R35C43[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_6_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.602 | 1.920 | tNET | RR | 1 | R35C43[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_6_s0/CLK |
12.291 | -0.311 | tSu | 1 | R35C43[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[2]_6_s0 |
Path Statistics:
Clock Skew | -0.055 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.789, 10.686%; route: 6.225, 84.335%; tC2Q: 0.368, 4.979% |
Required Clock Path Delay | cell: 0.683, 26.225%; route: 1.920, 73.775% |
Path18
Path Summary:
Slack | 2.267 |
Data Arrival Time | 10.043 |
Data Required Time | 12.310 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_5_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.628 | 1.946 | tNET | RR | 1 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
3.011 | 0.382 | tC2Q | RR | 6 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
4.443 | 1.432 | tNET | RR | 1 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/I2 |
4.965 | 0.521 | tINS | RR | 22 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/F |
6.467 | 1.502 | tNET | RR | 1 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/I2 |
6.988 | 0.521 | tINS | RR | 8 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/F |
7.465 | 0.476 | tNET | RR | 1 | R20C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n723_s1/I3 |
7.926 | 0.461 | tINS | RR | 16 | R20C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n723_s1/F |
10.043 | 2.118 | tNET | RR | 1 | R17C25[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_5_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.621 | 1.939 | tNET | RR | 1 | R17C25[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_5_s0/CLK |
12.310 | -0.311 | tSu | 1 | R17C25[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[4]_5_s0 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Arrival Data Path Delay | cell: 1.504, 20.280%; route: 5.529, 74.562%; tC2Q: 0.382, 5.158% |
Required Clock Path Delay | cell: 0.683, 26.037%; route: 1.939, 73.963% |
Path19
Path Summary:
Slack | 2.293 |
Data Arrival Time | 10.014 |
Data Required Time | 12.306 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_13_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.014 | 1.670 | tNET | RR | 1 | R33C41[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.618 | 1.935 | tNET | RR | 1 | R33C41[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_13_s0/CLK |
12.306 | -0.311 | tSu | 1 | R33C41[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_13_s0 |
Path Statistics:
Clock Skew | -0.040 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 13.424%; route: 6.001, 81.580%; tC2Q: 0.368, 4.996% |
Required Clock Path Delay | cell: 0.683, 26.074%; route: 1.935, 73.925% |
Path20
Path Summary:
Slack | 2.293 |
Data Arrival Time | 10.014 |
Data Required Time | 12.306 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_12_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.014 | 1.670 | tNET | RR | 1 | R33C41[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_12_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.618 | 1.935 | tNET | RR | 1 | R33C41[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_12_s0/CLK |
12.306 | -0.311 | tSu | 1 | R33C41[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_12_s0 |
Path Statistics:
Clock Skew | -0.040 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 13.424%; route: 6.001, 81.580%; tC2Q: 0.368, 4.996% |
Required Clock Path Delay | cell: 0.683, 26.074%; route: 1.935, 73.925% |
Path21
Path Summary:
Slack | 2.293 |
Data Arrival Time | 10.014 |
Data Required Time | 12.306 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_7_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.658 | 1.975 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
3.025 | 0.368 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
5.806 | 2.781 | tNET | FF | 1 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/I0 |
6.333 | 0.526 | tINS | FR | 3 | R6C13[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n707_s1/F |
7.883 | 1.550 | tNET | RR | 1 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/I0 |
8.344 | 0.461 | tINS | RR | 16 | R23C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/n707_s1/F |
10.014 | 1.670 | tNET | RR | 1 | R33C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.618 | 1.935 | tNET | RR | 1 | R33C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_7_s0/CLK |
12.306 | -0.311 | tSu | 1 | R33C41[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[3].spram_coeff_inst/mem[3]_7_s0 |
Path Statistics:
Clock Skew | -0.040 |
Setup Relationship | 10.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Arrival Data Path Delay | cell: 0.987, 13.424%; route: 6.001, 81.580%; tC2Q: 0.368, 4.996% |
Required Clock Path Delay | cell: 0.683, 26.074%; route: 1.935, 73.925% |
Path22
Path Summary:
Slack | 2.317 |
Data Arrival Time | 10.020 |
Data Required Time | 12.337 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[0]_13_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.628 | 1.946 | tNET | RR | 1 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
3.011 | 0.382 | tC2Q | RR | 6 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
4.443 | 1.432 | tNET | RR | 1 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/I2 |
4.965 | 0.521 | tINS | RR | 22 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/F |
6.467 | 1.502 | tNET | RR | 1 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/I2 |
6.988 | 0.521 | tINS | RR | 8 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/F |
8.016 | 1.028 | tNET | RR | 1 | R16C26[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s2/I3 |
8.477 | 0.461 | tINS | RR | 16 | R16C26[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s2/F |
10.020 | 1.543 | tNET | RR | 1 | R20C20[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[0]_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.648 | 1.966 | tNET | RR | 1 | R20C20[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[0]_13_s0/CLK |
12.337 | -0.311 | tSu | 1 | R20C20[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[0]_13_s0 |
Path Statistics:
Clock Skew | 0.020 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Arrival Data Path Delay | cell: 1.504, 20.345%; route: 5.505, 74.480%; tC2Q: 0.382, 5.175% |
Required Clock Path Delay | cell: 0.683, 25.773%; route: 1.966, 74.227% |
Path23
Path Summary:
Slack | 2.348 |
Data Arrival Time | 9.996 |
Data Required Time | 12.344 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_13_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.628 | 1.946 | tNET | RR | 1 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
3.011 | 0.382 | tC2Q | RR | 6 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
4.443 | 1.432 | tNET | RR | 1 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/I2 |
4.965 | 0.521 | tINS | RR | 22 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/F |
6.467 | 1.502 | tNET | RR | 1 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/I2 |
6.988 | 0.521 | tINS | RR | 8 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/F |
8.016 | 1.028 | tNET | RR | 1 | R16C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n739_s1/I3 |
8.477 | 0.461 | tINS | RR | 16 | R16C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n739_s1/F |
9.996 | 1.519 | tNET | RR | 1 | R21C21[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.655 | 1.972 | tNET | RR | 1 | R21C21[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_13_s0/CLK |
12.344 | -0.311 | tSu | 1 | R21C21[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_13_s0 |
Path Statistics:
Clock Skew | 0.027 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Arrival Data Path Delay | cell: 1.504, 20.411%; route: 5.481, 74.398%; tC2Q: 0.382, 5.192% |
Required Clock Path Delay | cell: 0.683, 25.706%; route: 1.972, 74.294% |
Path24
Path Summary:
Slack | 2.350 |
Data Arrival Time | 9.996 |
Data Required Time | 12.346 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_9_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.628 | 1.946 | tNET | RR | 1 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
3.011 | 0.382 | tC2Q | RR | 6 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
4.443 | 1.432 | tNET | RR | 1 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/I2 |
4.965 | 0.521 | tINS | RR | 22 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/F |
6.467 | 1.502 | tNET | RR | 1 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/I2 |
6.988 | 0.521 | tINS | RR | 8 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/F |
8.016 | 1.028 | tNET | RR | 1 | R16C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n739_s1/I3 |
8.477 | 0.461 | tINS | RR | 16 | R16C26[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n739_s1/F |
9.996 | 1.519 | tNET | RR | 1 | R20C21[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_9_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.658 | 1.975 | tNET | RR | 1 | R20C21[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_9_s0/CLK |
12.346 | -0.311 | tSu | 1 | R20C21[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[5]_9_s0 |
Path Statistics:
Clock Skew | 0.029 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Arrival Data Path Delay | cell: 1.504, 20.411%; route: 5.481, 74.398%; tC2Q: 0.382, 5.192% |
Required Clock Path Delay | cell: 0.683, 25.682%; route: 1.975, 74.318% |
Path25
Path Summary:
Slack | 2.384 |
Data Arrival Time | 9.926 |
Data Required Time | 12.310 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[1]_14_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
2.628 | 1.946 | tNET | RR | 1 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/CLK |
3.011 | 0.382 | tC2Q | RR | 6 | R26C26[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_load_flag_s0/Q |
4.443 | 1.432 | tNET | RR | 1 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/I2 |
4.965 | 0.521 | tINS | RR | 22 | R29C36[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[0].spram_coeff_inst/n660_s4/F |
6.467 | 1.502 | tNET | RR | 1 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/I2 |
6.988 | 0.521 | tINS | RR | 8 | R20C35[3][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n660_s1/F |
7.670 | 0.681 | tNET | RR | 1 | R20C29[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n675_s1/I3 |
8.186 | 0.516 | tINS | RR | 16 | R20C29[0][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/n675_s1/F |
9.926 | 1.740 | tNET | RR | 1 | R17C21[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[1]_14_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.621 | 1.939 | tNET | RR | 1 | R17C21[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[1]_14_s0/CLK |
12.310 | -0.311 | tSu | 1 | R17C21[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_spram_coeff[5].spram_coeff_inst/mem[1]_14_s0 |
Path Statistics:
Clock Skew | -0.007 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Arrival Data Path Delay | cell: 1.559, 21.360%; route: 5.356, 73.398%; tC2Q: 0.382, 5.242% |
Required Clock Path Delay | cell: 0.683, 26.037%; route: 1.939, 73.963% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.205 |
Data Arrival Time | 1.621 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.374 | 0.698 | tNET | RR | 1 | R11C65[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
1.515 | 0.141 | tC2Q | RF | 5 | R11C65[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q |
1.621 | 0.106 | tNET | FF | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[10] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.181%; route: 0.698, 50.819% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.106, 42.915%; tC2Q: 0.141, 57.085% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path2
Path Summary:
Slack | 0.208 |
Data Arrival Time | 1.623 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R9C66[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
1.523 | 0.144 | tC2Q | RR | 4 | R9C66[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q |
1.623 | 0.100 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[13] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.100, 40.984%; tC2Q: 0.144, 59.016% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path3
Path Summary:
Slack | 0.212 |
Data Arrival Time | 1.628 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.384 | 0.708 | tNET | RR | 1 | R9C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
1.528 | 0.144 | tC2Q | RR | 7 | R9C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q |
1.628 | 0.100 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.825%; route: 0.708, 51.175% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.100, 40.984%; tC2Q: 0.144, 59.016% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path4
Path Summary:
Slack | 0.215 |
Data Arrival Time | 1.629 |
Data Required Time | 1.413 |
From | sim_output_storage_inst/ram_dout_addrb_4_s3 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R3C68[2][A] | sim_output_storage_inst/ram_dout_addrb_4_s3/CLK |
1.538 | 0.141 | tC2Q | RF | 6 | R3C68[2][A] | sim_output_storage_inst/ram_dout_addrb_4_s3/Q |
1.629 | 0.091 | tNET | FF | 1 | BSRAM_R10[21] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[8] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[21] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
1.413 | 0.035 | tHld | 1 | BSRAM_R10[21] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | -0.018 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.091, 39.224%; tC2Q: 0.141, 60.776% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path5
Path Summary:
Slack | 0.223 |
Data Arrival Time | 1.639 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R8C66[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
1.529 | 0.144 | tC2Q | RR | 8 | R8C66[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q |
1.639 | 0.110 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.006 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.110, 43.307%; tC2Q: 0.144, 56.693% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path6
Path Summary:
Slack | 0.224 |
Data Arrival Time | 1.640 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.388 | 0.713 | tNET | RR | 1 | R8C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
1.533 | 0.144 | tC2Q | RR | 6 | R8C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
1.640 | 0.107 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.010 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.650%; route: 0.713, 51.350% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.107, 42.629%; tC2Q: 0.144, 57.371% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path7
Path Summary:
Slack | 0.236 |
Data Arrival Time | 1.651 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.391 | 0.716 | tNET | RR | 1 | R6C66[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/CLK |
1.535 | 0.144 | tC2Q | RR | 1 | R6C66[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q |
1.651 | 0.116 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.013 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.553%; route: 0.716, 51.447% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 44.615%; tC2Q: 0.144, 55.385% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path8
Path Summary:
Slack | 0.257 |
Data Arrival Time | 1.668 |
Data Required Time | 1.411 |
From | sim_output_storage_inst/ram_din_data_9_s0 |
To | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R11C68[1][A] | sim_output_storage_inst/ram_din_data_9_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 1 | R11C68[1][A] | sim_output_storage_inst/ram_din_data_9_s0/Q |
1.668 | 0.158 | tNET | FF | 1 | BSRAM_R10[21] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/DI[9] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.375 | 0.699 | tNET | RR | 1 | BSRAM_R10[21] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
1.411 | 0.037 | tHld | 1 | BSRAM_R10[21] | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.005 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157% |
Required Clock Path Delay | cell: 0.675, 49.145%; route: 0.699, 50.855% |
Path9
Path Summary:
Slack | 0.271 |
Data Arrival Time | 1.686 |
Data Required Time | 1.415 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.379 | 0.704 | tNET | RR | 1 | R9C66[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
1.523 | 0.144 | tC2Q | RR | 6 | R9C66[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q |
1.686 | 0.163 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.378 | 0.703 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
1.415 | 0.037 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.967%; route: 0.704, 51.033% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.163, 53.094%; tC2Q: 0.144, 46.906% |
Required Clock Path Delay | cell: 0.675, 49.003%; route: 0.703, 50.997% |
Path10
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.611 |
Data Required Time | 1.336 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/acc_out_18_s3 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/fir_acc_out_18_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R5C51[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/acc_out_18_s3/CLK |
1.533 | 0.144 | tC2Q | RR | 1 | R5C51[1][B] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/acc_out_18_s3/Q |
1.611 | 0.078 | tNET | RR | 1 | R5C51[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/fir_acc_out_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.389 | 0.714 | tNET | RR | 1 | R5C51[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/fir_acc_out_18_s0/CLK |
1.336 | -0.053 | tHld | 1 | R5C51[2][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/fir_acc_out_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.675, 48.632%; route: 0.714, 51.368% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865% |
Required Clock Path Delay | cell: 0.675, 48.632%; route: 0.714, 51.368% |
Path11
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.701 |
Data Required Time | 1.426 |
From | sim_output_storage_inst/ram_din_addra_4_s0 |
To | sim_output_storage_inst/ram_din_addra_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.401 | 0.725 | tNET | RR | 1 | R3C65[1][A] | sim_output_storage_inst/ram_din_addra_4_s0/CLK |
1.542 | 0.141 | tC2Q | RF | 5 | R3C65[1][A] | sim_output_storage_inst/ram_din_addra_4_s0/Q |
1.548 | 0.006 | tNET | FF | 1 | R3C65[1][A] | sim_output_storage_inst/n97_s1/I2 |
1.701 | 0.153 | tINS | FF | 1 | R3C65[1][A] | sim_output_storage_inst/n97_s1/F |
1.701 | 0.000 | tNET | FF | 1 | R3C65[1][A] | sim_output_storage_inst/ram_din_addra_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.401 | 0.725 | tNET | RR | 1 | R3C65[1][A] | sim_output_storage_inst/ram_din_addra_4_s0/CLK |
1.426 | 0.025 | tHld | 1 | R3C65[1][A] | sim_output_storage_inst/ram_din_addra_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.233%; route: 0.725, 51.767% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.233%; route: 0.725, 51.767% |
Path12
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.669 |
Data Required Time | 1.394 |
From | sim_input_gen_inst/cnt_chn_0_s0 |
To | sim_input_gen_inst/cnt_chn_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R29C22[0][A] | sim_input_gen_inst/cnt_chn_0_s0/CLK |
1.510 | 0.141 | tC2Q | RF | 3 | R29C22[0][A] | sim_input_gen_inst/cnt_chn_0_s0/Q |
1.516 | 0.006 | tNET | FF | 1 | R29C22[0][A] | sim_input_gen_inst/n49_s1/I2 |
1.669 | 0.153 | tINS | FF | 1 | R29C22[0][A] | sim_input_gen_inst/n49_s1/F |
1.669 | 0.000 | tNET | FF | 1 | R29C22[0][A] | sim_input_gen_inst/cnt_chn_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.369 | 0.694 | tNET | RR | 1 | R29C22[0][A] | sim_input_gen_inst/cnt_chn_0_s0/CLK |
1.394 | 0.025 | tHld | 1 | R29C22[0][A] | sim_input_gen_inst/cnt_chn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 49.325%; route: 0.694, 50.675% |
Path13
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.669 |
Data Required Time | 1.393 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_0_s1 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_0_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R14C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_0_s1/CLK |
1.510 | 0.141 | tC2Q | RF | 2 | R14C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_0_s1/Q |
1.516 | 0.006 | tNET | FF | 1 | R14C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n3254_s2/I0 |
1.669 | 0.153 | tINS | FF | 1 | R14C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n3254_s2/F |
1.669 | 0.000 | tNET | FF | 1 | R14C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.368 | 0.693 | tNET | RR | 1 | R14C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_0_s1/CLK |
1.393 | 0.025 | tHld | 1 | R14C50[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/cnt_acc_chn_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 49.361%; route: 0.693, 50.639% |
Path14
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.687 |
Data Required Time | 1.412 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_limit_1_s1 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_limit_1_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.387 | 0.712 | tNET | RR | 1 | R24C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_limit_1_s1/CLK |
1.528 | 0.141 | tC2Q | RF | 3 | R24C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_limit_1_s1/Q |
1.534 | 0.006 | tNET | FF | 1 | R24C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n342_s2/I3 |
1.687 | 0.153 | tINS | FF | 1 | R24C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n342_s2/F |
1.687 | 0.000 | tNET | FF | 1 | R24C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_limit_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.387 | 0.712 | tNET | RR | 1 | R24C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_limit_1_s1/CLK |
1.412 | 0.025 | tHld | 1 | R24C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_limit_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.693%; route: 0.712, 51.307% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.693%; route: 0.712, 51.307% |
Path15
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.685 |
Data Required Time | 1.410 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R26C28[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_0_s0/CLK |
1.526 | 0.141 | tC2Q | RF | 3 | R26C28[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_0_s0/Q |
1.532 | 0.006 | tNET | FF | 1 | R26C28[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n358_s3/I1 |
1.685 | 0.153 | tINS | FF | 1 | R26C28[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n358_s3/F |
1.685 | 0.000 | tNET | FF | 1 | R26C28[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.385 | 0.709 | tNET | RR | 1 | R26C28[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_0_s0/CLK |
1.410 | 0.025 | tHld | 1 | R26C28[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addrb_start_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.790%; route: 0.709, 51.210% |
Path16
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.686 |
Data Required Time | 1.410 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addra_0_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addra_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.385 | 0.710 | tNET | RR | 1 | R25C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addra_0_s0/CLK |
1.526 | 0.141 | tC2Q | RF | 3 | R25C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addra_0_s0/Q |
1.533 | 0.006 | tNET | FF | 1 | R25C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n278_s2/I1 |
1.686 | 0.153 | tINS | FF | 1 | R25C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n278_s2/F |
1.686 | 0.000 | tNET | FF | 1 | R25C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addra_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.385 | 0.710 | tNET | RR | 1 | R25C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addra_0_s0/CLK |
1.410 | 0.025 | tHld | 1 | R25C27[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/ram_shift_addra_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.755%; route: 0.710, 51.245% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.755%; route: 0.710, 51.245% |
Path17
Path Summary:
Slack | 0.275 |
Data Arrival Time | 1.686 |
Data Required Time | 1.410 |
From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.385 | 0.710 | tNET | RR | 1 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
1.526 | 0.141 | tC2Q | RF | 3 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q |
1.533 | 0.006 | tNET | FF | 1 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n236_s0/I1 |
1.686 | 0.153 | tINS | FF | 1 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n236_s0/F |
1.686 | 0.000 | tNET | FF | 1 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.385 | 0.710 | tNET | RR | 1 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
1.410 | 0.025 | tHld | 1 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.755%; route: 0.710, 51.245% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 0.675, 48.755%; route: 0.710, 51.245% |
Path18
Path Summary:
Slack | 0.275 |
Data Arrival Time | 2.703 |
Data Required Time | 2.428 |
From | gw_gao_inst_0/u_la0_top/bit_count_0_s1 |
To | gw_gao_inst_0/u_la0_top/bit_count_0_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.403 | 1.052 | tNET | RR | 1 | R31C65[1][A] | gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK |
2.544 | 0.141 | tC2Q | RF | 6 | R31C65[1][A] | gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q |
2.550 | 0.006 | tNET | FF | 1 | R31C65[1][A] | gw_gao_inst_0/u_la0_top/n527_s2/I0 |
2.703 | 0.153 | tINS | FF | 1 | R31C65[1][A] | gw_gao_inst_0/u_la0_top/n527_s2/F |
2.703 | 0.000 | tNET | FF | 1 | R31C65[1][A] | gw_gao_inst_0/u_la0_top/bit_count_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.403 | 1.052 | tNET | RR | 1 | R31C65[1][A] | gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK |
2.428 | 0.025 | tHld | 1 | R31C65[1][A] | gw_gao_inst_0/u_la0_top/bit_count_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 56.221%; route: 1.052, 43.779% |
Arrival Data Path Delay | cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000% |
Required Clock Path Delay | cell: 1.351, 56.221%; route: 1.052, 43.779% |
Path19
Path Summary:
Slack | 0.278 |
Data Arrival Time | 2.706 |
Data Required Time | 2.428 |
From | gw_gao_inst_0/u_la0_top/bit_count_2_s1 |
To | gw_gao_inst_0/u_la0_top/bit_count_2_s1 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.403 | 1.052 | tNET | RR | 1 | R31C67[1][A] | gw_gao_inst_0/u_la0_top/bit_count_2_s1/CLK |
2.544 | 0.141 | tC2Q | RF | 4 | R31C67[1][A] | gw_gao_inst_0/u_la0_top/bit_count_2_s1/Q |
2.553 | 0.009 | tNET | FF | 1 | R31C67[1][A] | gw_gao_inst_0/u_la0_top/n525_s4/I0 |
2.706 | 0.153 | tINS | FF | 1 | R31C67[1][A] | gw_gao_inst_0/u_la0_top/n525_s4/F |
2.706 | 0.000 | tNET | FF | 1 | R31C67[1][A] | gw_gao_inst_0/u_la0_top/bit_count_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.403 | 1.052 | tNET | RR | 1 | R31C67[1][A] | gw_gao_inst_0/u_la0_top/bit_count_2_s1/CLK |
2.428 | 0.025 | tHld | 1 | R31C67[1][A] | gw_gao_inst_0/u_la0_top/bit_count_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 56.221%; route: 1.052, 43.779% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 1.351, 56.221%; route: 1.052, 43.779% |
Path20
Path Summary:
Slack | 0.278 |
Data Arrival Time | 2.737 |
Data Required Time | 2.459 |
From | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
To | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.434 | 1.083 | tNET | RR | 1 | R24C68[0][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
2.575 | 0.141 | tC2Q | RF | 3 | R24C68[0][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/Q |
2.584 | 0.009 | tNET | FF | 1 | R24C68[0][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_3_s0/I1 |
2.737 | 0.153 | tINS | FF | 1 | R24C68[0][A] | gw_gao_inst_0/u_la0_top/data_to_word_counter_3_s0/F |
2.737 | 0.000 | tNET | FF | 1 | R24C68[0][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.434 | 1.083 | tNET | RR | 1 | R24C68[0][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK |
2.459 | 0.025 | tHld | 1 | R24C68[0][A] | gw_gao_inst_0/u_la0_top/word_count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 55.511%; route: 1.083, 44.489% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 1.351, 55.511%; route: 1.083, 44.489% |
Path21
Path Summary:
Slack | 0.278 |
Data Arrival Time | 2.731 |
Data Required Time | 2.453 |
From | gw_gao_inst_0/u_la0_top/address_counter_4_s0 |
To | gw_gao_inst_0/u_la0_top/address_counter_4_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.428 | 1.077 | tNET | RR | 1 | R7C69[0][A] | gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK |
2.569 | 0.141 | tC2Q | RF | 6 | R7C69[0][A] | gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q |
2.578 | 0.009 | tNET | FF | 1 | R7C69[0][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/I1 |
2.731 | 0.153 | tINS | FF | 1 | R7C69[0][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/F |
2.731 | 0.000 | tNET | FF | 1 | R7C69[0][A] | gw_gao_inst_0/u_la0_top/address_counter_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.428 | 1.077 | tNET | RR | 1 | R7C69[0][A] | gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK |
2.453 | 0.025 | tHld | 1 | R7C69[0][A] | gw_gao_inst_0/u_la0_top/address_counter_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 55.643%; route: 1.077, 44.357% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 1.351, 55.643%; route: 1.077, 44.357% |
Path22
Path Summary:
Slack | 0.278 |
Data Arrival Time | 2.722 |
Data Required Time | 2.444 |
From | gw_gao_inst_0/u_la0_top/address_counter_7_s0 |
To | gw_gao_inst_0/u_la0_top/address_counter_7_s0 |
Launch Clk | tck_pad_i:[R] |
Latch Clk | tck_pad_i:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.419 | 1.068 | tNET | RR | 1 | R26C66[0][A] | gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK |
2.560 | 0.141 | tC2Q | RF | 5 | R26C66[0][A] | gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q |
2.569 | 0.009 | tNET | FF | 1 | R26C66[0][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_7_s0/I1 |
2.722 | 0.153 | tINS | FF | 1 | R26C66[0][A] | gw_gao_inst_0/u_la0_top/data_to_addr_counter_7_s0/F |
2.722 | 0.000 | tNET | FF | 1 | R26C66[0][A] | gw_gao_inst_0/u_la0_top/address_counter_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | tck_pad_i | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/I |
0.675 | 0.675 | tINS | RR | 1 | IOR1[A] | gw_gao_inst_0/tck_ibuf/O |
0.675 | 0.000 | tNET | RR | 1 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_pad_i |
1.351 | 0.675 | tINS | RR | 225 | R28C89 | gw_gao_inst_0/u_gw_jtag/tck_o |
2.419 | 1.068 | tNET | RR | 1 | R26C66[0][A] | gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK |
2.444 | 0.025 | tHld | 1 | R26C66[0][A] | gw_gao_inst_0/u_la0_top/address_counter_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.351, 55.850%; route: 1.068, 44.150% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 1.351, 55.850%; route: 1.068, 44.150% |
Path23
Path Summary:
Slack | 0.278 |
Data Arrival Time | 1.700 |
Data Required Time | 1.422 |
From | sim_output_storage_inst/cnt_chn_0_s0 |
To | sim_output_storage_inst/cnt_chn_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R3C68[0][A] | sim_output_storage_inst/cnt_chn_0_s0/CLK |
1.538 | 0.141 | tC2Q | RF | 6 | R3C68[0][A] | sim_output_storage_inst/cnt_chn_0_s0/Q |
1.547 | 0.009 | tNET | FF | 1 | R3C68[0][A] | sim_output_storage_inst/n47_s3/I0 |
1.700 | 0.153 | tINS | FF | 1 | R3C68[0][A] | sim_output_storage_inst/n47_s3/F |
1.700 | 0.000 | tNET | FF | 1 | R3C68[0][A] | sim_output_storage_inst/cnt_chn_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R3C68[0][A] | sim_output_storage_inst/cnt_chn_0_s0/CLK |
1.422 | 0.025 | tHld | 1 | R3C68[0][A] | sim_output_storage_inst/cnt_chn_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Path24
Path Summary:
Slack | 0.278 |
Data Arrival Time | 1.668 |
Data Required Time | 1.390 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_index_cnt_5_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_index_cnt_5_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.365 | 0.689 | tNET | RR | 1 | R30C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_index_cnt_5_s0/CLK |
1.506 | 0.141 | tC2Q | RF | 5 | R30C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_index_cnt_5_s0/Q |
1.515 | 0.009 | tNET | FF | 1 | R30C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n976_s2/I3 |
1.668 | 0.153 | tINS | FF | 1 | R30C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n976_s2/F |
1.668 | 0.000 | tNET | FF | 1 | R30C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_index_cnt_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.365 | 0.689 | tNET | RR | 1 | R30C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_index_cnt_5_s0/CLK |
1.390 | 0.025 | tHld | 1 | R30C37[1][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_index_cnt_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 49.505%; route: 0.689, 50.495% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 0.675, 49.505%; route: 0.689, 50.495% |
Path25
Path Summary:
Slack | 0.278 |
Data Arrival Time | 1.705 |
Data Required Time | 1.427 |
From | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
To | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
1.543 | 0.141 | tC2Q | RF | 153 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/Q |
1.552 | 0.009 | tNET | FF | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n945_s2/I2 |
1.705 | 0.153 | tINS | FF | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/n945_s2/F |
1.705 | 0.000 | tNET | FF | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0/CLK |
1.427 | 0.025 | tHld | 1 | R20C37[0][A] | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addra_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Arrival Data Path Delay | cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 2.184 |
Data Arrival Time | 10.076 |
Data Required Time | 12.259 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
10.076 | 1.983 | tNET | FF | 1 | R11C68[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.607 | 1.924 | tNET | RR | 1 | R11C68[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
12.259 | -0.347 | tSu | 1 | R11C68[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
Clock Skew | -0.044 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.983, 81.753%; tC2Q: 0.442, 18.247% |
Required Clock Path Delay | cell: 0.683, 26.181%; route: 1.924, 73.819% |
Path2
Path Summary:
Slack | 2.293 |
Data Arrival Time | 9.997 |
Data Required Time | 12.290 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.997 | 1.904 | tNET | FF | 1 | R8C65[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.638 | 1.955 | tNET | RR | 1 | R8C65[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
12.290 | -0.347 | tSu | 1 | R8C65[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.904, 81.140%; tC2Q: 0.442, 18.860% |
Required Clock Path Delay | cell: 0.683, 25.874%; route: 1.955, 74.126% |
Path3
Path Summary:
Slack | 2.293 |
Data Arrival Time | 9.997 |
Data Required Time | 12.290 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.997 | 1.904 | tNET | FF | 1 | R8C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.638 | 1.955 | tNET | RR | 1 | R8C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
12.290 | -0.347 | tSu | 1 | R8C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
Clock Skew | -0.013 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.904, 81.140%; tC2Q: 0.442, 18.860% |
Required Clock Path Delay | cell: 0.683, 25.874%; route: 1.955, 74.126% |
Path4
Path Summary:
Slack | 2.358 |
Data Arrival Time | 9.892 |
Data Required Time | 12.250 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.892 | 1.799 | tNET | FF | 1 | R11C67[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.597 | 1.915 | tNET | RR | 1 | R11C67[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
12.250 | -0.347 | tSu | 1 | R11C67[0][B] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
Clock Skew | -0.053 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.799, 80.257%; tC2Q: 0.442, 19.743% |
Required Clock Path Delay | cell: 0.683, 26.275%; route: 1.915, 73.725% |
Path5
Path Summary:
Slack | 2.358 |
Data Arrival Time | 9.892 |
Data Required Time | 12.250 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.892 | 1.799 | tNET | FF | 1 | R11C67[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.597 | 1.915 | tNET | RR | 1 | R11C67[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
12.250 | -0.347 | tSu | 1 | R11C67[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
Clock Skew | -0.053 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.799, 80.257%; tC2Q: 0.442, 19.743% |
Required Clock Path Delay | cell: 0.683, 26.275%; route: 1.915, 73.725% |
Path6
Path Summary:
Slack | 2.358 |
Data Arrival Time | 9.892 |
Data Required Time | 12.250 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.892 | 1.799 | tNET | FF | 1 | R11C67[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.597 | 1.915 | tNET | RR | 1 | R11C67[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
12.250 | -0.347 | tSu | 1 | R11C67[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
Clock Skew | -0.053 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.799, 80.257%; tC2Q: 0.442, 19.743% |
Required Clock Path Delay | cell: 0.683, 26.275%; route: 1.915, 73.725% |
Path7
Path Summary:
Slack | 2.628 |
Data Arrival Time | 9.641 |
Data Required Time | 12.269 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.641 | 1.548 | tNET | FF | 1 | R11C65[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.616 | 1.934 | tNET | RR | 1 | R11C65[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
12.269 | -0.347 | tSu | 1 | R11C65[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
Clock Skew | -0.034 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.548, 77.764%; tC2Q: 0.442, 22.236% |
Required Clock Path Delay | cell: 0.683, 26.087%; route: 1.934, 73.913% |
Path8
Path Summary:
Slack | 2.682 |
Data Arrival Time | 9.592 |
Data Required Time | 12.274 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.592 | 1.499 | tNET | FF | 1 | R9C66[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.621 | 1.939 | tNET | RR | 1 | R9C66[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
12.274 | -0.347 | tSu | 1 | R9C66[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
Clock Skew | -0.029 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.499, 77.205%; tC2Q: 0.442, 22.795% |
Required Clock Path Delay | cell: 0.683, 26.037%; route: 1.939, 73.963% |
Path9
Path Summary:
Slack | 2.682 |
Data Arrival Time | 9.592 |
Data Required Time | 12.274 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.592 | 1.499 | tNET | FF | 1 | R9C66[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.621 | 1.939 | tNET | RR | 1 | R9C66[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
12.274 | -0.347 | tSu | 1 | R9C66[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
Clock Skew | -0.029 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.499, 77.205%; tC2Q: 0.442, 22.795% |
Required Clock Path Delay | cell: 0.683, 26.037%; route: 1.939, 73.963% |
Path10
Path Summary:
Slack | 2.691 |
Data Arrival Time | 9.592 |
Data Required Time | 12.283 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.592 | 1.499 | tNET | FF | 1 | R9C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.631 | 1.948 | tNET | RR | 1 | R9C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
12.283 | -0.347 | tSu | 1 | R9C65[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.499, 77.205%; tC2Q: 0.442, 22.795% |
Required Clock Path Delay | cell: 0.683, 25.944%; route: 1.948, 74.056% |
Path11
Path Summary:
Slack | 2.691 |
Data Arrival Time | 9.592 |
Data Required Time | 12.283 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.592 | 1.499 | tNET | FF | 1 | R9C65[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.631 | 1.948 | tNET | RR | 1 | R9C65[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
12.283 | -0.347 | tSu | 1 | R9C65[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
Clock Skew | -0.020 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.499, 77.205%; tC2Q: 0.442, 22.795% |
Required Clock Path Delay | cell: 0.683, 25.944%; route: 1.948, 74.056% |
Path12
Path Summary:
Slack | 2.767 |
Data Arrival Time | 9.517 |
Data Required Time | 12.284 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.517 | 1.424 | tNET | FF | 1 | R5C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.631 | 1.949 | tNET | RR | 1 | R5C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK |
12.284 | -0.347 | tSu | 1 | R5C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0 |
Path Statistics:
Clock Skew | -0.019 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.424, 76.289%; tC2Q: 0.442, 23.711% |
Required Clock Path Delay | cell: 0.683, 25.938%; route: 1.949, 74.062% |
Path13
Path Summary:
Slack | 3.097 |
Data Arrival Time | 9.174 |
Data Required Time | 12.272 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.174 | 1.081 | tNET | FF | 1 | R8C67[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.619 | 1.937 | tNET | RR | 1 | R8C67[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
12.272 | -0.347 | tSu | 1 | R8C67[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
Clock Skew | -0.032 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.081, 70.960%; tC2Q: 0.442, 29.040% |
Required Clock Path Delay | cell: 0.683, 26.059%; route: 1.937, 73.941% |
Path14
Path Summary:
Slack | 3.097 |
Data Arrival Time | 9.174 |
Data Required Time | 12.272 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.174 | 1.081 | tNET | FF | 1 | R8C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.619 | 1.937 | tNET | RR | 1 | R8C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
12.272 | -0.347 | tSu | 1 | R8C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
Clock Skew | -0.032 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.081, 70.960%; tC2Q: 0.442, 29.040% |
Required Clock Path Delay | cell: 0.683, 26.059%; route: 1.937, 73.941% |
Path15
Path Summary:
Slack | 3.107 |
Data Arrival Time | 9.174 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.174 | 1.081 | tNET | FF | 1 | R8C66[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R8C66[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
12.281 | -0.347 | tSu | 1 | R8C66[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Path Statistics:
Clock Skew | -0.022 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.081, 70.960%; tC2Q: 0.442, 29.040% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path16
Path Summary:
Slack | 3.107 |
Data Arrival Time | 9.174 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.174 | 1.081 | tNET | FF | 1 | R8C66[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R8C66[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
12.281 | -0.347 | tSu | 1 | R8C66[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
Clock Skew | -0.022 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.081, 70.960%; tC2Q: 0.442, 29.040% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path17
Path Summary:
Slack | 3.107 |
Data Arrival Time | 9.174 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.174 | 1.081 | tNET | FF | 1 | R8C66[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R8C66[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
12.281 | -0.347 | tSu | 1 | R8C66[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
Clock Skew | -0.022 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.081, 70.960%; tC2Q: 0.442, 29.040% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path18
Path Summary:
Slack | 3.107 |
Data Arrival Time | 9.174 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.174 | 1.081 | tNET | FF | 1 | R8C66[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R8C66[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
12.281 | -0.347 | tSu | 1 | R8C66[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
Clock Skew | -0.022 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.081, 70.960%; tC2Q: 0.442, 29.040% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path19
Path Summary:
Slack | 3.107 |
Data Arrival Time | 9.174 |
Data Required Time | 12.281 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.174 | 1.081 | tNET | FF | 1 | R8C66[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.628 | 1.946 | tNET | RR | 1 | R8C66[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
12.281 | -0.347 | tSu | 1 | R8C66[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
Clock Skew | -0.022 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.081, 70.960%; tC2Q: 0.442, 29.040% |
Required Clock Path Delay | cell: 0.683, 25.966%; route: 1.946, 74.034% |
Path20
Path Summary:
Slack | 3.129 |
Data Arrival Time | 9.149 |
Data Required Time | 12.279 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.149 | 1.056 | tNET | FF | 1 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.626 | 1.944 | tNET | RR | 1 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
12.279 | -0.347 | tSu | 1 | R7C67[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
Clock Skew | -0.024 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.056, 70.475%; tC2Q: 0.442, 29.525% |
Required Clock Path Delay | cell: 0.683, 25.988%; route: 1.944, 74.012% |
Path21
Path Summary:
Slack | 3.129 |
Data Arrival Time | 9.149 |
Data Required Time | 12.279 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.149 | 1.056 | tNET | FF | 1 | R7C67[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.626 | 1.944 | tNET | RR | 1 | R7C67[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
12.279 | -0.347 | tSu | 1 | R7C67[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
Clock Skew | -0.024 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.056, 70.475%; tC2Q: 0.442, 29.525% |
Required Clock Path Delay | cell: 0.683, 25.988%; route: 1.944, 74.012% |
Path22
Path Summary:
Slack | 3.129 |
Data Arrival Time | 9.149 |
Data Required Time | 12.279 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.149 | 1.056 | tNET | FF | 1 | R7C67[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.626 | 1.944 | tNET | RR | 1 | R7C67[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
12.279 | -0.347 | tSu | 1 | R7C67[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
Clock Skew | -0.024 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.056, 70.475%; tC2Q: 0.442, 29.525% |
Required Clock Path Delay | cell: 0.683, 25.988%; route: 1.944, 74.012% |
Path23
Path Summary:
Slack | 3.139 |
Data Arrival Time | 9.149 |
Data Required Time | 12.288 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.149 | 1.056 | tNET | FF | 1 | R7C66[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.636 | 1.953 | tNET | RR | 1 | R7C66[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
12.288 | -0.347 | tSu | 1 | R7C66[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.056, 70.475%; tC2Q: 0.442, 29.525% |
Required Clock Path Delay | cell: 0.683, 25.895%; route: 1.953, 74.105% |
Path24
Path Summary:
Slack | 3.139 |
Data Arrival Time | 9.149 |
Data Required Time | 12.288 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.149 | 1.056 | tNET | FF | 1 | R7C66[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.636 | 1.953 | tNET | RR | 1 | R7C66[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
12.288 | -0.347 | tSu | 1 | R7C66[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.056, 70.475%; tC2Q: 0.442, 29.525% |
Required Clock Path Delay | cell: 0.683, 25.895%; route: 1.953, 74.105% |
Path25
Path Summary:
Slack | 3.139 |
Data Arrival Time | 9.149 |
Data Required Time | 12.288 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
7.651 | 1.963 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
8.093 | 0.442 | tC2Q | FF | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
9.149 | 1.056 | tNET | FF | 1 | R7C66[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clk | ||||
10.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
12.636 | 1.953 | tNET | RR | 1 | R7C66[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
12.288 | -0.347 | tSu | 1 | R7C66[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
Clock Skew | -0.015 |
Setup Relationship | 5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.688, 25.937%; route: 1.963, 74.063% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.056, 70.475%; tC2Q: 0.442, 29.525% |
Required Clock Path Delay | cell: 0.683, 25.895%; route: 1.953, 74.105% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 5.361 |
Data Arrival Time | 6.710 |
Data Required Time | 1.349 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.710 | 0.149 | tNET | RR | 1 | R20C65[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R20C65[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
1.349 | -0.053 | tHld | 1 | R20C65[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.149, 48.534%; tC2Q: 0.158, 51.466% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Path2
Path Summary:
Slack | 5.361 |
Data Arrival Time | 6.710 |
Data Required Time | 1.349 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.710 | 0.149 | tNET | RR | 1 | R20C65[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R20C65[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
1.349 | -0.053 | tHld | 1 | R20C65[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.149, 48.534%; tC2Q: 0.158, 51.466% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Path3
Path Summary:
Slack | 5.361 |
Data Arrival Time | 6.710 |
Data Required Time | 1.349 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.710 | 0.149 | tNET | RR | 1 | R20C65[3][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.402 | 0.727 | tNET | RR | 1 | R20C65[3][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
1.349 | -0.053 | tHld | 1 | R20C65[3][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
Clock Skew | -0.001 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.149, 48.534%; tC2Q: 0.158, 51.466% |
Required Clock Path Delay | cell: 0.675, 48.173%; route: 0.727, 51.827% |
Path4
Path Summary:
Slack | 5.367 |
Data Arrival Time | 6.712 |
Data Required Time | 1.345 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.712 | 0.151 | tNET | RR | 1 | R20C66[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R20C66[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
1.345 | -0.053 | tHld | 1 | R20C66[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.151, 48.867%; tC2Q: 0.158, 51.133% |
Required Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Path5
Path Summary:
Slack | 5.367 |
Data Arrival Time | 6.712 |
Data Required Time | 1.345 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.712 | 0.151 | tNET | RR | 1 | R20C66[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R20C66[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
1.345 | -0.053 | tHld | 1 | R20C66[1][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.151, 48.867%; tC2Q: 0.158, 51.133% |
Required Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Path6
Path Summary:
Slack | 5.367 |
Data Arrival Time | 6.712 |
Data Required Time | 1.345 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.712 | 0.151 | tNET | RR | 1 | R20C66[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R20C66[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
1.345 | -0.053 | tHld | 1 | R20C66[2][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.151, 48.867%; tC2Q: 0.158, 51.133% |
Required Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Path7
Path Summary:
Slack | 5.367 |
Data Arrival Time | 6.712 |
Data Required Time | 1.345 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.712 | 0.151 | tNET | RR | 1 | R20C66[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R20C66[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
1.345 | -0.053 | tHld | 1 | R20C66[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.151, 48.867%; tC2Q: 0.158, 51.133% |
Required Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Path8
Path Summary:
Slack | 5.367 |
Data Arrival Time | 6.712 |
Data Required Time | 1.345 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.712 | 0.151 | tNET | RR | 1 | R20C66[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R20C66[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
1.345 | -0.053 | tHld | 1 | R20C66[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.151, 48.867%; tC2Q: 0.158, 51.133% |
Required Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Path9
Path Summary:
Slack | 5.422 |
Data Arrival Time | 6.765 |
Data Required Time | 1.344 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.765 | 0.204 | tNET | RR | 1 | R21C68[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R21C68[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK |
1.344 | -0.053 | tHld | 1 | R21C68[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.204, 56.354%; tC2Q: 0.158, 43.646% |
Required Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Path10
Path Summary:
Slack | 5.422 |
Data Arrival Time | 6.765 |
Data Required Time | 1.344 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.765 | 0.204 | tNET | RR | 1 | R21C68[3][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R21C68[3][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
1.344 | -0.053 | tHld | 1 | R21C68[3][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.204, 56.354%; tC2Q: 0.158, 43.646% |
Required Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Path11
Path Summary:
Slack | 5.422 |
Data Arrival Time | 6.765 |
Data Required Time | 1.344 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.765 | 0.204 | tNET | RR | 1 | R21C68[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R21C68[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
1.344 | -0.053 | tHld | 1 | R21C68[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.204, 56.354%; tC2Q: 0.158, 43.646% |
Required Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Path12
Path Summary:
Slack | 5.422 |
Data Arrival Time | 6.765 |
Data Required Time | 1.344 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.765 | 0.204 | tNET | RR | 1 | R21C68[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R21C68[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK |
1.344 | -0.053 | tHld | 1 | R21C68[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.204, 56.354%; tC2Q: 0.158, 43.646% |
Required Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Path13
Path Summary:
Slack | 5.422 |
Data Arrival Time | 6.765 |
Data Required Time | 1.344 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.765 | 0.204 | tNET | RR | 1 | R21C68[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.397 | 0.721 | tNET | RR | 1 | R21C68[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
1.344 | -0.053 | tHld | 1 | R21C68[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
Clock Skew | -0.007 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.204, 56.354%; tC2Q: 0.158, 43.646% |
Required Clock Path Delay | cell: 0.675, 48.371%; route: 0.721, 51.629% |
Path14
Path Summary:
Slack | 5.426 |
Data Arrival Time | 6.765 |
Data Required Time | 1.339 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.765 | 0.204 | tNET | RR | 1 | R21C67[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.392 | 0.717 | tNET | RR | 1 | R21C67[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
1.339 | -0.053 | tHld | 1 | R21C67[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.204, 56.354%; tC2Q: 0.158, 43.646% |
Required Clock Path Delay | cell: 0.675, 48.510%; route: 0.717, 51.490% |
Path15
Path Summary:
Slack | 5.426 |
Data Arrival Time | 6.765 |
Data Required Time | 1.339 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.765 | 0.204 | tNET | RR | 1 | R21C67[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.392 | 0.717 | tNET | RR | 1 | R21C67[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
1.339 | -0.053 | tHld | 1 | R21C67[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
Clock Skew | -0.011 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.204, 56.354%; tC2Q: 0.158, 43.646% |
Required Clock Path Delay | cell: 0.675, 48.510%; route: 0.717, 51.490% |
Path16
Path Summary:
Slack | 5.477 |
Data Arrival Time | 6.818 |
Data Required Time | 1.341 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.818 | 0.257 | tNET | RR | 1 | R20C67[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.394 | 0.719 | tNET | RR | 1 | R20C67[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
1.341 | -0.053 | tHld | 1 | R20C67[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.257, 61.928%; tC2Q: 0.158, 38.072% |
Required Clock Path Delay | cell: 0.675, 48.449%; route: 0.719, 51.551% |
Path17
Path Summary:
Slack | 5.477 |
Data Arrival Time | 6.818 |
Data Required Time | 1.341 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.818 | 0.257 | tNET | RR | 1 | R20C67[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.394 | 0.719 | tNET | RR | 1 | R20C67[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
1.341 | -0.053 | tHld | 1 | R20C67[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.257, 61.928%; tC2Q: 0.158, 38.072% |
Required Clock Path Delay | cell: 0.675, 48.449%; route: 0.719, 51.551% |
Path18
Path Summary:
Slack | 5.477 |
Data Arrival Time | 6.818 |
Data Required Time | 1.341 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.818 | 0.257 | tNET | RR | 1 | R20C67[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.394 | 0.719 | tNET | RR | 1 | R20C67[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
1.341 | -0.053 | tHld | 1 | R20C67[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
Clock Skew | -0.009 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.257, 61.928%; tC2Q: 0.158, 38.072% |
Required Clock Path Delay | cell: 0.675, 48.449%; route: 0.719, 51.551% |
Path19
Path Summary:
Slack | 5.516 |
Data Arrival Time | 6.863 |
Data Required Time | 1.348 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.863 | 0.302 | tNET | RR | 1 | R21C69[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.401 | 0.725 | tNET | RR | 1 | R21C69[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
1.348 | -0.053 | tHld | 1 | R21C69[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.302, 65.652%; tC2Q: 0.158, 34.348% |
Required Clock Path Delay | cell: 0.675, 48.233%; route: 0.725, 51.767% |
Path20
Path Summary:
Slack | 5.516 |
Data Arrival Time | 6.863 |
Data Required Time | 1.348 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.863 | 0.302 | tNET | RR | 1 | R21C69[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.401 | 0.725 | tNET | RR | 1 | R21C69[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
1.348 | -0.053 | tHld | 1 | R21C69[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
Clock Skew | -0.003 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.302, 65.652%; tC2Q: 0.158, 34.348% |
Required Clock Path Delay | cell: 0.675, 48.233%; route: 0.725, 51.767% |
Path21
Path Summary:
Slack | 5.527 |
Data Arrival Time | 6.849 |
Data Required Time | 1.322 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.849 | 0.288 | tNET | RR | 1 | R17C66[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.375 | 0.700 | tNET | RR | 1 | R17C66[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
1.322 | -0.053 | tHld | 1 | R17C66[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
Clock Skew | -0.029 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.288, 64.574%; tC2Q: 0.158, 35.426% |
Required Clock Path Delay | cell: 0.675, 49.127%; route: 0.700, 50.873% |
Path22
Path Summary:
Slack | 5.577 |
Data Arrival Time | 6.922 |
Data Required Time | 1.345 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
6.922 | 0.361 | tNET | RR | 1 | R20C68[2][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.398 | 0.723 | tNET | RR | 1 | R20C68[2][A] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
1.345 | -0.053 | tHld | 1 | R20C68[2][A] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
Clock Skew | -0.005 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.361, 69.557%; tC2Q: 0.158, 30.443% |
Required Clock Path Delay | cell: 0.675, 48.310%; route: 0.723, 51.690% |
Path23
Path Summary:
Slack | 5.676 |
Data Arrival Time | 7.003 |
Data Required Time | 1.327 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.003 | 0.442 | tNET | RR | 1 | R18C69[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.380 | 0.705 | tNET | RR | 1 | R18C69[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
1.327 | -0.053 | tHld | 1 | R18C69[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
Clock Skew | -0.023 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.442, 73.667%; tC2Q: 0.158, 26.333% |
Required Clock Path Delay | cell: 0.675, 48.940%; route: 0.705, 51.060% |
Path24
Path Summary:
Slack | 5.681 |
Data Arrival Time | 7.004 |
Data Required Time | 1.323 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.004 | 0.443 | tNET | RR | 1 | R18C68[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.376 | 0.701 | tNET | RR | 1 | R18C68[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
1.323 | -0.053 | tHld | 1 | R18C68[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
Clock Skew | -0.027 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.443, 73.710%; tC2Q: 0.158, 26.290% |
Required Clock Path Delay | cell: 0.675, 49.083%; route: 0.701, 50.917% |
Path25
Path Summary:
Slack | 5.681 |
Data Arrival Time | 7.004 |
Data Required Time | 1.323 |
From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Launch Clk | clk:[F] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
5.000 | 5.000 | active clock edge time | ||||
5.000 | 0.000 | clk | ||||
5.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
5.677 | 0.678 | tINS | FF | 6279 | IOB29[A] | clk_ibuf/O |
6.403 | 0.726 | tNET | FF | 1 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
6.561 | 0.158 | tC2Q | FR | 53 | R21C66[2][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
7.004 | 0.443 | tNET | RR | 1 | R18C68[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
0.675 | 0.675 | tINS | RR | 6279 | IOB29[A] | clk_ibuf/O |
1.376 | 0.701 | tNET | RR | 1 | R18C68[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
1.323 | -0.053 | tHld | 1 | R18C68[1][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
Clock Skew | -0.027 |
Hold Relationship | -5.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.678, 48.272%; route: 0.726, 51.728% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.443, 73.710%; tC2Q: 0.158, 26.290% |
Required Clock Path Delay | cell: 0.675, 49.083%; route: 0.701, 50.917% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.751 |
Actual Width: | 3.751 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.627 | 1.940 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.703 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
MPW2
MPW Summary:
Slack: | 2.751 |
Actual Width: | 3.751 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.627 | 1.940 | tNET | FF | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.703 | tNET | RR | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB |
MPW3
MPW Summary:
Slack: | 2.754 |
Actual Width: | 3.754 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[11].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.628 | 1.940 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[11].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.382 | 0.706 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[11].mult_dsp_inst/n47_s1/CLK[0] |
MPW4
MPW Summary:
Slack: | 2.754 |
Actual Width: | 3.754 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[12].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.628 | 1.940 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[12].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.382 | 0.706 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[12].mult_dsp_inst/n47_s1/CLK[0] |
MPW5
MPW Summary:
Slack: | 2.754 |
Actual Width: | 3.754 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[14].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.628 | 1.940 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[14].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.382 | 0.706 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[14].mult_dsp_inst/n47_s1/CLK[0] |
MPW6
MPW Summary:
Slack: | 2.754 |
Actual Width: | 3.754 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.628 | 1.940 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.382 | 0.706 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[17].mult_dsp_inst/n47_s1/CLK[0] |
MPW7
MPW Summary:
Slack: | 2.757 |
Actual Width: | 3.757 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.930 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.375 | 0.699 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW8
MPW Summary:
Slack: | 2.757 |
Actual Width: | 3.757 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.930 | tNET | FF | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.375 | 0.699 | tNET | RR | sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA |
MPW9
MPW Summary:
Slack: | 2.757 |
Actual Width: | 3.757 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_rom_inst/mem_mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.930 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_rom_inst/mem_mem_0_0_s/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.375 | 0.699 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/coeff_rom_inst/mem_mem_0_0_s/CLK |
MPW10
MPW Summary:
Slack: | 2.759 |
Actual Width: | 3.759 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | clk |
Objects: | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/n47_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clk | ||
5.000 | 0.000 | tCL | FF | clk_ibuf/I |
5.688 | 0.688 | tINS | FF | clk_ibuf/O |
7.618 | 1.931 | tNET | FF | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/n47_s1/CLK[0] |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk | ||
10.000 | 0.000 | tCL | RR | clk_ibuf/I |
10.675 | 0.675 | tINS | RR | clk_ibuf/O |
11.378 | 0.702 | tNET | RR | Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_fractional_inst/gen_mult_dsp[19].mult_dsp_inst/n47_s1/CLK[0] |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
6279 | clk_d | 1.521 | 1.985 |
1344 | coeff_ram_addrb[0] | 3.097 | 5.759 |
672 | coeff_ram_addrb[1] | 4.430 | 4.802 |
642 | mult_valid | 6.467 | 3.076 |
373 | mult_out_valid | 7.237 | 2.344 |
337 | delay_shift_addrb[0] | 5.439 | 3.646 |
336 | coeff_ram_addrb[2] | 4.221 | 5.153 |
320 | n284_5 | 4.878 | 2.141 |
320 | n269_7 | 5.022 | 2.000 |
225 | control0[0] | 3.574 | 2.735 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R19C67 | 63.89% |
R10C65 | 56.94% |
R11C62 | 56.94% |
R19C65 | 55.56% |
R19C62 | 54.17% |
R19C68 | 54.17% |
R19C56 | 54.17% |
R13C68 | 52.78% |
R11C63 | 52.78% |
R19C23 | 52.78% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}] |