Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\advanced_fir_filter.v
C:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\advanced_fir_filter_wrap.v
C:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\static_macro_define.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Dec 24 17:57:24 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Advanced_FIR_Filter_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.54s, Peak memory usage = 135.344MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 135.344MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.206s, Peak memory usage = 135.344MB
    Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 135.344MB
    Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.204s, Peak memory usage = 135.344MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 135.344MB
    Inferring Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 135.344MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 135.344MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 135.344MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 135.344MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 135.344MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 135.344MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.841s, Peak memory usage = 152.461MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.154s, Peak memory usage = 152.461MB
Generate output files:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.167s, Peak memory usage = 152.461MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 152.461MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 39
I/O Buf 39
    IBUF 20
    OBUF 19
Register 1382
    DFFPE 65
    DFFCE 1317
LUT 1021
    LUT2 293
    LUT3 527
    LUT4 201
ALU 47
    ALU 47
INV 8
    INV 8
DSP
    MULTALU27X18 1
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1076(1029 LUT, 47 ALU) / 23040 5%
Register 1382 / 23685 6%
  --Register as Latch 0 / 23685 0%
  --Register as FF 1382 / 23685 6%
BSRAM 1 / 56 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 139.714(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.843
Data Arrival Time 7.469
Data Required Time 10.311
From advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s667
To advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_s48
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1385 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s667/CLK
0.757 0.382 tC2Q RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s667/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1933/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1933/F
2.034 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1829/I1
2.170 0.136 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1829/O
2.545 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1777/I1
2.631 0.086 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1777/O
3.006 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1751/I1
3.093 0.086 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1751/O
3.468 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1382/I1
3.554 0.086 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1382/O
3.929 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1700/I0
4.455 0.526 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1700/F
4.830 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1685/I0
5.356 0.526 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1685/F
5.731 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1642/I2
6.193 0.461 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_CL_s1642/F
6.568 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_init/I0
7.094 0.526 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_init/F
7.469 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_s48/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1385 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_s48/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/mem[0]_ER_s48
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.961, 41.744%; route: 3.750, 52.864%; tC2Q: 0.382, 5.392%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 5.109
Data Arrival Time 5.202
Data Required Time 10.311
From advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0
To advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_6_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1385 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/CLK
0.757 0.382 tC2Q RR 5 advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/Q
1.132 0.375 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/I1
1.695 0.563 tINS RF 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/COUT
1.695 0.000 tNET FF 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/CIN
1.745 0.050 tINS FR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/COUT
1.745 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/CIN
1.795 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/COUT
1.795 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/CIN
1.845 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/COUT
1.845 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/CIN
1.895 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/COUT
1.895 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/CIN
1.945 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/COUT
1.945 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/CIN
2.189 0.244 tINS RR 3 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/SUM
2.564 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/I0
3.090 0.526 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/F
3.465 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/I2
3.926 0.461 tINS RR 3 advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/F
4.301 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n527_s0/I0
4.827 0.526 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n527_s0/F
5.202 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1385 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_6_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.570, 53.237%; route: 1.875, 38.840%; tC2Q: 0.382, 7.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 5.119
Data Arrival Time 5.192
Data Required Time 10.311
From advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0
To advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_7_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1385 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/CLK
0.757 0.382 tC2Q RR 5 advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/Q
1.132 0.375 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/I1
1.695 0.563 tINS RF 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/COUT
1.695 0.000 tNET FF 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/CIN
1.745 0.050 tINS FR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/COUT
1.745 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/CIN
1.795 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/COUT
1.795 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/CIN
1.845 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/COUT
1.845 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/CIN
1.895 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/COUT
1.895 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/CIN
1.945 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/COUT
1.945 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/CIN
2.189 0.244 tINS RR 3 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/SUM
2.564 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/I0
3.090 0.526 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/F
3.465 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/I2
3.926 0.461 tINS RR 3 advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/F
4.301 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s0/I1
4.817 0.516 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s0/F
5.192 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1385 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_7_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.560, 53.139%; route: 1.875, 38.921%; tC2Q: 0.382, 7.940%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 5.174
Data Arrival Time 5.137
Data Required Time 10.311
From advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0
To advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_5_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1385 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/CLK
0.757 0.382 tC2Q RR 5 advanced_fir_filter_inst/fir_singlerate_inst/cnt_tdm_d0_0_s0/Q
1.132 0.375 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/I1
1.695 0.563 tINS RF 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_0_s/COUT
1.695 0.000 tNET FF 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/CIN
1.745 0.050 tINS FR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_1_s/COUT
1.745 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/CIN
1.795 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_2_s/COUT
1.795 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/CIN
1.845 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_3_s/COUT
1.845 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/CIN
1.895 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_4_s/COUT
1.895 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/CIN
1.945 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_5_s/COUT
1.945 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/CIN
2.189 0.244 tINS RR 3 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_precal_6_s/SUM
2.564 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/I0
3.090 0.526 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s3/F
3.465 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/I2
3.926 0.461 tINS RR 3 advanced_fir_filter_inst/fir_singlerate_inst/n526_s1/F
4.301 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n528_s0/I2
4.762 0.461 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n528_s0/F
5.137 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1385 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_5_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_addrb_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.505, 52.599%; route: 1.875, 39.370%; tC2Q: 0.382, 8.031%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 5.406
Data Arrival Time 4.905
Data Required Time 10.311
From advanced_fir_filter_inst/fir_singlerate_inst/acc_out_0_s1
To advanced_fir_filter_inst/fir_singlerate_inst/acc_out_35_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1385 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/acc_out_0_s1/CLK
0.757 0.382 tC2Q RR 1 advanced_fir_filter_inst/fir_singlerate_inst/acc_out_0_s1/Q
1.132 0.375 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1043_s/I1
1.695 0.563 tINS RF 1 advanced_fir_filter_inst/fir_singlerate_inst/n1043_s/COUT
1.695 0.000 tNET FF 2 advanced_fir_filter_inst/fir_singlerate_inst/n1042_s/CIN
1.745 0.050 tINS FR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1042_s/COUT
1.745 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1041_s/CIN
1.795 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1041_s/COUT
1.795 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1040_s/CIN
1.845 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1040_s/COUT
1.845 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1039_s/CIN
1.895 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1039_s/COUT
1.895 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1038_s/CIN
1.945 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1038_s/COUT
1.945 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1037_s/CIN
1.995 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1037_s/COUT
1.995 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1036_s/CIN
2.045 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1036_s/COUT
2.045 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1035_s/CIN
2.095 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1035_s/COUT
2.095 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1034_s/CIN
2.145 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1034_s/COUT
2.145 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1033_s/CIN
2.195 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1033_s/COUT
2.195 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1032_s/CIN
2.245 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1032_s/COUT
2.245 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1031_s/CIN
2.295 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1031_s/COUT
2.295 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1030_s/CIN
2.345 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1030_s/COUT
2.345 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1029_s/CIN
2.395 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1029_s/COUT
2.395 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1028_s/CIN
2.445 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1028_s/COUT
2.445 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1027_s/CIN
2.495 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1027_s/COUT
2.495 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1026_s/CIN
2.545 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1026_s/COUT
2.545 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1025_s/CIN
2.595 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1025_s/COUT
2.595 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1024_s/CIN
2.645 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1024_s/COUT
2.645 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1023_s/CIN
2.695 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1023_s/COUT
2.695 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1022_s/CIN
2.745 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1022_s/COUT
2.745 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1021_s/CIN
2.795 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1021_s/COUT
2.795 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1020_s/CIN
2.845 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1020_s/COUT
2.845 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1019_s/CIN
2.895 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1019_s/COUT
2.895 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1018_s/CIN
2.945 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1018_s/COUT
2.945 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1017_s/CIN
2.995 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1017_s/COUT
2.995 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1016_s/CIN
3.045 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1016_s/COUT
3.045 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1015_s/CIN
3.095 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1015_s/COUT
3.095 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1014_s/CIN
3.145 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1014_s/COUT
3.145 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1013_s/CIN
3.195 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1013_s/COUT
3.195 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1012_s/CIN
3.245 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1012_s/COUT
3.245 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1011_s/CIN
3.295 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1011_s/COUT
3.295 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1010_s/CIN
3.345 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1010_s/COUT
3.345 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1009_s/CIN
3.395 0.050 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1009_s/COUT
3.395 0.000 tNET RR 2 advanced_fir_filter_inst/fir_singlerate_inst/n1008_s/CIN
3.639 0.244 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1008_s/SUM
4.014 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1044_s1/I1
4.530 0.516 tINS RR 1 advanced_fir_filter_inst/fir_singlerate_inst/n1044_s1/F
4.905 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/acc_out_35_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1385 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_singlerate_inst/acc_out_35_s1/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_singlerate_inst/acc_out_35_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.022, 66.722%; route: 1.125, 24.834%; tC2Q: 0.382, 8.444%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%