Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\advanced_fir_filter.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\advanced_fir_filter_wrap.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\ipcore\ADVANCED_FIR\data\static_macro_define.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Dec 25 12:45:56 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Advanced_FIR_Filter_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.68s, Peak memory usage = 168.789MB
Running netlist conversion:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 168.789MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.636s, Peak memory usage = 168.789MB
    Optimizing Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.252s, Peak memory usage = 168.789MB
    Optimizing Phase 2: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.535s, Peak memory usage = 168.789MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.666s, Peak memory usage = 168.789MB
    Inferring Phase 1: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 168.789MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 168.789MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 168.789MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 168.789MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.32s, Peak memory usage = 168.789MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.19s, Peak memory usage = 168.789MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 191.699MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.816s, Peak memory usage = 191.699MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 294.664MB
Total Time and Memory Usage CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 294.664MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 39
I/O Buf 39
    IBUF 20
    OBUF 19
Register 11063
    DFFPE 56
    DFFCE 11007
LUT 5654
    LUT2 383
    LUT3 4899
    LUT4 372
ALU 603
    ALU 603
INV 5
    INV 5
DSP
    MULTALU27X18 13
    MULT12X12 1
BSRAM 1
    pROM 1

Resource Utilization Summary

Resource Usage Utilization
Logic 6262(5659 LUT, 603 ALU) / 23040 28%
Register 11063 / 23685 47%
  --Register as Latch 0 / 23685 0%
  --Register as FF 11063 / 23685 47%
BSRAM 1 / 56 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 160.933(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.786
Data Arrival Time 6.525
Data Required Time 10.311
From advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_3_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 11077 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0]
4.109 2.075 tINS RF 2 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[2]
4.459 0.350 tNET FF 2 advanced_fir_filter_inst/fir_fractional_inst/n1170_s/I0
5.015 0.556 tINS FF 1 advanced_fir_filter_inst/fir_fractional_inst/n1170_s/COUT
5.015 0.000 tNET FF 2 advanced_fir_filter_inst/fir_fractional_inst/n1169_s/CIN
5.259 0.244 tINS FR 1 advanced_fir_filter_inst/fir_fractional_inst/n1169_s/SUM
5.634 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1174_s0/I1
6.150 0.516 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1174_s0/F
6.525 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 11077 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_3_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.918, 63.700%; route: 1.850, 30.081%; tC2Q: 0.382, 6.219%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 3.855
Data Arrival Time 6.456
Data Required Time 10.311
From advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 11077 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0]
4.109 2.075 tINS RF 2 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[2]
4.459 0.350 tNET FF 2 advanced_fir_filter_inst/fir_fractional_inst/n1170_s/I0
5.190 0.731 tINS FR 1 advanced_fir_filter_inst/fir_fractional_inst/n1170_s/SUM
5.565 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1175_s0/I1
6.081 0.516 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1175_s0/F
6.456 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 11077 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_2_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.849, 63.289%; route: 1.850, 30.421%; tC2Q: 0.382, 6.290%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 3.995
Data Arrival Time 6.317
Data Required Time 10.311
From advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 11077 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0]
3.875 1.842 tINS RR 2 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[0]
4.250 0.375 tNET RR 2 advanced_fir_filter_inst/fir_fractional_inst/n1172_s/I0
4.807 0.556 tINS RF 1 advanced_fir_filter_inst/fir_fractional_inst/n1172_s/COUT
4.807 0.000 tNET FF 2 advanced_fir_filter_inst/fir_fractional_inst/n1171_s/CIN
5.050 0.244 tINS FR 1 advanced_fir_filter_inst/fir_fractional_inst/n1171_s/SUM
5.425 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1176_s0/I1
5.942 0.516 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1176_s0/F
6.317 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 11077 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_1_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.684, 62.005%; route: 1.875, 31.557%; tC2Q: 0.382, 6.438%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 4.035
Data Arrival Time 6.276
Data Required Time 10.311
From advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_4_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 11077 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0]
4.109 2.075 tINS RF 2 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[2]
4.459 0.350 tNET FF 2 advanced_fir_filter_inst/fir_fractional_inst/n1170_s/I0
5.015 0.556 tINS FF 1 advanced_fir_filter_inst/fir_fractional_inst/n1170_s/COUT
5.015 0.000 tNET FF 2 advanced_fir_filter_inst/fir_fractional_inst/n1169_s/CIN
5.065 0.050 tINS FR 1 advanced_fir_filter_inst/fir_fractional_inst/n1169_s/COUT
5.440 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1173_s2/I2
5.901 0.461 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1173_s2/F
6.276 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 11077 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_4_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.669, 62.169%; route: 1.850, 31.349%; tC2Q: 0.382, 6.482%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 4.063
Data Arrival Time 6.248
Data Required Time 10.311
From advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0
To advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 11077 clk_ibuf/O
0.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 advanced_fir_filter_inst/fir_fractional_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/I0
1.659 0.526 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1000_s5/F
2.034 0.375 tNET RR 24 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/A[0]
3.875 1.842 tINS RR 2 advanced_fir_filter_inst/fir_fractional_inst/mult_660_s1/DOUT[0]
4.250 0.375 tNET RR 2 advanced_fir_filter_inst/fir_fractional_inst/n1172_s/I0
4.982 0.731 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1172_s/SUM
5.357 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1177_s0/I1
5.873 0.516 tINS RR 1 advanced_fir_filter_inst/fir_fractional_inst/n1177_s0/F
6.248 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 11077 clk_ibuf/O
10.375 0.375 tNET RR 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_0_s0/CLK
10.311 -0.064 tSu 1 advanced_fir_filter_inst/fir_fractional_inst/coeff_ram_addrb_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.615, 61.560%; route: 1.875, 31.927%; tC2Q: 0.382, 6.513%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%