Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\4_fir_interpolator\68taps_2chn_2tdm_34factor_31bit\proj\src\advanced_fir_filter\advanced_fir_filter.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\4_fir_interpolator\68taps_2chn_2tdm_34factor_31bit\proj\src\sim_input_gen.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\4_fir_interpolator\68taps_2chn_2tdm_34factor_31bit\proj\src\sim_output_storage.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\4_fir_interpolator\68taps_2chn_2tdm_34factor_31bit\proj\src\spram.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\4_fir_interpolator\68taps_2chn_2tdm_34factor_31bit\proj\src\tb_gw5a.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\4_fir_interpolator\68taps_2chn_2tdm_34factor_31bit\proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Dec 25 10:48:58 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module tb_gw5a
Synthesis Process Running parser:
    CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.7s, Peak memory usage = 558.242MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 558.242MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 558.242MB
    Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.207s, Peak memory usage = 558.242MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 558.242MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 558.242MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 558.242MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 558.242MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 558.242MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 558.242MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 558.242MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 558.242MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.146s, Peak memory usage = 558.242MB
Generate output files:
    CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.218s, Peak memory usage = 558.242MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 558.242MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 79
I/O Buf 79
    IBUF 5
    OBUF 74
Register 2199
    DFFRE 1
    DFFPE 80
    DFFCE 2118
LUT 1345
    LUT2 119
    LUT3 830
    LUT4 396
MUX 1
    MUX16 1
ALU 73
    ALU 73
INV 10
    INV 10
DSP
    MULTALU27X18 1
    MULT12X12 1
BSRAM 5
    SDPB 4
    pROM 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1436(1363 LUT, 73 ALU) / 23040 7%
Register 2199 / 23685 10%
  --Register as Latch 0 / 23685 0%
  --Register as FF 2199 / 23685 10%
BSRAM 5 / 56 9%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 156.252(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.600
Data Arrival Time 6.711
Data Required Time 10.311
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1950 clk_ibuf/O
0.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.270 2.236 tINS RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[5]
4.645 0.375 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n842_s/I0
5.201 0.556 tINS RF 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n842_s/COUT
5.201 0.000 tNET FF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n841_s/CIN
5.445 0.244 tINS FR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n841_s/SUM
5.820 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n848_s0/I1
6.336 0.516 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n848_s0/F
6.711 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1950 clk_ibuf/O
10.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0/CLK
10.311 -0.064 tSu 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.079, 64.371%; route: 1.875, 29.592%; tC2Q: 0.382, 6.037%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 3.669
Data Arrival Time 6.642
Data Required Time 10.311
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1950 clk_ibuf/O
0.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.270 2.236 tINS RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[5]
4.645 0.375 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n842_s/I0
5.376 0.731 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n842_s/SUM
5.751 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n849_s0/I1
6.267 0.516 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n849_s0/F
6.642 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1950 clk_ibuf/O
10.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0/CLK
10.311 -0.064 tSu 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.010, 63.980%; route: 1.875, 29.917%; tC2Q: 0.382, 6.103%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 3.734
Data Arrival Time 6.578
Data Required Time 10.311
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1950 clk_ibuf/O
0.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.136 2.103 tINS RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[3]
4.511 0.375 tNET RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/I0
5.068 0.556 tINS RF 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/COUT
5.068 0.000 tNET FF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n843_s/CIN
5.311 0.244 tINS FR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n843_s/SUM
5.686 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n850_s0/I1
6.203 0.516 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n850_s0/F
6.578 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1950 clk_ibuf/O
10.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0/CLK
10.311 -0.064 tSu 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.945, 63.603%; route: 1.875, 30.230%; tC2Q: 0.382, 6.167%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 3.786
Data Arrival Time 6.525
Data Required Time 10.311
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1950 clk_ibuf/O
0.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.109 2.075 tINS RF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[2]
4.459 0.350 tNET FF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/I0
5.015 0.556 tINS FF 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/COUT
5.015 0.000 tNET FF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/CIN
5.259 0.244 tINS FR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n844_s/SUM
5.634 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n851_s0/I1
6.150 0.516 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n851_s0/F
6.525 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1950 clk_ibuf/O
10.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0/CLK
10.311 -0.064 tSu 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.918, 63.700%; route: 1.850, 30.081%; tC2Q: 0.382, 6.219%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 3.855
Data Arrival Time 6.456
Data Required Time 10.311
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1950 clk_ibuf/O
0.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/CLK
0.757 0.382 tC2Q RR 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/cnt_tdm_d1_0_s0/Q
1.132 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/I0
1.659 0.526 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n670_s5/F
2.034 0.375 tNET RR 24 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/A[0]
4.109 2.075 tINS RF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/mult_543_s2/DOUT[2]
4.459 0.350 tNET FF 2 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/I0
5.190 0.731 tINS FR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n845_s/SUM
5.565 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n852_s0/I1
6.081 0.516 tINS RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/n852_s0/F
6.456 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1950 clk_ibuf/O
10.375 0.375 tNET RR 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0/CLK
10.311 -0.064 tSu 1 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_interpolator_inst/coeff_ram_addrb_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.849, 63.289%; route: 1.850, 30.421%; tC2Q: 0.382, 6.290%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%