Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\6_fir_halfband\151taps_1chn_38tdm_halfband_interpolator_16bit\proj\impl\gwsynthesis\fir_proj.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\6_fir_halfband\151taps_1chn_38tdm_halfband_interpolator_16bit\proj\src\fir_proj.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\6_fir_halfband\151taps_1chn_38tdm_halfband_interpolator_16bit\proj\src\fir_proj.sdc
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Dec 25 13:04:43 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 10057
Numbers of Endpoints Analyzed 10655
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk Base 10.000 100.000 0.000 5.000 clk
2 tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 111.591(MHz) 4 TOP
2 tck_pad_i 20.000(MHz) 165.255(MHz) 6 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.039 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_5_s0/CE clk:[R] clk:[R] 10.000 -0.019 8.669
2 1.044 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_5_s0/CE clk:[R] clk:[R] 10.000 -0.009 8.654
3 1.122 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_6_s0/CE clk:[R] clk:[R] 10.000 -0.004 8.571
4 1.124 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_5_s0/CE clk:[R] clk:[R] 10.000 -0.017 8.581
5 1.454 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_5_s0/CE clk:[R] clk:[R] 10.000 -0.017 8.251
6 1.476 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_0_s0/CE clk:[R] clk:[R] 10.000 0.006 8.206
7 1.480 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_5_s0/CE clk:[R] clk:[R] 10.000 -0.008 8.216
8 1.622 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_0_s0/CE clk:[R] clk:[R] 10.000 0.000 8.066
9 1.630 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_0_s0/CE clk:[R] clk:[R] 10.000 0.000 8.059
10 1.641 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_6_s0/CE clk:[R] clk:[R] 10.000 -0.014 8.061
11 1.686 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_6_s0/CE clk:[R] clk:[R] 10.000 -0.014 8.016
12 1.716 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_0_s0/CE clk:[R] clk:[R] 10.000 0.006 7.966
13 1.724 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_3_s0/CE clk:[R] clk:[R] 10.000 -0.014 7.979
14 1.724 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_2_s0/CE clk:[R] clk:[R] 10.000 -0.014 7.979
15 1.739 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_5_s0/CE clk:[R] clk:[R] 10.000 -0.017 7.966
16 1.796 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_0_s0/CE clk:[R] clk:[R] 10.000 0.016 7.878
17 1.808 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[19]_3_s0/CE clk:[R] clk:[R] 10.000 -0.041 7.921
18 1.820 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_5_s0/CE clk:[R] clk:[R] 10.000 -0.008 7.876
19 1.840 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_0_s0/CE clk:[R] clk:[R] 10.000 0.012 7.836
20 1.872 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_1_s0/CE clk:[R] clk:[R] 10.000 -0.004 7.821
21 1.895 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_1_s0/CE clk:[R] clk:[R] 10.000 -0.019 7.813
22 1.899 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_6_s0/CE clk:[R] clk:[R] 10.000 -0.019 7.809
23 1.913 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_2_s0/CE clk:[R] clk:[R] 10.000 0.012 7.764
24 1.941 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_0_s0/CE clk:[R] clk:[R] 10.000 -0.045 7.793
25 1.941 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_3_s0/CE clk:[R] clk:[R] 10.000 -0.045 7.793

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.205 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[8] clk:[R] clk:[R] 0.000 0.005 0.237
2 0.206 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[7] clk:[R] clk:[R] 0.000 0.005 0.238
3 0.229 gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADB[7] tck_pad_i:[R] tck_pad_i:[R] 0.000 0.019 0.245
4 0.251 sim_output_storage_inst/ram_din_addra_2_s0/Q sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[6] clk:[R] clk:[R] 0.000 -0.014 0.302
5 0.255 sim_output_storage_inst/ram_din_addra_5_s0/Q sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[9] clk:[R] clk:[R] 0.000 -0.010 0.302
6 0.257 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_out6_12_s0/CE clk:[R] clk:[R] 0.000 -0.009 0.197
7 0.257 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_1_s0/CE clk:[R] clk:[R] 0.000 -0.009 0.197
8 0.257 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_8_s0/CE clk:[R] clk:[R] 0.000 -0.009 0.197
9 0.257 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_10_s0/CE clk:[R] clk:[R] 0.000 -0.009 0.197
10 0.257 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_11_s0/CE clk:[R] clk:[R] 0.000 -0.009 0.197
11 0.264 sim_output_storage_inst/ram_dout_addrb_7_s0/Q sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[11] clk:[R] clk:[R] 0.000 -0.006 0.305
12 0.275 gw_gao_inst_0/u_la0_top/word_count_15_s0/Q gw_gao_inst_0/u_la0_top/word_count_15_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
13 0.275 sim_output_storage_inst/ram_dout_addrb_5_s0/Q sim_output_storage_inst/ram_dout_addrb_5_s0/D clk:[R] clk:[R] 0.000 0.000 0.300
14 0.275 sim_output_storage_inst/ram_din_addra_6_s0/Q sim_output_storage_inst/ram_din_addra_6_s0/D clk:[R] clk:[R] 0.000 0.000 0.300
15 0.275 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/ram_shift_addra_start_0_s1/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/ram_shift_addra_start_0_s1/D clk:[R] clk:[R] 0.000 0.000 0.300
16 0.278 gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q gw_gao_inst_0/u_la0_top/address_counter_0_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
17 0.278 gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q gw_gao_inst_0/u_la0_top/address_counter_4_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
18 0.278 gw_gao_inst_0/u_la0_top/address_counter_5_s0/Q gw_gao_inst_0/u_la0_top/address_counter_5_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
19 0.278 sim_output_storage_inst/ram_din_addra_0_s0/Q sim_output_storage_inst/ram_din_addra_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
20 0.278 sim_output_storage_inst/ram_din_addra_3_s0/Q sim_output_storage_inst/ram_din_addra_3_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
21 0.278 sim_input_gen_inst/cnt_cycle_4_s1/Q sim_input_gen_inst/cnt_cycle_4_s1/D clk:[R] clk:[R] 0.000 0.000 0.303
22 0.278 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_ram_addra_2_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_ram_addra_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
23 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D clk:[R] clk:[R] 0.000 0.000 0.303
24 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D clk:[R] clk:[R] 0.000 0.000 0.303
25 0.278 gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D clk:[R] clk:[R] 0.000 0.000 0.303

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.778 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR clk:[F] clk:[R] 5.000 0.032 1.843
2 2.778 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR clk:[F] clk:[R] 5.000 0.032 1.843
3 2.778 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR clk:[F] clk:[R] 5.000 0.032 1.843
4 2.778 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR clk:[F] clk:[R] 5.000 0.032 1.843
5 2.778 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR clk:[F] clk:[R] 5.000 0.010 1.865
6 2.780 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR clk:[F] clk:[R] 5.000 0.007 1.865
7 2.780 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR clk:[F] clk:[R] 5.000 0.007 1.865
8 2.785 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR clk:[F] clk:[R] 5.000 0.012 1.856
9 2.785 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR clk:[F] clk:[R] 5.000 0.012 1.856
10 2.785 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR clk:[F] clk:[R] 5.000 0.024 1.843
11 2.789 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR clk:[F] clk:[R] 5.000 0.024 1.839
12 2.794 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR clk:[F] clk:[R] 5.000 0.002 1.856
13 2.794 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR clk:[F] clk:[R] 5.000 0.002 1.856
14 2.797 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR clk:[F] clk:[R] 5.000 0.017 1.839
15 2.884 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR clk:[F] clk:[R] 5.000 0.067 1.701
16 2.975 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET clk:[F] clk:[R] 5.000 0.014 1.663
17 2.975 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR clk:[F] clk:[R] 5.000 0.014 1.663
18 2.975 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR clk:[F] clk:[R] 5.000 0.014 1.663
19 2.975 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR clk:[F] clk:[R] 5.000 0.014 1.663
20 2.975 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR clk:[F] clk:[R] 5.000 0.014 1.663
21 2.975 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET clk:[F] clk:[R] 5.000 0.014 1.663
22 2.976 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR clk:[F] clk:[R] 5.000 0.022 1.655
23 2.976 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR clk:[F] clk:[R] 5.000 0.022 1.655
24 2.976 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR clk:[F] clk:[R] 5.000 0.022 1.655
25 2.976 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR clk:[F] clk:[R] 5.000 0.022 1.655

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 5.421 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR clk:[F] clk:[R] -5.000 0.013 0.355
2 5.421 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.013 0.355
3 5.423 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR clk:[F] clk:[R] -5.000 0.011 0.359
4 5.423 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR clk:[F] clk:[R] -5.000 0.011 0.359
5 5.423 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR clk:[F] clk:[R] -5.000 0.011 0.359
6 5.423 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.011 0.359
7 5.423 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.011 0.359
8 5.427 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR clk:[F] clk:[R] -5.000 0.015 0.359
9 5.629 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR clk:[F] clk:[R] -5.000 0.033 0.544
10 5.629 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR clk:[F] clk:[R] -5.000 0.033 0.544
11 5.629 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR clk:[F] clk:[R] -5.000 0.033 0.544
12 5.629 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR clk:[F] clk:[R] -5.000 0.033 0.544
13 5.629 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR clk:[F] clk:[R] -5.000 0.033 0.544
14 5.825 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR clk:[F] clk:[R] -5.000 0.034 0.738
15 5.885 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR clk:[F] clk:[R] -5.000 0.012 0.820
16 5.885 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR clk:[F] clk:[R] -5.000 0.007 0.825
17 5.885 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR clk:[F] clk:[R] -5.000 0.007 0.825
18 5.885 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR clk:[F] clk:[R] -5.000 0.007 0.825
19 5.885 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR clk:[F] clk:[R] -5.000 0.007 0.825
20 5.886 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR clk:[F] clk:[R] -5.000 0.028 0.805
21 5.886 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR clk:[F] clk:[R] -5.000 0.028 0.805
22 5.886 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR clk:[F] clk:[R] -5.000 0.028 0.805
23 5.886 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.028 0.805
24 5.886 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.028 0.805
25 5.886 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.028 0.805

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.751 3.751 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
2 2.754 3.754 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1
3 2.757 3.757 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
4 2.757 3.757 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s
5 2.757 3.757 1.000 Low Pulse Width clk sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
6 2.762 3.762 1.000 High Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
7 2.762 3.762 1.000 Low Pulse Width clk sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
8 2.762 3.762 1.000 High Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1
9 2.767 3.767 1.000 High Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
10 2.767 3.767 1.000 High Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.039
Data Arrival Time 11.271
Data Required Time 12.310
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.707 0.776 tNET RR 1 R30C47[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5163_s1/I3
6.169 0.461 tINS RR 10 R30C47[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5163_s1/F
7.115 0.946 tNET RR 1 R26C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5803_s0/I0
7.631 0.516 tINS RR 16 R26C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5803_s0/F
11.271 3.640 tNET RR 1 R35C69[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R35C69[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_5_s0/CLK
12.310 -0.311 tSu 1 R35C69[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_5_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.494, 17.231%; route: 6.793, 78.356%; tC2Q: 0.382, 4.412%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path2

Path Summary:

Slack 1.044
Data Arrival Time 11.256
Data Required Time 12.301
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.530 0.599 tNET RR 1 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/I3
6.046 0.516 tINS RR 9 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/F
6.466 0.420 tNET RR 1 R29C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n6107_s0/I0
6.983 0.516 tINS RR 16 R29C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n6107_s0/F
11.256 4.274 tNET RR 1 R35C68[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R35C68[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_5_s0/CLK
12.301 -0.311 tSu 1 R35C68[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_5_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.549, 17.897%; route: 6.723, 77.683%; tC2Q: 0.382, 4.420%
Required Clock Path Delay cell: 0.683, 26.131%; route: 1.929, 73.869%

Path3

Path Summary:

Slack 1.122
Data Arrival Time 11.174
Data Required Time 12.296
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.530 0.599 tNET RR 1 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/I3
6.046 0.516 tINS RR 9 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/F
6.466 0.420 tNET RR 1 R29C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n6107_s0/I0
6.983 0.516 tINS RR 16 R29C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n6107_s0/F
11.174 4.191 tNET RR 1 R29C68[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.607 1.924 tNET RR 1 R29C68[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_6_s0/CLK
12.296 -0.311 tSu 1 R29C68[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_6_s0

Path Statistics:

Clock Skew 0.004
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.549, 18.069%; route: 6.640, 77.468%; tC2Q: 0.382, 4.463%
Required Clock Path Delay cell: 0.683, 26.181%; route: 1.924, 73.819%

Path4

Path Summary:

Slack 1.124
Data Arrival Time 11.184
Data Required Time 12.308
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.798 0.866 tNET RR 1 R30C46[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5243_s2/I0
6.213 0.415 tINS RR 9 R30C46[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5243_s2/F
7.110 0.897 tNET RR 1 R26C43[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5883_s0/I0
7.631 0.521 tINS RR 16 R26C43[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5883_s0/F
11.184 3.553 tNET RR 1 R34C69[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.619 1.937 tNET RR 1 R34C69[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_5_s0/CLK
12.308 -0.311 tSu 1 R34C69[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_5_s0

Path Statistics:

Clock Skew 0.017
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.452, 16.926%; route: 6.746, 78.616%; tC2Q: 0.382, 4.457%
Required Clock Path Delay cell: 0.683, 26.056%; route: 1.937, 73.944%

Path5

Path Summary:

Slack 1.454
Data Arrival Time 10.854
Data Required Time 12.308
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.798 0.866 tNET RR 1 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/I3
6.259 0.461 tINS RR 10 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/F
7.555 1.296 tNET RR 1 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/I0
8.081 0.526 tINS RR 16 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/F
10.854 2.773 tNET RR 1 R34C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.619 1.937 tNET RR 1 R34C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_5_s0/CLK
12.308 -0.311 tSu 1 R34C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_5_s0

Path Statistics:

Clock Skew 0.017
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.504, 18.225%; route: 6.365, 77.140%; tC2Q: 0.382, 4.636%
Required Clock Path Delay cell: 0.683, 26.056%; route: 1.937, 73.944%

Path6

Path Summary:

Slack 1.476
Data Arrival Time 10.809
Data Required Time 12.285
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.707 0.776 tNET RR 1 R30C47[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5163_s1/I3
6.169 0.461 tINS RR 10 R30C47[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5163_s1/F
7.115 0.946 tNET RR 1 R26C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5803_s0/I0
7.631 0.516 tINS RR 16 R26C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5803_s0/F
10.809 3.177 tNET RR 1 R31C68[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.596 1.914 tNET RR 1 R31C68[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_0_s0/CLK
12.285 -0.311 tSu 1 R31C68[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_0_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.494, 18.203%; route: 6.330, 77.136%; tC2Q: 0.382, 4.661%
Required Clock Path Delay cell: 0.683, 26.288%; route: 1.914, 73.712%

Path7

Path Summary:

Slack 1.480
Data Arrival Time 10.819
Data Required Time 12.299
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.530 0.599 tNET RR 1 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/I3
6.046 0.516 tINS RR 9 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/F
6.689 0.642 tNET RR 1 R26C43[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5851_s0/I0
7.205 0.516 tINS RR 16 R26C43[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5851_s0/F
10.819 3.614 tNET RR 1 R34C66[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R34C66[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_5_s0/CLK
12.299 -0.311 tSu 1 R34C66[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_5_s0

Path Statistics:

Clock Skew 0.008
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.549, 18.850%; route: 6.285, 76.495%; tC2Q: 0.382, 4.655%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path8

Path Summary:

Slack 1.622
Data Arrival Time 10.669
Data Required Time 12.291
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.798 0.866 tNET RR 1 R30C46[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5243_s2/I0
6.213 0.415 tINS RR 9 R30C46[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5243_s2/F
7.110 0.897 tNET RR 1 R26C43[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5883_s0/I0
7.631 0.521 tINS RR 16 R26C43[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5883_s0/F
10.669 3.038 tNET RR 1 R32C66[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.602 1.920 tNET RR 1 R32C66[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_0_s0/CLK
12.291 -0.311 tSu 1 R32C66[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[47]_0_s0

Path Statistics:

Clock Skew -0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.452, 18.007%; route: 6.231, 77.251%; tC2Q: 0.382, 4.742%
Required Clock Path Delay cell: 0.683, 26.228%; route: 1.920, 73.772%

Path9

Path Summary:

Slack 1.630
Data Arrival Time 10.661
Data Required Time 12.291
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.798 0.866 tNET RR 1 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/I3
6.259 0.461 tINS RR 10 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/F
7.555 1.296 tNET RR 1 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/I0
8.081 0.526 tINS RR 16 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/F
10.661 2.580 tNET RR 1 R32C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.602 1.920 tNET RR 1 R32C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_0_s0/CLK
12.291 -0.311 tSu 1 R32C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_0_s0

Path Statistics:

Clock Skew -0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.504, 18.660%; route: 6.173, 76.594%; tC2Q: 0.382, 4.746%
Required Clock Path Delay cell: 0.683, 26.228%; route: 1.920, 73.772%

Path10

Path Summary:

Slack 1.641
Data Arrival Time 10.664
Data Required Time 12.305
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.798 0.866 tNET RR 1 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/I3
6.259 0.461 tINS RR 10 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/F
7.555 1.296 tNET RR 1 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/I0
8.081 0.526 tINS RR 16 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/F
10.664 2.583 tNET RR 1 R29C69[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.616 1.934 tNET RR 1 R29C69[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_6_s0/CLK
12.305 -0.311 tSu 1 R29C69[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_6_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.504, 18.654%; route: 6.175, 76.601%; tC2Q: 0.382, 4.745%
Required Clock Path Delay cell: 0.683, 26.087%; route: 1.934, 73.913%

Path11

Path Summary:

Slack 1.686
Data Arrival Time 10.619
Data Required Time 12.305
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.707 0.776 tNET RR 1 R30C47[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5163_s1/I3
6.169 0.461 tINS RR 10 R30C47[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5163_s1/F
7.115 0.946 tNET RR 1 R26C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5803_s0/I0
7.631 0.516 tINS RR 16 R26C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5803_s0/F
10.619 2.987 tNET RR 1 R29C69[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.616 1.934 tNET RR 1 R29C69[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_6_s0/CLK
12.305 -0.311 tSu 1 R29C69[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_6_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.494, 18.634%; route: 6.140, 76.594%; tC2Q: 0.382, 4.772%
Required Clock Path Delay cell: 0.683, 26.087%; route: 1.934, 73.913%

Path12

Path Summary:

Slack 1.716
Data Arrival Time 10.569
Data Required Time 12.285
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.707 0.776 tNET RR 1 R30C47[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5179_s2/I3
6.169 0.461 tINS RR 10 R30C47[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5179_s2/F
6.902 0.734 tNET RR 1 R27C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5691_s0/I0
7.419 0.516 tINS RR 16 R27C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5691_s0/F
10.569 3.150 tNET RR 1 R31C68[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.596 1.914 tNET RR 1 R31C68[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_0_s0/CLK
12.285 -0.311 tSu 1 R31C68[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_0_s0

Path Statistics:

Clock Skew -0.006
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.494, 18.751%; route: 6.090, 76.448%; tC2Q: 0.382, 4.802%
Required Clock Path Delay cell: 0.683, 26.288%; route: 1.914, 73.712%

Path13

Path Summary:

Slack 1.724
Data Arrival Time 10.581
Data Required Time 12.305
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.798 0.866 tNET RR 1 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/I3
6.259 0.461 tINS RR 10 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/F
7.555 1.296 tNET RR 1 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/I0
8.081 0.526 tINS RR 16 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/F
10.581 2.500 tNET RR 1 R29C65[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.616 1.934 tNET RR 1 R29C65[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_3_s0/CLK
12.305 -0.311 tSu 1 R29C65[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_3_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.504, 18.847%; route: 6.093, 76.359%; tC2Q: 0.382, 4.794%
Required Clock Path Delay cell: 0.683, 26.087%; route: 1.934, 73.913%

Path14

Path Summary:

Slack 1.724
Data Arrival Time 10.581
Data Required Time 12.305
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.798 0.866 tNET RR 1 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/I3
6.259 0.461 tINS RR 10 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/F
7.555 1.296 tNET RR 1 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/I0
8.081 0.526 tINS RR 16 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/F
10.581 2.500 tNET RR 1 R29C65[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.616 1.934 tNET RR 1 R29C65[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_2_s0/CLK
12.305 -0.311 tSu 1 R29C65[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_2_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.504, 18.847%; route: 6.093, 76.359%; tC2Q: 0.382, 4.794%
Required Clock Path Delay cell: 0.683, 26.087%; route: 1.934, 73.913%

Path15

Path Summary:

Slack 1.739
Data Arrival Time 10.569
Data Required Time 12.308
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.707 0.776 tNET RR 1 R30C47[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5179_s2/I3
6.169 0.461 tINS RR 10 R30C47[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5179_s2/F
6.902 0.734 tNET RR 1 R27C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5691_s0/I0
7.419 0.516 tINS RR 16 R27C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5691_s0/F
10.569 3.150 tNET RR 1 R34C69[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.619 1.937 tNET RR 1 R34C69[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_5_s0/CLK
12.308 -0.311 tSu 1 R34C69[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_5_s0

Path Statistics:

Clock Skew 0.017
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.494, 18.751%; route: 6.090, 76.448%; tC2Q: 0.382, 4.802%
Required Clock Path Delay cell: 0.683, 26.056%; route: 1.937, 73.944%

Path16

Path Summary:

Slack 1.796
Data Arrival Time 10.480
Data Required Time 12.276
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.530 0.599 tNET RR 1 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/I3
6.046 0.516 tINS RR 9 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/F
6.466 0.420 tNET RR 1 R29C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n6107_s0/I0
6.983 0.516 tINS RR 16 R29C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n6107_s0/F
10.480 3.498 tNET RR 1 R31C63[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.587 1.904 tNET RR 1 R31C63[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_0_s0/CLK
12.276 -0.311 tSu 1 R31C63[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[61]_0_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.549, 19.660%; route: 5.946, 75.484%; tC2Q: 0.382, 4.856%
Required Clock Path Delay cell: 0.683, 26.383%; route: 1.904, 73.617%

Path17

Path Summary:

Slack 1.808
Data Arrival Time 10.524
Data Required Time 12.332
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[19]_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.707 0.776 tNET RR 1 R30C47[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5179_s2/I3
6.169 0.461 tINS RR 10 R30C47[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5179_s2/F
6.486 0.317 tNET RR 1 R30C45[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5435_s0/I0
7.003 0.516 tINS RR 16 R30C45[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5435_s0/F
10.524 3.521 tNET RR 1 R22C64[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[19]_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.643 1.961 tNET RR 1 R22C64[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[19]_3_s0/CLK
12.332 -0.311 tSu 1 R22C64[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[19]_3_s0

Path Statistics:

Clock Skew 0.041
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.494, 18.858%; route: 6.045, 76.314%; tC2Q: 0.382, 4.829%
Required Clock Path Delay cell: 0.683, 25.822%; route: 1.961, 74.178%

Path18

Path Summary:

Slack 1.820
Data Arrival Time 10.479
Data Required Time 12.299
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.530 0.599 tNET RR 1 R30C45[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5227_s1/I3
6.051 0.521 tINS RR 9 R30C45[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5227_s1/F
6.803 0.751 tNET RR 1 R26C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5867_s0/I0
7.319 0.516 tINS RR 16 R26C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5867_s0/F
10.479 3.160 tNET RR 1 R34C70[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R34C70[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_5_s0/CLK
12.299 -0.311 tSu 1 R34C70[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_5_s0

Path Statistics:

Clock Skew 0.008
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.554, 19.727%; route: 5.940, 75.417%; tC2Q: 0.382, 4.856%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path19

Path Summary:

Slack 1.840
Data Arrival Time 10.439
Data Required Time 12.279
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.530 0.599 tNET RR 1 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/I3
6.046 0.516 tINS RR 9 R30C45[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5211_s1/F
6.689 0.642 tNET RR 1 R26C43[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5851_s0/I0
7.205 0.516 tINS RR 16 R26C43[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5851_s0/F
10.439 3.234 tNET RR 1 R30C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.590 1.908 tNET RR 1 R30C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_0_s0/CLK
12.279 -0.311 tSu 1 R30C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[45]_0_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.549, 19.764%; route: 5.905, 75.355%; tC2Q: 0.382, 4.881%
Required Clock Path Delay cell: 0.683, 26.348%; route: 1.908, 73.652%

Path20

Path Summary:

Slack 1.872
Data Arrival Time 10.424
Data Required Time 12.296
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.707 0.776 tNET RR 1 R30C47[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5163_s1/I3
6.169 0.461 tINS RR 10 R30C47[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5163_s1/F
7.115 0.946 tNET RR 1 R26C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5803_s0/I0
7.631 0.516 tINS RR 16 R26C43[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5803_s0/F
10.424 2.793 tNET RR 1 R29C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.607 1.924 tNET RR 1 R29C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_1_s0/CLK
12.296 -0.311 tSu 1 R29C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[42]_1_s0

Path Statistics:

Clock Skew 0.004
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.494, 19.099%; route: 5.945, 76.011%; tC2Q: 0.382, 4.891%
Required Clock Path Delay cell: 0.683, 26.181%; route: 1.924, 73.819%

Path21

Path Summary:

Slack 1.895
Data Arrival Time 10.415
Data Required Time 12.310
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.798 0.866 tNET RR 1 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/I3
6.259 0.461 tINS RR 10 R30C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5147_s1/F
7.555 1.296 tNET RR 1 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/I0
8.081 0.526 tINS RR 16 R26C43[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5787_s0/F
10.415 2.334 tNET RR 1 R27C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R27C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_1_s0/CLK
12.310 -0.311 tSu 1 R27C66[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[41]_1_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.504, 19.248%; route: 5.926, 75.856%; tC2Q: 0.382, 4.896%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path22

Path Summary:

Slack 1.899
Data Arrival Time 10.411
Data Required Time 12.310
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.530 0.599 tNET RR 1 R30C45[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5227_s1/I3
6.051 0.521 tINS RR 9 R30C45[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5227_s1/F
6.803 0.751 tNET RR 1 R26C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5867_s0/I0
7.319 0.516 tINS RR 16 R26C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5867_s0/F
10.411 3.092 tNET RR 1 R27C70[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R27C70[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_6_s0/CLK
12.310 -0.311 tSu 1 R27C70[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[46]_6_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.554, 19.898%; route: 5.873, 75.204%; tC2Q: 0.382, 4.898%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path23

Path Summary:

Slack 1.913
Data Arrival Time 10.366
Data Required Time 12.279
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.707 0.776 tNET RR 1 R30C47[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5179_s2/I3
6.169 0.461 tINS RR 10 R30C47[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5179_s2/F
6.902 0.734 tNET RR 1 R27C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5691_s0/I0
7.419 0.516 tINS RR 16 R27C43[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5691_s0/F
10.366 2.948 tNET RR 1 R30C64[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.590 1.908 tNET RR 1 R30C64[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_2_s0/CLK
12.279 -0.311 tSu 1 R30C64[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[35]_2_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.494, 19.240%; route: 5.888, 75.833%; tC2Q: 0.382, 4.927%
Required Clock Path Delay cell: 0.683, 26.348%; route: 1.908, 73.652%

Path24

Path Summary:

Slack 1.941
Data Arrival Time 10.395
Data Required Time 12.336
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.530 0.599 tNET RR 1 R30C45[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5195_s1/I3
6.046 0.516 tINS RR 9 R30C45[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5195_s1/F
6.404 0.357 tNET RR 1 R30C43[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5579_s0/I0
6.819 0.415 tINS RR 16 R30C43[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5579_s0/F
10.395 3.576 tNET RR 1 R24C65[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.648 1.965 tNET RR 1 R24C65[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_0_s0/CLK
12.336 -0.311 tSu 1 R24C65[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_0_s0

Path Statistics:

Clock Skew 0.045
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.447, 18.576%; route: 5.963, 76.516%; tC2Q: 0.382, 4.909%
Required Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%

Path25

Path Summary:

Slack 1.941
Data Arrival Time 10.395
Data Required Time 12.336
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
2.602 1.920 tNET RR 1 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/CLK
2.985 0.382 tC2Q RR 8 R35C71[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_load_flag_s0/Q
4.415 1.430 tNET RR 1 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/I1
4.931 0.516 tINS RR 8 R30C60[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5132_s4/F
5.530 0.599 tNET RR 1 R30C45[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5195_s1/I3
6.046 0.516 tINS RR 9 R30C45[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5195_s1/F
6.404 0.357 tNET RR 1 R30C43[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5579_s0/I0
6.819 0.415 tINS RR 16 R30C43[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/n5579_s0/F
10.395 3.576 tNET RR 1 R24C65[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.648 1.965 tNET RR 1 R24C65[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_3_s0/CLK
12.336 -0.311 tSu 1 R24C65[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[28]_3_s0

Path Statistics:

Clock Skew 0.045
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 26.225%; route: 1.920, 73.775%
Arrival Data Path Delay cell: 1.447, 18.576%; route: 5.963, 76.516%; tC2Q: 0.382, 4.909%
Required Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.205
Data Arrival Time 1.621
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.384 0.708 tNET RR 1 R9C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/CLK
1.528 0.144 tC2Q RR 1 R9C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_8_s0/Q
1.621 0.093 tNET RR 1 BSRAM_R10[24] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[24] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[24] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.825%; route: 0.708, 51.175%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path2

Path Summary:

Slack 0.206
Data Arrival Time 1.622
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.384 0.708 tNET RR 1 R9C77[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/CLK
1.525 0.141 tC2Q RF 1 R9C77[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q
1.622 0.097 tNET FF 1 BSRAM_R10[24] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[24] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[24] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.825%; route: 0.708, 51.175%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.097, 40.756%; tC2Q: 0.141, 59.244%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path3

Path Summary:

Slack 0.229
Data Arrival Time 2.697
Data Required Time 2.468
From gw_gao_inst_0/u_la0_top/address_counter_3_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.452 1.101 tNET RR 1 R25C77[2][A] gw_gao_inst_0/u_la0_top/address_counter_3_s0/CLK
2.593 0.141 tC2Q RF 4 R25C77[2][A] gw_gao_inst_0/u_la0_top/address_counter_3_s0/Q
2.697 0.104 tNET FF 1 BSRAM_R10[24] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADB[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.433 1.082 tNET RR 1 BSRAM_R10[24] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB
2.468 0.035 tHld 1 BSRAM_R10[24] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.019
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 1.351, 55.098%; route: 1.101, 44.902%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.104, 42.449%; tC2Q: 0.141, 57.551%
Required Clock Path Delay cell: 1.351, 55.528%; route: 1.082, 44.472%

Path4

Path Summary:

Slack 0.251
Data Arrival Time 1.663
Data Required Time 1.411
From sim_output_storage_inst/ram_din_addra_2_s0
To sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.361 0.685 tNET RR 1 R12C74[0][A] sim_output_storage_inst/ram_din_addra_2_s0/CLK
1.502 0.141 tC2Q RF 4 R12C74[0][A] sim_output_storage_inst/ram_din_addra_2_s0/Q
1.663 0.161 tNET FF 1 BSRAM_R10[23] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[23] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[23] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.651%; route: 0.685, 50.349%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path5

Path Summary:

Slack 0.255
Data Arrival Time 1.667
Data Required Time 1.411
From sim_output_storage_inst/ram_din_addra_5_s0
To sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R13C74[2][A] sim_output_storage_inst/ram_din_addra_5_s0/CLK
1.506 0.141 tC2Q RF 4 R13C74[2][A] sim_output_storage_inst/ram_din_addra_5_s0/Q
1.667 0.161 tNET FF 1 BSRAM_R10[23] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[23] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[23] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path6

Path Summary:

Slack 0.257
Data Arrival Time 1.562
Data Required Time 1.305
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_out6_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/CLK
1.509 0.144 tC2Q RR 34 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q
1.562 0.053 tNET RR 1 R11C73[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_out6_12_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C73[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_out6_12_s0/CLK
1.305 -0.069 tHld 1 R11C73[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_out6_12_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.053, 26.904%; tC2Q: 0.144, 73.096%
Required Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%

Path7

Path Summary:

Slack 0.257
Data Arrival Time 1.562
Data Required Time 1.305
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/CLK
1.509 0.144 tC2Q RR 34 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q
1.562 0.053 tNET RR 1 R11C73[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C73[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_1_s0/CLK
1.305 -0.069 tHld 1 R11C73[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_1_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.053, 26.904%; tC2Q: 0.144, 73.096%
Required Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%

Path8

Path Summary:

Slack 0.257
Data Arrival Time 1.562
Data Required Time 1.305
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/CLK
1.509 0.144 tC2Q RR 34 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q
1.562 0.053 tNET RR 1 R11C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_8_s0/CLK
1.305 -0.069 tHld 1 R11C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_8_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.053, 26.904%; tC2Q: 0.144, 73.096%
Required Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%

Path9

Path Summary:

Slack 0.257
Data Arrival Time 1.562
Data Required Time 1.305
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/CLK
1.509 0.144 tC2Q RR 34 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q
1.562 0.053 tNET RR 1 R11C73[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C73[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_10_s0/CLK
1.305 -0.069 tHld 1 R11C73[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_10_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.053, 26.904%; tC2Q: 0.144, 73.096%
Required Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%

Path10

Path Summary:

Slack 0.257
Data Arrival Time 1.562
Data Required Time 1.305
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/CLK
1.509 0.144 tC2Q RR 34 R12C73[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/adder_valid_r1_s0/Q
1.562 0.053 tNET RR 1 R11C73[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_11_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C73[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_11_s0/CLK
1.305 -0.069 tHld 1 R11C73[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_adder_tree_layer0[0].adder_inst/lbit_out_11_s0

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.053, 26.904%; tC2Q: 0.144, 73.096%
Required Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%

Path11

Path Summary:

Slack 0.264
Data Arrival Time 1.670
Data Required Time 1.406
From sim_output_storage_inst/ram_dout_addrb_7_s0
To sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R13C74[0][B] sim_output_storage_inst/ram_dout_addrb_7_s0/CLK
1.506 0.141 tC2Q RF 4 R13C74[0][B] sim_output_storage_inst/ram_dout_addrb_7_s0/Q
1.670 0.164 tNET FF 1 BSRAM_R10[23] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.371 0.695 tNET RR 1 BSRAM_R10[23] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB
1.406 0.035 tHld 1 BSRAM_R10[23] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.164, 53.770%; tC2Q: 0.141, 46.230%
Required Clock Path Delay cell: 0.675, 49.289%; route: 0.695, 50.711%

Path12

Path Summary:

Slack 0.275
Data Arrival Time 2.736
Data Required Time 2.461
From gw_gao_inst_0/u_la0_top/word_count_15_s0
To gw_gao_inst_0/u_la0_top/word_count_15_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.436 1.085 tNET RR 1 R29C76[0][A] gw_gao_inst_0/u_la0_top/word_count_15_s0/CLK
2.577 0.141 tC2Q RF 3 R29C76[0][A] gw_gao_inst_0/u_la0_top/word_count_15_s0/Q
2.583 0.006 tNET FF 1 R29C76[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s0/I1
2.736 0.153 tINS FF 1 R29C76[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s0/F
2.736 0.000 tNET FF 1 R29C76[0][A] gw_gao_inst_0/u_la0_top/word_count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.436 1.085 tNET RR 1 R29C76[0][A] gw_gao_inst_0/u_la0_top/word_count_15_s0/CLK
2.461 0.025 tHld 1 R29C76[0][A] gw_gao_inst_0/u_la0_top/word_count_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.460%; route: 1.085, 44.540%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 55.460%; route: 1.085, 44.540%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 1.661
Data Required Time 1.386
From sim_output_storage_inst/ram_dout_addrb_5_s0
To sim_output_storage_inst/ram_dout_addrb_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.361 0.685 tNET RR 1 R13C75[0][A] sim_output_storage_inst/ram_dout_addrb_5_s0/CLK
1.502 0.141 tC2Q RF 5 R13C75[0][A] sim_output_storage_inst/ram_dout_addrb_5_s0/Q
1.508 0.006 tNET FF 1 R13C75[0][A] sim_output_storage_inst/n165_s4/I0
1.661 0.153 tINS FF 1 R13C75[0][A] sim_output_storage_inst/n165_s4/F
1.661 0.000 tNET FF 1 R13C75[0][A] sim_output_storage_inst/ram_dout_addrb_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.361 0.685 tNET RR 1 R13C75[0][A] sim_output_storage_inst/ram_dout_addrb_5_s0/CLK
1.386 0.025 tHld 1 R13C75[0][A] sim_output_storage_inst/ram_dout_addrb_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.651%; route: 0.685, 50.349%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 49.651%; route: 0.685, 50.349%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 1.665
Data Required Time 1.390
From sim_output_storage_inst/ram_din_addra_6_s0
To sim_output_storage_inst/ram_din_addra_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R13C74[1][A] sim_output_storage_inst/ram_din_addra_6_s0/CLK
1.506 0.141 tC2Q RF 3 R13C74[1][A] sim_output_storage_inst/ram_din_addra_6_s0/Q
1.512 0.006 tNET FF 1 R13C74[1][A] sim_output_storage_inst/n95_s1/I3
1.665 0.153 tINS FF 1 R13C74[1][A] sim_output_storage_inst/n95_s1/F
1.665 0.000 tNET FF 1 R13C74[1][A] sim_output_storage_inst/ram_din_addra_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R13C74[1][A] sim_output_storage_inst/ram_din_addra_6_s0/CLK
1.390 0.025 tHld 1 R13C74[1][A] sim_output_storage_inst/ram_din_addra_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%

Path15

Path Summary:

Slack 0.275
Data Arrival Time 1.672
Data Required Time 1.397
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/ram_shift_addra_start_0_s1
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/ram_shift_addra_start_0_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.372 0.697 tNET RR 1 R18C43[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/ram_shift_addra_start_0_s1/CLK
1.513 0.141 tC2Q RF 9 R18C43[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/ram_shift_addra_start_0_s1/Q
1.519 0.006 tNET FF 1 R18C43[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/n316_s5/I3
1.672 0.153 tINS FF 1 R18C43[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/n316_s5/F
1.672 0.000 tNET FF 1 R18C43[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/ram_shift_addra_start_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.372 0.697 tNET RR 1 R18C43[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/ram_shift_addra_start_0_s1/CLK
1.397 0.025 tHld 1 R18C43[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/ram_shift_addra_start_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.226%; route: 0.697, 50.774%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 49.226%; route: 0.697, 50.774%

Path16

Path Summary:

Slack 0.278
Data Arrival Time 2.755
Data Required Time 2.477
From gw_gao_inst_0/u_la0_top/address_counter_0_s0
To gw_gao_inst_0/u_la0_top/address_counter_0_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.452 1.101 tNET RR 1 R25C77[1][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.593 0.141 tC2Q RF 7 R25C77[1][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q
2.602 0.009 tNET FF 1 R25C77[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_0_s0/I0
2.755 0.153 tINS FF 1 R25C77[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_0_s0/F
2.755 0.000 tNET FF 1 R25C77[1][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.452 1.101 tNET RR 1 R25C77[1][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.477 0.025 tHld 1 R25C77[1][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.098%; route: 1.101, 44.902%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 55.098%; route: 1.101, 44.902%

Path17

Path Summary:

Slack 0.278
Data Arrival Time 2.751
Data Required Time 2.473
From gw_gao_inst_0/u_la0_top/address_counter_4_s0
To gw_gao_inst_0/u_la0_top/address_counter_4_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.448 1.097 tNET RR 1 R25C78[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.589 0.141 tC2Q RF 5 R25C78[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q
2.598 0.009 tNET FF 1 R25C78[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/I1
2.751 0.153 tINS FF 1 R25C78[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/F
2.751 0.000 tNET FF 1 R25C78[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.448 1.097 tNET RR 1 R25C78[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.473 0.025 tHld 1 R25C78[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.188%; route: 1.097, 44.812%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 55.188%; route: 1.097, 44.812%

Path18

Path Summary:

Slack 0.278
Data Arrival Time 2.755
Data Required Time 2.477
From gw_gao_inst_0/u_la0_top/address_counter_5_s0
To gw_gao_inst_0/u_la0_top/address_counter_5_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.452 1.101 tNET RR 1 R25C77[0][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0/CLK
2.593 0.141 tC2Q RF 4 R25C77[0][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0/Q
2.602 0.009 tNET FF 1 R25C77[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_5_s0/I1
2.755 0.153 tINS FF 1 R25C77[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_5_s0/F
2.755 0.000 tNET FF 1 R25C77[0][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.452 1.101 tNET RR 1 R25C77[0][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0/CLK
2.477 0.025 tHld 1 R25C77[0][A] gw_gao_inst_0/u_la0_top/address_counter_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.098%; route: 1.101, 44.902%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 55.098%; route: 1.101, 44.902%

Path19

Path Summary:

Slack 0.278
Data Arrival Time 1.671
Data Required Time 1.393
From sim_output_storage_inst/ram_din_addra_0_s0
To sim_output_storage_inst/ram_din_addra_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R13C73[0][A] sim_output_storage_inst/ram_din_addra_0_s0/CLK
1.510 0.141 tC2Q RF 6 R13C73[0][A] sim_output_storage_inst/ram_din_addra_0_s0/Q
1.518 0.009 tNET FF 1 R13C73[0][A] sim_output_storage_inst/n101_s3/I3
1.671 0.153 tINS FF 1 R13C73[0][A] sim_output_storage_inst/n101_s3/F
1.671 0.000 tNET FF 1 R13C73[0][A] sim_output_storage_inst/ram_din_addra_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R13C73[0][A] sim_output_storage_inst/ram_din_addra_0_s0/CLK
1.393 0.025 tHld 1 R13C73[0][A] sim_output_storage_inst/ram_din_addra_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%

Path20

Path Summary:

Slack 0.278
Data Arrival Time 1.671
Data Required Time 1.393
From sim_output_storage_inst/ram_din_addra_3_s0
To sim_output_storage_inst/ram_din_addra_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R13C73[1][A] sim_output_storage_inst/ram_din_addra_3_s0/CLK
1.510 0.141 tC2Q RF 3 R13C73[1][A] sim_output_storage_inst/ram_din_addra_3_s0/Q
1.518 0.009 tNET FF 1 R13C73[1][A] sim_output_storage_inst/n98_s1/I2
1.671 0.153 tINS FF 1 R13C73[1][A] sim_output_storage_inst/n98_s1/F
1.671 0.000 tNET FF 1 R13C73[1][A] sim_output_storage_inst/ram_din_addra_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R13C73[1][A] sim_output_storage_inst/ram_din_addra_3_s0/CLK
1.393 0.025 tHld 1 R13C73[1][A] sim_output_storage_inst/ram_din_addra_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%

Path21

Path Summary:

Slack 0.278
Data Arrival Time 1.697
Data Required Time 1.419
From sim_input_gen_inst/cnt_cycle_4_s1
To sim_input_gen_inst/cnt_cycle_4_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.394 0.719 tNET RR 1 R2C55[0][A] sim_input_gen_inst/cnt_cycle_4_s1/CLK
1.535 0.141 tC2Q RF 5 R2C55[0][A] sim_input_gen_inst/cnt_cycle_4_s1/Q
1.544 0.009 tNET FF 1 R2C55[0][A] sim_input_gen_inst/n42_s2/I1
1.697 0.153 tINS FF 1 R2C55[0][A] sim_input_gen_inst/n42_s2/F
1.697 0.000 tNET FF 1 R2C55[0][A] sim_input_gen_inst/cnt_cycle_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.394 0.719 tNET RR 1 R2C55[0][A] sim_input_gen_inst/cnt_cycle_4_s1/CLK
1.419 0.025 tHld 1 R2C55[0][A] sim_input_gen_inst/cnt_cycle_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.449%; route: 0.719, 51.551%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 48.449%; route: 0.719, 51.551%

Path22

Path Summary:

Slack 0.278
Data Arrival Time 1.671
Data Required Time 1.393
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_ram_addra_2_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_ram_addra_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R31C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_ram_addra_2_s0/CLK
1.510 0.141 tC2Q RF 11 R31C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_ram_addra_2_s0/Q
1.518 0.009 tNET FF 1 R31C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/n1973_s2/I3
1.671 0.153 tINS FF 1 R31C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/n1973_s2/F
1.671 0.000 tNET FF 1 R31C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_ram_addra_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R31C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_ram_addra_2_s0/CLK
1.393 0.025 tHld 1 R31C69[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_ram_addra_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%

Path23

Path Summary:

Slack 0.278
Data Arrival Time 1.694
Data Required Time 1.416
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.532 0.141 tC2Q RF 6 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
1.541 0.009 tNET FF 1 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n328_s1/I1
1.694 0.153 tINS FF 1 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n328_s1/F
1.694 0.000 tNET FF 1 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.416 0.025 tHld 1 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path24

Path Summary:

Slack 0.278
Data Arrival Time 1.704
Data Required Time 1.426
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.542 0.141 tC2Q RF 4 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q
1.551 0.009 tNET FF 1 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n232_s0/I1
1.704 0.153 tINS FF 1 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n232_s0/F
1.704 0.000 tNET FF 1 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.426 0.025 tHld 1 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%

Path25

Path Summary:

Slack 0.278
Data Arrival Time 1.688
Data Required Time 1.410
From gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.385 0.709 tNET RR 1 R8C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.526 0.141 tC2Q RF 12 R8C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
1.535 0.009 tNET FF 1 R8C78[1][A] gw_gao_inst_0/u_la0_top/n1648_s1/I0
1.688 0.153 tINS FF 1 R8C78[1][A] gw_gao_inst_0/u_la0_top/n1648_s1/F
1.688 0.000 tNET FF 1 R8C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.385 0.709 tNET RR 1 R8C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.410 0.025 tHld 1 R8C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.790%; route: 0.709, 51.210%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 48.790%; route: 0.709, 51.210%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.778
Data Arrival Time 9.503
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.503 1.401 tNET FF 1 R8C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.628 1.946 tNET RR 1 R8C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
12.281 -0.347 tSu 1 R8C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew -0.032
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.401, 75.996%; tC2Q: 0.442, 24.004%
Required Clock Path Delay cell: 0.683, 25.966%; route: 1.946, 74.034%

Path2

Path Summary:

Slack 2.778
Data Arrival Time 9.503
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.503 1.401 tNET FF 1 R8C78[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.628 1.946 tNET RR 1 R8C78[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
12.281 -0.347 tSu 1 R8C78[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -0.032
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.401, 75.996%; tC2Q: 0.442, 24.004%
Required Clock Path Delay cell: 0.683, 25.966%; route: 1.946, 74.034%

Path3

Path Summary:

Slack 2.778
Data Arrival Time 9.503
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.503 1.401 tNET FF 1 R8C78[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.628 1.946 tNET RR 1 R8C78[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
12.281 -0.347 tSu 1 R8C78[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew -0.032
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.401, 75.996%; tC2Q: 0.442, 24.004%
Required Clock Path Delay cell: 0.683, 25.966%; route: 1.946, 74.034%

Path4

Path Summary:

Slack 2.778
Data Arrival Time 9.503
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.503 1.401 tNET FF 1 R8C78[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.628 1.946 tNET RR 1 R8C78[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
12.281 -0.347 tSu 1 R8C78[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew -0.032
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.401, 75.996%; tC2Q: 0.442, 24.004%
Required Clock Path Delay cell: 0.683, 25.966%; route: 1.946, 74.034%

Path5

Path Summary:

Slack 2.778
Data Arrival Time 9.525
Data Required Time 12.302
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.525 1.422 tNET FF 1 R5C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.650 1.967 tNET RR 1 R5C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
12.302 -0.347 tSu 1 R5C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew -0.010
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.422, 76.269%; tC2Q: 0.442, 23.731%
Required Clock Path Delay cell: 0.683, 25.755%; route: 1.967, 74.245%

Path6

Path Summary:

Slack 2.780
Data Arrival Time 9.525
Data Required Time 12.305
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.525 1.422 tNET FF 1 R4C77[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.653 1.970 tNET RR 1 R4C77[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
12.305 -0.347 tSu 1 R4C77[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew -0.007
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.422, 76.269%; tC2Q: 0.442, 23.731%
Required Clock Path Delay cell: 0.683, 25.730%; route: 1.970, 74.270%

Path7

Path Summary:

Slack 2.780
Data Arrival Time 9.525
Data Required Time 12.305
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.525 1.422 tNET FF 1 R4C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.653 1.970 tNET RR 1 R4C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
12.305 -0.347 tSu 1 R4C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew -0.007
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.422, 76.269%; tC2Q: 0.442, 23.731%
Required Clock Path Delay cell: 0.683, 25.730%; route: 1.970, 74.270%

Path8

Path Summary:

Slack 2.785
Data Arrival Time 9.516
Data Required Time 12.301
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.516 1.413 tNET FF 1 R2C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.648 1.966 tNET RR 1 R2C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.301 -0.347 tSu 1 R2C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew -0.012
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.413, 76.158%; tC2Q: 0.442, 23.842%
Required Clock Path Delay cell: 0.683, 25.773%; route: 1.966, 74.227%

Path9

Path Summary:

Slack 2.785
Data Arrival Time 9.516
Data Required Time 12.301
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.516 1.413 tNET FF 1 R2C76[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.648 1.966 tNET RR 1 R2C76[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
12.301 -0.347 tSu 1 R2C76[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew -0.012
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.413, 76.158%; tC2Q: 0.442, 23.842%
Required Clock Path Delay cell: 0.683, 25.773%; route: 1.966, 74.227%

Path10

Path Summary:

Slack 2.785
Data Arrival Time 9.503
Data Required Time 12.288
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.503 1.401 tNET FF 1 R7C78[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.636 1.953 tNET RR 1 R7C78[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
12.288 -0.347 tSu 1 R7C78[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew -0.024
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.401, 75.996%; tC2Q: 0.442, 24.004%
Required Clock Path Delay cell: 0.683, 25.895%; route: 1.953, 74.105%

Path11

Path Summary:

Slack 2.789
Data Arrival Time 9.499
Data Required Time 12.288
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.499 1.396 tNET FF 1 R7C76[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.636 1.953 tNET RR 1 R7C76[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
12.288 -0.347 tSu 1 R7C76[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew -0.024
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.396, 75.935%; tC2Q: 0.442, 24.065%
Required Clock Path Delay cell: 0.683, 25.895%; route: 1.953, 74.105%

Path12

Path Summary:

Slack 2.794
Data Arrival Time 9.516
Data Required Time 12.310
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.516 1.413 tNET FF 1 R2C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.658 1.975 tNET RR 1 R2C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
12.310 -0.347 tSu 1 R2C77[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.413, 76.158%; tC2Q: 0.442, 23.842%
Required Clock Path Delay cell: 0.683, 25.682%; route: 1.975, 74.318%

Path13

Path Summary:

Slack 2.794
Data Arrival Time 9.516
Data Required Time 12.310
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.516 1.413 tNET FF 1 R2C77[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.658 1.975 tNET RR 1 R2C77[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
12.310 -0.347 tSu 1 R2C77[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.413, 76.158%; tC2Q: 0.442, 23.842%
Required Clock Path Delay cell: 0.683, 25.682%; route: 1.975, 74.318%

Path14

Path Summary:

Slack 2.797
Data Arrival Time 9.499
Data Required Time 12.296
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.499 1.396 tNET FF 1 R4C76[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.643 1.961 tNET RR 1 R4C76[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
12.296 -0.347 tSu 1 R4C76[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew -0.017
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.396, 75.935%; tC2Q: 0.442, 24.065%
Required Clock Path Delay cell: 0.683, 25.822%; route: 1.961, 74.178%

Path15

Path Summary:

Slack 2.884
Data Arrival Time 9.361
Data Required Time 12.245
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.361 1.259 tNET FF 1 R14C75[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.593 1.910 tNET RR 1 R14C75[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
12.245 -0.347 tSu 1 R14C75[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew -0.067
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.259, 73.990%; tC2Q: 0.442, 26.010%
Required Clock Path Delay cell: 0.683, 26.323%; route: 1.910, 73.677%

Path16

Path Summary:

Slack 2.975
Data Arrival Time 9.323
Data Required Time 12.298
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.323 1.221 tNET FF 1 R3C76[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R3C76[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
12.298 -0.347 tSu 1 R3C76[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew -0.014
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.221, 73.398%; tC2Q: 0.442, 26.602%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path17

Path Summary:

Slack 2.975
Data Arrival Time 9.323
Data Required Time 12.298
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.323 1.221 tNET FF 1 R3C76[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R3C76[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
12.298 -0.347 tSu 1 R3C76[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew -0.014
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.221, 73.398%; tC2Q: 0.442, 26.602%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path18

Path Summary:

Slack 2.975
Data Arrival Time 9.323
Data Required Time 12.298
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.323 1.221 tNET FF 1 R3C76[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R3C76[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
12.298 -0.347 tSu 1 R3C76[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew -0.014
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.221, 73.398%; tC2Q: 0.442, 26.602%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path19

Path Summary:

Slack 2.975
Data Arrival Time 9.323
Data Required Time 12.298
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.323 1.221 tNET FF 1 R3C76[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R3C76[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
12.298 -0.347 tSu 1 R3C76[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew -0.014
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.221, 73.398%; tC2Q: 0.442, 26.602%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path20

Path Summary:

Slack 2.975
Data Arrival Time 9.323
Data Required Time 12.298
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.323 1.221 tNET FF 1 R3C76[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R3C76[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
12.298 -0.347 tSu 1 R3C76[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew -0.014
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.221, 73.398%; tC2Q: 0.442, 26.602%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path21

Path Summary:

Slack 2.975
Data Arrival Time 9.323
Data Required Time 12.298
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.323 1.221 tNET FF 1 R3C78[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R3C78[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
12.298 -0.347 tSu 1 R3C78[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew -0.014
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.221, 73.398%; tC2Q: 0.442, 26.602%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path22

Path Summary:

Slack 2.976
Data Arrival Time 9.315
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.315 1.212 tNET FF 1 R6C76[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C76[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
12.291 -0.347 tSu 1 R6C76[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew -0.022
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.212, 73.263%; tC2Q: 0.442, 26.737%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path23

Path Summary:

Slack 2.976
Data Arrival Time 9.315
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.315 1.212 tNET FF 1 R6C76[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C76[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
12.291 -0.347 tSu 1 R6C76[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew -0.022
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.212, 73.263%; tC2Q: 0.442, 26.737%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path24

Path Summary:

Slack 2.976
Data Arrival Time 9.315
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.315 1.212 tNET FF 1 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
12.291 -0.347 tSu 1 R6C76[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew -0.022
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.212, 73.263%; tC2Q: 0.442, 26.737%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path25

Path Summary:

Slack 2.976
Data Arrival Time 9.315
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3254 IOB29[A] clk_ibuf/O
7.660 1.972 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.102 0.442 tC2Q FF 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.315 1.212 tNET FF 1 R6C76[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3254 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C76[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
12.291 -0.347 tSu 1 R6C76[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew -0.022
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.846%; route: 1.972, 74.154%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.212, 73.263%; tC2Q: 0.442, 26.737%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 5.421
Data Arrival Time 6.762
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.762 0.197 tNET RR 1 R22C76[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.395 0.719 tNET RR 1 R22C76[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
1.342 -0.053 tHld 1 R22C76[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.197, 55.493%; tC2Q: 0.158, 44.507%
Required Clock Path Delay cell: 0.675, 48.432%; route: 0.719, 51.568%

Path2

Path Summary:

Slack 5.421
Data Arrival Time 6.762
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.762 0.197 tNET RR 1 R22C76[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.395 0.719 tNET RR 1 R22C76[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
1.342 -0.053 tHld 1 R22C76[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.197, 55.493%; tC2Q: 0.158, 44.507%
Required Clock Path Delay cell: 0.675, 48.432%; route: 0.719, 51.568%

Path3

Path Summary:

Slack 5.423
Data Arrival Time 6.766
Data Required Time 1.344
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.766 0.201 tNET RR 1 R21C76[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.397 0.721 tNET RR 1 R21C76[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
1.344 -0.053 tHld 1 R21C76[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay cell: 0.675, 48.371%; route: 0.721, 51.629%

Path4

Path Summary:

Slack 5.423
Data Arrival Time 6.766
Data Required Time 1.344
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.766 0.201 tNET RR 1 R21C76[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.397 0.721 tNET RR 1 R21C76[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
1.344 -0.053 tHld 1 R21C76[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay cell: 0.675, 48.371%; route: 0.721, 51.629%

Path5

Path Summary:

Slack 5.423
Data Arrival Time 6.766
Data Required Time 1.344
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.766 0.201 tNET RR 1 R21C76[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.397 0.721 tNET RR 1 R21C76[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
1.344 -0.053 tHld 1 R21C76[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay cell: 0.675, 48.371%; route: 0.721, 51.629%

Path6

Path Summary:

Slack 5.423
Data Arrival Time 6.766
Data Required Time 1.344
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.766 0.201 tNET RR 1 R21C76[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.397 0.721 tNET RR 1 R21C76[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
1.344 -0.053 tHld 1 R21C76[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay cell: 0.675, 48.371%; route: 0.721, 51.629%

Path7

Path Summary:

Slack 5.423
Data Arrival Time 6.766
Data Required Time 1.344
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.766 0.201 tNET RR 1 R21C76[1][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.397 0.721 tNET RR 1 R21C76[1][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.344 -0.053 tHld 1 R21C76[1][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay cell: 0.675, 48.371%; route: 0.721, 51.629%

Path8

Path Summary:

Slack 5.427
Data Arrival Time 6.766
Data Required Time 1.339
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.766 0.201 tNET RR 1 R21C75[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.392 0.717 tNET RR 1 R21C75[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.339 -0.053 tHld 1 R21C75[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew -0.015
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.201, 55.989%; tC2Q: 0.158, 44.011%
Required Clock Path Delay cell: 0.675, 48.510%; route: 0.717, 51.490%

Path9

Path Summary:

Slack 5.629
Data Arrival Time 6.951
Data Required Time 1.322
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.951 0.386 tNET RR 1 R17C78[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.375 0.700 tNET RR 1 R17C78[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.322 -0.053 tHld 1 R17C78[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew -0.033
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.386, 70.956%; tC2Q: 0.158, 29.044%
Required Clock Path Delay cell: 0.675, 49.127%; route: 0.700, 50.873%

Path10

Path Summary:

Slack 5.629
Data Arrival Time 6.951
Data Required Time 1.322
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.951 0.386 tNET RR 1 R17C78[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.375 0.700 tNET RR 1 R17C78[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.322 -0.053 tHld 1 R17C78[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew -0.033
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.386, 70.956%; tC2Q: 0.158, 29.044%
Required Clock Path Delay cell: 0.675, 49.127%; route: 0.700, 50.873%

Path11

Path Summary:

Slack 5.629
Data Arrival Time 6.951
Data Required Time 1.322
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.951 0.386 tNET RR 1 R17C78[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.375 0.700 tNET RR 1 R17C78[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.322 -0.053 tHld 1 R17C78[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew -0.033
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.386, 70.956%; tC2Q: 0.158, 29.044%
Required Clock Path Delay cell: 0.675, 49.127%; route: 0.700, 50.873%

Path12

Path Summary:

Slack 5.629
Data Arrival Time 6.951
Data Required Time 1.322
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.951 0.386 tNET RR 1 R17C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.375 0.700 tNET RR 1 R17C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.322 -0.053 tHld 1 R17C78[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew -0.033
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.386, 70.956%; tC2Q: 0.158, 29.044%
Required Clock Path Delay cell: 0.675, 49.127%; route: 0.700, 50.873%

Path13

Path Summary:

Slack 5.629
Data Arrival Time 6.951
Data Required Time 1.322
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.951 0.386 tNET RR 1 R17C78[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.375 0.700 tNET RR 1 R17C78[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.322 -0.053 tHld 1 R17C78[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew -0.033
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.386, 70.956%; tC2Q: 0.158, 29.044%
Required Clock Path Delay cell: 0.675, 49.127%; route: 0.700, 50.873%

Path14

Path Summary:

Slack 5.825
Data Arrival Time 7.145
Data Required Time 1.321
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.145 0.580 tNET RR 1 R16C78[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R16C78[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.321 -0.053 tHld 1 R16C78[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew -0.034
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.580, 78.591%; tC2Q: 0.158, 21.409%
Required Clock Path Delay cell: 0.675, 49.172%; route: 0.698, 50.828%

Path15

Path Summary:

Slack 5.885
Data Arrival Time 7.227
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.227 0.662 tNET RR 1 R6C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.395 0.720 tNET RR 1 R6C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.342 -0.053 tHld 1 R6C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew -0.012
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.662, 80.732%; tC2Q: 0.158, 19.268%
Required Clock Path Delay cell: 0.675, 48.414%; route: 0.720, 51.586%

Path16

Path Summary:

Slack 5.885
Data Arrival Time 7.233
Data Required Time 1.348
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.233 0.667 tNET RR 1 R3C77[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R3C77[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.348 -0.053 tHld 1 R3C77[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.667, 80.854%; tC2Q: 0.158, 19.146%
Required Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%

Path17

Path Summary:

Slack 5.885
Data Arrival Time 7.233
Data Required Time 1.348
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.233 0.667 tNET RR 1 R3C77[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R3C77[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.348 -0.053 tHld 1 R3C77[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.667, 80.854%; tC2Q: 0.158, 19.146%
Required Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%

Path18

Path Summary:

Slack 5.885
Data Arrival Time 7.233
Data Required Time 1.348
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.233 0.667 tNET RR 1 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.348 -0.053 tHld 1 R3C77[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.667, 80.854%; tC2Q: 0.158, 19.146%
Required Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%

Path19

Path Summary:

Slack 5.885
Data Arrival Time 7.233
Data Required Time 1.348
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.233 0.667 tNET RR 1 R3C77[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R3C77[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.348 -0.053 tHld 1 R3C77[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.667, 80.854%; tC2Q: 0.158, 19.146%
Required Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%

Path20

Path Summary:

Slack 5.886
Data Arrival Time 7.212
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.212 0.647 tNET RR 1 R9C78[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C78[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.326 -0.053 tHld 1 R9C78[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew -0.028
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.647, 80.373%; tC2Q: 0.158, 19.627%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path21

Path Summary:

Slack 5.886
Data Arrival Time 7.212
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.212 0.647 tNET RR 1 R9C78[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C78[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.326 -0.053 tHld 1 R9C78[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew -0.028
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.647, 80.373%; tC2Q: 0.158, 19.627%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path22

Path Summary:

Slack 5.886
Data Arrival Time 7.212
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.212 0.647 tNET RR 1 R9C78[2][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C78[2][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.326 -0.053 tHld 1 R9C78[2][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew -0.028
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.647, 80.373%; tC2Q: 0.158, 19.627%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path23

Path Summary:

Slack 5.886
Data Arrival Time 7.212
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.212 0.647 tNET RR 1 R9C78[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C78[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
1.326 -0.053 tHld 1 R9C78[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew -0.028
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.647, 80.373%; tC2Q: 0.158, 19.627%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path24

Path Summary:

Slack 5.886
Data Arrival Time 7.212
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.212 0.647 tNET RR 1 R9C78[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C78[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.326 -0.053 tHld 1 R9C78[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew -0.028
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.647, 80.373%; tC2Q: 0.158, 19.627%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path25

Path Summary:

Slack 5.886
Data Arrival Time 7.212
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3254 IOB29[A] clk_ibuf/O
6.407 0.730 tNET FF 1 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.565 0.158 tC2Q FR 53 R21C77[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.212 0.647 tNET RR 1 R9C78[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3254 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C78[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.326 -0.053 tHld 1 R9C78[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew -0.028
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.135%; route: 0.730, 51.865%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.647, 80.373%; tC2Q: 0.158, 19.627%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.751
Actual Width: 3.751
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.627 1.940 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.703 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack: 2.754
Actual Width: 3.754
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.628 1.940 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.382 0.706 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

MPW3

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW4

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK

MPW5

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA

MPW6

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.623 1.941 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.385 0.708 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW7

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.608 1.921 tNET FF sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.371 0.695 tNET RR sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB

MPW8

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.625 1.942 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.387 0.710 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

MPW9

MPW Summary:

Slack: 2.767
Actual Width: 3.767
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.614 1.932 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.381 0.704 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW10

MPW Summary:

Slack: 2.767
Actual Width: 3.767
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.614 1.932 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.381 0.704 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_interpolator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
3254 clk_d 1.039 1.985
608 coeff_ram_addrb[0] 2.392 4.533
305 delay_shift_addrb[0] 5.559 2.593
304 delay_shift_addrb_symm[0] 4.645 2.911
304 coeff_ram_addrb[1] 3.531 3.856
225 control0[0] 3.835 2.729
161 delay_shift_addrb[1] 3.658 3.954
160 coeff_ram_addrb[2] 3.222 3.553
160 delay_shift_addrb_symm[1] 4.749 2.720
81 delay_shift_addrb[2] 6.171 2.377

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R13C66 54.17%
R14C67 54.17%
R14C66 50.00%
R22C70 50.00%
R9C47 48.61%
R12C65 48.61%
R13C65 48.61%
R13C77 48.61%
R30C45 48.61%
R25C70 47.22%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]