Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\161taps_2chn_1tdm_8inter_3decim_16bit\proj\src\advanced_fir_filter\advanced_fir_filter.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\161taps_2chn_1tdm_8inter_3decim_16bit\proj\src\sim_input_gen.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\161taps_2chn_1tdm_8inter_3decim_16bit\proj\src\sim_output_storage.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\161taps_2chn_1tdm_8inter_3decim_16bit\proj\src\spram.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\161taps_2chn_1tdm_8inter_3decim_16bit\proj\src\tb_gw5a.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\78162\Gowin_V1.9.11_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\5_fir_fractional_rate\161taps_2chn_1tdm_8inter_3decim_16bit\proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Dec 25 12:42:35 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module tb_gw5a
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 591.758MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.29s, Peak memory usage = 591.758MB
    Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.202s, Peak memory usage = 591.758MB
    Optimizing Phase 2: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.461s, Peak memory usage = 591.758MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.243s, Peak memory usage = 591.758MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 591.758MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 591.758MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 591.758MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.259s, Peak memory usage = 591.758MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 591.758MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 591.758MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 591.758MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.275s, Peak memory usage = 591.758MB
Generate output files:
    CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.731s, Peak memory usage = 591.758MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 591.758MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 49
I/O Buf 49
    IBUF 5
    OBUF 44
Register 6476
    DFFRE 1
    DFFPE 89
    DFFCE 6386
LUT 2515
    LUT2 81
    LUT3 1903
    LUT4 531
MUX 1
    MUX16 1
ALU 935
    ALU 935
INV 8
    INV 8
DSP
    MULTALU27X18 21
BSRAM 4
    SDPB 3
    pROM 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3466(2531 LUT, 935 ALU) / 23040 16%
Register 6476 / 23685 28%
  --Register as Latch 0 / 23685 0%
  --Register as FF 6476 / 23685 28%
BSRAM 4 / 56 8%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 200.451(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.011
Data Arrival Time 5.300
Data Required Time 10.311
From gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6279 clk_ibuf/O
0.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.757 0.382 tC2Q RR 14 gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q
1.132 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s12/I1
1.649 0.516 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s12/F
2.024 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s11/I0
2.550 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s11/F
2.925 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/I0
3.451 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/F
3.826 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s9/I3
4.089 0.262 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s9/F
4.464 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/I2
4.925 0.461 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/F
5.300 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6279 clk_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/CLK
10.311 -0.064 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.293, 46.549%; route: 2.250, 45.685%; tC2Q: 0.382, 7.766%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 5.018
Data Arrival Time 5.046
Data Required Time 10.064
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6279 clk_ibuf/O
0.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.757 0.382 tC2Q RR 4 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/Q
1.132 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/I0
1.659 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/F
2.034 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s6/I3
2.296 0.262 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s6/F
2.671 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/I3
2.934 0.262 tINS RR 2 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/F
3.309 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
3.835 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
4.210 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2
4.671 0.461 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
5.046 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6279 clk_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.064 -0.311 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.039, 43.645%; route: 2.250, 48.167%; tC2Q: 0.382, 8.188%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 5.336
Data Arrival Time 4.727
Data Required Time 10.064
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6279 clk_ibuf/O
0.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
0.757 0.382 tC2Q RR 5 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
1.132 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s9/I0
1.659 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s9/F
2.034 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s6/I0
2.560 0.526 tINS RR 2 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s6/F
2.935 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/I1
3.451 0.516 tINS RR 10 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/F
3.826 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
4.352 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
4.727 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6279 clk_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.064 -0.311 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 5.584
Data Arrival Time 4.727
Data Required Time 10.311
From gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6279 clk_ibuf/O
0.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.757 0.382 tC2Q RR 14 gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q
1.132 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s15/I1
1.649 0.516 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s15/F
2.024 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/I0
2.550 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s13/F
2.925 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s10/I0
3.451 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s10/F
3.826 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/I0
4.352 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_8_s9/F
4.727 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6279 clk_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0/CLK
10.311 -0.064 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 5.584
Data Arrival Time 4.727
Data Required Time 10.311
From gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 6279 clk_ibuf/O
0.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.757 0.382 tC2Q RR 14 gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/Q
1.132 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I1
1.649 0.516 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F
2.024 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/I0
2.550 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/F
2.925 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s11/I0
3.451 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s11/F
3.826 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I0
4.352 0.526 tINS RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
4.727 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 6279 clk_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
10.311 -0.064 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%