Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\1_fir_singlerate\32taps_8chn_32tdm_16bit\proj\impl\gwsynthesis\fir_proj.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\1_fir_singlerate\32taps_8chn_32tdm_16bit\proj\src\fir_proj.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\1_fir_singlerate\32taps_8chn_32tdm_16bit\proj\src\fir_proj.sdc
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Dec 24 17:58:01 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 4932
Numbers of Endpoints Analyzed 5746
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk Base 10.000 100.000 0.000 5.000 clk
2 tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 146.265(MHz) 3 TOP
2 tck_pad_i 20.000(MHz) 150.157(MHz) 5 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 3.163 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_14_s0/CE clk:[R] clk:[R] 10.000 0.009 6.516
2 3.499 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_13_s0/CE clk:[R] clk:[R] 10.000 0.019 6.171
3 3.499 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_14_s0/CE clk:[R] clk:[R] 10.000 0.019 6.171
4 3.553 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_4_s0/CE clk:[R] clk:[R] 10.000 0.000 6.136
5 3.588 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_14_s0/CE clk:[R] clk:[R] 10.000 0.021 6.080
6 3.601 gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE tck_pad_i:[R] clk:[R] 10.000 1.452 4.601
7 3.708 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_4_s0/CE clk:[R] clk:[R] 10.000 0.000 5.981
8 3.917 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_2_s0/CE clk:[R] clk:[R] 10.000 0.018 5.754
9 3.917 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_13_s0/CE clk:[R] clk:[R] 10.000 0.018 5.754
10 3.950 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_0_s0/CE clk:[R] clk:[R] 10.000 -0.016 5.755
11 3.973 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_13_s0/CE clk:[R] clk:[R] 10.000 0.011 5.705
12 3.973 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_1_s0/CE clk:[R] clk:[R] 10.000 0.011 5.705
13 4.075 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_3_s0/CE clk:[R] clk:[R] 10.000 0.015 5.599
14 4.107 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_3_s0/CE clk:[R] clk:[R] 10.000 0.015 5.566
15 4.120 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_0_s0/CE clk:[R] clk:[R] 10.000 -0.014 5.583
16 4.120 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_5_s0/CE clk:[R] clk:[R] 10.000 -0.014 5.583
17 4.163 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[6]_0_s0/CE clk:[R] clk:[R] 10.000 -0.028 5.554
18 4.168 gw_gao_inst_0/u_la0_top/capture_windows_num_6_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D tck_pad_i:[R] clk:[R] 10.000 1.443 4.291
19 4.190 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE tck_pad_i:[R] clk:[R] 10.000 1.423 4.040
20 4.272 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D tck_pad_i:[R] clk:[R] 10.000 1.440 4.189
21 4.279 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D tck_pad_i:[R] clk:[R] 10.000 1.431 4.191
22 4.288 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_4_s0/CE clk:[R] clk:[R] 10.000 0.025 5.376
23 4.289 gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D tck_pad_i:[R] clk:[R] 10.000 1.431 4.181
24 4.294 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_13_s0/CE clk:[R] clk:[R] 10.000 0.021 5.374
25 4.294 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_2_s0/CE clk:[R] clk:[R] 10.000 0.021 5.374

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.155 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_2_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[2] clk:[R] clk:[R] 0.000 -0.014 0.206
2 0.164 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_7_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[7] clk:[R] clk:[R] 0.000 -0.005 0.206
3 0.189 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11] clk:[R] clk:[R] 0.000 -0.009 0.235
4 0.189 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10] clk:[R] clk:[R] 0.000 -0.009 0.235
5 0.193 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6] clk:[R] clk:[R] 0.000 -0.005 0.235
6 0.193 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1] clk:[R] clk:[R] 0.000 -0.005 0.235
7 0.198 sim_output_storage_inst/ram_din_addra_0_s0/Q sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[4] clk:[R] clk:[R] 0.000 -0.009 0.244
8 0.211 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[7] clk:[R] clk:[R] 0.000 0.005 0.243
9 0.212 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13] clk:[R] clk:[R] 0.000 -0.009 0.258
10 0.212 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[12] clk:[R] clk:[R] 0.000 -0.009 0.258
11 0.214 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[11] clk:[R] clk:[R] 0.000 0.005 0.246
12 0.216 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] clk:[R] clk:[R] 0.000 0.010 0.243
13 0.216 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4] clk:[R] clk:[R] 0.000 0.010 0.243
14 0.216 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2] clk:[R] clk:[R] 0.000 0.010 0.243
15 0.216 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] clk:[R] clk:[R] 0.000 -0.005 0.258
16 0.227 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_8_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[8] clk:[R] clk:[R] 0.000 -0.005 0.269
17 0.227 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_6_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[6] clk:[R] clk:[R] 0.000 -0.005 0.269
18 0.254 sim_output_storage_inst/ram_din_addra_8_s0/Q sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[12] clk:[R] clk:[R] 0.000 -0.018 0.309
19 0.254 sim_output_storage_inst/ram_din_addra_4_s0/Q sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[8] clk:[R] clk:[R] 0.000 -0.018 0.309
20 0.257 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/delay_shift_addrb_0_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/ADB[4] clk:[R] clk:[R] 0.000 0.001 0.291
21 0.257 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15] clk:[R] clk:[R] 0.000 -0.005 0.299
22 0.257 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[14] clk:[R] clk:[R] 0.000 -0.005 0.299
23 0.259 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_15_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[15] clk:[R] clk:[R] 0.000 -0.014 0.310
24 0.260 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[4] clk:[R] clk:[R] 0.000 0.005 0.292
25 0.263 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[1] clk:[R] clk:[R] 0.000 -0.010 0.310

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.840 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR clk:[F] clk:[R] 5.000 0.013 1.799
2 2.840 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR clk:[F] clk:[R] 5.000 0.013 1.799
3 3.042 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR clk:[F] clk:[R] 5.000 0.004 1.606
4 3.042 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR clk:[F] clk:[R] 5.000 0.004 1.606
5 3.042 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR clk:[F] clk:[R] 5.000 0.004 1.606
6 3.047 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR clk:[F] clk:[R] 5.000 0.021 1.585
7 3.047 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR clk:[F] clk:[R] 5.000 0.021 1.585
8 3.047 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR clk:[F] clk:[R] 5.000 0.021 1.585
9 3.047 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR clk:[F] clk:[R] 5.000 0.021 1.585
10 3.047 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR clk:[F] clk:[R] 5.000 0.021 1.585
11 3.052 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR clk:[F] clk:[R] 5.000 -0.005 1.606
12 3.056 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR clk:[F] clk:[R] 5.000 0.012 1.585
13 3.056 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR clk:[F] clk:[R] 5.000 0.012 1.585
14 3.056 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR clk:[F] clk:[R] 5.000 0.012 1.585
15 3.056 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR clk:[F] clk:[R] 5.000 0.012 1.585
16 3.056 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR clk:[F] clk:[R] 5.000 0.012 1.585
17 3.106 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR clk:[F] clk:[R] 5.000 0.004 1.543
18 3.106 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR clk:[F] clk:[R] 5.000 0.004 1.543
19 3.106 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR clk:[F] clk:[R] 5.000 0.004 1.543
20 3.106 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR clk:[F] clk:[R] 5.000 0.004 1.543
21 3.115 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET clk:[F] clk:[R] 5.000 -0.005 1.543
22 3.115 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR clk:[F] clk:[R] 5.000 -0.005 1.543
23 3.359 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR clk:[F] clk:[R] 5.000 0.013 1.280
24 3.359 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR clk:[F] clk:[R] 5.000 0.013 1.280
25 3.359 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR clk:[F] clk:[R] 5.000 0.013 1.280

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 5.422 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR clk:[F] clk:[R] -5.000 0.006 0.363
2 5.426 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR clk:[F] clk:[R] -5.000 0.010 0.363
3 5.426 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR clk:[F] clk:[R] -5.000 0.010 0.363
4 5.426 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR clk:[F] clk:[R] -5.000 0.010 0.363
5 5.426 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR clk:[F] clk:[R] -5.000 0.010 0.363
6 5.426 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR clk:[F] clk:[R] -5.000 0.010 0.363
7 5.429 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR clk:[F] clk:[R] -5.000 0.013 0.363
8 5.429 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.013 0.363
9 5.429 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.013 0.363
10 5.429 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR clk:[F] clk:[R] -5.000 0.013 0.363
11 5.434 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR clk:[F] clk:[R] -5.000 0.018 0.363
12 5.434 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR clk:[F] clk:[R] -5.000 0.018 0.363
13 5.434 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR clk:[F] clk:[R] -5.000 0.018 0.363
14 5.434 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.018 0.363
15 5.434 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.018 0.363
16 5.526 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR clk:[F] clk:[R] -5.000 0.006 0.467
17 5.526 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR clk:[F] clk:[R] -5.000 0.006 0.467
18 5.526 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.006 0.467
19 5.526 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.006 0.467
20 5.526 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.006 0.467
21 5.526 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.006 0.467
22 5.578 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR clk:[F] clk:[R] -5.000 0.002 0.523
23 5.582 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET clk:[F] clk:[R] -5.000 0.006 0.523
24 5.630 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR clk:[F] clk:[R] -5.000 0.006 0.571
25 5.634 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR clk:[F] clk:[R] -5.000 0.010 0.571

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.751 3.751 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
2 2.751 3.751 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
3 2.757 3.757 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
4 2.757 3.757 1.000 Low Pulse Width clk sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
5 2.757 3.757 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
6 2.759 3.759 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1
7 2.762 3.762 1.000 High Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
8 2.762 3.762 1.000 High Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
9 2.762 3.762 1.000 Low Pulse Width clk sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
10 2.767 3.767 1.000 High Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 3.163
Data Arrival Time 9.134
Data Required Time 12.297
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.053 1.191 tNET RR 1 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/I3
6.579 0.526 tINS RR 16 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/F
9.134 2.555 tNET RR 1 R33C36[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.608 1.926 tNET RR 1 R33C36[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_14_s0/CLK
12.297 -0.311 tSu 1 R33C36[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_14_s0

Path Statistics:

Clock Skew -0.009
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 1.043, 15.998%; route: 5.091, 78.132%; tC2Q: 0.382, 5.870%
Required Clock Path Delay cell: 0.683, 26.168%; route: 1.926, 73.832%

Path2

Path Summary:

Slack 3.499
Data Arrival Time 8.789
Data Required Time 12.288
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.245 1.384 tNET RR 1 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/I0
6.508 0.262 tINS RR 16 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/F
8.789 2.281 tNET RR 1 R33C35[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.599 1.916 tNET RR 1 R33C35[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_13_s0/CLK
12.288 -0.311 tSu 1 R33C35[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_13_s0

Path Statistics:

Clock Skew -0.019
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.779, 12.619%; route: 5.010, 81.183%; tC2Q: 0.382, 6.198%
Required Clock Path Delay cell: 0.683, 26.263%; route: 1.916, 73.737%

Path3

Path Summary:

Slack 3.499
Data Arrival Time 8.789
Data Required Time 12.288
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.245 1.384 tNET RR 1 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/I0
6.508 0.262 tINS RR 16 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/F
8.789 2.281 tNET RR 1 R33C35[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.599 1.916 tNET RR 1 R33C35[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_14_s0/CLK
12.288 -0.311 tSu 1 R33C35[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_14_s0

Path Statistics:

Clock Skew -0.019
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.779, 12.619%; route: 5.010, 81.183%; tC2Q: 0.382, 6.198%
Required Clock Path Delay cell: 0.683, 26.263%; route: 1.916, 73.737%

Path4

Path Summary:

Slack 3.553
Data Arrival Time 8.754
Data Required Time 12.306
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.053 1.191 tNET RR 1 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/I3
6.579 0.526 tINS RR 16 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/F
8.754 2.175 tNET RR 1 R33C33[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.618 1.935 tNET RR 1 R33C33[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_4_s0/CLK
12.306 -0.311 tSu 1 R33C33[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 1.043, 16.989%; route: 4.711, 76.777%; tC2Q: 0.382, 6.233%
Required Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%

Path5

Path Summary:

Slack 3.588
Data Arrival Time 8.698
Data Required Time 12.285
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
5.670 0.809 tNET RR 1 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/I0
6.131 0.461 tINS RR 16 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/F
8.698 2.566 tNET RR 1 R31C36[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.596 1.914 tNET RR 1 R31C36[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_14_s0/CLK
12.285 -0.311 tSu 1 R31C36[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_14_s0

Path Statistics:

Clock Skew -0.021
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.977, 16.077%; route: 4.720, 77.632%; tC2Q: 0.382, 6.291%
Required Clock Path Delay cell: 0.683, 26.288%; route: 1.914, 73.712%

Path6

Path Summary:

Slack 3.601
Data Arrival Time 8.682
Data Required Time 12.283
From gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk tck_pad_i:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
4.080 2.715 tNET RR 1 R8C32[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK
4.463 0.382 tC2Q RR 2 R8C32[2][A] gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/Q
5.169 0.706 tNET RR 2 R11C36[0][B] gw_gao_inst_0/u_la0_top/n1578_s0/I1
5.732 0.563 tINS RF 1 R11C36[0][B] gw_gao_inst_0/u_la0_top/n1578_s0/COUT
5.732 0.000 tNET FF 2 R11C36[1][A] gw_gao_inst_0/u_la0_top/n1579_s0/CIN
5.782 0.050 tINS FR 1 R11C36[1][A] gw_gao_inst_0/u_la0_top/n1579_s0/COUT
5.782 0.000 tNET RR 2 R11C36[1][B] gw_gao_inst_0/u_la0_top/n1580_s0/CIN
5.832 0.050 tINS RR 5 R11C36[1][B] gw_gao_inst_0/u_la0_top/n1580_s0/COUT
7.299 1.467 tNET RR 1 R6C31[2][B] gw_gao_inst_0/u_la0_top/n1621_s1/I0
7.562 0.262 tINS RR 1 R6C31[2][B] gw_gao_inst_0/u_la0_top/n1621_s1/F
7.564 0.003 tNET RR 1 R6C31[3][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
8.062 0.498 tINS RR 1 R6C31[3][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
8.682 0.620 tNET RR 1 R6C31[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R6C31[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
12.594 -0.035 tUnc gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
12.283 -0.311 tSu 1 R6C31[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -1.452
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 33.453%; route: 2.715, 66.547%
Arrival Data Path Delay cell: 1.423, 30.916%; route: 2.796, 60.772%; tC2Q: 0.382, 8.313%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path7

Path Summary:

Slack 3.708
Data Arrival Time 8.599
Data Required Time 12.306
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.245 1.384 tNET RR 1 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/I0
6.508 0.262 tINS RR 16 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/F
8.599 2.091 tNET RR 1 R33C33[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.618 1.935 tNET RR 1 R33C33[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_4_s0/CLK
12.306 -0.311 tSu 1 R33C33[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.779, 13.020%; route: 4.820, 80.585%; tC2Q: 0.382, 6.395%
Required Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%

Path8

Path Summary:

Slack 3.917
Data Arrival Time 8.371
Data Required Time 12.288
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.053 1.191 tNET RR 1 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/I3
6.579 0.526 tINS RR 16 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/F
8.371 1.793 tNET RR 1 R30C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.600 1.917 tNET RR 1 R30C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_2_s0/CLK
12.288 -0.311 tSu 1 R30C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_2_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 1.043, 18.119%; route: 4.329, 75.234%; tC2Q: 0.382, 6.648%
Required Clock Path Delay cell: 0.683, 26.253%; route: 1.917, 73.747%

Path9

Path Summary:

Slack 3.917
Data Arrival Time 8.371
Data Required Time 12.288
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.053 1.191 tNET RR 1 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/I3
6.579 0.526 tINS RR 16 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/F
8.371 1.793 tNET RR 1 R30C33[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.600 1.917 tNET RR 1 R30C33[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_13_s0/CLK
12.288 -0.311 tSu 1 R30C33[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_13_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 1.043, 18.119%; route: 4.329, 75.234%; tC2Q: 0.382, 6.648%
Required Clock Path Delay cell: 0.683, 26.253%; route: 1.917, 73.747%

Path10

Path Summary:

Slack 3.950
Data Arrival Time 8.372
Data Required Time 12.323
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.245 1.384 tNET RR 1 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/I0
6.508 0.262 tINS RR 16 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/F
8.373 1.865 tNET RR 1 R22C35[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.634 1.951 tNET RR 1 R22C35[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_0_s0/CLK
12.323 -0.311 tSu 1 R22C35[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_0_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.779, 13.532%; route: 4.594, 79.822%; tC2Q: 0.382, 6.646%
Required Clock Path Delay cell: 0.683, 25.914%; route: 1.951, 74.086%

Path11

Path Summary:

Slack 3.973
Data Arrival Time 8.323
Data Required Time 12.296
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
5.670 0.809 tNET RR 1 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/I0
6.131 0.461 tINS RR 16 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/F
8.323 2.191 tNET RR 1 R29C36[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.607 1.924 tNET RR 1 R29C36[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_13_s0/CLK
12.296 -0.311 tSu 1 R29C36[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_13_s0

Path Statistics:

Clock Skew -0.011
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.977, 17.134%; route: 4.345, 76.161%; tC2Q: 0.382, 6.705%
Required Clock Path Delay cell: 0.683, 26.181%; route: 1.924, 73.819%

Path12

Path Summary:

Slack 3.973
Data Arrival Time 8.323
Data Required Time 12.296
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
5.670 0.809 tNET RR 1 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/I0
6.131 0.461 tINS RR 16 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/F
8.323 2.191 tNET RR 1 R29C36[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.607 1.924 tNET RR 1 R29C36[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_1_s0/CLK
12.296 -0.311 tSu 1 R29C36[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_1_s0

Path Statistics:

Clock Skew -0.011
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.977, 17.134%; route: 4.345, 76.161%; tC2Q: 0.382, 6.705%
Required Clock Path Delay cell: 0.683, 26.181%; route: 1.924, 73.819%

Path13

Path Summary:

Slack 4.075
Data Arrival Time 8.216
Data Required Time 12.291
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.245 1.384 tNET RR 1 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/I0
6.508 0.262 tINS RR 16 R26C25[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2267_s2/F
8.216 1.709 tNET RR 1 R32C30[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.602 1.920 tNET RR 1 R32C30[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_3_s0/CLK
12.291 -0.311 tSu 1 R32C30[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[3]_3_s0

Path Statistics:

Clock Skew -0.015
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.779, 13.909%; route: 4.438, 79.259%; tC2Q: 0.382, 6.832%
Required Clock Path Delay cell: 0.683, 26.228%; route: 1.920, 73.772%

Path14

Path Summary:

Slack 4.107
Data Arrival Time 8.184
Data Required Time 12.291
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
5.670 0.809 tNET RR 1 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/I0
6.131 0.461 tINS RR 16 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/F
8.184 2.053 tNET RR 1 R32C30[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.602 1.920 tNET RR 1 R32C30[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_3_s0/CLK
12.291 -0.311 tSu 1 R32C30[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_3_s0

Path Statistics:

Clock Skew -0.015
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.977, 17.561%; route: 4.206, 75.567%; tC2Q: 0.382, 6.872%
Required Clock Path Delay cell: 0.683, 26.228%; route: 1.920, 73.772%

Path15

Path Summary:

Slack 4.120
Data Arrival Time 8.200
Data Required Time 12.320
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.053 1.191 tNET RR 1 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/I3
6.579 0.526 tINS RR 16 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/F
8.200 1.621 tNET RR 1 R23C35[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.631 1.949 tNET RR 1 R23C35[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_0_s0/CLK
12.320 -0.311 tSu 1 R23C35[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_0_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 1.043, 18.674%; route: 4.158, 74.474%; tC2Q: 0.382, 6.852%
Required Clock Path Delay cell: 0.683, 25.938%; route: 1.949, 74.062%

Path16

Path Summary:

Slack 4.120
Data Arrival Time 8.200
Data Required Time 12.320
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.053 1.191 tNET RR 1 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/I3
6.579 0.526 tINS RR 16 R25C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2331_s1/F
8.200 1.621 tNET RR 1 R23C35[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.631 1.949 tNET RR 1 R23C35[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_5_s0/CLK
12.320 -0.311 tSu 1 R23C35[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[7]_5_s0

Path Statistics:

Clock Skew 0.014
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 1.043, 18.674%; route: 4.158, 74.474%; tC2Q: 0.382, 6.852%
Required Clock Path Delay cell: 0.683, 25.938%; route: 1.949, 74.062%

Path17

Path Summary:

Slack 4.163
Data Arrival Time 8.171
Data Required Time 12.334
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[6]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
6.245 1.384 tNET RR 1 R26C25[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2315_s2/I0
6.706 0.461 tINS RR 16 R26C25[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2315_s2/F
8.171 1.465 tNET RR 1 R21C34[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[6]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R21C34[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[6]_0_s0/CLK
12.334 -0.311 tSu 1 R21C34[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[6]_0_s0

Path Statistics:

Clock Skew 0.028
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.977, 17.601%; route: 4.194, 75.512%; tC2Q: 0.382, 6.887%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path18

Path Summary:

Slack 4.168
Data Arrival Time 8.369
Data Required Time 12.537
From gw_gao_inst_0/u_la0_top/capture_windows_num_6_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk tck_pad_i:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
4.078 2.713 tNET RR 1 R7C29[0][A] gw_gao_inst_0/u_la0_top/capture_windows_num_6_s0/CLK
4.461 0.382 tC2Q RR 4 R7C29[0][A] gw_gao_inst_0/u_la0_top/capture_windows_num_6_s0/Q
5.623 1.163 tNET RR 1 R11C25[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s12/I0
6.084 0.461 tINS RR 8 R11C25[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s12/F
6.094 0.010 tNET RR 1 R11C25[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s9/I1
6.616 0.521 tINS RR 3 R11C25[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s9/F
7.324 0.709 tNET RR 1 R7C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/I3
7.851 0.526 tINS RR 1 R7C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s14/F
7.853 0.003 tNET RR 1 R7C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I3
8.369 0.516 tINS RR 1 R7C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
8.369 0.000 tNET RR 1 R7C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.636 1.953 tNET RR 1 R7C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
12.601 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
12.537 -0.064 tSu 1 R7C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0

Path Statistics:

Clock Skew -1.443
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 33.471%; route: 2.713, 66.529%
Arrival Data Path Delay cell: 2.025, 47.189%; route: 1.884, 43.897%; tC2Q: 0.382, 8.913%
Required Clock Path Delay cell: 0.683, 25.895%; route: 1.953, 74.105%

Path19

Path Summary:

Slack 4.190
Data Arrival Time 8.102
Data Required Time 12.292
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk tck_pad_i:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
4.062 2.697 tNET RR 1 R8C38[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK
4.444 0.382 tC2Q RR 2 R8C38[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q
5.199 0.755 tNET RR 1 R9C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s7/I3
5.715 0.516 tINS RR 1 R9C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s7/F
6.098 0.382 tNET RR 1 R9C30[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s5/I0
6.388 0.290 tINS RF 2 R9C30[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s5/F
6.807 0.419 tNET FF 1 R9C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/I0
7.222 0.415 tINS FR 10 R9C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/F
7.607 0.385 tNET RR 1 R6C27[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
7.872 0.265 tINS RR 1 R6C27[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
8.102 0.230 tNET RR 1 R6C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.603 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
12.292 -0.311 tSu 1 R6C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew -1.423
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 33.608%; route: 2.697, 66.392%
Arrival Data Path Delay cell: 1.486, 36.788%; route: 2.171, 53.744%; tC2Q: 0.382, 9.468%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path20

Path Summary:

Slack 4.272
Data Arrival Time 8.250
Data Required Time 12.523
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk tck_pad_i:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
4.062 2.697 tNET RR 1 R8C38[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK
4.444 0.382 tC2Q RR 2 R8C38[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q
5.199 0.755 tNET RR 1 R9C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s7/I3
5.715 0.516 tINS RR 1 R9C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s7/F
6.098 0.382 tNET RR 1 R9C30[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s5/I0
6.388 0.290 tINS RF 2 R9C30[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s5/F
6.807 0.419 tNET FF 1 R9C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/I0
7.222 0.415 tINS FR 10 R9C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/F
7.724 0.502 tNET RR 1 R9C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n333_s1/I2
8.250 0.526 tINS RR 1 R9C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n333_s1/F
8.250 0.000 tNET RR 1 R9C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R9C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
12.586 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
12.523 -0.064 tSu 1 R9C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew -1.440
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 33.608%; route: 2.697, 66.392%
Arrival Data Path Delay cell: 1.747, 41.719%; route: 2.059, 49.150%; tC2Q: 0.382, 9.132%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path21

Path Summary:

Slack 4.279
Data Arrival Time 8.253
Data Required Time 12.532
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk tck_pad_i:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
4.062 2.697 tNET RR 1 R8C38[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK
4.444 0.382 tC2Q RR 2 R8C38[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q
5.199 0.755 tNET RR 1 R9C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s7/I3
5.715 0.516 tINS RR 1 R9C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s7/F
6.098 0.382 tNET RR 1 R9C30[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s5/I0
6.388 0.290 tINS RF 2 R9C30[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s5/F
6.807 0.419 tNET FF 1 R9C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/I0
7.222 0.415 tINS FR 10 R9C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/F
7.727 0.505 tNET RR 1 R9C25[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n330_s1/I3
8.253 0.526 tINS RR 1 R9C25[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n330_s1/F
8.253 0.000 tNET RR 1 R9C25[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.631 1.948 tNET RR 1 R9C25[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
12.596 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
12.532 -0.064 tSu 1 R9C25[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew -1.431
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 33.608%; route: 2.697, 66.392%
Arrival Data Path Delay cell: 1.747, 41.694%; route: 2.061, 49.180%; tC2Q: 0.382, 9.126%
Required Clock Path Delay cell: 0.683, 25.944%; route: 1.948, 74.056%

Path22

Path Summary:

Slack 4.288
Data Arrival Time 7.994
Data Required Time 12.282
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/I3
4.861 0.516 tINS RR 8 R18C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2220_s5/F
5.670 0.809 tNET RR 1 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/I0
6.131 0.461 tINS RR 16 R22C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2283_s2/F
7.994 1.863 tNET RR 1 R32C31[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.593 1.910 tNET RR 1 R32C31[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_4_s0/CLK
12.282 -0.311 tSu 1 R32C31[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[4]_4_s0

Path Statistics:

Clock Skew -0.025
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 0.977, 18.182%; route: 4.016, 74.704%; tC2Q: 0.382, 7.115%
Required Clock Path Delay cell: 0.683, 26.323%; route: 1.910, 73.677%

Path23

Path Summary:

Slack 4.289
Data Arrival Time 8.243
Data Required Time 12.532
From gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk tck_pad_i:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.683 0.683 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.683 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365 0.683 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
4.062 2.697 tNET RR 1 R8C38[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK
4.444 0.382 tC2Q RR 2 R8C38[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/Q
5.199 0.755 tNET RR 1 R9C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s7/I3
5.715 0.516 tINS RR 1 R9C34[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s7/F
6.098 0.382 tNET RR 1 R9C30[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s5/I0
6.388 0.290 tINS RF 2 R9C30[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s5/F
6.807 0.419 tNET FF 1 R9C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/I0
7.222 0.415 tINS FR 10 R9C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n325_s4/F
7.727 0.505 tNET RR 1 R9C25[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n326_s1/I3
8.243 0.516 tINS RR 1 R9C25[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n326_s1/F
8.243 0.000 tNET RR 1 R9C25[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.631 1.948 tNET RR 1 R9C25[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
12.596 -0.035 tUnc gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
12.532 -0.064 tSu 1 R9C25[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew -1.431
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 1.365, 33.608%; route: 2.697, 66.392%
Arrival Data Path Delay cell: 1.737, 41.555%; route: 2.061, 49.297%; tC2Q: 0.382, 9.148%
Required Clock Path Delay cell: 0.683, 25.944%; route: 1.948, 74.056%

Path24

Path Summary:

Slack 4.294
Data Arrival Time 7.991
Data Required Time 12.285
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2603_s3/I3
4.861 0.516 tINS RR 8 R18C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2603_s3/F
5.911 1.050 tNET RR 1 R22C29[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2619_s1/I3
6.433 0.521 tINS RR 16 R22C29[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2619_s1/F
7.991 1.559 tNET RR 1 R31C32[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.596 1.914 tNET RR 1 R31C32[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_13_s0/CLK
12.285 -0.311 tSu 1 R31C32[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_13_s0

Path Statistics:

Clock Skew -0.021
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 1.038, 19.307%; route: 3.954, 73.575%; tC2Q: 0.382, 7.118%
Required Clock Path Delay cell: 0.683, 26.288%; route: 1.914, 73.712%

Path25

Path Summary:

Slack 4.294
Data Arrival Time 7.991
Data Required Time 12.285
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
2.618 1.935 tNET RR 1 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/CLK
3.000 0.382 tC2Q RR 9 R15C33[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/coeff_load_flag_s0/Q
4.345 1.345 tNET RR 1 R18C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2603_s3/I3
4.861 0.516 tINS RR 8 R18C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2603_s3/F
5.911 1.050 tNET RR 1 R22C29[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2619_s1/I3
6.433 0.521 tINS RR 16 R22C29[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/n2619_s1/F
7.991 1.559 tNET RR 1 R31C32[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.596 1.914 tNET RR 1 R31C32[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_2_s0/CLK
12.285 -0.311 tSu 1 R31C32[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_coeff[0].spram_coeff_inst/mem[25]_2_s0

Path Statistics:

Clock Skew -0.021
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 26.074%; route: 1.935, 73.925%
Arrival Data Path Delay cell: 1.038, 19.307%; route: 3.954, 73.575%; tC2Q: 0.382, 7.118%
Required Clock Path Delay cell: 0.683, 26.288%; route: 1.914, 73.712%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.155
Data Arrival Time 1.567
Data Required Time 1.411
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_2_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.361 0.685 tNET RR 1 R30C40[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_2_s0/CLK
1.502 0.141 tC2Q RF 1 R30C40[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_2_s0/Q
1.567 0.065 tNET FF 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Path Statistics:

Clock Skew 0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.651%; route: 0.685, 50.349%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.065, 31.553%; tC2Q: 0.141, 68.447%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path2

Path Summary:

Slack 0.164
Data Arrival Time 1.576
Data Required Time 1.411
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_7_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R29C40[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_7_s0/CLK
1.510 0.141 tC2Q RF 1 R29C40[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_7_s0/Q
1.576 0.065 tNET FF 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.065, 31.553%; tC2Q: 0.141, 68.447%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path3

Path Summary:

Slack 0.189
Data Arrival Time 1.600
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.365 0.690 tNET RR 1 R11C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK
1.507 0.141 tC2Q RF 1 R11C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q
1.600 0.094 tNET FF 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path4

Path Summary:

Slack 0.189
Data Arrival Time 1.600
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.365 0.690 tNET RR 1 R11C27[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/CLK
1.507 0.141 tC2Q RF 1 R11C27[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q
1.600 0.094 tNET FF 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path5

Path Summary:

Slack 0.193
Data Arrival Time 1.609
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/CLK
1.515 0.141 tC2Q RF 1 R11C29[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q
1.609 0.094 tNET FF 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path6

Path Summary:

Slack 0.193
Data Arrival Time 1.609
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/CLK
1.515 0.141 tC2Q RF 1 R11C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q
1.609 0.094 tNET FF 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path7

Path Summary:

Slack 0.198
Data Arrival Time 1.610
Data Required Time 1.411
From sim_output_storage_inst/ram_din_addra_0_s0
To sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.365 0.690 tNET RR 1 R11C39[0][A] sim_output_storage_inst/ram_din_addra_0_s0/CLK
1.507 0.141 tC2Q RF 6 R11C39[0][A] sim_output_storage_inst/ram_din_addra_0_s0/Q
1.610 0.103 tNET FF 1 BSRAM_R10[11] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[11] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[11] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.103, 42.213%; tC2Q: 0.141, 57.787%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path8

Path Summary:

Slack 0.211
Data Arrival Time 1.622
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C26[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.523 0.144 tC2Q RR 5 R9C26[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.622 0.099 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path9

Path Summary:

Slack 0.212
Data Arrival Time 1.623
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.365 0.690 tNET RR 1 R11C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
1.507 0.141 tC2Q RF 1 R11C27[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
1.623 0.117 tNET FF 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path10

Path Summary:

Slack 0.212
Data Arrival Time 1.623
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.365 0.690 tNET RR 1 R11C27[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/CLK
1.507 0.141 tC2Q RF 1 R11C27[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q
1.623 0.117 tNET FF 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path11

Path Summary:

Slack 0.214
Data Arrival Time 1.625
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.523 0.144 tC2Q RR 5 R9C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.625 0.102 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.102, 41.463%; tC2Q: 0.144, 58.537%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path12

Path Summary:

Slack 0.216
Data Arrival Time 1.632
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.388 0.713 tNET RR 1 R8C29[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK
1.533 0.144 tC2Q RR 1 R8C29[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q
1.632 0.099 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.650%; route: 0.713, 51.350%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path13

Path Summary:

Slack 0.216
Data Arrival Time 1.632
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.388 0.713 tNET RR 1 R8C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/CLK
1.533 0.144 tC2Q RR 1 R8C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q
1.632 0.099 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.650%; route: 0.713, 51.350%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path14

Path Summary:

Slack 0.216
Data Arrival Time 1.632
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.388 0.713 tNET RR 1 R8C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/CLK
1.533 0.144 tC2Q RR 1 R8C29[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q
1.632 0.099 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.650%; route: 0.713, 51.350%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path15

Path Summary:

Slack 0.216
Data Arrival Time 1.632
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C29[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/CLK
1.515 0.141 tC2Q RF 1 R11C29[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q
1.632 0.117 tNET FF 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path16

Path Summary:

Slack 0.227
Data Arrival Time 1.638
Data Required Time 1.411
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_8_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R29C40[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_8_s0/CLK
1.510 0.141 tC2Q RF 1 R29C40[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_8_s0/Q
1.638 0.128 tNET FF 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 47.584%; tC2Q: 0.141, 52.416%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path17

Path Summary:

Slack 0.227
Data Arrival Time 1.638
Data Required Time 1.411
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_6_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R29C40[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_6_s0/CLK
1.510 0.141 tC2Q RF 1 R29C40[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_6_s0/Q
1.638 0.128 tNET FF 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 47.584%; tC2Q: 0.141, 52.416%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path18

Path Summary:

Slack 0.254
Data Arrival Time 1.665
Data Required Time 1.411
From sim_output_storage_inst/ram_din_addra_8_s0
To sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.356 0.681 tNET RR 1 R12C39[1][A] sim_output_storage_inst/ram_din_addra_8_s0/CLK
1.497 0.141 tC2Q RF 6 R12C39[1][A] sim_output_storage_inst/ram_din_addra_8_s0/Q
1.665 0.168 tNET FF 1 BSRAM_R10[11] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[11] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[11] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.018
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.797%; route: 0.681, 50.203%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.168, 54.369%; tC2Q: 0.141, 45.631%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path19

Path Summary:

Slack 0.254
Data Arrival Time 1.665
Data Required Time 1.411
From sim_output_storage_inst/ram_din_addra_4_s0
To sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.356 0.681 tNET RR 1 R12C39[2][B] sim_output_storage_inst/ram_din_addra_4_s0/CLK
1.497 0.141 tC2Q RF 5 R12C39[2][B] sim_output_storage_inst/ram_din_addra_4_s0/Q
1.665 0.168 tNET FF 1 BSRAM_R10[11] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADA[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[11] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[11] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.018
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.797%; route: 0.681, 50.203%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.168, 54.369%; tC2Q: 0.141, 45.631%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path20

Path Summary:

Slack 0.257
Data Arrival Time 1.670
Data Required Time 1.413
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/delay_shift_addrb_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R27C42[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/delay_shift_addrb_0_s0/CLK
1.523 0.144 tC2Q RR 129 R27C42[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/delay_shift_addrb_0_s0/Q
1.670 0.147 tNET RR 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/ADB[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKB
1.413 0.035 tHld 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.147, 50.515%; tC2Q: 0.144, 49.485%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path21

Path Summary:

Slack 0.257
Data Arrival Time 1.668
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/CLK
1.510 0.141 tC2Q RF 1 R11C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q
1.668 0.158 tNET FF 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path22

Path Summary:

Slack 0.257
Data Arrival Time 1.668
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/CLK
1.510 0.141 tC2Q RF 1 R11C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q
1.668 0.158 tNET FF 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path23

Path Summary:

Slack 0.259
Data Arrival Time 1.671
Data Required Time 1.411
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_15_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.361 0.685 tNET RR 1 R30C40[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_15_s0/CLK
1.502 0.141 tC2Q RF 1 R30C40[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_15_s0/Q
1.671 0.169 tNET FF 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Path Statistics:

Clock Skew 0.014
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.651%; route: 0.685, 50.349%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.169, 54.516%; tC2Q: 0.141, 45.484%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path24

Path Summary:

Slack 0.260
Data Arrival Time 1.671
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C26[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.523 0.144 tC2Q RR 8 R9C26[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
1.671 0.148 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[7] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.148, 50.685%; tC2Q: 0.144, 49.315%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path25

Path Summary:

Slack 0.263
Data Arrival Time 1.675
Data Required Time 1.411
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R31C40[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_1_s0/CLK
1.506 0.141 tC2Q RF 1 R31C40[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/ram_shift_din_1_s0/Q
1.675 0.169 tNET FF 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKA
1.411 0.037 tHld 1 BSRAM_R28[13] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Path Statistics:

Clock Skew 0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.169, 54.516%; tC2Q: 0.141, 45.484%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.840
Data Arrival Time 9.441
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.441 1.356 tNET FF 1 R6C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R6C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
12.281 -0.347 tSu 1 R6C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew -0.013
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.356, 75.400%; tC2Q: 0.442, 24.600%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path2

Path Summary:

Slack 2.840
Data Arrival Time 9.441
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.441 1.356 tNET FF 1 R6C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R6C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
12.281 -0.347 tSu 1 R6C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew -0.013
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.356, 75.400%; tC2Q: 0.442, 24.600%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path3

Path Summary:

Slack 3.042
Data Arrival Time 9.248
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.248 1.164 tNET FF 1 R6C26[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C26[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
12.291 -0.347 tSu 1 R6C26[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.164, 72.451%; tC2Q: 0.442, 27.549%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path4

Path Summary:

Slack 3.042
Data Arrival Time 9.248
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.248 1.164 tNET FF 1 R6C26[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C26[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
12.291 -0.347 tSu 1 R6C26[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.164, 72.451%; tC2Q: 0.442, 27.549%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path5

Path Summary:

Slack 3.042
Data Arrival Time 9.248
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.248 1.164 tNET FF 1 R6C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
12.291 -0.347 tSu 1 R6C26[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.164, 72.451%; tC2Q: 0.442, 27.549%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path6

Path Summary:

Slack 3.047
Data Arrival Time 9.227
Data Required Time 12.274
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C26[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R9C26[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
12.274 -0.347 tSu 1 R9C26[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew -0.021
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path7

Path Summary:

Slack 3.047
Data Arrival Time 9.227
Data Required Time 12.274
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R9C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
12.274 -0.347 tSu 1 R9C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew -0.021
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path8

Path Summary:

Slack 3.047
Data Arrival Time 9.227
Data Required Time 12.274
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R9C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
12.274 -0.347 tSu 1 R9C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew -0.021
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path9

Path Summary:

Slack 3.047
Data Arrival Time 9.227
Data Required Time 12.274
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C26[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R9C26[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
12.274 -0.347 tSu 1 R9C26[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew -0.021
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path10

Path Summary:

Slack 3.047
Data Arrival Time 9.227
Data Required Time 12.274
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R9C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
12.274 -0.347 tSu 1 R9C26[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew -0.021
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path11

Path Summary:

Slack 3.052
Data Arrival Time 9.248
Data Required Time 12.300
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.248 1.164 tNET FF 1 R6C25[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.648 1.965 tNET RR 1 R6C25[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
12.300 -0.347 tSu 1 R6C25[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.164, 72.451%; tC2Q: 0.442, 27.549%
Required Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%

Path12

Path Summary:

Slack 3.056
Data Arrival Time 9.227
Data Required Time 12.283
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C25[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.631 1.948 tNET RR 1 R9C25[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
12.283 -0.347 tSu 1 R9C25[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew -0.012
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 25.944%; route: 1.948, 74.056%

Path13

Path Summary:

Slack 3.056
Data Arrival Time 9.227
Data Required Time 12.283
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C25[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.631 1.948 tNET RR 1 R9C25[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
12.283 -0.347 tSu 1 R9C25[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew -0.012
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 25.944%; route: 1.948, 74.056%

Path14

Path Summary:

Slack 3.056
Data Arrival Time 9.227
Data Required Time 12.283
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C25[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.631 1.948 tNET RR 1 R9C25[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
12.283 -0.347 tSu 1 R9C25[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew -0.012
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 25.944%; route: 1.948, 74.056%

Path15

Path Summary:

Slack 3.056
Data Arrival Time 9.227
Data Required Time 12.283
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C25[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.631 1.948 tNET RR 1 R9C25[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
12.283 -0.347 tSu 1 R9C25[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew -0.012
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 25.944%; route: 1.948, 74.056%

Path16

Path Summary:

Slack 3.056
Data Arrival Time 9.227
Data Required Time 12.283
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.227 1.142 tNET FF 1 R9C25[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.631 1.948 tNET RR 1 R9C25[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
12.283 -0.347 tSu 1 R9C25[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew -0.012
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.142, 72.077%; tC2Q: 0.442, 27.923%
Required Clock Path Delay cell: 0.683, 25.944%; route: 1.948, 74.056%

Path17

Path Summary:

Slack 3.106
Data Arrival Time 9.185
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.185 1.100 tNET FF 1 R6C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.291 -0.347 tSu 1 R6C28[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.100, 71.313%; tC2Q: 0.442, 28.687%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path18

Path Summary:

Slack 3.106
Data Arrival Time 9.185
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.185 1.100 tNET FF 1 R6C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
12.291 -0.347 tSu 1 R6C28[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.100, 71.313%; tC2Q: 0.442, 28.687%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path19

Path Summary:

Slack 3.106
Data Arrival Time 9.185
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.185 1.100 tNET FF 1 R6C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
12.291 -0.347 tSu 1 R6C28[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.100, 71.313%; tC2Q: 0.442, 28.687%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path20

Path Summary:

Slack 3.106
Data Arrival Time 9.185
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.185 1.100 tNET FF 1 R6C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
12.291 -0.347 tSu 1 R6C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.100, 71.313%; tC2Q: 0.442, 28.687%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path21

Path Summary:

Slack 3.115
Data Arrival Time 9.185
Data Required Time 12.300
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.185 1.100 tNET FF 1 R6C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.648 1.965 tNET RR 1 R6C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
12.300 -0.347 tSu 1 R6C29[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.100, 71.313%; tC2Q: 0.442, 28.687%
Required Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%

Path22

Path Summary:

Slack 3.115
Data Arrival Time 9.185
Data Required Time 12.300
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.185 1.100 tNET FF 1 R6C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.648 1.965 tNET RR 1 R6C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
12.300 -0.347 tSu 1 R6C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.100, 71.313%; tC2Q: 0.442, 28.687%
Required Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%

Path23

Path Summary:

Slack 3.359
Data Arrival Time 8.922
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.922 0.837 tNET FF 1 R6C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R6C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
12.281 -0.347 tSu 1 R6C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew -0.013
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.837, 65.430%; tC2Q: 0.442, 34.570%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path24

Path Summary:

Slack 3.359
Data Arrival Time 8.922
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.922 0.837 tNET FF 1 R6C31[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R6C31[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
12.281 -0.347 tSu 1 R6C31[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -0.013
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.837, 65.430%; tC2Q: 0.442, 34.570%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path25

Path Summary:

Slack 3.359
Data Arrival Time 8.922
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 1607 IOB29[A] clk_ibuf/O
7.642 1.955 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.085 0.442 tC2Q FF 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.922 0.837 tNET FF 1 R6C31[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 1607 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R6C31[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
12.281 -0.347 tSu 1 R6C31[0][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew -0.013
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.020%; route: 1.955, 73.980%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.837, 65.430%; tC2Q: 0.442, 34.570%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 5.422
Data Arrival Time 6.760
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R6C34[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C34[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.338 -0.053 tHld 1 R6C34[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path2

Path Summary:

Slack 5.426
Data Arrival Time 6.760
Data Required Time 1.334
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R6C35[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.387 0.712 tNET RR 1 R6C35[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.334 -0.053 tHld 1 R6C35[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew -0.010
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.693%; route: 0.712, 51.307%

Path3

Path Summary:

Slack 5.426
Data Arrival Time 6.760
Data Required Time 1.334
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R6C35[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.387 0.712 tNET RR 1 R6C35[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.334 -0.053 tHld 1 R6C35[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew -0.010
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.693%; route: 0.712, 51.307%

Path4

Path Summary:

Slack 5.426
Data Arrival Time 6.760
Data Required Time 1.334
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R6C35[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.387 0.712 tNET RR 1 R6C35[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.334 -0.053 tHld 1 R6C35[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew -0.010
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.693%; route: 0.712, 51.307%

Path5

Path Summary:

Slack 5.426
Data Arrival Time 6.760
Data Required Time 1.334
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R6C35[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.387 0.712 tNET RR 1 R6C35[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.334 -0.053 tHld 1 R6C35[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew -0.010
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.693%; route: 0.712, 51.307%

Path6

Path Summary:

Slack 5.426
Data Arrival Time 6.760
Data Required Time 1.334
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R6C35[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.387 0.712 tNET RR 1 R6C35[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.334 -0.053 tHld 1 R6C35[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew -0.010
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.693%; route: 0.712, 51.307%

Path7

Path Summary:

Slack 5.429
Data Arrival Time 6.760
Data Required Time 1.332
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R8C36[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.385 0.709 tNET RR 1 R8C36[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
1.332 -0.053 tHld 1 R8C36[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.790%; route: 0.709, 51.210%

Path8

Path Summary:

Slack 5.429
Data Arrival Time 6.760
Data Required Time 1.332
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R8C36[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.385 0.709 tNET RR 1 R8C36[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
1.332 -0.053 tHld 1 R8C36[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.790%; route: 0.709, 51.210%

Path9

Path Summary:

Slack 5.429
Data Arrival Time 6.760
Data Required Time 1.332
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R8C36[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.385 0.709 tNET RR 1 R8C36[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
1.332 -0.053 tHld 1 R8C36[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.790%; route: 0.709, 51.210%

Path10

Path Summary:

Slack 5.429
Data Arrival Time 6.760
Data Required Time 1.332
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R8C36[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.385 0.709 tNET RR 1 R8C36[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.332 -0.053 tHld 1 R8C36[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.790%; route: 0.709, 51.210%

Path11

Path Summary:

Slack 5.434
Data Arrival Time 6.760
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R9C36[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C36[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
1.326 -0.053 tHld 1 R9C36[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew -0.018
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path12

Path Summary:

Slack 5.434
Data Arrival Time 6.760
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R9C36[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C36[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
1.326 -0.053 tHld 1 R9C36[1][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew -0.018
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path13

Path Summary:

Slack 5.434
Data Arrival Time 6.760
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R9C36[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C36[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
1.326 -0.053 tHld 1 R9C36[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew -0.018
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path14

Path Summary:

Slack 5.434
Data Arrival Time 6.760
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R9C36[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C36[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
1.326 -0.053 tHld 1 R9C36[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew -0.018
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path15

Path Summary:

Slack 5.434
Data Arrival Time 6.760
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.760 0.205 tNET RR 1 R9C36[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C36[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.326 -0.053 tHld 1 R9C36[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew -0.018
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.205, 56.474%; tC2Q: 0.158, 43.526%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path16

Path Summary:

Slack 5.526
Data Arrival Time 6.865
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.865 0.309 tNET RR 1 R6C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
1.338 -0.053 tHld 1 R6C32[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path17

Path Summary:

Slack 5.526
Data Arrival Time 6.865
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.865 0.309 tNET RR 1 R6C32[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C32[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.338 -0.053 tHld 1 R6C32[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path18

Path Summary:

Slack 5.526
Data Arrival Time 6.865
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.865 0.309 tNET RR 1 R6C32[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C32[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
1.338 -0.053 tHld 1 R6C32[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path19

Path Summary:

Slack 5.526
Data Arrival Time 6.865
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.865 0.309 tNET RR 1 R6C32[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C32[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
1.338 -0.053 tHld 1 R6C32[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path20

Path Summary:

Slack 5.526
Data Arrival Time 6.865
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.865 0.309 tNET RR 1 R6C32[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C32[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.338 -0.053 tHld 1 R6C32[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path21

Path Summary:

Slack 5.526
Data Arrival Time 6.865
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.865 0.309 tNET RR 1 R6C32[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C32[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.338 -0.053 tHld 1 R6C32[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 66.167%; tC2Q: 0.158, 33.833%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path22

Path Summary:

Slack 5.578
Data Arrival Time 6.921
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.920 0.365 tNET RR 1 R6C25[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.395 0.720 tNET RR 1 R6C25[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
1.342 -0.053 tHld 1 R6C25[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew -0.002
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.365, 69.790%; tC2Q: 0.158, 30.210%
Required Clock Path Delay cell: 0.675, 48.414%; route: 0.720, 51.586%

Path23

Path Summary:

Slack 5.582
Data Arrival Time 6.920
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.920 0.365 tNET RR 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
1.338 -0.053 tHld 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.365, 69.790%; tC2Q: 0.158, 30.210%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path24

Path Summary:

Slack 5.630
Data Arrival Time 6.969
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.969 0.413 tNET RR 1 R6C30[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C30[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.338 -0.053 tHld 1 R6C30[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.413, 72.329%; tC2Q: 0.158, 27.671%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path25

Path Summary:

Slack 5.634
Data Arrival Time 6.969
Data Required Time 1.334
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 1607 IOB29[A] clk_ibuf/O
6.398 0.720 tNET FF 1 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.556 0.158 tC2Q FR 53 R6C36[1][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.969 0.413 tNET RR 1 R6C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 1607 IOB29[A] clk_ibuf/O
1.387 0.712 tNET RR 1 R6C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.334 -0.053 tHld 1 R6C31[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew -0.010
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.413, 72.329%; tC2Q: 0.158, 27.671%
Required Clock Path Delay cell: 0.675, 48.693%; route: 0.712, 51.307%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.751
Actual Width: 3.751
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.627 1.940 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.703 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW2

MPW Summary:

Slack: 2.751
Actual Width: 3.751
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.627 1.940 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.703 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKB

MPW3

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW4

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA

MPW5

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKA

MPW6

MPW Summary:

Slack: 2.759
Actual Width: 3.759
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.931 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.702 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

MPW7

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.623 1.941 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.385 0.708 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW8

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.623 1.941 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.385 0.708 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_singlerate_inst/gen_spram_shift[0].spram_shift_inst/ram_shift_dout[0]_ram_shift_dout[0]_0_0_s/CLKB

MPW9

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.608 1.921 tNET FF sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.371 0.695 tNET RR sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB

MPW10

MPW Summary:

Slack: 2.767
Actual Width: 3.767
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.614 1.932 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.381 0.704 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
1607 clk_d 3.163 1.982
257 coeff_ram_addrb[0] 5.724 2.029
225 control0[0] 3.601 2.741
129 delay_shift_addrb[0] 4.294 1.194
129 coeff_ram_addrb[1] 5.775 2.522
67 ram_data_addrb[0] 7.280 1.661
65 delay_shift_addrb[1] 4.888 1.370
64 coeff_ram_addrb[2] 5.319 3.049
53 rst_ao 2.840 1.369
46 n20_3 46.748 1.146

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R30C42 45.83%
R27C36 44.44%
R27C38 44.44%
R8C31 43.06%
R29C41 43.06%
R9C26 43.06%
R10C27 43.06%
R10C29 43.06%
R24C32 43.06%
R8C30 41.67%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]