Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\6_fir_halfband\151taps_2chn_19tdm_halfband_decimator_16bit\proj\impl\gwsynthesis\fir_proj.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\6_fir_halfband\151taps_2chn_19tdm_halfband_decimator_16bit\proj\src\fir_proj.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\6_fir_halfband\151taps_2chn_19tdm_halfband_decimator_16bit\proj\src\fir_proj.sdc
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Dec 25 13:11:14 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 17987
Numbers of Endpoints Analyzed 18704
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk Base 10.000 100.000 0.000 5.000 clk
2 tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 112.320(MHz) 4 TOP
2 tck_pad_i 20.000(MHz) 168.199(MHz) 5 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.097 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_3_s0/CE clk:[R] clk:[R] 10.000 -0.009 8.601
2 1.243 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_13_s0/CE clk:[R] clk:[R] 10.000 0.000 8.446
3 1.243 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_3_s0/CE clk:[R] clk:[R] 10.000 0.000 8.446
4 1.308 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[8]_4_s0/CE clk:[R] clk:[R] 10.000 0.000 8.381
5 1.421 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_14_s0/CE clk:[R] clk:[R] 10.000 0.012 8.256
6 1.525 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_10_s0/CE clk:[R] clk:[R] 10.000 0.034 8.130
7 1.525 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_11_s0/CE clk:[R] clk:[R] 10.000 0.034 8.130
8 1.525 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_15_s0/CE clk:[R] clk:[R] 10.000 0.034 8.130
9 1.534 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_7_s0/CE clk:[R] clk:[R] 10.000 0.036 8.119
10 1.534 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_8_s0/CE clk:[R] clk:[R] 10.000 0.036 8.119
11 1.549 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[34]_12_s0/CE clk:[R] clk:[R] 10.000 0.005 8.135
12 1.573 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_11_s0/CE clk:[R] clk:[R] 10.000 0.012 8.104
13 1.573 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_10_s0/CE clk:[R] clk:[R] 10.000 0.012 8.104
14 1.580 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_13_s0/CE clk:[R] clk:[R] 10.000 0.008 8.101
15 1.586 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_5_s0/CE clk:[R] clk:[R] 10.000 0.012 8.091
16 1.586 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_13_s0/CE clk:[R] clk:[R] 10.000 0.012 8.091
17 1.599 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_6_s0/CE clk:[R] clk:[R] 10.000 0.034 8.056
18 1.599 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_11_s0/CE clk:[R] clk:[R] 10.000 0.034 8.056
19 1.599 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_15_s0/CE clk:[R] clk:[R] 10.000 0.034 8.056
20 1.601 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addrb_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_12_s0/D clk:[R] clk:[R] 10.000 0.000 8.335
21 1.605 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_8_s0/CE clk:[R] clk:[R] 10.000 0.005 8.079
22 1.615 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_4_s0/CE clk:[R] clk:[R] 10.000 0.003 8.071
23 1.650 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[26]_8_s0/CE clk:[R] clk:[R] 10.000 0.008 8.031
24 1.653 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addrb_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_7_s0/D clk:[R] clk:[R] 10.000 0.043 8.240
25 1.657 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_1_s0/CE clk:[R] clk:[R] 10.000 0.044 7.988

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.213 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[9] clk:[R] clk:[R] 0.000 0.005 0.245
2 0.214 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[5] clk:[R] clk:[R] 0.000 0.001 0.250
3 0.221 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] clk:[R] clk:[R] 0.000 0.013 0.245
4 0.249 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9] clk:[R] clk:[R] 0.000 -0.013 0.299
5 0.251 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[7] clk:[R] clk:[R] 0.000 0.001 0.287
6 0.252 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2] clk:[R] clk:[R] 0.000 0.010 0.279
7 0.257 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[8] clk:[R] clk:[R] 0.000 0.001 0.293
8 0.275 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_22_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/D clk:[R] clk:[R] 0.000 0.000 0.222
9 0.275 gw_gao_inst_0/u_la0_top/word_count_4_s0/Q gw_gao_inst_0/u_la0_top/word_count_4_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
10 0.275 sim_output_storage_inst/ram_din_addra_1_s0/Q sim_output_storage_inst/ram_din_addra_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.300
11 0.275 sim_input_gen_inst/cnt_cycle_3_s1/Q sim_input_gen_inst/cnt_cycle_3_s1/D clk:[R] clk:[R] 0.000 0.000 0.300
12 0.275 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_0_s1/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_0_s1/D clk:[R] clk:[R] 0.000 0.000 0.300
13 0.275 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_4_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_4_s0/D clk:[R] clk:[R] 0.000 0.000 0.300
14 0.275 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/ram_shift_addra_start_5_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/ram_shift_addra_start_5_s0/D clk:[R] clk:[R] 0.000 0.000 0.300
15 0.275 gw_gao_inst_0/u_la0_top/word_count_7_s0/Q gw_gao_inst_0/u_la0_top/word_count_7_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
16 0.275 gw_gao_inst_0/u_la0_top/word_count_8_s0/Q gw_gao_inst_0/u_la0_top/word_count_8_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
17 0.278 gw_gao_inst_0/u_la0_top/bit_count_3_s1/Q gw_gao_inst_0/u_la0_top/bit_count_3_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
18 0.278 gw_gao_inst_0/u_la0_top/address_counter_6_s0/Q gw_gao_inst_0/u_la0_top/address_counter_6_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
19 0.278 gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q gw_gao_inst_0/u_la0_top/address_counter_8_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
20 0.278 sim_output_storage_inst/ram_din_addra_2_s0/Q sim_output_storage_inst/ram_din_addra_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
21 0.278 sim_input_gen_inst/cnt_cycle_4_s1/Q sim_input_gen_inst/cnt_cycle_4_s1/D clk:[R] clk:[R] 0.000 0.000 0.303
22 0.278 sim_input_gen_inst/cnt_cycle_1_s1/Q sim_input_gen_inst/cnt_cycle_1_s1/D clk:[R] clk:[R] 0.000 0.000 0.303
23 0.278 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_factor_0_s2/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_factor_0_s2/D clk:[R] clk:[R] 0.000 0.000 0.303
24 0.278 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_index_cnt_0_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_index_cnt_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
25 0.278 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_ram_addra_1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_ram_addra_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.303

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.904 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR clk:[F] clk:[R] 5.000 -0.022 1.770
2 2.912 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR clk:[F] clk:[R] 5.000 -0.029 1.770
3 3.091 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR clk:[F] clk:[R] 5.000 -0.024 1.586
4 3.091 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR clk:[F] clk:[R] 5.000 -0.024 1.586
5 3.091 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR clk:[F] clk:[R] 5.000 -0.024 1.586
6 3.091 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR clk:[F] clk:[R] 5.000 -0.024 1.586
7 3.102 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR clk:[F] clk:[R] 5.000 -0.036 1.586
8 3.102 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR clk:[F] clk:[R] 5.000 -0.036 1.586
9 3.102 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR clk:[F] clk:[R] 5.000 -0.036 1.586
10 3.146 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR clk:[F] clk:[R] 5.000 0.006 1.500
11 3.146 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR clk:[F] clk:[R] 5.000 0.006 1.500
12 3.146 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR clk:[F] clk:[R] 5.000 0.006 1.500
13 3.146 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR clk:[F] clk:[R] 5.000 0.006 1.500
14 3.146 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR clk:[F] clk:[R] 5.000 0.006 1.500
15 3.148 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR clk:[F] clk:[R] 5.000 0.004 1.500
16 3.260 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR clk:[F] clk:[R] 5.000 -0.041 1.434
17 3.260 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR clk:[F] clk:[R] 5.000 -0.041 1.434
18 3.260 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR clk:[F] clk:[R] 5.000 -0.041 1.434
19 3.310 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR clk:[F] clk:[R] 5.000 -0.034 1.376
20 3.360 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR clk:[F] clk:[R] 5.000 0.003 1.290
21 3.369 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR clk:[F] clk:[R] 5.000 -0.007 1.290
22 3.369 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR clk:[F] clk:[R] 5.000 -0.007 1.290
23 3.369 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR clk:[F] clk:[R] 5.000 -0.007 1.290
24 3.369 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR clk:[F] clk:[R] 5.000 -0.007 1.290
25 3.410 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR clk:[F] clk:[R] 5.000 0.020 1.222

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 5.397 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR clk:[F] clk:[R] -5.000 0.003 0.341
2 5.497 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR clk:[F] clk:[R] -5.000 -0.002 0.445
3 5.497 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR clk:[F] clk:[R] -5.000 -0.002 0.445
4 5.497 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR clk:[F] clk:[R] -5.000 -0.002 0.445
5 5.501 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR clk:[F] clk:[R] -5.000 0.003 0.445
6 5.501 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR clk:[F] clk:[R] -5.000 0.003 0.445
7 5.501 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR clk:[F] clk:[R] -5.000 0.003 0.445
8 5.501 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR clk:[F] clk:[R] -5.000 0.003 0.445
9 5.501 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR clk:[F] clk:[R] -5.000 0.003 0.445
10 5.547 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.006 0.488
11 5.589 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR clk:[F] clk:[R] -5.000 0.008 0.527
12 5.589 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.008 0.527
13 5.589 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.008 0.527
14 5.589 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.008 0.527
15 5.592 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET clk:[F] clk:[R] -5.000 0.013 0.527
16 5.592 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR clk:[F] clk:[R] -5.000 0.013 0.527
17 5.592 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR clk:[F] clk:[R] -5.000 0.013 0.527
18 5.592 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR clk:[F] clk:[R] -5.000 0.013 0.527
19 5.592 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR clk:[F] clk:[R] -5.000 0.013 0.527
20 5.593 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR clk:[F] clk:[R] -5.000 -0.007 0.547
21 5.593 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET clk:[F] clk:[R] -5.000 -0.007 0.547
22 5.597 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR clk:[F] clk:[R] -5.000 -0.002 0.547
23 5.597 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR clk:[F] clk:[R] -5.000 -0.002 0.547
24 5.597 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR clk:[F] clk:[R] -5.000 -0.002 0.547
25 5.647 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR clk:[F] clk:[R] -5.000 0.002 0.592

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.751 3.751 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
2 2.751 3.751 1.000 Low Pulse Width clk sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
3 2.754 3.754 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[1].mult_dsp_inst/n47_s1
4 2.757 3.757 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
5 2.757 3.757 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_rom_inst/mem_mem_0_0_s
6 2.757 3.757 1.000 Low Pulse Width clk sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
7 2.759 3.759 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1
8 2.762 3.762 1.000 High Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
9 2.762 3.762 1.000 High Pulse Width clk sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
10 2.762 3.762 1.000 High Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[1].mult_dsp_inst/n47_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.097
Data Arrival Time 11.247
Data Required Time 12.344
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.339 0.492 tNET RR 1 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/I0
8.801 0.461 tINS RR 16 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/F
11.247 2.446 tNET RR 1 R21C29[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.655 1.972 tNET RR 1 R21C29[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_3_s0/CLK
12.344 -0.311 tSu 1 R21C29[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_3_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.514, 17.599%; route: 6.705, 77.954%; tC2Q: 0.382, 4.447%
Required Clock Path Delay cell: 0.683, 25.706%; route: 1.972, 74.294%

Path2

Path Summary:

Slack 1.243
Data Arrival Time 11.092
Data Required Time 12.334
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.202 0.355 tNET RR 1 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/I0
8.718 0.516 tINS RR 16 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/F
11.092 2.374 tNET RR 1 R21C30[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R21C30[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_13_s0/CLK
12.334 -0.311 tSu 1 R21C30[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.569, 18.573%; route: 6.495, 76.898%; tC2Q: 0.382, 4.529%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path3

Path Summary:

Slack 1.243
Data Arrival Time 11.092
Data Required Time 12.334
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.202 0.355 tNET RR 1 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/I0
8.718 0.516 tINS RR 16 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/F
11.092 2.374 tNET RR 1 R21C30[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R21C30[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_3_s0/CLK
12.334 -0.311 tSu 1 R21C30[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.569, 18.573%; route: 6.495, 76.898%; tC2Q: 0.382, 4.529%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path4

Path Summary:

Slack 1.308
Data Arrival Time 11.027
Data Required Time 12.334
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[8]_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.009 0.162 tNET RR 1 R6C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2763_s2/I0
8.526 0.516 tINS RR 16 R6C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2763_s2/F
11.027 2.501 tNET RR 1 R21C40[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[8]_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R21C40[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[8]_4_s0/CLK
12.334 -0.311 tSu 1 R21C40[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[8]_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.569, 18.717%; route: 6.430, 76.719%; tC2Q: 0.382, 4.564%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path5

Path Summary:

Slack 1.421
Data Arrival Time 10.899
Data Required Time 12.320
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.643 1.961 tNET RR 1 R22C24[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0/CLK
3.026 0.382 tC2Q RR 81 R22C24[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0/Q
6.113 3.088 tNET RR 1 R12C51[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[2].spram_shift_inst/n2907_s1/I2
6.634 0.521 tINS RR 32 R12C51[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[2].spram_shift_inst/n2907_s1/F
10.899 4.265 tNET RR 1 R5C67[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.631 1.949 tNET RR 1 R5C67[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_14_s0/CLK
12.320 -0.311 tSu 1 R5C67[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_14_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 25.822%; route: 1.961, 74.178%
Arrival Data Path Delay cell: 0.521, 6.313%; route: 7.353, 89.054%; tC2Q: 0.382, 4.633%
Required Clock Path Delay cell: 0.683, 25.938%; route: 1.949, 74.062%

Path6

Path Summary:

Slack 1.525
Data Arrival Time 10.776
Data Required Time 12.300
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.339 0.492 tNET RR 1 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/I0
8.801 0.461 tINS RR 16 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/F
10.776 1.975 tNET RR 1 R14C29[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R14C29[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_10_s0/CLK
12.300 -0.311 tSu 1 R14C29[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_10_s0

Path Statistics:

Clock Skew -0.034
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.514, 18.619%; route: 6.234, 76.676%; tC2Q: 0.382, 4.705%
Required Clock Path Delay cell: 0.683, 26.134%; route: 1.929, 73.866%

Path7

Path Summary:

Slack 1.525
Data Arrival Time 10.776
Data Required Time 12.300
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.339 0.492 tNET RR 1 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/I0
8.801 0.461 tINS RR 16 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/F
10.776 1.975 tNET RR 1 R14C29[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_11_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R14C29[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_11_s0/CLK
12.300 -0.311 tSu 1 R14C29[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_11_s0

Path Statistics:

Clock Skew -0.034
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.514, 18.619%; route: 6.234, 76.676%; tC2Q: 0.382, 4.705%
Required Clock Path Delay cell: 0.683, 26.134%; route: 1.929, 73.866%

Path8

Path Summary:

Slack 1.525
Data Arrival Time 10.776
Data Required Time 12.300
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.339 0.492 tNET RR 1 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/I0
8.801 0.461 tINS RR 16 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/F
10.776 1.975 tNET RR 1 R14C29[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_15_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R14C29[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_15_s0/CLK
12.300 -0.311 tSu 1 R14C29[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_15_s0

Path Statistics:

Clock Skew -0.034
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.514, 18.619%; route: 6.234, 76.676%; tC2Q: 0.382, 4.705%
Required Clock Path Delay cell: 0.683, 26.134%; route: 1.929, 73.866%

Path9

Path Summary:

Slack 1.534
Data Arrival Time 10.764
Data Required Time 12.299
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_7_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.339 0.492 tNET RR 1 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/I0
8.801 0.461 tINS RR 16 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/F
10.764 1.964 tNET RR 1 R16C40[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_7_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R16C40[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_7_s0/CLK
12.299 -0.311 tSu 1 R16C40[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_7_s0

Path Statistics:

Clock Skew -0.036
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.514, 18.645%; route: 6.222, 76.644%; tC2Q: 0.382, 4.711%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path10

Path Summary:

Slack 1.534
Data Arrival Time 10.764
Data Required Time 12.299
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.339 0.492 tNET RR 1 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/I0
8.801 0.461 tINS RR 16 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/F
10.764 1.964 tNET RR 1 R16C40[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R16C40[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_8_s0/CLK
12.299 -0.311 tSu 1 R16C40[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_8_s0

Path Statistics:

Clock Skew -0.036
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.514, 18.645%; route: 6.222, 76.644%; tC2Q: 0.382, 4.711%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path11

Path Summary:

Slack 1.549
Data Arrival Time 10.781
Data Required Time 12.329
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[34]_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/CLK
3.028 0.382 tC2Q RR 8 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q
5.718 2.690 tNET RR 1 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/I1
6.234 0.516 tINS RR 8 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/F
7.014 0.780 tNET RR 1 R32C24[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2667_s2/I0
7.531 0.516 tINS RR 5 R32C24[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2667_s2/F
7.886 0.355 tNET RR 1 R33C23[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n3179_s1/I0
8.347 0.461 tINS RR 16 R33C23[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n3179_s1/F
10.781 2.434 tNET RR 1 R23C22[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[34]_12_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R23C22[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[34]_12_s0/CLK
12.329 -0.311 tSu 1 R23C22[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[34]_12_s0

Path Statistics:

Clock Skew -0.005
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.494, 18.362%; route: 6.259, 76.936%; tC2Q: 0.382, 4.702%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path12

Path Summary:

Slack 1.573
Data Arrival Time 10.749
Data Required Time 12.323
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/CLK
3.028 0.382 tC2Q RR 8 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q
5.718 2.690 tNET RR 1 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/I1
6.234 0.516 tINS RR 8 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/F
7.014 0.780 tNET RR 1 R32C24[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s4/I0
7.531 0.516 tINS RR 5 R32C24[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s4/F
7.693 0.162 tNET RR 1 R32C23[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2891_s2/I0
8.219 0.526 tINS RR 16 R32C23[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2891_s2/F
10.749 2.530 tNET RR 1 R22C19[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_11_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.634 1.951 tNET RR 1 R22C19[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_11_s0/CLK
12.323 -0.311 tSu 1 R22C19[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_11_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.559, 19.235%; route: 6.162, 76.045%; tC2Q: 0.382, 4.720%
Required Clock Path Delay cell: 0.683, 25.914%; route: 1.951, 74.086%

Path13

Path Summary:

Slack 1.573
Data Arrival Time 10.749
Data Required Time 12.323
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/CLK
3.028 0.382 tC2Q RR 8 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q
5.718 2.690 tNET RR 1 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/I1
6.234 0.516 tINS RR 8 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/F
7.014 0.780 tNET RR 1 R32C24[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s4/I0
7.531 0.516 tINS RR 5 R32C24[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s4/F
7.693 0.162 tNET RR 1 R32C23[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2891_s2/I0
8.219 0.526 tINS RR 16 R32C23[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2891_s2/F
10.749 2.530 tNET RR 1 R22C19[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.634 1.951 tNET RR 1 R22C19[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_10_s0/CLK
12.323 -0.311 tSu 1 R22C19[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_10_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.559, 19.235%; route: 6.162, 76.045%; tC2Q: 0.382, 4.720%
Required Clock Path Delay cell: 0.683, 25.914%; route: 1.951, 74.086%

Path14

Path Summary:

Slack 1.580
Data Arrival Time 10.744
Data Required Time 12.324
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.643 1.961 tNET RR 1 R22C24[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0/CLK
3.026 0.382 tC2Q RR 81 R22C24[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0/Q
6.113 3.088 tNET RR 1 R12C51[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[2].spram_shift_inst/n2907_s1/I2
6.634 0.521 tINS RR 32 R12C51[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[2].spram_shift_inst/n2907_s1/F
10.744 4.110 tNET RR 1 R7C68[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.636 1.953 tNET RR 1 R7C68[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_13_s0/CLK
12.324 -0.311 tSu 1 R7C68[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_13_s0

Path Statistics:

Clock Skew -0.008
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 25.822%; route: 1.961, 74.178%
Arrival Data Path Delay cell: 0.521, 6.434%; route: 7.198, 88.844%; tC2Q: 0.382, 4.721%
Required Clock Path Delay cell: 0.683, 25.895%; route: 1.953, 74.105%

Path15

Path Summary:

Slack 1.586
Data Arrival Time 10.737
Data Required Time 12.323
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.339 0.492 tNET RR 1 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/I0
8.801 0.461 tINS RR 16 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/F
10.737 1.936 tNET RR 1 R22C35[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.634 1.951 tNET RR 1 R22C35[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_5_s0/CLK
12.323 -0.311 tSu 1 R22C35[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_5_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.514, 18.708%; route: 6.195, 76.564%; tC2Q: 0.382, 4.727%
Required Clock Path Delay cell: 0.683, 25.914%; route: 1.951, 74.086%

Path16

Path Summary:

Slack 1.586
Data Arrival Time 10.737
Data Required Time 12.323
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.339 0.492 tNET RR 1 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/I0
8.801 0.461 tINS RR 16 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/F
10.737 1.936 tNET RR 1 R22C35[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.634 1.951 tNET RR 1 R22C35[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_13_s0/CLK
12.323 -0.311 tSu 1 R22C35[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_13_s0

Path Statistics:

Clock Skew -0.012
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.514, 18.708%; route: 6.195, 76.564%; tC2Q: 0.382, 4.727%
Required Clock Path Delay cell: 0.683, 25.914%; route: 1.951, 74.086%

Path17

Path Summary:

Slack 1.599
Data Arrival Time 10.702
Data Required Time 12.301
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.202 0.355 tNET RR 1 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/I0
8.718 0.516 tINS RR 16 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/F
10.702 1.984 tNET RR 1 R17C30[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R17C30[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_6_s0/CLK
12.301 -0.311 tSu 1 R17C30[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_6_s0

Path Statistics:

Clock Skew -0.034
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.569, 19.472%; route: 6.105, 75.780%; tC2Q: 0.382, 4.748%
Required Clock Path Delay cell: 0.683, 26.131%; route: 1.929, 73.869%

Path18

Path Summary:

Slack 1.599
Data Arrival Time 10.702
Data Required Time 12.301
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.202 0.355 tNET RR 1 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/I0
8.718 0.516 tINS RR 16 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/F
10.702 1.984 tNET RR 1 R17C30[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_11_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R17C30[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_11_s0/CLK
12.301 -0.311 tSu 1 R17C30[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_11_s0

Path Statistics:

Clock Skew -0.034
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.569, 19.472%; route: 6.105, 75.780%; tC2Q: 0.382, 4.748%
Required Clock Path Delay cell: 0.683, 26.131%; route: 1.929, 73.869%

Path19

Path Summary:

Slack 1.599
Data Arrival Time 10.702
Data Required Time 12.301
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.202 0.355 tNET RR 1 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/I0
8.718 0.516 tINS RR 16 R5C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n3019_s2/F
10.702 1.984 tNET RR 1 R17C30[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_15_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R17C30[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_15_s0/CLK
12.301 -0.311 tSu 1 R17C30[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[24]_15_s0

Path Statistics:

Clock Skew -0.034
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.569, 19.472%; route: 6.105, 75.780%; tC2Q: 0.382, 4.748%
Required Clock Path Delay cell: 0.683, 26.131%; route: 1.929, 73.869%

Path20

Path Summary:

Slack 1.601
Data Arrival Time 10.978
Data Required Time 12.579
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addrb_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.643 1.961 tNET RR 1 R22C54[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addrb_3_s0/CLK
3.026 0.382 tC2Q RR 130 R22C54[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addrb_3_s0/Q
5.804 2.779 tNET RR 1 R36C61[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[0].spram_shift_inst/n1930_s192/I0
6.331 0.526 tINS RR 64 R36C61[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[0].spram_shift_inst/n1930_s192/F
10.452 4.121 tNET RR 1 R22C24[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n1933_s190/I1
10.978 0.526 tINS RR 1 R22C24[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n1933_s190/F
10.978 0.000 tNET RR 1 R22C24[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.643 1.961 tNET RR 1 R22C24[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_12_s0/CLK
12.579 -0.064 tSu 1 R22C24[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.822%; route: 1.961, 74.178%
Arrival Data Path Delay cell: 1.053, 12.627%; route: 6.900, 82.783%; tC2Q: 0.382, 4.589%
Required Clock Path Delay cell: 0.683, 25.822%; route: 1.961, 74.178%

Path21

Path Summary:

Slack 1.605
Data Arrival Time 10.724
Data Required Time 12.329
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/CLK
3.028 0.382 tC2Q RR 8 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q
5.718 2.690 tNET RR 1 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/I1
6.234 0.516 tINS RR 8 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/F
7.014 0.780 tNET RR 1 R32C24[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s4/I0
7.531 0.516 tINS RR 5 R32C24[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s4/F
7.693 0.162 tNET RR 1 R32C23[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2891_s2/I0
8.219 0.526 tINS RR 16 R32C23[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2891_s2/F
10.724 2.505 tNET RR 1 R23C14[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R23C14[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_8_s0/CLK
12.329 -0.311 tSu 1 R23C14[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[16]_8_s0

Path Statistics:

Clock Skew -0.005
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.559, 19.294%; route: 6.137, 75.971%; tC2Q: 0.382, 4.735%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path22

Path Summary:

Slack 1.615
Data Arrival Time 10.717
Data Required Time 12.332
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/CLK
3.028 0.382 tC2Q RR 13 R21C48[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_load_flag_s0/Q
5.217 2.189 tNET RR 1 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/I2
5.743 0.526 tINS RR 8 R11C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s3/F
7.321 1.577 tNET RR 1 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/I0
7.847 0.526 tINS RR 5 R7C33[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s4/F
8.339 0.492 tNET RR 1 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/I0
8.801 0.461 tINS RR 16 R4C33[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/n2636_s5/F
10.717 1.916 tNET RR 1 R22C40[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.643 1.961 tNET RR 1 R22C40[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_4_s0/CLK
12.332 -0.311 tSu 1 R22C40[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_coeff[0].spram_coeff_inst/mem[0]_4_s0

Path Statistics:

Clock Skew -0.003
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.514, 18.755%; route: 6.175, 76.506%; tC2Q: 0.382, 4.739%
Required Clock Path Delay cell: 0.683, 25.822%; route: 1.961, 74.178%

Path23

Path Summary:

Slack 1.650
Data Arrival Time 10.677
Data Required Time 12.327
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[26]_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.646 1.963 tNET RR 1 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/CLK
3.028 0.382 tC2Q RR 8 R21C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_d3_1_s0/Q
5.718 2.690 tNET RR 1 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/I1
6.234 0.516 tINS RR 8 R29C27[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2636_s3/F
7.014 0.780 tNET RR 1 R32C24[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2667_s2/I0
7.531 0.516 tINS RR 5 R32C24[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n2667_s2/F
8.213 0.683 tNET RR 1 R33C21[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n3051_s1/I0
8.729 0.516 tINS RR 16 R33C21[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n3051_s1/F
10.677 1.947 tNET RR 1 R26C13[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[26]_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.638 1.955 tNET RR 1 R26C13[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[26]_8_s0/CLK
12.327 -0.311 tSu 1 R26C13[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/mem[26]_8_s0

Path Statistics:

Clock Skew -0.008
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%
Arrival Data Path Delay cell: 1.549, 19.284%; route: 6.100, 75.953%; tC2Q: 0.382, 4.763%
Required Clock Path Delay cell: 0.683, 25.874%; route: 1.955, 74.126%

Path24

Path Summary:

Slack 1.653
Data Arrival Time 10.883
Data Required Time 12.536
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addrb_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_7_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.643 1.961 tNET RR 1 R22C54[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addrb_3_s0/CLK
3.026 0.382 tC2Q RR 130 R22C54[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addrb_3_s0/Q
5.804 2.779 tNET RR 1 R36C61[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[0].spram_shift_inst/n1930_s192/I0
6.331 0.526 tINS RR 64 R36C61[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[0].spram_shift_inst/n1930_s192/F
10.422 4.091 tNET RR 1 R30C13[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n1938_s190/I1
10.883 0.461 tINS RR 1 R30C13[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/n1938_s190/F
10.883 0.000 tNET RR 1 R30C13[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.600 1.917 tNET RR 1 R30C13[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_7_s0/CLK
12.536 -0.064 tSu 1 R30C13[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[1].spram_shift_inst/data_b_o_7_s0

Path Statistics:

Clock Skew -0.043
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.822%; route: 1.961, 74.178%
Arrival Data Path Delay cell: 0.987, 11.984%; route: 6.870, 83.374%; tC2Q: 0.382, 4.642%
Required Clock Path Delay cell: 0.683, 26.253%; route: 1.917, 73.747%

Path25

Path Summary:

Slack 1.657
Data Arrival Time 10.631
Data Required Time 12.288
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
2.643 1.961 tNET RR 1 R22C24[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0/CLK
3.026 0.382 tC2Q RR 81 R22C24[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/delay_shift_addra_5_s0/Q
6.113 3.088 tNET RR 1 R12C51[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[2].spram_shift_inst/n2907_s1/I2
6.634 0.521 tINS RR 32 R12C51[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[2].spram_shift_inst/n2907_s1/F
10.631 3.996 tNET RR 1 R15C67[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.599 1.916 tNET RR 1 R15C67[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_1_s0/CLK
12.288 -0.311 tSu 1 R15C67[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_spram_shift[3].spram_shift_inst/mem[17]_1_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.683, 25.822%; route: 1.961, 74.178%
Arrival Data Path Delay cell: 0.521, 6.526%; route: 7.084, 88.685%; tC2Q: 0.382, 4.789%
Required Clock Path Delay cell: 0.683, 26.263%; route: 1.916, 73.737%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.213
Data Arrival Time 1.629
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.384 0.708 tNET RR 1 R9C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.528 0.144 tC2Q RR 5 R9C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
1.629 0.101 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.825%; route: 0.708, 51.175%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path2

Path Summary:

Slack 0.214
Data Arrival Time 1.629
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.523 0.144 tC2Q RR 7 R9C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.629 0.106 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.106, 42.400%; tC2Q: 0.144, 57.600%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path3

Path Summary:

Slack 0.221
Data Arrival Time 1.636
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
1.535 0.144 tC2Q RR 1 R6C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q
1.636 0.101 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path4

Path Summary:

Slack 0.249
Data Arrival Time 1.664
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.365 0.690 tNET RR 1 R11C7[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/CLK
1.507 0.141 tC2Q RF 1 R11C7[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_9_s0/Q
1.664 0.158 tNET FF 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path5

Path Summary:

Slack 0.251
Data Arrival Time 1.666
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.523 0.144 tC2Q RR 5 R9C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.666 0.143 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.143, 49.826%; tC2Q: 0.144, 50.174%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path6

Path Summary:

Slack 0.252
Data Arrival Time 1.668
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.388 0.713 tNET RR 1 R8C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/CLK
1.533 0.144 tC2Q RR 1 R8C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q
1.668 0.135 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.650%; route: 0.713, 51.350%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.135, 48.387%; tC2Q: 0.144, 51.613%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path7

Path Summary:

Slack 0.257
Data Arrival Time 1.673
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C6[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.523 0.144 tC2Q RR 6 R9C6[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.673 0.149 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[0] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.149, 50.853%; tC2Q: 0.144, 49.147%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path8

Path Summary:

Slack 0.275
Data Arrival Time 1.601
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_22_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R17C5[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_22_s0/CLK
1.523 0.144 tC2Q RR 1 R17C5[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_22_s0/Q
1.601 0.078 tNET RR 1 R17C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R17C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/CLK
1.326 -0.053 tHld 1 R17C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.985%; route: 0.704, 51.015%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay cell: 0.675, 48.985%; route: 0.704, 51.015%

Path9

Path Summary:

Slack 0.275
Data Arrival Time 2.718
Data Required Time 2.443
From gw_gao_inst_0/u_la0_top/word_count_4_s0
To gw_gao_inst_0/u_la0_top/word_count_4_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.418 1.067 tNET RR 1 R27C5[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.559 0.141 tC2Q RF 5 R27C5[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/Q
2.565 0.006 tNET FF 1 R27C5[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/I1
2.718 0.153 tINS FF 1 R27C5[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s0/F
2.718 0.000 tNET FF 1 R27C5[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.418 1.067 tNET RR 1 R27C5[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0/CLK
2.443 0.025 tHld 1 R27C5[1][A] gw_gao_inst_0/u_la0_top/word_count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.873%; route: 1.067, 44.127%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 55.873%; route: 1.067, 44.127%

Path10

Path Summary:

Slack 0.275
Data Arrival Time 1.661
Data Required Time 1.386
From sim_output_storage_inst/ram_din_addra_1_s0
To sim_output_storage_inst/ram_din_addra_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.361 0.685 tNET RR 1 R13C7[1][A] sim_output_storage_inst/ram_din_addra_1_s0/CLK
1.502 0.141 tC2Q RF 5 R13C7[1][A] sim_output_storage_inst/ram_din_addra_1_s0/Q
1.508 0.006 tNET FF 1 R13C7[1][A] sim_output_storage_inst/n100_s1/I1
1.661 0.153 tINS FF 1 R13C7[1][A] sim_output_storage_inst/n100_s1/F
1.661 0.000 tNET FF 1 R13C7[1][A] sim_output_storage_inst/ram_din_addra_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.361 0.685 tNET RR 1 R13C7[1][A] sim_output_storage_inst/ram_din_addra_1_s0/CLK
1.386 0.025 tHld 1 R13C7[1][A] sim_output_storage_inst/ram_din_addra_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.651%; route: 0.685, 50.349%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 49.651%; route: 0.685, 50.349%

Path11

Path Summary:

Slack 0.275
Data Arrival Time 1.669
Data Required Time 1.393
From sim_input_gen_inst/cnt_cycle_3_s1
To sim_input_gen_inst/cnt_cycle_3_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R14C56[1][A] sim_input_gen_inst/cnt_cycle_3_s1/CLK
1.510 0.141 tC2Q RF 3 R14C56[1][A] sim_input_gen_inst/cnt_cycle_3_s1/Q
1.516 0.006 tNET FF 1 R14C56[1][A] sim_input_gen_inst/n39_s2/I1
1.669 0.153 tINS FF 1 R14C56[1][A] sim_input_gen_inst/n39_s2/F
1.669 0.000 tNET FF 1 R14C56[1][A] sim_input_gen_inst/cnt_cycle_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R14C56[1][A] sim_input_gen_inst/cnt_cycle_3_s1/CLK
1.393 0.025 tHld 1 R14C56[1][A] sim_input_gen_inst/cnt_cycle_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%

Path12

Path Summary:

Slack 0.275
Data Arrival Time 1.701
Data Required Time 1.426
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_0_s1
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_0_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R21C45[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_0_s1/CLK
1.542 0.141 tC2Q RF 4 R21C45[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_0_s1/Q
1.548 0.006 tNET FF 1 R21C45[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n155_s4/I3
1.701 0.153 tINS FF 1 R21C45[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n155_s4/F
1.701 0.000 tNET FF 1 R21C45[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R21C45[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_0_s1/CLK
1.426 0.025 tHld 1 R21C45[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_factor_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 1.666
Data Required Time 1.390
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_4_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.365 0.690 tNET RR 1 R11C23[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_4_s0/CLK
1.507 0.141 tC2Q RF 2 R11C23[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_4_s0/Q
1.513 0.006 tNET FF 1 R11C23[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n2575_s2/I2
1.666 0.153 tINS FF 1 R11C23[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n2575_s2/F
1.666 0.000 tNET FF 1 R11C23[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.365 0.690 tNET RR 1 R11C23[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_4_s0/CLK
1.390 0.025 tHld 1 R11C23[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 49.469%; route: 0.690, 50.531%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 1.706
Data Required Time 1.431
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/ram_shift_addra_start_5_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/ram_shift_addra_start_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.406 0.730 tNET RR 1 R20C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/ram_shift_addra_start_5_s0/CLK
1.547 0.141 tC2Q RF 6 R20C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/ram_shift_addra_start_5_s0/Q
1.553 0.006 tNET FF 1 R20C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n269_s2/I2
1.706 0.153 tINS FF 1 R20C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n269_s2/F
1.706 0.000 tNET FF 1 R20C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/ram_shift_addra_start_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.406 0.730 tNET RR 1 R20C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/ram_shift_addra_start_5_s0/CLK
1.431 0.025 tHld 1 R20C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/ram_shift_addra_start_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.053%; route: 0.730, 51.947%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 48.053%; route: 0.730, 51.947%

Path15

Path Summary:

Slack 0.275
Data Arrival Time 2.719
Data Required Time 2.444
From gw_gao_inst_0/u_la0_top/word_count_7_s0
To gw_gao_inst_0/u_la0_top/word_count_7_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.419 1.068 tNET RR 1 R26C6[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
2.560 0.141 tC2Q RF 3 R26C6[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/Q
2.566 0.006 tNET FF 1 R26C6[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/I1
2.719 0.153 tINS FF 1 R26C6[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/F
2.719 0.000 tNET FF 1 R26C6[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.419 1.068 tNET RR 1 R26C6[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK
2.444 0.025 tHld 1 R26C6[0][A] gw_gao_inst_0/u_la0_top/word_count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.850%; route: 1.068, 44.150%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 55.850%; route: 1.068, 44.150%

Path16

Path Summary:

Slack 0.275
Data Arrival Time 2.719
Data Required Time 2.444
From gw_gao_inst_0/u_la0_top/word_count_8_s0
To gw_gao_inst_0/u_la0_top/word_count_8_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.419 1.068 tNET RR 1 R26C6[1][A] gw_gao_inst_0/u_la0_top/word_count_8_s0/CLK
2.560 0.141 tC2Q RF 4 R26C6[1][A] gw_gao_inst_0/u_la0_top/word_count_8_s0/Q
2.566 0.006 tNET FF 1 R26C6[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_8_s0/I1
2.719 0.153 tINS FF 1 R26C6[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_8_s0/F
2.719 0.000 tNET FF 1 R26C6[1][A] gw_gao_inst_0/u_la0_top/word_count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.419 1.068 tNET RR 1 R26C6[1][A] gw_gao_inst_0/u_la0_top/word_count_8_s0/CLK
2.444 0.025 tHld 1 R26C6[1][A] gw_gao_inst_0/u_la0_top/word_count_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.850%; route: 1.068, 44.150%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 55.850%; route: 1.068, 44.150%

Path17

Path Summary:

Slack 0.278
Data Arrival Time 2.710
Data Required Time 2.432
From gw_gao_inst_0/u_la0_top/bit_count_3_s1
To gw_gao_inst_0/u_la0_top/bit_count_3_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.407 1.056 tNET RR 1 R32C5[0][A] gw_gao_inst_0/u_la0_top/bit_count_3_s1/CLK
2.548 0.141 tC2Q RF 4 R32C5[0][A] gw_gao_inst_0/u_la0_top/bit_count_3_s1/Q
2.557 0.009 tNET FF 1 R32C5[0][A] gw_gao_inst_0/u_la0_top/n524_s2/I0
2.710 0.153 tINS FF 1 R32C5[0][A] gw_gao_inst_0/u_la0_top/n524_s2/F
2.710 0.000 tNET FF 1 R32C5[0][A] gw_gao_inst_0/u_la0_top/bit_count_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.407 1.056 tNET RR 1 R32C5[0][A] gw_gao_inst_0/u_la0_top/bit_count_3_s1/CLK
2.432 0.025 tHld 1 R32C5[0][A] gw_gao_inst_0/u_la0_top/bit_count_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 56.128%; route: 1.056, 43.872%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 56.128%; route: 1.056, 43.872%

Path18

Path Summary:

Slack 0.278
Data Arrival Time 2.737
Data Required Time 2.459
From gw_gao_inst_0/u_la0_top/address_counter_6_s0
To gw_gao_inst_0/u_la0_top/address_counter_6_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.434 1.083 tNET RR 1 R24C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/CLK
2.575 0.141 tC2Q RF 5 R24C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/Q
2.584 0.009 tNET FF 1 R24C4[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_6_s0/I1
2.737 0.153 tINS FF 1 R24C4[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_6_s0/F
2.737 0.000 tNET FF 1 R24C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.434 1.083 tNET RR 1 R24C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/CLK
2.459 0.025 tHld 1 R24C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.511%; route: 1.083, 44.489%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 55.511%; route: 1.083, 44.489%

Path19

Path Summary:

Slack 0.278
Data Arrival Time 2.735
Data Required Time 2.457
From gw_gao_inst_0/u_la0_top/address_counter_8_s0
To gw_gao_inst_0/u_la0_top/address_counter_8_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.432 1.081 tNET RR 1 R25C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_8_s0/CLK
2.573 0.141 tC2Q RF 4 R25C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q
2.582 0.009 tNET FF 1 R25C4[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_8_s0/I1
2.735 0.153 tINS FF 1 R25C4[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_8_s0/F
2.735 0.000 tNET FF 1 R25C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 225 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.432 1.081 tNET RR 1 R25C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_8_s0/CLK
2.457 0.025 tHld 1 R25C4[0][A] gw_gao_inst_0/u_la0_top/address_counter_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.551%; route: 1.081, 44.449%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 55.551%; route: 1.081, 44.449%

Path20

Path Summary:

Slack 0.278
Data Arrival Time 1.668
Data Required Time 1.390
From sim_output_storage_inst/ram_din_addra_2_s0
To sim_output_storage_inst/ram_din_addra_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R14C7[0][A] sim_output_storage_inst/ram_din_addra_2_s0/CLK
1.506 0.141 tC2Q RF 4 R14C7[0][A] sim_output_storage_inst/ram_din_addra_2_s0/Q
1.515 0.009 tNET FF 1 R14C7[0][A] sim_output_storage_inst/n99_s1/I3
1.668 0.153 tINS FF 1 R14C7[0][A] sim_output_storage_inst/n99_s1/F
1.668 0.000 tNET FF 1 R14C7[0][A] sim_output_storage_inst/ram_din_addra_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R14C7[0][A] sim_output_storage_inst/ram_din_addra_2_s0/CLK
1.390 0.025 tHld 1 R14C7[0][A] sim_output_storage_inst/ram_din_addra_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%

Path21

Path Summary:

Slack 0.278
Data Arrival Time 1.675
Data Required Time 1.397
From sim_input_gen_inst/cnt_cycle_4_s1
To sim_input_gen_inst/cnt_cycle_4_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.372 0.697 tNET RR 1 R14C57[1][A] sim_input_gen_inst/cnt_cycle_4_s1/CLK
1.513 0.141 tC2Q RF 5 R14C57[1][A] sim_input_gen_inst/cnt_cycle_4_s1/Q
1.522 0.009 tNET FF 1 R14C57[1][A] sim_input_gen_inst/n38_s2/I1
1.675 0.153 tINS FF 1 R14C57[1][A] sim_input_gen_inst/n38_s2/F
1.675 0.000 tNET FF 1 R14C57[1][A] sim_input_gen_inst/cnt_cycle_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.372 0.697 tNET RR 1 R14C57[1][A] sim_input_gen_inst/cnt_cycle_4_s1/CLK
1.397 0.025 tHld 1 R14C57[1][A] sim_input_gen_inst/cnt_cycle_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.217%; route: 0.697, 50.783%

Path22

Path Summary:

Slack 0.278
Data Arrival Time 1.668
Data Required Time 1.390
From sim_input_gen_inst/cnt_cycle_1_s1
To sim_input_gen_inst/cnt_cycle_1_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R13C56[0][A] sim_input_gen_inst/cnt_cycle_1_s1/CLK
1.506 0.141 tC2Q RF 7 R13C56[0][A] sim_input_gen_inst/cnt_cycle_1_s1/Q
1.515 0.009 tNET FF 1 R13C56[0][A] sim_input_gen_inst/n41_s2/I2
1.668 0.153 tINS FF 1 R13C56[0][A] sim_input_gen_inst/n41_s2/F
1.668 0.000 tNET FF 1 R13C56[0][A] sim_input_gen_inst/cnt_cycle_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R13C56[0][A] sim_input_gen_inst/cnt_cycle_1_s1/CLK
1.390 0.025 tHld 1 R13C56[0][A] sim_input_gen_inst/cnt_cycle_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%

Path23

Path Summary:

Slack 0.278
Data Arrival Time 1.687
Data Required Time 1.409
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_factor_0_s2
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_factor_0_s2
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.384 0.708 tNET RR 1 R9C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_factor_0_s2/CLK
1.525 0.141 tC2Q RF 39 R9C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_factor_0_s2/Q
1.534 0.009 tNET FF 1 R9C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n2618_s3/I2
1.687 0.153 tINS FF 1 R9C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n2618_s3/F
1.687 0.000 tNET FF 1 R9C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_factor_0_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.384 0.708 tNET RR 1 R9C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_factor_0_s2/CLK
1.409 0.025 tHld 1 R9C25[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/cnt_acc_factor_0_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.825%; route: 0.708, 51.175%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 48.825%; route: 0.708, 51.175%

Path24

Path Summary:

Slack 0.278
Data Arrival Time 1.682
Data Required Time 1.404
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_index_cnt_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_index_cnt_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_index_cnt_0_s0/CLK
1.520 0.141 tC2Q RF 8 R9C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_index_cnt_0_s0/Q
1.529 0.009 tNET FF 1 R9C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n2088_s3/I0
1.682 0.153 tINS FF 1 R9C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n2088_s3/F
1.682 0.000 tNET FF 1 R9C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_index_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_index_cnt_0_s0/CLK
1.404 0.025 tHld 1 R9C20[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_index_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path25

Path Summary:

Slack 0.278
Data Arrival Time 1.704
Data Required Time 1.426
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_ram_addra_1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_ram_addra_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R21C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_ram_addra_1_s0/CLK
1.542 0.141 tC2Q RF 50 R21C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_ram_addra_1_s0/Q
1.551 0.009 tNET FF 1 R21C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n2058_s2/I2
1.704 0.153 tINS FF 1 R21C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/n2058_s2/F
1.704 0.000 tNET FF 1 R21C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_ram_addra_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R21C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_ram_addra_1_s0/CLK
1.426 0.025 tHld 1 R21C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_ram_addra_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.904
Data Arrival Time 9.386
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.386 1.328 tNET FF 1 R6C6[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C6[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
12.291 -0.347 tSu 1 R6C6[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew 0.022
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.328, 75.000%; tC2Q: 0.442, 25.000%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path2

Path Summary:

Slack 2.912
Data Arrival Time 9.386
Data Required Time 12.298
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.386 1.328 tNET FF 1 R3C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R3C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
12.298 -0.347 tSu 1 R3C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew 0.029
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.328, 75.000%; tC2Q: 0.442, 25.000%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path3

Path Summary:

Slack 3.091
Data Arrival Time 9.203
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.203 1.144 tNET FF 1 R5C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
12.293 -0.347 tSu 1 R5C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew 0.024
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 72.104%; tC2Q: 0.442, 27.896%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path4

Path Summary:

Slack 3.091
Data Arrival Time 9.203
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.203 1.144 tNET FF 1 R5C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
12.293 -0.347 tSu 1 R5C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew 0.024
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 72.104%; tC2Q: 0.442, 27.896%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path5

Path Summary:

Slack 3.091
Data Arrival Time 9.203
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.203 1.144 tNET FF 1 R5C6[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C6[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
12.293 -0.347 tSu 1 R5C6[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew 0.024
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 72.104%; tC2Q: 0.442, 27.896%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path6

Path Summary:

Slack 3.091
Data Arrival Time 9.203
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.203 1.144 tNET FF 1 R5C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
12.293 -0.347 tSu 1 R5C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew 0.024
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 72.104%; tC2Q: 0.442, 27.896%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path7

Path Summary:

Slack 3.102
Data Arrival Time 9.203
Data Required Time 12.305
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.203 1.144 tNET FF 1 R4C5[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.653 1.970 tNET RR 1 R4C5[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.305 -0.347 tSu 1 R4C5[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.036
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 72.104%; tC2Q: 0.442, 27.896%
Required Clock Path Delay cell: 0.683, 25.730%; route: 1.970, 74.270%

Path8

Path Summary:

Slack 3.102
Data Arrival Time 9.203
Data Required Time 12.305
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.203 1.144 tNET FF 1 R4C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.653 1.970 tNET RR 1 R4C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
12.305 -0.347 tSu 1 R4C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew 0.036
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 72.104%; tC2Q: 0.442, 27.896%
Required Clock Path Delay cell: 0.683, 25.730%; route: 1.970, 74.270%

Path9

Path Summary:

Slack 3.102
Data Arrival Time 9.203
Data Required Time 12.305
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.203 1.144 tNET FF 1 R4C5[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.653 1.970 tNET RR 1 R4C5[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
12.305 -0.347 tSu 1 R4C5[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew 0.036
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 72.104%; tC2Q: 0.442, 27.896%
Required Clock Path Delay cell: 0.683, 25.730%; route: 1.970, 74.270%

Path10

Path Summary:

Slack 3.146
Data Arrival Time 9.116
Data Required Time 12.263
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.116 1.057 tNET FF 1 R16C6[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R16C6[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
12.263 -0.347 tSu 1 R16C6[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew -0.006
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.057, 70.500%; tC2Q: 0.442, 29.500%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path11

Path Summary:

Slack 3.146
Data Arrival Time 9.116
Data Required Time 12.263
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.116 1.057 tNET FF 1 R16C6[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R16C6[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
12.263 -0.347 tSu 1 R16C6[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew -0.006
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.057, 70.500%; tC2Q: 0.442, 29.500%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path12

Path Summary:

Slack 3.146
Data Arrival Time 9.116
Data Required Time 12.263
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.116 1.057 tNET FF 1 R16C6[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R16C6[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
12.263 -0.347 tSu 1 R16C6[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew -0.006
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.057, 70.500%; tC2Q: 0.442, 29.500%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path13

Path Summary:

Slack 3.146
Data Arrival Time 9.116
Data Required Time 12.263
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.116 1.057 tNET FF 1 R16C6[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R16C6[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
12.263 -0.347 tSu 1 R16C6[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew -0.006
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.057, 70.500%; tC2Q: 0.442, 29.500%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path14

Path Summary:

Slack 3.146
Data Arrival Time 9.116
Data Required Time 12.263
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.116 1.057 tNET FF 1 R16C6[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R16C6[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
12.263 -0.347 tSu 1 R16C6[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew -0.006
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.057, 70.500%; tC2Q: 0.442, 29.500%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path15

Path Summary:

Slack 3.148
Data Arrival Time 9.116
Data Required Time 12.264
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.116 1.057 tNET FF 1 R17C6[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R17C6[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
12.264 -0.347 tSu 1 R17C6[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew -0.004
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.057, 70.500%; tC2Q: 0.442, 29.500%
Required Clock Path Delay cell: 0.683, 26.131%; route: 1.929, 73.869%

Path16

Path Summary:

Slack 3.260
Data Arrival Time 9.050
Data Required Time 12.310
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.050 0.991 tNET FF 1 R20C5[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.658 1.975 tNET RR 1 R20C5[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
12.310 -0.347 tSu 1 R20C5[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew 0.041
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.991, 69.137%; tC2Q: 0.442, 30.863%
Required Clock Path Delay cell: 0.683, 25.682%; route: 1.975, 74.318%

Path17

Path Summary:

Slack 3.260
Data Arrival Time 9.050
Data Required Time 12.310
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.050 0.991 tNET FF 1 R20C5[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.658 1.975 tNET RR 1 R20C5[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
12.310 -0.347 tSu 1 R20C5[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew 0.041
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.991, 69.137%; tC2Q: 0.442, 30.863%
Required Clock Path Delay cell: 0.683, 25.682%; route: 1.975, 74.318%

Path18

Path Summary:

Slack 3.260
Data Arrival Time 9.050
Data Required Time 12.310
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.050 0.991 tNET FF 1 R20C5[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.658 1.975 tNET RR 1 R20C5[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
12.310 -0.347 tSu 1 R20C5[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew 0.041
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.991, 69.137%; tC2Q: 0.442, 30.863%
Required Clock Path Delay cell: 0.683, 25.682%; route: 1.975, 74.318%

Path19

Path Summary:

Slack 3.310
Data Arrival Time 8.993
Data Required Time 12.302
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.993 0.934 tNET FF 1 R5C5[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.650 1.967 tNET RR 1 R5C5[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
12.302 -0.347 tSu 1 R5C5[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew 0.034
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.934, 67.847%; tC2Q: 0.442, 32.153%
Required Clock Path Delay cell: 0.683, 25.755%; route: 1.967, 74.245%

Path20

Path Summary:

Slack 3.360
Data Arrival Time 8.906
Data Required Time 12.266
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.906 0.847 tNET FF 1 R18C6[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.614 1.931 tNET RR 1 R18C6[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
12.266 -0.347 tSu 1 R18C6[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew -0.003
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.847, 65.698%; tC2Q: 0.442, 34.302%
Required Clock Path Delay cell: 0.683, 26.112%; route: 1.931, 73.888%

Path21

Path Summary:

Slack 3.369
Data Arrival Time 8.906
Data Required Time 12.276
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.906 0.847 tNET FF 1 R18C5[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.623 1.941 tNET RR 1 R18C5[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
12.276 -0.347 tSu 1 R18C5[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew 0.007
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.847, 65.698%; tC2Q: 0.442, 34.302%
Required Clock Path Delay cell: 0.683, 26.019%; route: 1.941, 73.981%

Path22

Path Summary:

Slack 3.369
Data Arrival Time 8.906
Data Required Time 12.276
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.906 0.847 tNET FF 1 R18C5[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.623 1.941 tNET RR 1 R18C5[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
12.276 -0.347 tSu 1 R18C5[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew 0.007
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.847, 65.698%; tC2Q: 0.442, 34.302%
Required Clock Path Delay cell: 0.683, 26.019%; route: 1.941, 73.981%

Path23

Path Summary:

Slack 3.369
Data Arrival Time 8.906
Data Required Time 12.276
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.906 0.847 tNET FF 1 R18C5[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.623 1.941 tNET RR 1 R18C5[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
12.276 -0.347 tSu 1 R18C5[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew 0.007
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.847, 65.698%; tC2Q: 0.442, 34.302%
Required Clock Path Delay cell: 0.683, 26.019%; route: 1.941, 73.981%

Path24

Path Summary:

Slack 3.369
Data Arrival Time 8.906
Data Required Time 12.276
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.906 0.847 tNET FF 1 R18C5[1][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.623 1.941 tNET RR 1 R18C5[1][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
12.276 -0.347 tSu 1 R18C5[1][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew 0.007
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.847, 65.698%; tC2Q: 0.442, 34.302%
Required Clock Path Delay cell: 0.683, 26.019%; route: 1.941, 73.981%

Path25

Path Summary:

Slack 3.410
Data Arrival Time 8.839
Data Required Time 12.249
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 5922 IOB29[A] clk_ibuf/O
7.616 1.929 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.059 0.442 tC2Q FF 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.839 0.780 tNET FF 1 R13C6[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 5922 IOB29[A] clk_ibuf/O
12.596 1.914 tNET RR 1 R13C6[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
12.249 -0.347 tSu 1 R13C6[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew -0.020
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 26.278%; route: 1.929, 73.722%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.780, 63.804%; tC2Q: 0.442, 36.196%
Required Clock Path Delay cell: 0.683, 26.288%; route: 1.914, 73.712%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 5.397
Data Arrival Time 6.723
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.723 0.183 tNET RR 1 R9C4[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C4[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
1.326 -0.053 tHld 1 R9C4[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -0.003
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.183, 53.666%; tC2Q: 0.158, 46.334%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path2

Path Summary:

Slack 5.497
Data Arrival Time 6.827
Data Required Time 1.331
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.827 0.287 tNET RR 1 R9C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.384 0.708 tNET RR 1 R9C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.331 -0.053 tHld 1 R9C5[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.002
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay cell: 0.675, 48.825%; route: 0.708, 51.175%

Path3

Path Summary:

Slack 5.497
Data Arrival Time 6.827
Data Required Time 1.331
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.827 0.287 tNET RR 1 R9C5[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.384 0.708 tNET RR 1 R9C5[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.331 -0.053 tHld 1 R9C5[0][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew 0.002
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay cell: 0.675, 48.825%; route: 0.708, 51.175%

Path4

Path Summary:

Slack 5.497
Data Arrival Time 6.827
Data Required Time 1.331
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.827 0.287 tNET RR 1 R9C5[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.384 0.708 tNET RR 1 R9C5[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
1.331 -0.053 tHld 1 R9C5[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew 0.002
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay cell: 0.675, 48.825%; route: 0.708, 51.175%

Path5

Path Summary:

Slack 5.501
Data Arrival Time 6.827
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.827 0.287 tNET RR 1 R9C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.326 -0.053 tHld 1 R9C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew -0.003
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path6

Path Summary:

Slack 5.501
Data Arrival Time 6.827
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.827 0.287 tNET RR 1 R9C6[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C6[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
1.326 -0.053 tHld 1 R9C6[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew -0.003
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path7

Path Summary:

Slack 5.501
Data Arrival Time 6.827
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.827 0.287 tNET RR 1 R9C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.326 -0.053 tHld 1 R9C6[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew -0.003
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path8

Path Summary:

Slack 5.501
Data Arrival Time 6.827
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.827 0.287 tNET RR 1 R9C6[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C6[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.326 -0.053 tHld 1 R9C6[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew -0.003
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path9

Path Summary:

Slack 5.501
Data Arrival Time 6.827
Data Required Time 1.326
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.827 0.287 tNET RR 1 R9C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.379 0.704 tNET RR 1 R9C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
1.326 -0.053 tHld 1 R9C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew -0.003
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay cell: 0.675, 48.967%; route: 0.704, 51.033%

Path10

Path Summary:

Slack 5.547
Data Arrival Time 6.870
Data Required Time 1.323
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.870 0.330 tNET RR 1 R18C4[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.376 0.701 tNET RR 1 R18C4[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
1.323 -0.053 tHld 1 R18C4[0][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew -0.006
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.330, 67.623%; tC2Q: 0.158, 32.377%
Required Clock Path Delay cell: 0.675, 49.083%; route: 0.701, 50.917%

Path11

Path Summary:

Slack 5.589
Data Arrival Time 6.909
Data Required Time 1.320
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.909 0.369 tNET RR 1 R11C5[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C5[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.321 -0.053 tHld 1 R11C5[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew -0.008
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.369, 70.019%; tC2Q: 0.158, 29.981%
Required Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%

Path12

Path Summary:

Slack 5.589
Data Arrival Time 6.909
Data Required Time 1.320
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.909 0.369 tNET RR 1 R11C5[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C5[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
1.321 -0.053 tHld 1 R11C5[2][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew -0.008
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.369, 70.019%; tC2Q: 0.158, 29.981%
Required Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%

Path13

Path Summary:

Slack 5.589
Data Arrival Time 6.909
Data Required Time 1.320
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.909 0.369 tNET RR 1 R11C5[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C5[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.321 -0.053 tHld 1 R11C5[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew -0.008
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.369, 70.019%; tC2Q: 0.158, 29.981%
Required Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%

Path14

Path Summary:

Slack 5.589
Data Arrival Time 6.909
Data Required Time 1.320
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.909 0.369 tNET RR 1 R11C5[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C5[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.321 -0.053 tHld 1 R11C5[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew -0.008
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.369, 70.019%; tC2Q: 0.158, 29.981%
Required Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%

Path15

Path Summary:

Slack 5.592
Data Arrival Time 6.909
Data Required Time 1.317
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.909 0.369 tNET RR 1 R11C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
1.316 -0.053 tHld 1 R11C6[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.369, 70.019%; tC2Q: 0.158, 29.981%
Required Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%

Path16

Path Summary:

Slack 5.592
Data Arrival Time 6.909
Data Required Time 1.317
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.909 0.369 tNET RR 1 R11C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.316 -0.053 tHld 1 R11C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.369, 70.019%; tC2Q: 0.158, 29.981%
Required Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%

Path17

Path Summary:

Slack 5.592
Data Arrival Time 6.909
Data Required Time 1.317
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.909 0.369 tNET RR 1 R11C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.316 -0.053 tHld 1 R11C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.369, 70.019%; tC2Q: 0.158, 29.981%
Required Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%

Path18

Path Summary:

Slack 5.592
Data Arrival Time 6.909
Data Required Time 1.317
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.909 0.369 tNET RR 1 R11C6[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C6[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
1.316 -0.053 tHld 1 R11C6[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.369, 70.019%; tC2Q: 0.158, 29.981%
Required Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%

Path19

Path Summary:

Slack 5.592
Data Arrival Time 6.909
Data Required Time 1.317
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.909 0.369 tNET RR 1 R11C6[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C6[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.316 -0.053 tHld 1 R11C6[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.369, 70.019%; tC2Q: 0.158, 29.981%
Required Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%

Path20

Path Summary:

Slack 5.593
Data Arrival Time 6.929
Data Required Time 1.336
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.929 0.389 tNET RR 1 R7C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.389 0.714 tNET RR 1 R7C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.336 -0.053 tHld 1 R7C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.007
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.389, 71.115%; tC2Q: 0.158, 28.885%
Required Clock Path Delay cell: 0.675, 48.615%; route: 0.714, 51.385%

Path21

Path Summary:

Slack 5.593
Data Arrival Time 6.929
Data Required Time 1.336
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.929 0.389 tNET RR 1 R7C6[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.389 0.714 tNET RR 1 R7C6[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
1.336 -0.053 tHld 1 R7C6[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew 0.007
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.389, 71.115%; tC2Q: 0.158, 28.885%
Required Clock Path Delay cell: 0.675, 48.615%; route: 0.714, 51.385%

Path22

Path Summary:

Slack 5.597
Data Arrival Time 6.929
Data Required Time 1.332
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.929 0.389 tNET RR 1 R8C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.385 0.709 tNET RR 1 R8C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
1.332 -0.053 tHld 1 R8C6[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew 0.002
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.389, 71.115%; tC2Q: 0.158, 28.885%
Required Clock Path Delay cell: 0.675, 48.790%; route: 0.709, 51.210%

Path23

Path Summary:

Slack 5.597
Data Arrival Time 6.929
Data Required Time 1.332
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.929 0.389 tNET RR 1 R8C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.385 0.709 tNET RR 1 R8C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.332 -0.053 tHld 1 R8C6[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew 0.002
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.389, 71.115%; tC2Q: 0.158, 28.885%
Required Clock Path Delay cell: 0.675, 48.790%; route: 0.709, 51.210%

Path24

Path Summary:

Slack 5.597
Data Arrival Time 6.929
Data Required Time 1.332
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.929 0.389 tNET RR 1 R8C6[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.385 0.709 tNET RR 1 R8C6[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.332 -0.053 tHld 1 R8C6[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.002
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.389, 71.115%; tC2Q: 0.158, 28.885%
Required Clock Path Delay cell: 0.675, 48.790%; route: 0.709, 51.210%

Path25

Path Summary:

Slack 5.647
Data Arrival Time 6.974
Data Required Time 1.327
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 5922 IOB29[A] clk_ibuf/O
6.382 0.705 tNET FF 1 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.540 0.158 tC2Q FR 53 R18C4[2][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.974 0.434 tNET RR 1 R18C5[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 5922 IOB29[A] clk_ibuf/O
1.380 0.705 tNET RR 1 R18C5[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
1.327 -0.053 tHld 1 R18C5[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew -0.002
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 49.023%; route: 0.705, 50.977%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.434, 73.311%; tC2Q: 0.158, 26.689%
Required Clock Path Delay cell: 0.675, 48.940%; route: 0.705, 51.060%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.751
Actual Width: 3.751
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.627 1.940 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.703 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack: 2.751
Actual Width: 3.751
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.627 1.940 tNET FF sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.703 tNET RR sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB

MPW3

MPW Summary:

Slack: 2.754
Actual Width: 3.754
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[1].mult_dsp_inst/n47_s1

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.628 1.940 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[1].mult_dsp_inst/n47_s1/CLK[0]

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.382 0.706 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[1].mult_dsp_inst/n47_s1/CLK[0]

MPW4

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW5

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_rom_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/coeff_rom_inst/mem_mem_0_0_s/CLK

MPW6

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA

MPW7

MPW Summary:

Slack: 2.759
Actual Width: 3.759
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.931 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.702 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

MPW8

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.623 1.941 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.385 0.708 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW9

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.623 1.941 tNET RR sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.385 0.708 tNET FF sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB

MPW10

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[1].mult_dsp_inst/n47_s1

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.625 1.942 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[1].mult_dsp_inst/n47_s1/CLK[0]

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.387 0.710 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_hb_decimator_inst/gen_mult_dsp[1].mult_dsp_inst/n47_s1/CLK[0]

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
5922 clk_d 1.097 1.985
1217 delay_shift_addrb[0] 4.067 3.338
641 delay_shift_addrb[1] 3.415 3.951
608 coeff_ram_addrb[0] 4.803 2.965
608 delay_shift_addrb_symm[0] 4.218 3.498
321 delay_shift_addrb[2] 3.580 4.589
320 coeff_ram_addrb[1] 4.727 3.180
320 delay_shift_addrb_symm[1] 5.219 2.700
225 control0[0] 4.298 2.735
160 coeff_ram_addrb[2] 3.954 4.084

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R13C52 62.50%
R13C51 56.94%
R9C6 55.56%
R13C53 54.17%
R12C14 54.17%
R32C63 51.39%
R20C40 50.00%
R33C22 50.00%
R6C5 48.61%
R11C52 48.61%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]