Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\2_fir_symmetry\33taps_3chn_4tdm_31bit\proj\impl\gwsynthesis\fir_proj.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\2_fir_symmetry\33taps_3chn_4tdm_31bit\proj\src\fir_proj.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.11\Advanced_FIR_Filter_RefDesign\2_fir_symmetry\33taps_3chn_4tdm_31bit\proj\src\fir_proj.sdc
Tool Version V1.9.11 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Dec 24 18:27:22 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C ES
Hold Delay Model Fast 0.945V 85C ES
Numbers of Paths Analyzed 10328
Numbers of Endpoints Analyzed 11313
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk Base 10.000 100.000 0.000 5.000 clk
2 tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 124.839(MHz) 3 TOP
2 tck_pad_i 20.000(MHz) 148.595(MHz) 6 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.990 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_8_s0/D clk:[R] clk:[R] 10.000 0.048 7.899
2 2.354 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_14_s0/CE clk:[R] clk:[R] 10.000 0.037 7.298
3 2.354 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_13_s0/CE clk:[R] clk:[R] 10.000 0.037 7.298
4 2.364 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_15_s0/D clk:[R] clk:[R] 10.000 0.047 7.525
5 2.366 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_10_s0/CE clk:[R] clk:[R] 10.000 0.026 7.298
6 2.380 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_0_s0/D clk:[R] clk:[R] 10.000 0.036 7.520
7 2.546 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_11_s0/CE clk:[R] clk:[R] 10.000 0.035 7.107
8 2.646 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_13_s0/CE clk:[R] clk:[R] 10.000 0.044 6.999
9 2.713 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_5_s0/D clk:[R] clk:[R] 10.000 0.039 7.184
10 2.732 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_3_s0/D clk:[R] clk:[R] 10.000 0.042 7.162
11 2.751 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_1_s0/D clk:[R] clk:[R] 10.000 0.051 7.134
12 2.819 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_14_s0/CE clk:[R] clk:[R] 10.000 0.033 6.836
13 2.819 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_12_s0/CE clk:[R] clk:[R] 10.000 0.033 6.836
14 2.921 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_14_s0/CE clk:[R] clk:[R] 10.000 0.045 6.723
15 2.921 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_13_s0/CE clk:[R] clk:[R] 10.000 0.045 6.723
16 2.929 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_0_s0/CE clk:[R] clk:[R] 10.000 0.024 6.736
17 2.940 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_2_s0/D clk:[R] clk:[R] 10.000 0.037 6.959
18 3.024 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_15_s0/CE clk:[R] clk:[R] 10.000 0.024 6.641
19 3.039 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[8].spram_shift_inst/mem[7]_3_s0/CE clk:[R] clk:[R] 10.000 0.041 6.609
20 3.047 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_10_s0/CE clk:[R] clk:[R] 10.000 0.022 6.620
21 3.076 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_6_s0/CE clk:[R] clk:[R] 10.000 0.016 6.596
22 3.076 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_4_s0/CE clk:[R] clk:[R] 10.000 0.016 6.596
23 3.135 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_9_s0/CE clk:[R] clk:[R] 10.000 0.043 6.511
24 3.146 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_8_s0/CE clk:[R] clk:[R] 10.000 0.037 6.506
25 3.149 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_13_s0/CE clk:[R] clk:[R] 10.000 0.035 6.505

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.193 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4] clk:[R] clk:[R] 0.000 -0.005 0.235
2 0.220 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10] clk:[R] clk:[R] 0.000 -0.001 0.258
3 0.251 sim_output_storage_inst/ram_dout_addrb_3_s0/Q sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/ADB[8] clk:[R] clk:[R] 0.000 -0.006 0.292
4 0.255 sim_output_storage_inst/ram_dout_addrb_3_s0/Q sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[8] clk:[R] clk:[R] 0.000 -0.002 0.292
5 0.257 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] clk:[R] clk:[R] 0.000 -0.005 0.299
6 0.257 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11] clk:[R] clk:[R] 0.000 -0.005 0.299
7 0.268 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5] clk:[R] clk:[R] 0.000 -0.009 0.314
8 0.275 sim_output_storage_inst/ram_dout_addrb_1_s0/Q sim_output_storage_inst/ram_dout_addrb_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.300
9 0.275 sim_output_storage_inst/ram_din_addra_2_s0/Q sim_output_storage_inst/ram_din_addra_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.300
10 0.275 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D clk:[R] clk:[R] 0.000 0.000 0.300
11 0.275 gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D clk:[R] clk:[R] 0.000 0.000 0.300
12 0.275 gw_gao_inst_0/u_la0_top/word_count_1_s0/Q gw_gao_inst_0/u_la0_top/word_count_1_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
13 0.275 gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q gw_gao_inst_0/u_la0_top/address_counter_0_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
14 0.275 gw_gao_inst_0/u_la0_top/address_counter_6_s0/Q gw_gao_inst_0/u_la0_top/address_counter_6_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.300
15 0.278 gw_gao_inst_0/u_la0_top/bit_count_4_s1/Q gw_gao_inst_0/u_la0_top/bit_count_4_s1/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
16 0.278 gw_gao_inst_0/u_la0_top/word_count_10_s0/Q gw_gao_inst_0/u_la0_top/word_count_10_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
17 0.278 gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q gw_gao_inst_0/u_la0_top/address_counter_4_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.303
18 0.278 sim_output_storage_inst/cnt_chn_1_s0/Q sim_output_storage_inst/cnt_chn_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
19 0.278 sim_output_storage_inst/ram_dout_addrb_6_s0/Q sim_output_storage_inst/ram_dout_addrb_6_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
20 0.278 sim_output_storage_inst/ram_din_addra_0_s0/Q sim_output_storage_inst/ram_din_addra_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
21 0.278 sim_output_storage_inst/ram_din_addra_3_s0/Q sim_output_storage_inst/ram_din_addra_3_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
22 0.278 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/coeff_ram_addrb_1_s3/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/coeff_ram_addrb_1_s3/D clk:[R] clk:[R] 0.000 0.000 0.303
23 0.278 Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/cnt_acc_chn_1_s0/Q Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/cnt_acc_chn_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.303
24 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14] clk:[R] clk:[R] 0.000 -0.009 0.324
25 0.278 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D clk:[R] clk:[R] 0.000 0.000 0.303

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.847 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR clk:[F] clk:[R] 5.000 0.026 1.780
2 3.040 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR clk:[F] clk:[R] 5.000 0.017 1.596
3 3.040 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR clk:[F] clk:[R] 5.000 0.017 1.596
4 3.222 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR clk:[F] clk:[R] 5.000 0.050 1.380
5 3.222 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR clk:[F] clk:[R] 5.000 0.050 1.380
6 3.407 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR clk:[F] clk:[R] 5.000 0.017 1.229
7 3.407 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR clk:[F] clk:[R] 5.000 0.017 1.229
8 3.407 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR clk:[F] clk:[R] 5.000 0.017 1.229
9 3.510 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR clk:[F] clk:[R] 5.000 0.019 1.124
10 3.510 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR clk:[F] clk:[R] 5.000 0.019 1.124
11 3.510 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR clk:[F] clk:[R] 5.000 0.019 1.124
12 3.532 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET clk:[F] clk:[R] 5.000 0.031 1.090
13 3.541 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR clk:[F] clk:[R] 5.000 0.022 1.090
14 3.567 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR clk:[F] clk:[R] 5.000 0.012 1.074
15 3.635 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR clk:[F] clk:[R] 5.000 0.012 1.005
16 3.694 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR clk:[F] clk:[R] 5.000 0.026 0.933
17 3.694 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR clk:[F] clk:[R] 5.000 0.026 0.933
18 3.694 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR clk:[F] clk:[R] 5.000 0.026 0.933
19 3.694 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR clk:[F] clk:[R] 5.000 0.026 0.933
20 3.702 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR clk:[F] clk:[R] 5.000 0.028 0.923
21 3.702 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR clk:[F] clk:[R] 5.000 0.028 0.923
22 3.702 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR clk:[F] clk:[R] 5.000 0.028 0.923
23 3.703 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET clk:[F] clk:[R] 5.000 0.017 0.933
24 3.703 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR clk:[F] clk:[R] 5.000 0.017 0.933
25 3.703 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR clk:[F] clk:[R] 5.000 0.017 0.933

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 5.308 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR clk:[F] clk:[R] -5.000 0.007 0.248
2 5.340 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR clk:[F] clk:[R] -5.000 0.011 0.276
3 5.340 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR clk:[F] clk:[R] -5.000 0.011 0.276
4 5.340 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR clk:[F] clk:[R] -5.000 0.011 0.276
5 5.340 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR clk:[F] clk:[R] -5.000 0.011 0.276
6 5.340 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR clk:[F] clk:[R] -5.000 0.011 0.276
7 5.344 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR clk:[F] clk:[R] -5.000 0.015 0.276
8 5.344 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR clk:[F] clk:[R] -5.000 0.015 0.276
9 5.344 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR clk:[F] clk:[R] -5.000 0.015 0.276
10 5.344 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR clk:[F] clk:[R] -5.000 0.015 0.276
11 5.344 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.015 0.276
12 5.401 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR clk:[F] clk:[R] -5.000 0.005 0.343
13 5.412 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR clk:[F] clk:[R] -5.000 0.010 0.349
14 5.412 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR clk:[F] clk:[R] -5.000 0.010 0.349
15 5.413 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR clk:[F] clk:[R] -5.000 0.008 0.352
16 5.413 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR clk:[F] clk:[R] -5.000 0.008 0.352
17 5.436 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR clk:[F] clk:[R] -5.000 0.009 0.374
18 5.436 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR clk:[F] clk:[R] -5.000 0.009 0.374
19 5.440 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR clk:[F] clk:[R] -5.000 0.013 0.374
20 5.440 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.013 0.374
21 5.440 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.013 0.374
22 5.440 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR clk:[F] clk:[R] -5.000 0.013 0.374
23 5.440 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR clk:[F] clk:[R] -5.000 0.013 0.374
24 5.447 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR clk:[F] clk:[R] -5.000 0.014 0.380
25 5.447 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR clk:[F] clk:[R] -5.000 0.014 0.380

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.751 3.751 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
2 2.751 3.751 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
3 2.754 3.754 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1
4 2.757 3.757 1.000 Low Pulse Width clk sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
5 2.757 3.757 1.000 Low Pulse Width clk sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s
6 2.757 3.757 1.000 Low Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
7 2.759 3.759 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[2].mult_dsp_inst/n47_s1
8 2.759 3.759 1.000 Low Pulse Width clk Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[3].mult_dsp_inst/n47_s1
9 2.762 3.762 1.000 High Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
10 2.762 3.762 1.000 High Pulse Width clk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.990
Data Arrival Time 10.546
Data Required Time 12.536
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.648 1.965 tNET RR 1 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/CLK
3.015 0.368 tC2Q RF 481 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q
8.544 5.529 tNET FF 1 R12C57[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n641_s51/I2
9.070 0.526 tINS FR 1 R12C57[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n641_s51/F
9.070 0.000 tNET RR 1 R12C57[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n641_s48/I0
9.206 0.136 tINS RR 1 R12C57[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n641_s48/O
9.206 0.000 tNET RR 1 R12C57[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n641_s45/I1
9.293 0.086 tINS RR 1 R12C57[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n641_s45/O
10.020 0.728 tNET RR 1 R12C57[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n641_s46/I2
10.546 0.526 tINS RR 1 R12C57[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n641_s46/F
10.546 0.000 tNET RR 1 R12C57[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.600 1.917 tNET RR 1 R12C57[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_8_s0/CLK
12.536 -0.064 tSu 1 R12C57[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_8_s0

Path Statistics:

Clock Skew -0.048
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%
Arrival Data Path Delay cell: 1.275, 16.142%; route: 6.256, 79.206%; tC2Q: 0.368, 4.653%
Required Clock Path Delay cell: 0.683, 26.253%; route: 1.917, 73.747%

Path2

Path Summary:

Slack 2.354
Data Arrival Time 9.942
Data Required Time 12.297
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/I0
5.935 0.526 tINS RR 64 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/F
9.943 4.008 tNET RR 1 R33C40[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.608 1.926 tNET RR 1 R33C40[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_14_s0/CLK
12.297 -0.311 tSu 1 R33C40[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_14_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 14.286%; route: 5.872, 80.473%; tC2Q: 0.382, 5.242%
Required Clock Path Delay cell: 0.683, 26.168%; route: 1.926, 73.832%

Path3

Path Summary:

Slack 2.354
Data Arrival Time 9.942
Data Required Time 12.297
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/I0
5.935 0.526 tINS RR 64 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/F
9.943 4.008 tNET RR 1 R33C40[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.608 1.926 tNET RR 1 R33C40[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_13_s0/CLK
12.297 -0.311 tSu 1 R33C40[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_13_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 14.286%; route: 5.872, 80.473%; tC2Q: 0.382, 5.242%
Required Clock Path Delay cell: 0.683, 26.168%; route: 1.926, 73.832%

Path4

Path Summary:

Slack 2.364
Data Arrival Time 10.172
Data Required Time 12.537
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.648 1.965 tNET RR 1 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/CLK
3.015 0.368 tC2Q RF 481 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q
8.725 5.710 tNET FF 1 R16C55[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n634_s52/I2
9.241 0.516 tINS FR 1 R16C55[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n634_s52/F
9.241 0.000 tNET RR 1 R16C55[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n634_s48/I1
9.377 0.136 tINS RR 1 R16C55[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n634_s48/O
9.377 0.000 tNET RR 1 R16C55[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n634_s45/I1
9.464 0.086 tINS RR 1 R16C55[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n634_s45/O
9.656 0.192 tNET RR 1 R16C55[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n634_s46/I2
10.172 0.516 tINS RR 1 R16C55[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n634_s46/F
10.172 0.000 tNET RR 1 R16C55[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.601 1.918 tNET RR 1 R16C55[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_15_s0/CLK
12.537 -0.064 tSu 1 R16C55[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_15_s0

Path Statistics:

Clock Skew -0.047
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%
Arrival Data Path Delay cell: 1.255, 16.678%; route: 5.903, 78.439%; tC2Q: 0.368, 4.884%
Required Clock Path Delay cell: 0.683, 26.244%; route: 1.918, 73.756%

Path5

Path Summary:

Slack 2.366
Data Arrival Time 9.943
Data Required Time 12.308
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/I0
5.935 0.526 tINS RR 64 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/F
9.943 4.008 tNET RR 1 R34C41[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.619 1.937 tNET RR 1 R34C41[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_10_s0/CLK
12.308 -0.311 tSu 1 R34C41[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_10_s0

Path Statistics:

Clock Skew -0.026
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 14.286%; route: 5.872, 80.473%; tC2Q: 0.382, 5.242%
Required Clock Path Delay cell: 0.683, 26.056%; route: 1.937, 73.944%

Path6

Path Summary:

Slack 2.380
Data Arrival Time 10.167
Data Required Time 12.548
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.648 1.965 tNET RR 1 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/CLK
3.015 0.368 tC2Q RF 481 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q
8.755 5.740 tNET FF 1 R15C57[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n649_s52/I2
9.271 0.516 tINS FR 1 R15C57[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n649_s52/F
9.271 0.000 tNET RR 1 R15C57[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n649_s48/I1
9.408 0.136 tINS RR 1 R15C57[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n649_s48/O
9.408 0.000 tNET RR 1 R15C57[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n649_s45/I1
9.494 0.086 tINS RR 1 R15C57[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n649_s45/O
9.651 0.157 tNET RR 1 R14C57[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n649_s46/I2
10.168 0.516 tINS RR 1 R14C57[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n649_s46/F
10.168 0.000 tNET RR 1 R14C57[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R14C57[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_0_s0/CLK
12.548 -0.064 tSu 1 R14C57[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_0_s0

Path Statistics:

Clock Skew -0.036
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%
Arrival Data Path Delay cell: 1.255, 16.689%; route: 5.898, 78.424%; tC2Q: 0.368, 4.887%
Required Clock Path Delay cell: 0.683, 26.134%; route: 1.929, 73.866%

Path7

Path Summary:

Slack 2.546
Data Arrival Time 9.752
Data Required Time 12.299
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/I0
5.935 0.526 tINS RR 64 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/F
9.752 3.817 tNET RR 1 R34C42[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_11_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R34C42[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_11_s0/CLK
12.299 -0.311 tSu 1 R34C42[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_11_s0

Path Statistics:

Clock Skew -0.035
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 14.668%; route: 5.682, 79.951%; tC2Q: 0.382, 5.382%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path8

Path Summary:

Slack 2.646
Data Arrival Time 9.644
Data Required Time 12.289
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/I3
5.935 0.526 tINS RR 64 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/F
9.644 3.709 tNET RR 1 R34C39[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.601 1.918 tNET RR 1 R34C39[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_13_s0/CLK
12.289 -0.311 tSu 1 R34C39[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_13_s0

Path Statistics:

Clock Skew -0.044
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 14.896%; route: 5.574, 79.639%; tC2Q: 0.382, 5.465%
Required Clock Path Delay cell: 0.683, 26.244%; route: 1.918, 73.756%

Path9

Path Summary:

Slack 2.713
Data Arrival Time 9.831
Data Required Time 12.544
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.648 1.965 tNET RR 1 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/CLK
3.015 0.368 tC2Q RF 481 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q
8.024 5.009 tNET FF 1 R15C52[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n644_s50/I2
8.314 0.290 tINS FF 1 R15C52[3][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n644_s50/F
8.314 0.000 tNET FF 1 R15C52[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n644_s47/I1
8.510 0.196 tINS FF 1 R15C52[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n644_s47/O
8.510 0.000 tNET FF 1 R15C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n644_s45/I0
8.611 0.101 tINS FF 1 R15C52[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n644_s45/O
9.305 0.694 tNET FF 1 R15C52[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n644_s46/I2
9.831 0.526 tINS FR 1 R15C52[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n644_s46/F
9.831 0.000 tNET RR 1 R15C52[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.608 1.926 tNET RR 1 R15C52[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_5_s0/CLK
12.544 -0.064 tSu 1 R15C52[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_5_s0

Path Statistics:

Clock Skew -0.039
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%
Arrival Data Path Delay cell: 1.114, 15.504%; route: 5.702, 79.381%; tC2Q: 0.368, 5.116%
Required Clock Path Delay cell: 0.683, 26.168%; route: 1.926, 73.832%

Path10

Path Summary:

Slack 2.732
Data Arrival Time 9.810
Data Required Time 12.542
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.648 1.965 tNET RR 1 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/CLK
3.015 0.368 tC2Q RF 481 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q
7.813 4.798 tNET FF 1 R13C53[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n646_s49/I2
8.334 0.521 tINS FR 1 R13C53[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n646_s49/F
8.334 0.000 tNET RR 1 R13C53[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n646_s47/I0
8.470 0.136 tINS RR 1 R13C53[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n646_s47/O
8.470 0.000 tNET RR 1 R13C53[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n646_s45/I0
8.556 0.086 tINS RR 1 R13C53[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n646_s45/O
9.284 0.728 tNET RR 1 R13C53[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n646_s46/I2
9.810 0.526 tINS RR 1 R13C53[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n646_s46/F
9.810 0.000 tNET RR 1 R13C53[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.606 1.923 tNET RR 1 R13C53[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_3_s0/CLK
12.542 -0.064 tSu 1 R13C53[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_3_s0

Path Statistics:

Clock Skew -0.042
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%
Arrival Data Path Delay cell: 1.270, 17.731%; route: 5.525, 77.138%; tC2Q: 0.368, 5.131%
Required Clock Path Delay cell: 0.683, 26.193%; route: 1.923, 73.807%

Path11

Path Summary:

Slack 2.751
Data Arrival Time 9.781
Data Required Time 12.533
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.648 1.965 tNET RR 1 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/CLK
3.015 0.368 tC2Q RF 481 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q
8.534 5.519 tNET FF 1 R14C56[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n648_s53/I2
8.916 0.382 tINS FF 1 R14C56[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n648_s53/F
8.916 0.000 tNET FF 1 R14C56[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n648_s44/I0
9.113 0.196 tINS FF 1 R14C56[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n648_s44/O
9.255 0.142 tNET FF 1 R13C56[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n648_s46/I1
9.781 0.526 tINS FR 1 R13C56[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n648_s46/F
9.781 0.000 tNET RR 1 R13C56[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.596 1.914 tNET RR 1 R13C56[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_1_s0/CLK
12.533 -0.064 tSu 1 R13C56[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_1_s0

Path Statistics:

Clock Skew -0.051
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%
Arrival Data Path Delay cell: 1.105, 15.490%; route: 5.661, 79.359%; tC2Q: 0.368, 5.152%
Required Clock Path Delay cell: 0.683, 26.288%; route: 1.914, 73.712%

Path12

Path Summary:

Slack 2.819
Data Arrival Time 9.481
Data Required Time 12.300
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/I3
5.935 0.526 tINS RR 64 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/F
9.481 3.546 tNET RR 1 R32C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R32C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_14_s0/CLK
12.300 -0.311 tSu 1 R32C41[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_14_s0

Path Statistics:

Clock Skew -0.033
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 15.250%; route: 5.411, 79.155%; tC2Q: 0.382, 5.595%
Required Clock Path Delay cell: 0.683, 26.134%; route: 1.929, 73.866%

Path13

Path Summary:

Slack 2.819
Data Arrival Time 9.481
Data Required Time 12.300
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/I3
5.935 0.526 tINS RR 64 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/F
9.481 3.546 tNET RR 1 R32C41[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_12_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.612 1.929 tNET RR 1 R32C41[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_12_s0/CLK
12.300 -0.311 tSu 1 R32C41[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_12_s0

Path Statistics:

Clock Skew -0.033
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 15.250%; route: 5.411, 79.155%; tC2Q: 0.382, 5.595%
Required Clock Path Delay cell: 0.683, 26.134%; route: 1.929, 73.866%

Path14

Path Summary:

Slack 2.921
Data Arrival Time 9.368
Data Required Time 12.288
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/I0
5.935 0.526 tINS RR 64 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/F
9.368 3.433 tNET RR 1 R30C41[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.600 1.917 tNET RR 1 R30C41[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_14_s0/CLK
12.288 -0.311 tSu 1 R30C41[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_14_s0

Path Statistics:

Clock Skew -0.045
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 15.508%; route: 5.297, 78.803%; tC2Q: 0.382, 5.690%
Required Clock Path Delay cell: 0.683, 26.253%; route: 1.917, 73.747%

Path15

Path Summary:

Slack 2.921
Data Arrival Time 9.368
Data Required Time 12.288
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/I0
5.935 0.526 tINS RR 64 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/F
9.368 3.433 tNET RR 1 R30C41[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.600 1.917 tNET RR 1 R30C41[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_13_s0/CLK
12.288 -0.311 tSu 1 R30C41[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[6].spram_shift_inst/mem[3]_13_s0

Path Statistics:

Clock Skew -0.045
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 15.508%; route: 5.297, 78.803%; tC2Q: 0.382, 5.690%
Required Clock Path Delay cell: 0.683, 26.253%; route: 1.917, 73.747%

Path16

Path Summary:

Slack 2.929
Data Arrival Time 9.381
Data Required Time 12.310
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/I0
5.935 0.526 tINS RR 64 R20C51[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n971_s2/F
9.381 3.446 tNET RR 1 R35C49[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R35C49[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_0_s0/CLK
12.310 -0.311 tSu 1 R35C49[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[3]_0_s0

Path Statistics:

Clock Skew -0.024
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 15.476%; route: 5.311, 78.846%; tC2Q: 0.382, 5.678%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path17

Path Summary:

Slack 2.940
Data Arrival Time 9.606
Data Required Time 12.546
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.648 1.965 tNET RR 1 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/CLK
3.015 0.368 tC2Q RF 481 R6C29[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addrb_0_s0/Q
8.144 5.129 tNET FF 1 R16C53[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n647_s49/I2
8.665 0.521 tINS FR 1 R16C53[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n647_s49/F
8.665 0.000 tNET RR 1 R16C53[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n647_s47/I0
8.801 0.136 tINS RR 1 R16C53[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n647_s47/O
8.801 0.000 tNET RR 1 R16C53[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n647_s45/I0
8.888 0.086 tINS RR 1 R16C53[2][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n647_s45/O
9.080 0.192 tNET RR 1 R16C54[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n647_s46/I2
9.606 0.526 tINS RR 1 R16C54[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/n647_s46/F
9.606 0.000 tNET RR 1 R16C54[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R16C54[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_2_s0/CLK
12.546 -0.064 tSu 1 R16C54[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[2].spram_shift_inst/data_b_o_2_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.779%; route: 1.965, 74.221%
Arrival Data Path Delay cell: 1.270, 18.250%; route: 5.321, 76.468%; tC2Q: 0.368, 5.281%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Path18

Path Summary:

Slack 3.024
Data Arrival Time 9.286
Data Required Time 12.310
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/I3
5.935 0.526 tINS RR 64 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/F
9.286 3.351 tNET RR 1 R35C45[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_15_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.621 1.939 tNET RR 1 R35C45[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_15_s0/CLK
12.310 -0.311 tSu 1 R35C45[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_15_s0

Path Statistics:

Clock Skew -0.024
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 15.697%; route: 5.216, 78.543%; tC2Q: 0.382, 5.759%
Required Clock Path Delay cell: 0.683, 26.037%; route: 1.939, 73.963%

Path19

Path Summary:

Slack 3.039
Data Arrival Time 9.254
Data Required Time 12.293
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[8].spram_shift_inst/mem[7]_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.601 0.766 tNET RR 1 R21C51[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1035_s0/I3
6.123 0.521 tINS RR 64 R21C51[3][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1035_s0/F
9.254 3.131 tNET RR 1 R36C55[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[8].spram_shift_inst/mem[7]_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.604 1.922 tNET RR 1 R36C55[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[8].spram_shift_inst/mem[7]_3_s0/CLK
12.293 -0.311 tSu 1 R36C55[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[8].spram_shift_inst/mem[7]_3_s0

Path Statistics:

Clock Skew -0.041
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.038, 15.699%; route: 5.189, 78.513%; tC2Q: 0.382, 5.788%
Required Clock Path Delay cell: 0.683, 26.206%; route: 1.922, 73.794%

Path20

Path Summary:

Slack 3.047
Data Arrival Time 9.265
Data Required Time 12.312
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1019_s0/I3
5.935 0.526 tINS RR 64 R20C51[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1019_s0/F
9.265 3.330 tNET RR 1 R36C41[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_10_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.623 1.941 tNET RR 1 R36C41[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_10_s0/CLK
12.312 -0.311 tSu 1 R36C41[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_10_s0

Path Statistics:

Clock Skew -0.022
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 15.748%; route: 5.195, 78.474%; tC2Q: 0.382, 5.778%
Required Clock Path Delay cell: 0.683, 26.019%; route: 1.941, 73.981%

Path21

Path Summary:

Slack 3.076
Data Arrival Time 9.241
Data Required Time 12.318
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/I3
5.935 0.526 tINS RR 64 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/F
9.241 3.306 tNET RR 1 R34C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R34C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_6_s0/CLK
12.318 -0.311 tSu 1 R34C46[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_6_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 15.804%; route: 5.171, 78.397%; tC2Q: 0.382, 5.799%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path22

Path Summary:

Slack 3.076
Data Arrival Time 9.241
Data Required Time 12.318
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/I3
5.935 0.526 tINS RR 64 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/F
9.241 3.306 tNET RR 1 R34C46[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R34C46[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_4_s0/CLK
12.318 -0.311 tSu 1 R34C46[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_4_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 15.804%; route: 5.171, 78.397%; tC2Q: 0.382, 5.799%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path23

Path Summary:

Slack 3.135
Data Arrival Time 9.156
Data Required Time 12.291
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_9_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/I3
5.935 0.526 tINS RR 64 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/F
9.156 3.221 tNET RR 1 R32C44[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_9_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.602 1.920 tNET RR 1 R32C44[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_9_s0/CLK
12.291 -0.311 tSu 1 R32C44[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_9_s0

Path Statistics:

Clock Skew -0.043
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 16.011%; route: 5.086, 78.115%; tC2Q: 0.382, 5.874%
Required Clock Path Delay cell: 0.683, 26.228%; route: 1.920, 73.772%

Path24

Path Summary:

Slack 3.146
Data Arrival Time 9.151
Data Required Time 12.297
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/I3
5.935 0.526 tINS RR 64 R20C51[1][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1003_s0/F
9.151 3.216 tNET RR 1 R33C44[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_8_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.608 1.926 tNET RR 1 R33C44[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_8_s0/CLK
12.297 -0.311 tSu 1 R33C44[1][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[5]_8_s0

Path Statistics:

Clock Skew -0.037
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 16.023%; route: 5.081, 78.098%; tC2Q: 0.382, 5.879%
Required Clock Path Delay cell: 0.683, 26.168%; route: 1.926, 73.832%

Path25

Path Summary:

Slack 3.149
Data Arrival Time 9.150
Data Required Time 12.299
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.683 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
2.645 1.962 tNET RR 1 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/CLK
3.027 0.382 tC2Q RR 4 R7C37[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/delay_shift_addra_3_s0/Q
4.319 1.291 tNET RR 1 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/I0
4.835 0.516 tINS RR 8 R20C46[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n924_s1/F
5.409 0.574 tNET RR 1 R20C51[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1019_s0/I3
5.935 0.526 tINS RR 64 R20C51[0][B] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[5].spram_shift_inst/n1019_s0/F
9.150 3.215 tNET RR 1 R34C40[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.610 1.928 tNET RR 1 R34C40[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_13_s0/CLK
12.299 -0.311 tSu 1 R34C40[2][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_spram_shift[7].spram_shift_inst/mem[6]_13_s0

Path Statistics:

Clock Skew -0.035
Setup Relationship 10.000
Logic Level 3
Arrival Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%
Arrival Data Path Delay cell: 1.043, 16.026%; route: 5.080, 78.094%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.683, 26.149%; route: 1.928, 73.851%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.193
Data Arrival Time 1.604
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C20[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/CLK
1.510 0.141 tC2Q RF 1 R11C20[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/Q
1.604 0.094 tNET FF 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path2

Path Summary:

Slack 0.220
Data Arrival Time 1.632
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.374 0.698 tNET RR 1 R11C21[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK
1.515 0.141 tC2Q RF 1 R11C21[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q
1.632 0.117 tNET FF 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path3

Path Summary:

Slack 0.251
Data Arrival Time 1.661
Data Required Time 1.410
From sim_output_storage_inst/ram_dout_addrb_3_s0
To sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R14C24[2][B] sim_output_storage_inst/ram_dout_addrb_3_s0/CLK
1.513 0.144 tC2Q RR 5 R14C24[2][B] sim_output_storage_inst/ram_dout_addrb_3_s0/Q
1.661 0.148 tNET RR 1 BSRAM_R10[6] sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/ADB[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[6] sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKB
1.410 0.035 tHld 1 BSRAM_R10[6] sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s

Path Statistics:

Clock Skew 0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.148, 50.685%; tC2Q: 0.144, 49.315%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path4

Path Summary:

Slack 0.255
Data Arrival Time 1.661
Data Required Time 1.406
From sim_output_storage_inst/ram_dout_addrb_3_s0
To sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R14C24[2][B] sim_output_storage_inst/ram_dout_addrb_3_s0/CLK
1.513 0.144 tC2Q RR 5 R14C24[2][B] sim_output_storage_inst/ram_dout_addrb_3_s0/Q
1.661 0.148 tNET RR 1 BSRAM_R10[7] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/ADB[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.371 0.695 tNET RR 1 BSRAM_R10[7] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKB
1.406 0.035 tHld 1 BSRAM_R10[7] sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.148, 50.685%; tC2Q: 0.144, 49.315%
Required Clock Path Delay cell: 0.675, 49.289%; route: 0.695, 50.711%

Path5

Path Summary:

Slack 0.257
Data Arrival Time 1.668
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK
1.510 0.141 tC2Q RF 1 R11C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q
1.668 0.158 tNET FF 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path6

Path Summary:

Slack 0.257
Data Arrival Time 1.668
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/CLK
1.510 0.141 tC2Q RF 1 R11C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q
1.668 0.158 tNET FF 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path7

Path Summary:

Slack 0.268
Data Arrival Time 1.683
Data Required Time 1.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.369 0.694 tNET RR 1 R11C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/CLK
1.510 0.141 tC2Q RF 1 R11C28[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q
1.683 0.173 tNET FF 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.378 0.703 tNET RR 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.415 0.037 tHld 1 BSRAM_R10[8] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.173, 55.096%; tC2Q: 0.141, 44.904%
Required Clock Path Delay cell: 0.675, 49.003%; route: 0.703, 50.997%

Path8

Path Summary:

Slack 0.275
Data Arrival Time 1.673
Data Required Time 1.397
From sim_output_storage_inst/ram_dout_addrb_1_s0
To sim_output_storage_inst/ram_dout_addrb_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.372 0.697 tNET RR 1 R14C25[0][A] sim_output_storage_inst/ram_dout_addrb_1_s0/CLK
1.513 0.141 tC2Q RF 7 R14C25[0][A] sim_output_storage_inst/ram_dout_addrb_1_s0/Q
1.520 0.006 tNET FF 1 R14C25[0][A] sim_output_storage_inst/n221_s2/I1
1.673 0.153 tINS FF 1 R14C25[0][A] sim_output_storage_inst/n221_s2/F
1.673 0.000 tNET FF 1 R14C25[0][A] sim_output_storage_inst/ram_dout_addrb_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.372 0.697 tNET RR 1 R14C25[0][A] sim_output_storage_inst/ram_dout_addrb_1_s0/CLK
1.397 0.025 tHld 1 R14C25[0][A] sim_output_storage_inst/ram_dout_addrb_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 49.217%; route: 0.697, 50.783%

Path9

Path Summary:

Slack 0.275
Data Arrival Time 1.673
Data Required Time 1.397
From sim_output_storage_inst/ram_din_addra_2_s0
To sim_output_storage_inst/ram_din_addra_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.372 0.697 tNET RR 1 R14C25[1][A] sim_output_storage_inst/ram_din_addra_2_s0/CLK
1.513 0.141 tC2Q RF 5 R14C25[1][A] sim_output_storage_inst/ram_din_addra_2_s0/Q
1.520 0.006 tNET FF 1 R14C25[1][A] sim_output_storage_inst/n136_s1/I3
1.673 0.153 tINS FF 1 R14C25[1][A] sim_output_storage_inst/n136_s1/F
1.673 0.000 tNET FF 1 R14C25[1][A] sim_output_storage_inst/ram_din_addra_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.372 0.697 tNET RR 1 R14C25[1][A] sim_output_storage_inst/ram_din_addra_2_s0/CLK
1.397 0.025 tHld 1 R14C25[1][A] sim_output_storage_inst/ram_din_addra_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 49.217%; route: 0.697, 50.783%

Path10

Path Summary:

Slack 0.275
Data Arrival Time 1.691
Data Required Time 1.416
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.532 0.141 tC2Q RF 5 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
1.538 0.006 tNET FF 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n318_s0/I2
1.691 0.153 tINS FF 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n318_s0/F
1.691 0.000 tNET FF 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.416 0.025 tHld 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path11

Path Summary:

Slack 0.275
Data Arrival Time 1.699
Data Required Time 1.424
From gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.399 0.723 tNET RR 1 R4C21[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.540 0.141 tC2Q RF 5 R4C21[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/Q
1.546 0.006 tNET FF 1 R4C21[1][A] gw_gao_inst_0/u_la0_top/n2079_s1/I0
1.699 0.153 tINS FF 1 R4C21[1][A] gw_gao_inst_0/u_la0_top/n2079_s1/F
1.699 0.000 tNET FF 1 R4C21[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.399 0.723 tNET RR 1 R4C21[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.424 0.025 tHld 1 R4C21[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.293%; route: 0.723, 51.707%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.675, 48.293%; route: 0.723, 51.707%

Path12

Path Summary:

Slack 0.275
Data Arrival Time 2.727
Data Required Time 2.452
From gw_gao_inst_0/u_la0_top/word_count_1_s0
To gw_gao_inst_0/u_la0_top/word_count_1_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.427 1.076 tNET RR 1 R26C24[1][A] gw_gao_inst_0/u_la0_top/word_count_1_s0/CLK
2.568 0.141 tC2Q RF 5 R26C24[1][A] gw_gao_inst_0/u_la0_top/word_count_1_s0/Q
2.574 0.006 tNET FF 1 R26C24[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_1_s0/I2
2.727 0.153 tINS FF 1 R26C24[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_1_s0/F
2.727 0.000 tNET FF 1 R26C24[1][A] gw_gao_inst_0/u_la0_top/word_count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.427 1.076 tNET RR 1 R26C24[1][A] gw_gao_inst_0/u_la0_top/word_count_1_s0/CLK
2.452 0.025 tHld 1 R26C24[1][A] gw_gao_inst_0/u_la0_top/word_count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.665%; route: 1.076, 44.335%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 55.665%; route: 1.076, 44.335%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 2.734
Data Required Time 2.459
From gw_gao_inst_0/u_la0_top/address_counter_0_s0
To gw_gao_inst_0/u_la0_top/address_counter_0_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.434 1.083 tNET RR 1 R24C24[0][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.575 0.141 tC2Q RF 8 R24C24[0][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q
2.581 0.006 tNET FF 1 R24C24[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_0_s0/I0
2.734 0.153 tINS FF 1 R24C24[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_0_s0/F
2.734 0.000 tNET FF 1 R24C24[0][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.434 1.083 tNET RR 1 R24C24[0][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.459 0.025 tHld 1 R24C24[0][A] gw_gao_inst_0/u_la0_top/address_counter_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.511%; route: 1.083, 44.489%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 55.511%; route: 1.083, 44.489%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 2.730
Data Required Time 2.455
From gw_gao_inst_0/u_la0_top/address_counter_6_s0
To gw_gao_inst_0/u_la0_top/address_counter_6_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.430 1.079 tNET RR 1 R24C23[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/CLK
2.571 0.141 tC2Q RF 6 R24C23[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/Q
2.577 0.006 tNET FF 1 R24C23[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_6_s0/I1
2.730 0.153 tINS FF 1 R24C23[0][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_6_s0/F
2.730 0.000 tNET FF 1 R24C23[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.430 1.079 tNET RR 1 R24C23[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0/CLK
2.455 0.025 tHld 1 R24C23[0][A] gw_gao_inst_0/u_la0_top/address_counter_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.602%; route: 1.079, 44.398%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.351, 55.602%; route: 1.079, 44.398%

Path15

Path Summary:

Slack 0.278
Data Arrival Time 2.702
Data Required Time 2.424
From gw_gao_inst_0/u_la0_top/bit_count_4_s1
To gw_gao_inst_0/u_la0_top/bit_count_4_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.399 1.048 tNET RR 1 R30C23[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1/CLK
2.540 0.141 tC2Q RF 3 R30C23[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1/Q
2.549 0.009 tNET FF 1 R30C23[0][A] gw_gao_inst_0/u_la0_top/n589_s2/I0
2.702 0.153 tINS FF 1 R30C23[0][A] gw_gao_inst_0/u_la0_top/n589_s2/F
2.702 0.000 tNET FF 1 R30C23[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.399 1.048 tNET RR 1 R30C23[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1/CLK
2.424 0.025 tHld 1 R30C23[0][A] gw_gao_inst_0/u_la0_top/bit_count_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 56.315%; route: 1.048, 43.685%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 56.315%; route: 1.048, 43.685%

Path16

Path Summary:

Slack 0.278
Data Arrival Time 2.735
Data Required Time 2.457
From gw_gao_inst_0/u_la0_top/word_count_10_s0
To gw_gao_inst_0/u_la0_top/word_count_10_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.432 1.081 tNET RR 1 R25C24[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/CLK
2.573 0.141 tC2Q RF 3 R25C24[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/Q
2.582 0.009 tNET FF 1 R25C24[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_10_s0/I1
2.735 0.153 tINS FF 1 R25C24[1][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_10_s0/F
2.735 0.000 tNET FF 1 R25C24[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.432 1.081 tNET RR 1 R25C24[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0/CLK
2.457 0.025 tHld 1 R25C24[1][A] gw_gao_inst_0/u_la0_top/word_count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.551%; route: 1.081, 44.449%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 55.551%; route: 1.081, 44.449%

Path17

Path Summary:

Slack 0.278
Data Arrival Time 2.733
Data Required Time 2.455
From gw_gao_inst_0/u_la0_top/address_counter_4_s0
To gw_gao_inst_0/u_la0_top/address_counter_4_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.430 1.079 tNET RR 1 R24C23[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.571 0.141 tC2Q RF 6 R24C23[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q
2.580 0.009 tNET FF 1 R24C23[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/I1
2.733 0.153 tINS FF 1 R24C23[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_4_s0/F
2.733 0.000 tNET FF 1 R24C23[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.675 0.675 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.675 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351 0.675 tINS RR 259 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.430 1.079 tNET RR 1 R24C23[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.455 0.025 tHld 1 R24C23[1][A] gw_gao_inst_0/u_la0_top/address_counter_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.351, 55.602%; route: 1.079, 44.398%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 1.351, 55.602%; route: 1.079, 44.398%

Path18

Path Summary:

Slack 0.278
Data Arrival Time 1.668
Data Required Time 1.390
From sim_output_storage_inst/cnt_chn_1_s0
To sim_output_storage_inst/cnt_chn_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R13C24[0][A] sim_output_storage_inst/cnt_chn_1_s0/CLK
1.506 0.141 tC2Q RF 5 R13C24[0][A] sim_output_storage_inst/cnt_chn_1_s0/Q
1.515 0.009 tNET FF 1 R13C24[0][A] sim_output_storage_inst/n79_s1/I0
1.668 0.153 tINS FF 1 R13C24[0][A] sim_output_storage_inst/n79_s1/F
1.668 0.000 tNET FF 1 R13C24[0][A] sim_output_storage_inst/cnt_chn_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.365 0.689 tNET RR 1 R13C24[0][A] sim_output_storage_inst/cnt_chn_1_s0/CLK
1.390 0.025 tHld 1 R13C24[0][A] sim_output_storage_inst/cnt_chn_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.505%; route: 0.689, 50.495%

Path19

Path Summary:

Slack 0.278
Data Arrival Time 1.671
Data Required Time 1.393
From sim_output_storage_inst/ram_dout_addrb_6_s0
To sim_output_storage_inst/ram_dout_addrb_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R13C25[0][A] sim_output_storage_inst/ram_dout_addrb_6_s0/CLK
1.510 0.141 tC2Q RF 5 R13C25[0][A] sim_output_storage_inst/ram_dout_addrb_6_s0/Q
1.518 0.009 tNET FF 1 R13C25[0][A] sim_output_storage_inst/n216_s5/I0
1.671 0.153 tINS FF 1 R13C25[0][A] sim_output_storage_inst/n216_s5/F
1.671 0.000 tNET FF 1 R13C25[0][A] sim_output_storage_inst/ram_dout_addrb_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R13C25[0][A] sim_output_storage_inst/ram_dout_addrb_6_s0/CLK
1.393 0.025 tHld 1 R13C25[0][A] sim_output_storage_inst/ram_dout_addrb_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%

Path20

Path Summary:

Slack 0.278
Data Arrival Time 1.671
Data Required Time 1.393
From sim_output_storage_inst/ram_din_addra_0_s0
To sim_output_storage_inst/ram_din_addra_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R14C26[0][A] sim_output_storage_inst/ram_din_addra_0_s0/CLK
1.510 0.141 tC2Q RF 7 R14C26[0][A] sim_output_storage_inst/ram_din_addra_0_s0/Q
1.518 0.009 tNET FF 1 R14C26[0][A] sim_output_storage_inst/n138_s3/I3
1.671 0.153 tINS FF 1 R14C26[0][A] sim_output_storage_inst/n138_s3/F
1.671 0.000 tNET FF 1 R14C26[0][A] sim_output_storage_inst/ram_din_addra_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R14C26[0][A] sim_output_storage_inst/ram_din_addra_0_s0/CLK
1.393 0.025 tHld 1 R14C26[0][A] sim_output_storage_inst/ram_din_addra_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%

Path21

Path Summary:

Slack 0.278
Data Arrival Time 1.671
Data Required Time 1.393
From sim_output_storage_inst/ram_din_addra_3_s0
To sim_output_storage_inst/ram_din_addra_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R14C26[1][A] sim_output_storage_inst/ram_din_addra_3_s0/CLK
1.510 0.141 tC2Q RF 4 R14C26[1][A] sim_output_storage_inst/ram_din_addra_3_s0/Q
1.518 0.009 tNET FF 1 R14C26[1][A] sim_output_storage_inst/n135_s1/I2
1.671 0.153 tINS FF 1 R14C26[1][A] sim_output_storage_inst/n135_s1/F
1.671 0.000 tNET FF 1 R14C26[1][A] sim_output_storage_inst/ram_din_addra_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.368 0.693 tNET RR 1 R14C26[1][A] sim_output_storage_inst/ram_din_addra_3_s0/CLK
1.393 0.025 tHld 1 R14C26[1][A] sim_output_storage_inst/ram_din_addra_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.361%; route: 0.693, 50.639%

Path22

Path Summary:

Slack 0.278
Data Arrival Time 1.680
Data Required Time 1.402
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/coeff_ram_addrb_1_s3
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/coeff_ram_addrb_1_s3
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.377 0.701 tNET RR 1 R15C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/coeff_ram_addrb_1_s3/CLK
1.518 0.141 tC2Q RF 81 R15C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/coeff_ram_addrb_1_s3/Q
1.527 0.009 tNET FF 1 R15C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2106_s2/I0
1.680 0.153 tINS FF 1 R15C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2106_s2/F
1.680 0.000 tNET FF 1 R15C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/coeff_ram_addrb_1_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.377 0.701 tNET RR 1 R15C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/coeff_ram_addrb_1_s3/CLK
1.402 0.025 tHld 1 R15C25[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/coeff_ram_addrb_1_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.074%; route: 0.701, 50.926%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.074%; route: 0.701, 50.926%

Path23

Path Summary:

Slack 0.278
Data Arrival Time 1.678
Data Required Time 1.400
From Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/cnt_acc_chn_1_s0
To Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/cnt_acc_chn_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.375 0.700 tNET RR 1 R35C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/cnt_acc_chn_1_s0/CLK
1.516 0.141 tC2Q RF 3 R35C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/cnt_acc_chn_1_s0/Q
1.525 0.009 tNET FF 1 R35C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2652_s1/I0
1.678 0.153 tINS FF 1 R35C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/n2652_s1/F
1.678 0.000 tNET FF 1 R35C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/cnt_acc_chn_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.375 0.700 tNET RR 1 R35C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/cnt_acc_chn_1_s0/CLK
1.400 0.025 tHld 1 R35C26[0][A] Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/cnt_acc_chn_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 49.127%; route: 0.700, 50.873%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 49.127%; route: 0.700, 50.873%

Path24

Path Summary:

Slack 0.278
Data Arrival Time 1.689
Data Required Time 1.411
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.365 0.690 tNET RR 1 R11C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/CLK
1.510 0.144 tC2Q RR 1 R11C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q
1.689 0.180 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.375 0.699 tNET RR 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.411 0.037 tHld 1 BSRAM_R10[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.180, 55.556%; tC2Q: 0.144, 44.444%
Required Clock Path Delay cell: 0.675, 49.145%; route: 0.699, 50.855%

Path25

Path Summary:

Slack 0.278
Data Arrival Time 1.698
Data Required Time 1.420
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.395 0.720 tNET RR 1 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.536 0.141 tC2Q RF 7 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.545 0.009 tNET FF 1 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n410_s1/I1
1.698 0.153 tINS FF 1 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n410_s1/F
1.698 0.000 tNET FF 1 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.395 0.720 tNET RR 1 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.420 0.025 tHld 1 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.414%; route: 0.720, 51.586%
Arrival Data Path Delay cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay cell: 0.675, 48.414%; route: 0.720, 51.586%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.847
Data Arrival Time 9.437
Data Required Time 12.284
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.437 1.337 tNET FF 1 R23C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.631 1.949 tNET RR 1 R23C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
12.284 -0.347 tSu 1 R23C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew -0.026
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.337, 75.140%; tC2Q: 0.442, 24.860%
Required Clock Path Delay cell: 0.683, 25.938%; route: 1.949, 74.062%

Path2

Path Summary:

Slack 3.040
Data Arrival Time 9.253
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.253 1.154 tNET FF 1 R23C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R23C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
12.293 -0.347 tSu 1 R23C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew -0.017
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.154, 72.279%; tC2Q: 0.442, 27.721%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path3

Path Summary:

Slack 3.040
Data Arrival Time 9.253
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.253 1.154 tNET FF 1 R23C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R23C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
12.293 -0.347 tSu 1 R23C22[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew -0.017
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.154, 72.279%; tC2Q: 0.442, 27.721%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path4

Path Summary:

Slack 3.222
Data Arrival Time 9.037
Data Required Time 12.259
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.037 0.938 tNET FF 1 R11C20[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.607 1.924 tNET RR 1 R11C20[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
12.259 -0.347 tSu 1 R11C20[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew -0.050
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.938, 67.935%; tC2Q: 0.442, 32.065%
Required Clock Path Delay cell: 0.683, 26.181%; route: 1.924, 73.819%

Path5

Path Summary:

Slack 3.222
Data Arrival Time 9.037
Data Required Time 12.259
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.037 0.938 tNET FF 1 R11C20[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.607 1.924 tNET RR 1 R11C20[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
12.259 -0.347 tSu 1 R11C20[0][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew -0.050
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.938, 67.935%; tC2Q: 0.442, 32.065%
Required Clock Path Delay cell: 0.683, 26.181%; route: 1.924, 73.819%

Path6

Path Summary:

Slack 3.407
Data Arrival Time 8.886
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.886 0.786 tNET FF 1 R5C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
12.293 -0.347 tSu 1 R5C24[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew -0.017
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.786, 63.988%; tC2Q: 0.442, 36.012%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path7

Path Summary:

Slack 3.407
Data Arrival Time 8.886
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.886 0.786 tNET FF 1 R5C24[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C24[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
12.293 -0.347 tSu 1 R5C24[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew -0.017
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.786, 63.988%; tC2Q: 0.442, 36.012%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path8

Path Summary:

Slack 3.407
Data Arrival Time 8.886
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.886 0.786 tNET FF 1 R5C24[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C24[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
12.293 -0.347 tSu 1 R5C24[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew -0.017
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.786, 63.988%; tC2Q: 0.442, 36.012%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path9

Path Summary:

Slack 3.510
Data Arrival Time 8.781
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.781 0.681 tNET FF 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
12.291 -0.347 tSu 1 R6C24[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.681, 60.623%; tC2Q: 0.442, 39.377%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path10

Path Summary:

Slack 3.510
Data Arrival Time 8.781
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.781 0.681 tNET FF 1 R6C24[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C24[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
12.291 -0.347 tSu 1 R6C24[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.681, 60.623%; tC2Q: 0.442, 39.377%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path11

Path Summary:

Slack 3.510
Data Arrival Time 8.781
Data Required Time 12.291
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.781 0.681 tNET FF 1 R6C24[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.638 1.956 tNET RR 1 R6C24[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
12.291 -0.347 tSu 1 R6C24[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.681, 60.623%; tC2Q: 0.442, 39.377%
Required Clock Path Delay cell: 0.683, 25.871%; route: 1.956, 74.129%

Path12

Path Summary:

Slack 3.532
Data Arrival Time 8.747
Data Required Time 12.279
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.747 0.647 tNET FF 1 R7C23[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.626 1.944 tNET RR 1 R7C23[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
12.279 -0.347 tSu 1 R7C23[0][A] gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew -0.031
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.647, 59.404%; tC2Q: 0.442, 40.596%
Required Clock Path Delay cell: 0.683, 25.988%; route: 1.944, 74.012%

Path13

Path Summary:

Slack 3.541
Data Arrival Time 8.747
Data Required Time 12.288
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.747 0.647 tNET FF 1 R7C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.636 1.953 tNET RR 1 R7C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
12.288 -0.347 tSu 1 R7C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew -0.022
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.647, 59.404%; tC2Q: 0.442, 40.596%
Required Clock Path Delay cell: 0.683, 25.895%; route: 1.953, 74.105%

Path14

Path Summary:

Slack 3.567
Data Arrival Time 8.731
Data Required Time 12.298
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.731 0.631 tNET FF 1 R3C24[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.646 1.963 tNET RR 1 R3C24[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
12.298 -0.347 tSu 1 R3C24[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew -0.012
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.631, 58.789%; tC2Q: 0.442, 41.211%
Required Clock Path Delay cell: 0.683, 25.797%; route: 1.963, 74.203%

Path15

Path Summary:

Slack 3.635
Data Arrival Time 8.662
Data Required Time 12.298
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.662 0.563 tNET FF 1 R7C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.645 1.962 tNET RR 1 R7C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
12.298 -0.347 tSu 1 R7C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew -0.012
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.563, 55.970%; tC2Q: 0.442, 44.030%
Required Clock Path Delay cell: 0.683, 25.803%; route: 1.962, 74.197%

Path16

Path Summary:

Slack 3.694
Data Arrival Time 8.590
Data Required Time 12.284
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.590 0.490 tNET FF 1 R5C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.631 1.949 tNET RR 1 R5C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
12.284 -0.347 tSu 1 R5C23[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.490, 52.547%; tC2Q: 0.442, 47.453%
Required Clock Path Delay cell: 0.683, 25.938%; route: 1.949, 74.062%

Path17

Path Summary:

Slack 3.694
Data Arrival Time 8.590
Data Required Time 12.284
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.590 0.490 tNET FF 1 R5C23[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.631 1.949 tNET RR 1 R5C23[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
12.284 -0.347 tSu 1 R5C23[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.490, 52.547%; tC2Q: 0.442, 47.453%
Required Clock Path Delay cell: 0.683, 25.938%; route: 1.949, 74.062%

Path18

Path Summary:

Slack 3.694
Data Arrival Time 8.590
Data Required Time 12.284
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.590 0.490 tNET FF 1 R5C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.631 1.949 tNET RR 1 R5C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
12.284 -0.347 tSu 1 R5C23[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.490, 52.547%; tC2Q: 0.442, 47.453%
Required Clock Path Delay cell: 0.683, 25.938%; route: 1.949, 74.062%

Path19

Path Summary:

Slack 3.694
Data Arrival Time 8.590
Data Required Time 12.284
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.590 0.490 tNET FF 1 R5C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.631 1.949 tNET RR 1 R5C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
12.284 -0.347 tSu 1 R5C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.490, 52.547%; tC2Q: 0.442, 47.453%
Required Clock Path Delay cell: 0.683, 25.938%; route: 1.949, 74.062%

Path20

Path Summary:

Slack 3.702
Data Arrival Time 8.580
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.580 0.480 tNET FF 1 R6C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R6C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
12.281 -0.347 tSu 1 R6C23[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.480, 52.033%; tC2Q: 0.442, 47.967%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path21

Path Summary:

Slack 3.702
Data Arrival Time 8.580
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.580 0.480 tNET FF 1 R6C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R6C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
12.281 -0.347 tSu 1 R6C23[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.480, 52.033%; tC2Q: 0.442, 47.967%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path22

Path Summary:

Slack 3.702
Data Arrival Time 8.580
Data Required Time 12.281
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.580 0.480 tNET FF 1 R6C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.629 1.946 tNET RR 1 R6C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
12.281 -0.347 tSu 1 R6C23[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.480, 52.033%; tC2Q: 0.442, 47.967%
Required Clock Path Delay cell: 0.683, 25.963%; route: 1.946, 74.037%

Path23

Path Summary:

Slack 3.703
Data Arrival Time 8.590
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.590 0.490 tNET FF 1 R5C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
12.293 -0.347 tSu 1 R5C22[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew -0.017
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.490, 52.547%; tC2Q: 0.442, 47.453%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path24

Path Summary:

Slack 3.703
Data Arrival Time 8.590
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.590 0.490 tNET FF 1 R5C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.293 -0.347 tSu 1 R5C22[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew -0.017
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.490, 52.547%; tC2Q: 0.442, 47.453%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Path25

Path Summary:

Slack 3.703
Data Arrival Time 8.590
Data Required Time 12.293
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.688 0.688 tINS FF 3345 IOB29[A] clk_ibuf/O
7.657 1.970 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.100 0.442 tC2Q FF 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
8.590 0.490 tNET FF 1 R5C22[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
10.682 0.683 tINS RR 3345 IOB29[A] clk_ibuf/O
12.641 1.958 tNET RR 1 R5C22[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
12.293 -0.347 tSu 1 R5C22[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew -0.017
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.688, 25.873%; route: 1.970, 74.127%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.490, 52.547%; tC2Q: 0.442, 47.453%
Required Clock Path Delay cell: 0.683, 25.846%; route: 1.958, 74.154%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 5.308
Data Arrival Time 6.654
Data Required Time 1.346
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.654 0.090 tNET RR 1 R4C21[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.399 0.723 tNET RR 1 R4C21[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.346 -0.053 tHld 1 R4C21[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew -0.007
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.090, 36.290%; tC2Q: 0.158, 63.710%
Required Clock Path Delay cell: 0.675, 48.293%; route: 0.723, 51.707%

Path2

Path Summary:

Slack 5.340
Data Arrival Time 6.681
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C22[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.395 0.719 tNET RR 1 R4C22[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.342 -0.053 tHld 1 R4C22[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.432%; route: 0.719, 51.568%

Path3

Path Summary:

Slack 5.340
Data Arrival Time 6.681
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C22[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.395 0.719 tNET RR 1 R4C22[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.342 -0.053 tHld 1 R4C22[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.432%; route: 0.719, 51.568%

Path4

Path Summary:

Slack 5.340
Data Arrival Time 6.681
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C22[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.395 0.719 tNET RR 1 R4C22[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.342 -0.053 tHld 1 R4C22[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.432%; route: 0.719, 51.568%

Path5

Path Summary:

Slack 5.340
Data Arrival Time 6.681
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C22[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.395 0.719 tNET RR 1 R4C22[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.342 -0.053 tHld 1 R4C22[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.432%; route: 0.719, 51.568%

Path6

Path Summary:

Slack 5.340
Data Arrival Time 6.681
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C22[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.395 0.719 tNET RR 1 R4C22[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.342 -0.053 tHld 1 R4C22[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.432%; route: 0.719, 51.568%

Path7

Path Summary:

Slack 5.344
Data Arrival Time 6.681
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C23[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.391 0.715 tNET RR 1 R4C23[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
1.338 -0.053 tHld 1 R4C23[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew -0.015
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.571%; route: 0.715, 51.429%

Path8

Path Summary:

Slack 5.344
Data Arrival Time 6.681
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C23[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.391 0.715 tNET RR 1 R4C23[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.338 -0.053 tHld 1 R4C23[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew -0.015
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.571%; route: 0.715, 51.429%

Path9

Path Summary:

Slack 5.344
Data Arrival Time 6.681
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C23[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.391 0.715 tNET RR 1 R4C23[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.338 -0.053 tHld 1 R4C23[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew -0.015
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.571%; route: 0.715, 51.429%

Path10

Path Summary:

Slack 5.344
Data Arrival Time 6.681
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C23[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.391 0.715 tNET RR 1 R4C23[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.338 -0.053 tHld 1 R4C23[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew -0.015
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.571%; route: 0.715, 51.429%

Path11

Path Summary:

Slack 5.344
Data Arrival Time 6.681
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.681 0.118 tNET RR 1 R4C23[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.391 0.715 tNET RR 1 R4C23[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.338 -0.053 tHld 1 R4C23[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew -0.015
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 42.754%; tC2Q: 0.158, 57.246%
Required Clock Path Delay cell: 0.675, 48.571%; route: 0.715, 51.429%

Path12

Path Summary:

Slack 5.401
Data Arrival Time 6.748
Data Required Time 1.348
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.748 0.185 tNET RR 1 R3C21[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.401 0.725 tNET RR 1 R3C21[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.348 -0.053 tHld 1 R3C21[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew -0.005
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.185, 53.936%; tC2Q: 0.158, 46.064%
Required Clock Path Delay cell: 0.675, 48.233%; route: 0.725, 51.767%

Path13

Path Summary:

Slack 5.412
Data Arrival Time 6.754
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.754 0.191 tNET RR 1 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.395 0.720 tNET RR 1 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.342 -0.053 tHld 1 R6C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew -0.010
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 54.728%; tC2Q: 0.158, 45.272%
Required Clock Path Delay cell: 0.675, 48.414%; route: 0.720, 51.586%

Path14

Path Summary:

Slack 5.412
Data Arrival Time 6.754
Data Required Time 1.342
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.754 0.191 tNET RR 1 R6C21[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.395 0.720 tNET RR 1 R6C21[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.342 -0.053 tHld 1 R6C21[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew -0.010
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.191, 54.728%; tC2Q: 0.158, 45.272%
Required Clock Path Delay cell: 0.675, 48.414%; route: 0.720, 51.586%

Path15

Path Summary:

Slack 5.413
Data Arrival Time 6.758
Data Required Time 1.344
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.757 0.194 tNET RR 1 R5C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.397 0.722 tNET RR 1 R5C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.344 -0.053 tHld 1 R5C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew -0.008
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.194, 55.114%; tC2Q: 0.158, 44.886%
Required Clock Path Delay cell: 0.675, 48.354%; route: 0.722, 51.646%

Path16

Path Summary:

Slack 5.413
Data Arrival Time 6.758
Data Required Time 1.344
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.757 0.194 tNET RR 1 R5C21[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.397 0.722 tNET RR 1 R5C21[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
1.344 -0.053 tHld 1 R5C21[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew -0.008
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.194, 55.114%; tC2Q: 0.158, 44.886%
Required Clock Path Delay cell: 0.675, 48.354%; route: 0.722, 51.646%

Path17

Path Summary:

Slack 5.436
Data Arrival Time 6.780
Data Required Time 1.344
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.780 0.216 tNET RR 1 R3C22[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.397 0.721 tNET RR 1 R3C22[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
1.344 -0.053 tHld 1 R3C22[2][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -0.009
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.216, 57.754%; tC2Q: 0.158, 42.246%
Required Clock Path Delay cell: 0.675, 48.371%; route: 0.721, 51.629%

Path18

Path Summary:

Slack 5.436
Data Arrival Time 6.780
Data Required Time 1.344
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.780 0.216 tNET RR 1 R3C22[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.397 0.721 tNET RR 1 R3C22[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
1.344 -0.053 tHld 1 R3C22[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew -0.009
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.216, 57.754%; tC2Q: 0.158, 42.246%
Required Clock Path Delay cell: 0.675, 48.371%; route: 0.721, 51.629%

Path19

Path Summary:

Slack 5.440
Data Arrival Time 6.780
Data Required Time 1.339
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.780 0.216 tNET RR 1 R3C23[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.392 0.717 tNET RR 1 R3C23[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
1.339 -0.053 tHld 1 R3C23[0][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.216, 57.754%; tC2Q: 0.158, 42.246%
Required Clock Path Delay cell: 0.675, 48.510%; route: 0.717, 51.490%

Path20

Path Summary:

Slack 5.440
Data Arrival Time 6.780
Data Required Time 1.339
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.780 0.216 tNET RR 1 R3C23[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.392 0.717 tNET RR 1 R3C23[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
1.339 -0.053 tHld 1 R3C23[1][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.216, 57.754%; tC2Q: 0.158, 42.246%
Required Clock Path Delay cell: 0.675, 48.510%; route: 0.717, 51.490%

Path21

Path Summary:

Slack 5.440
Data Arrival Time 6.780
Data Required Time 1.339
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.780 0.216 tNET RR 1 R3C23[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.392 0.717 tNET RR 1 R3C23[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
1.339 -0.053 tHld 1 R3C23[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.216, 57.754%; tC2Q: 0.158, 42.246%
Required Clock Path Delay cell: 0.675, 48.510%; route: 0.717, 51.490%

Path22

Path Summary:

Slack 5.440
Data Arrival Time 6.780
Data Required Time 1.339
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.780 0.216 tNET RR 1 R3C23[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.392 0.717 tNET RR 1 R3C23[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
1.339 -0.053 tHld 1 R3C23[2][B] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.216, 57.754%; tC2Q: 0.158, 42.246%
Required Clock Path Delay cell: 0.675, 48.510%; route: 0.717, 51.490%

Path23

Path Summary:

Slack 5.440
Data Arrival Time 6.780
Data Required Time 1.339
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.780 0.216 tNET RR 1 R3C23[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.392 0.717 tNET RR 1 R3C23[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.339 -0.053 tHld 1 R3C23[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew -0.013
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.216, 57.754%; tC2Q: 0.158, 42.246%
Required Clock Path Delay cell: 0.675, 48.510%; route: 0.717, 51.490%

Path24

Path Summary:

Slack 5.447
Data Arrival Time 6.786
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.786 0.222 tNET RR 1 R6C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.338 -0.053 tHld 1 R6C22[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew -0.014
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.222, 58.421%; tC2Q: 0.158, 41.579%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Path25

Path Summary:

Slack 5.447
Data Arrival Time 6.786
Data Required Time 1.338
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk clk:[F]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF 1 IOB29[A] clk_ibuf/I
5.677 0.678 tINS FF 3345 IOB29[A] clk_ibuf/O
6.405 0.728 tNET FF 1 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.563 0.158 tC2Q FR 53 R4C21[0][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.786 0.222 tNET RR 1 R6C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOB29[A] clk_ibuf/I
0.675 0.675 tINS RR 3345 IOB29[A] clk_ibuf/O
1.391 0.716 tNET RR 1 R6C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.338 -0.053 tHld 1 R6C22[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew -0.014
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.678, 48.203%; route: 0.728, 51.797%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.222, 58.421%; tC2Q: 0.158, 41.579%
Required Clock Path Delay cell: 0.675, 48.553%; route: 0.716, 51.447%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.751
Actual Width: 3.751
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.627 1.940 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.703 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack: 2.751
Actual Width: 3.751
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.627 1.940 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.703 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW3

MPW Summary:

Slack: 2.754
Actual Width: 3.754
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.628 1.940 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.382 0.706 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[0].mult_dsp_inst/n47_s1/CLK[0]

MPW4

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR sim_output_storage_inst/spram_dout_inst/mem_mem_0_0_s/CLKA

MPW5

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR sim_output_storage_inst/spram_dout_inst/gowin_add_SDPB_mem_mem_0_0_s/CLKB

MPW6

MPW Summary:

Slack: 2.757
Actual Width: 3.757
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.930 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.375 0.699 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW7

MPW Summary:

Slack: 2.759
Actual Width: 3.759
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[2].mult_dsp_inst/n47_s1

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.931 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[2].mult_dsp_inst/n47_s1/CLK[0]

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.702 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[2].mult_dsp_inst/n47_s1/CLK[0]

MPW8

MPW Summary:

Slack: 2.759
Actual Width: 3.759
Required Width: 1.000
Type: Low Pulse Width
Clock: clk
Objects: Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[3].mult_dsp_inst/n47_s1

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.688 0.688 tINS FF clk_ibuf/O
7.618 1.931 tNET FF Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[3].mult_dsp_inst/n47_s1/CLK[0]

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR clk_ibuf/I
10.675 0.675 tINS RR clk_ibuf/O
11.378 0.702 tNET RR Advanced_FIR_Filter_Top_isnt/advanced_fir_filter_inst/fir_symmetry_inst/gen_mult_dsp[3].mult_dsp_inst/n47_s1/CLK[0]

MPW9

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.623 1.941 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.385 0.708 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW10

MPW Summary:

Slack: 2.762
Actual Width: 3.762
Required Width: 1.000
Type: High Pulse Width
Clock: clk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
0.683 0.683 tINS RR clk_ibuf/O
2.623 1.941 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk
5.000 0.000 tCL FF clk_ibuf/I
5.677 0.678 tINS FF clk_ibuf/O
6.385 0.708 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
3345 clk_d 1.990 1.985
481 delay_shift_addrb[0] 1.990 5.740
384 delay_shift_addrb_symm[0] 4.747 3.449
259 control0[0] 4.104 2.735
241 delay_shift_addrb[1] 4.194 4.065
192 delay_shift_addrb_symm[1] 5.930 2.513
161 coeff_ram_addrb[0] 6.868 1.898
161 delay_shift_addrb[2] 3.691 4.309
128 delay_shift_addrb_symm[2] 5.195 3.187
103 mult_out_valid 7.255 2.086

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R10C24 50.00%
R21C38 48.61%
R19C35 48.61%
R32C24 48.61%
R32C25 48.61%
R20C39 47.22%
R19C38 47.22%
R6C23 47.22%
R22C48 45.83%
R13C24 45.83%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]