Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\src\BLC_exp.v E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\src\black_level_correction\black_level_correction.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.11_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Mon Dec 23 10:46:33 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | BLC_exp |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.539s, Peak memory usage = 466.082MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 466.082MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 466.082MB Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 466.082MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 466.082MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 466.082MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 466.082MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 466.082MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 466.082MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 466.082MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 466.082MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 466.082MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 466.082MB Generate output files: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 466.082MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 466.082MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 18 |
| I/O Buf | 18 |
| IBUF | 6 |
| OBUF | 12 |
| Register | 1236 |
| DFF | 89 |
| DFFE | 110 |
| DFFS | 3 |
| DFFSE | 15 |
| DFFR | 20 |
| DFFRE | 330 |
| DFFP | 3 |
| DFFPE | 36 |
| DFFC | 228 |
| DFFCE | 402 |
| LUT | 1126 |
| LUT2 | 116 |
| LUT3 | 251 |
| LUT4 | 759 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 553 |
| ALU | 553 |
| SSRAM | 2 |
| RAM16S4 | 2 |
| INV | 7 |
| INV | 7 |
| BSRAM | 5 |
| SDPB | 3 |
| pROM | 2 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1706(1141 LUT, 553 ALU, 2 RAM16) / 20736 | 9% |
| Register | 1236 / 16173 | 8% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 1236 / 16173 | 8% |
| BSRAM | 5 / 46 | 11% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | SYM_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | SYM_CLK_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | SYM_CLK | 100.000(MHz) | 140.327(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.874 |
| Data Arrival Time | 7.451 |
| Data Required Time | 10.325 |
| From | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2 |
| To | BLC_Top/BLC_top/BLC_Correction/data_corrected_7_s1 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/CLK |
| 0.592 | 0.232 | tC2Q | RF | 6 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/Q |
| 1.066 | 0.474 | tNET | FF | 4 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/AD[0] |
| 1.583 | 0.517 | tINS | FF | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/DO[0] |
| 2.057 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/I0 |
| 2.574 | 0.517 | tINS | FF | 9 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/F |
| 3.048 | 0.474 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n76_s/I0 |
| 3.597 | 0.549 | tINS | FR | 1 | BLC_Top/BLC_top/BLC_Correction/n76_s/COUT |
| 3.597 | 0.000 | tNET | RR | 2 | BLC_Top/BLC_top/BLC_Correction/n75_s/CIN |
| 3.632 | 0.035 | tINS | RF | 1 | BLC_Top/BLC_top/BLC_Correction/n75_s/COUT |
| 3.632 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n74_s/CIN |
| 3.667 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n74_s/COUT |
| 3.667 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n73_s/CIN |
| 3.703 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n73_s/COUT |
| 3.703 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n72_s/CIN |
| 3.738 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n72_s/COUT |
| 3.738 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n71_s/CIN |
| 3.773 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n71_s/COUT |
| 3.773 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n70_s/CIN |
| 3.808 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n70_s/COUT |
| 3.808 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n69_s/CIN |
| 4.278 | 0.470 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n69_s/SUM |
| 4.752 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n93_s5/I2 |
| 5.205 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n93_s5/F |
| 5.679 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n93_s3/I3 |
| 6.050 | 0.371 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n93_s3/F |
| 6.524 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n93_s1/I2 |
| 6.977 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n93_s1/F |
| 7.451 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_7_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_7_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_7_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 3.541, 49.938%; route: 3.318, 46.790%; tC2Q: 0.232, 3.272% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | 2.909 |
| Data Arrival Time | 7.416 |
| Data Required Time | 10.325 |
| From | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2 |
| To | BLC_Top/BLC_top/BLC_Correction/data_corrected_6_s1 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/CLK |
| 0.592 | 0.232 | tC2Q | RF | 6 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/Q |
| 1.066 | 0.474 | tNET | FF | 4 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/AD[0] |
| 1.583 | 0.517 | tINS | FF | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/DO[0] |
| 2.057 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/I0 |
| 2.574 | 0.517 | tINS | FF | 9 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/F |
| 3.048 | 0.474 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n76_s/I0 |
| 3.597 | 0.549 | tINS | FR | 1 | BLC_Top/BLC_top/BLC_Correction/n76_s/COUT |
| 3.597 | 0.000 | tNET | RR | 2 | BLC_Top/BLC_top/BLC_Correction/n75_s/CIN |
| 3.632 | 0.035 | tINS | RF | 1 | BLC_Top/BLC_top/BLC_Correction/n75_s/COUT |
| 3.632 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n74_s/CIN |
| 3.667 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n74_s/COUT |
| 3.667 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n73_s/CIN |
| 3.703 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n73_s/COUT |
| 3.703 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n72_s/CIN |
| 3.738 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n72_s/COUT |
| 3.738 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n71_s/CIN |
| 3.773 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n71_s/COUT |
| 3.773 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n70_s/CIN |
| 4.243 | 0.470 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n70_s/SUM |
| 4.717 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n94_s6/I2 |
| 5.170 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n94_s6/F |
| 5.644 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n94_s4/I3 |
| 6.015 | 0.371 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n94_s4/F |
| 6.489 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n94_s3/I2 |
| 6.942 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n94_s3/F |
| 7.416 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_6_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_6_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_6_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 3.506, 49.688%; route: 3.318, 47.024%; tC2Q: 0.232, 3.288% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 2.944 |
| Data Arrival Time | 7.381 |
| Data Required Time | 10.325 |
| From | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2 |
| To | BLC_Top/BLC_top/BLC_Correction/data_corrected_5_s1 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/CLK |
| 0.592 | 0.232 | tC2Q | RF | 6 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/Q |
| 1.066 | 0.474 | tNET | FF | 4 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/AD[0] |
| 1.583 | 0.517 | tINS | FF | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/DO[0] |
| 2.057 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/I0 |
| 2.574 | 0.517 | tINS | FF | 9 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/F |
| 3.048 | 0.474 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n76_s/I0 |
| 3.597 | 0.549 | tINS | FR | 1 | BLC_Top/BLC_top/BLC_Correction/n76_s/COUT |
| 3.597 | 0.000 | tNET | RR | 2 | BLC_Top/BLC_top/BLC_Correction/n75_s/CIN |
| 3.632 | 0.035 | tINS | RF | 1 | BLC_Top/BLC_top/BLC_Correction/n75_s/COUT |
| 3.632 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n74_s/CIN |
| 3.667 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n74_s/COUT |
| 3.667 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n73_s/CIN |
| 3.703 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n73_s/COUT |
| 3.703 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n72_s/CIN |
| 3.738 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n72_s/COUT |
| 3.738 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n71_s/CIN |
| 4.208 | 0.470 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n71_s/SUM |
| 4.682 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n95_s4/I2 |
| 5.135 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n95_s4/F |
| 5.609 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n95_s2/I3 |
| 5.980 | 0.371 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n95_s2/F |
| 6.454 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n95_s1/I2 |
| 6.907 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n95_s1/F |
| 7.381 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_5_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_5_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_5_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 3.471, 49.436%; route: 3.318, 47.260%; tC2Q: 0.232, 3.304% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 2.979 |
| Data Arrival Time | 7.346 |
| Data Required Time | 10.325 |
| From | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2 |
| To | BLC_Top/BLC_top/BLC_Correction/data_corrected_4_s1 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/CLK |
| 0.592 | 0.232 | tC2Q | RF | 6 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/Q |
| 1.066 | 0.474 | tNET | FF | 4 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/AD[0] |
| 1.583 | 0.517 | tINS | FF | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/DO[0] |
| 2.057 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/I0 |
| 2.574 | 0.517 | tINS | FF | 9 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/F |
| 3.048 | 0.474 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n76_s/I0 |
| 3.597 | 0.549 | tINS | FR | 1 | BLC_Top/BLC_top/BLC_Correction/n76_s/COUT |
| 3.597 | 0.000 | tNET | RR | 2 | BLC_Top/BLC_top/BLC_Correction/n75_s/CIN |
| 3.632 | 0.035 | tINS | RF | 1 | BLC_Top/BLC_top/BLC_Correction/n75_s/COUT |
| 3.632 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n74_s/CIN |
| 3.667 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n74_s/COUT |
| 3.667 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n73_s/CIN |
| 3.703 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n73_s/COUT |
| 3.703 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n72_s/CIN |
| 4.173 | 0.470 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n72_s/SUM |
| 4.647 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n96_s4/I2 |
| 5.100 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n96_s4/F |
| 5.574 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n96_s2/I3 |
| 5.945 | 0.371 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n96_s2/F |
| 6.419 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n96_s1/I2 |
| 6.872 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n96_s1/F |
| 7.346 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_4_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 3.436, 49.181%; route: 3.318, 47.498%; tC2Q: 0.232, 3.321% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 3.015 |
| Data Arrival Time | 7.310 |
| Data Required Time | 10.325 |
| From | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2 |
| To | BLC_Top/BLC_top/BLC_Correction/data_corrected_3_s1 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/CLK |
| 0.592 | 0.232 | tC2Q | RF | 6 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s2/Q |
| 1.066 | 0.474 | tNET | FF | 4 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/AD[0] |
| 1.583 | 0.517 | tINS | FF | 1 | BLC_Top/BLC_top/delay_din_d/dReg[0]_0_s8/DO[0] |
| 2.057 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/I0 |
| 2.574 | 0.517 | tINS | FF | 9 | BLC_Top/BLC_top/delay_din_d/din_d_0_s2/F |
| 3.048 | 0.474 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n76_s/I0 |
| 3.597 | 0.549 | tINS | FR | 1 | BLC_Top/BLC_top/BLC_Correction/n76_s/COUT |
| 3.597 | 0.000 | tNET | RR | 2 | BLC_Top/BLC_top/BLC_Correction/n75_s/CIN |
| 3.632 | 0.035 | tINS | RF | 1 | BLC_Top/BLC_top/BLC_Correction/n75_s/COUT |
| 3.632 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n74_s/CIN |
| 3.667 | 0.035 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n74_s/COUT |
| 3.667 | 0.000 | tNET | FF | 2 | BLC_Top/BLC_top/BLC_Correction/n73_s/CIN |
| 4.137 | 0.470 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n73_s/SUM |
| 4.611 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n97_s4/I2 |
| 5.064 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n97_s4/F |
| 5.538 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n97_s2/I3 |
| 5.909 | 0.371 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n97_s2/F |
| 6.383 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n97_s1/I2 |
| 6.836 | 0.453 | tINS | FF | 1 | BLC_Top/BLC_top/BLC_Correction/n97_s1/F |
| 7.310 | 0.474 | tNET | FF | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 926 | SYM_CLK_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_3_s1/CLK |
| 10.325 | -0.035 | tSu | 1 | BLC_Top/BLC_top/BLC_Correction/data_corrected_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 3.400, 48.924%; route: 3.318, 47.738%; tC2Q: 0.232, 3.338% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |