Power Messages

Report Title Power Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\src\demo.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\src\fpga_project.sdc
Tool Version V1.9.11 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Mon Dec 23 10:46:40 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade Commercial
Process Typical
Ambient Temperature 25.000
Use Custom Theta JA false
Heat Sink None
Air Flow LFM_0
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Related Vcd File
Related Saif File
Filter Glitches false
Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125

Power Summary

Power Information:

Total Power (mW) 164.468
Quiescent Power (mW) 121.180
Dynamic Power (mW) 43.287

Thermal Information:

Junction Temperature 30.266
Theta JA 32.020
Max Allowed Ambient Temperature 79.734

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.000 38.658 69.983 108.641
VCCX 3.300 0.911 15.000 52.505
VCCIO18 1.800 0.902 0.943 3.321

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 2.917 NA 7.665
IO 9.937 4.396 14.236
BSRAM 34.803 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
BLC_exp 37.720 37.720(36.444)
BLC_exp/BLC_Top/ 2.085 2.085(2.085)
BLC_exp/BLC_Top/BLC_top/ 2.085 2.085(2.085)
BLC_exp/BLC_Top/BLC_top/BLC_Controller/ 0.088 0.088(0.000)
BLC_exp/BLC_Top/BLC_top/BLC_Controller/delay_inpvalid/ 0.000 0.000(0.000)
BLC_exp/BLC_Top/BLC_top/BLC_Correction/ 0.153 0.153(0.000)
BLC_exp/BLC_Top/BLC_top/black_average/ 1.833 1.833(1.388)
BLC_exp/BLC_Top/BLC_top/black_average/Mean_B/ 0.462 0.462(0.000)
BLC_exp/BLC_Top/BLC_top/black_average/Mean_G/ 0.462 0.462(0.000)
BLC_exp/BLC_Top/BLC_top/black_average/Mean_R/ 0.462 0.462(0.000)
BLC_exp/BLC_Top/BLC_top/black_average/complete_mean_edge/ 0.001 0.001(0.000)
BLC_exp/BLC_Top/BLC_top/black_average/delay_CMF_d/ 0.000 0.000(0.000)
BLC_exp/BLC_Top/BLC_top/black_average/delay_CMF_d2/ 0.000 0.000(0.000)
BLC_exp/BLC_Top/BLC_top/black_average/delay_average_done/ 0.000 0.000(0.000)
BLC_exp/BLC_Top/BLC_top/delay_din_d/ 0.009 0.009(0.000)
BLC_exp/BLC_Top/BLC_top/delay_sync/ 0.002 0.002(0.000)
BLC_exp/gw_gao_inst_0/ 34.359 34.359(34.359)
BLC_exp/gw_gao_inst_0/u_icon_top/ 0.026 0.026(0.000)
BLC_exp/gw_gao_inst_0/u_la0_top/ 34.333 34.333(33.843)
BLC_exp/gw_gao_inst_0/u_la0_top/u_ao_crc32/ 0.051 0.051(0.000)
BLC_exp/gw_gao_inst_0/u_la0_top/u_ao_match_0/ 0.007 0.007(0.000)
BLC_exp/gw_gao_inst_0/u_la0_top/u_ao_match_1/ 0.074 0.074(0.000)
BLC_exp/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/ 33.711 33.711(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
SYM_CLK 50.000 14.693
tck_pad_i 100.000 23.054
NO CLOCK DOMAIN 0.000 0.000