PnR Messages

Report Title PnR Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\src\demo.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\src\fpga_project.sdc
Tool Version V1.9.11 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Mon Dec 23 10:46:40 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.215s, Elapsed time = 0h 0m 0.215s Placement Phase 1: CPU time = 0h 0m 0.239s, Elapsed time = 0h 0m 0.239s Placement Phase 2: CPU time = 0h 0m 0.338s, Elapsed time = 0h 0m 0.338s Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.16s, Elapsed time = 0h 0m 0.159s Routing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 471MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1759/20736 9%
    --LUT,ALU,ROM16 1747(1166 LUT, 581 ALU, 0 ROM16) -
    --SSRAM(RAM16) 2 -
Register 1266/16173 8%
    --Logic Register as Latch 0/15552 0%
    --Logic Register as FF 1265/15552 9%
    --I/O Register as Latch 0/621 0%
    --I/O Register as FF 1/621 <1%
CLS 1269/10368 13%
I/O Port 18/207 9%
I/O Buf 18 -
    --Input Buf 6 -
    --Output Buf 12 -
    --Inout Buf 0 -
BSRAM 3 SDPB
2 pROM
11%

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 4/2914%
bank 1 0/200%
bank 2 4/2020%
bank 3 0/320%
bank 4 3/369%
bank 5 3/369%
bank 6 3/1817%
bank 7 1/167%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 2/8 25%
LW 6/8 75%
GCLK_PIN 1/8 13%

Global Clock Signals:

Signal Global Clock Location
SYM_CLK_d PRIMARY TR TL BR BL
gw_gao_inst_0/control0[0] PRIMARY BR BL
KEY1_d LW -
gw_gao_inst_0/gao_jtag_reset LW -
gw_gao_inst_0/u_la0_top/rst_ao LW -
BLC_Top/BLC_top/black_average/Mean_R/n888_6 LW -
BLC_Top/BLC_top/black_average/Mean_G/n888_6 LW -
BLC_Top/BLC_top/black_average/Mean_B/n888_6 LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
SYM_CLK - H11/0 Y in IOT27[A] GCLKT_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
KEY1 - T2/4 Y in IOB48[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
SW1 - E9/6 Y in IOL38[B] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
tms_pad_i - B8/2 N in IOR25[B] TMS LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
tck_pad_i - A7/2 N in IOR26[A] TCK LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
tdi_pad_i - A6/2 N in IOR26[B] TDI LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
outvalid - L5/4 N out IOB39[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
line_sync_o - C16/0 N out IOT5[A] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
frame_sync_o - G14/0 N out IOT13[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
dout[0] - H3/4 N out IOB32[A] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
dout[1] - J15/0 N out IOT24[A] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
dout[2] - H6/5 N out IOB22[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
dout[3] - C1/5 N out IOB14[A] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
dout[4] - A12/7 N out IOL13[B] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
dout[5] - B6/5 N out IOB7[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
dout[6] - F7/6 N out IOL45[A] LPLL2_T_in LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
dout[7] - E11/6 N out IOL31[B] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
tdo_pad_o - C6/2 N out IOR25[A] TDO LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
L15/0 - in IOT2[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D16/0 - in IOT4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E14/0 - in IOT4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C16/0 line_sync_o out IOT5[A] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
D15/0 - in IOT5[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E16/0 - in IOT6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F15/0 - in IOT6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F13/0 - in IOT8[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G12/0 - in IOT8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F14/0 - in IOT9[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F16/0 - in IOT9[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F12/0 - in IOT12[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G13/0 - in IOT12[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G15/0 - in IOT13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G14/0 frame_sync_o out IOT13[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
G11/0 - in IOT14[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H12/0 - in IOT14[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G16/0 - in IOT16[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H15/0 - in IOT16[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H13/0 - in IOT18[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J12/0 - in IOT18[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H14/0 - in IOT20[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H16/0 - in IOT20[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J16/0 - in IOT22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J14/0 - in IOT22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J15/0 dout[1] out IOT24[A] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
K16/0 - in IOT24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H11/0 SYM_CLK in IOT27[A] GCLKT_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J13/0 - in IOT27[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K14/1 - in IOT30[A] GCLKT_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K15/1 - in IOT30[B] GCLKC_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J11/1 - in IOT32[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L12/1 - in IOT32[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L16/1 - in IOT34[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L14/1 - in IOT34[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K13/1 - in IOT36[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K12/1 - in IOT36[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K11/1 - in IOT38[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L13/1 - in IOT38[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M14/1 - in IOT40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M15/1 - in IOT40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D14/1 - in IOT44[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E15/1 - in IOT44[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N15/1 - in IOT48[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P16/1 - in IOT48[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N16/1 - in IOT52[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N14/1 - in IOT52[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P15/1 - in IOT54[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R16/1 - in IOT54[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A4/5 - in IOB2[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C5/5 - in IOB2[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D6/5 - in IOB3[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E7/5 - in IOB3[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A3/5 - in IOB4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B4/5 - in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A5/5 - in IOB7[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B6/5 dout[5] out IOB7[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
B1/5 - in IOB8[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C2/5 - in IOB8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D3/5 - in IOB9[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D1/5 - in IOB9[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E2/5 - in IOB12[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E3/5 - in IOB12[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B3/5 - in IOB13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A2/5 - in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C1/5 dout[3] out IOB14[A] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
D2/5 - in IOB14[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E1/5 - in IOB16[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F2/5 - in IOB16[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F4/5 - in IOB18[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G6/5 - in IOB18[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F3/5 - in IOB19[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F1/5 - in IOB19[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G5/5 - in IOB20[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G4/5 - in IOB20[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G2/5 - in IOB21[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G3/5 - in IOB21[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F5/5 - in IOB22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H6/5 dout[2] out IOB22[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
G1/5 - in IOB24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H2/5 - in IOB24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H4/5 - in IOB26[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J6/5 - in IOB26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J1/5 - in IOB27[A] GCLKT_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J3/5 - in IOB27[B] GCLKC_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L2/4 - in IOB30[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M1/4 - in IOB30[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H3/4 dout[0] out IOB32[A] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
H1/4 - in IOB32[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J2/4 - in IOB34[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K1/4 - in IOB34[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H5/4 - in IOB35[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J4/4 - in IOB35[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K3/4 - in IOB36[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K2/4 - in IOB36[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J5/4 - in IOB37[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K6/4 - in IOB37[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L1/4 - in IOB38[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L3/4 - in IOB38[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K4/4 - in IOB39[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L5/4 outvalid out IOB39[B] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
K5/4 - in IOB40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L4/4 - in IOB40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N2/4 - in IOB41[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P1/4 - in IOB41[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M3/4 - in IOB42[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N1/4 - in IOB42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M2/4 - in IOB43[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N3/4 - in IOB43[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R1/4 - in IOB44[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P2/4 - in IOB44[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P4/4 - in IOB45[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T4/4 - in IOB45[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R3/4 - in IOB48[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T2/4 KEY1 in IOB48[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P5/4 - in IOB50[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R5/4 - in IOB50[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R4/4 - in IOB52[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T3/4 - in IOB52[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R6/4 - in IOB54[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T5/4 - in IOB54[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B14/7 - in IOL2[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A15/7 - in IOL2[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C12/7 - in IOL7[A] LPLL1_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B12/7 - in IOL7[B] LPLL1_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B13/7 - in IOL8[A] LPLL1_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A14/7 - in IOL8[B] LPLL1_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F10/7 - in IOL11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B11/7 - in IOL13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A12/7 dout[4] out IOL13[B] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
A11/7 - in IOL15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C11/7 - in IOL15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D10/7 - in IOL17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E10/7 - in IOL17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D11/7 - in IOL22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A9/7 - in IOL27[A] GCLKT_7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C9/7 - in IOL27[B] GCLKC_7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C8/6 - in IOL29[A] GCLKT_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A8/6 - in IOL29[B] GCLKC_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F9/6 - in IOL31[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E11/6 dout[7] out IOL31[B] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
B9/6 - in IOL33[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A10/6 - in IOL33[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F8/6 - in IOL35[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D9/6 - in IOL35[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D8/6 - in IOL38[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E9/6 SW1 in IOL38[B] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
B7/6 - in IOL40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C7/6 - in IOL40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F7/6 dout[6] out IOL45[A] LPLL2_T_in LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
E8/6 - in IOL45[B] LPLL2_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C4/6 - in IOL47[A] LPLL2_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B5/6 - in IOL47[B] LPLL2_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E6/6 - in IOL53[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D7/6 - in IOL53[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T15/2 - in IOR7[A] RPLL1_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R14/2 - in IOR7[B] RPLL1_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P12/2 - in IOR8[A] RPLL1_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T13/2 - in IOR8[B] RPLL1_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R12/2 - in IOR11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P13/2 - in IOR11[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R11/2 - in IOR17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T12/2 - in IOR17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R13/2 - in IOR20[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T14/2 - in IOR20[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M10/2 - in IOR22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N11/2 - in IOR22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T11/2 - in IOR24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P11/2 - in IOR24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C6/2 tdo_pad_o out IOR25[A] TDO LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
B8/2 tms_pad_i in IOR25[B] TMS LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
A7/2 tck_pad_i in IOR26[A] TCK LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
A6/2 tdi_pad_i in IOR26[B] TDI LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
N10/2 - in IOR27[A] GCLKT_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M11/2 - in IOR27[B] GCLKC_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T7/3 - in IOR29[A] GCLKT_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R8/3 - in IOR29[B] GCLKC_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M16/3 - in IOR30[A] MODE0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B16/3 - in IOR30[B] MODE1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C15/3 - in IOR31[A] MODE2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B10/3 - in IOR31[B] RECONFIG_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A13/3 - in IOR32[A] READY LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C13/3 - in IOR32[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P10/3 - in IOR33[A] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R10/3 - in IOR33[B] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M9/3 - in IOR34[A] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L10/3 - in IOR34[B] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R9/3 - in IOR35[A] FASTRD_N/D3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T10/3 - in IOR35[B] SI/D2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M8/3 - in IOR36[A] SO/D1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N9/3 - in IOR36[B] SSPI_CS_N/D0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T9/3 - in IOR38[A] DIN/CLKHOLD_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P9/3 - in IOR38[B] DOUT/WE_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C10/3 - in IOR39[A] SCLK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N8/3 - in IOR40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L9/3 - in IOR40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P8/3 - in IOR42[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T8/3 - in IOR42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M6/3 - in IOR44[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L8/3 - in IOR44[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M7/3 - in IOR47[A] RPLL2_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N7/3 - in IOR47[B] RPLL2_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
R7/3 - in IOR49[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P7/3 - in IOR49[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N6/3 - in IOR51[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P6/3 - in IOR53[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
T6/3 - in IOR53[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8