Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\src\demo.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_BLC_RefDesign\project\src\fpga_project.sdc
Tool Version V1.9.11 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Mon Dec 23 10:46:40 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C C8/I7
Hold Delay Model Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed 4157
Numbers of Endpoints Analyzed 3432
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 SYM_CLK Base 20.000 50.000 0.000 10.000 SYM_CLK
2 tck_pad_i Base 10.000 100.000 0.000 5.000 tck_pad_i

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 SYM_CLK 50.000(MHz) 108.887(MHz) 12 TOP
2 tck_pad_i 100.000(MHz) 168.844(MHz) 6 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
SYM_CLK Setup 0.000 0
SYM_CLK Hold 0.000 0
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.077 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.888
2 4.106 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.859
3 4.112 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s1/D tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.853
4 4.147 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.818
5 4.147 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_3_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.818
6 4.147 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.818
7 4.153 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.812
8 4.182 gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/D tck_pad_i:[R] SYM_CLK:[R] 10.000 1.221 4.527
9 4.206 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/module_state_0_s0/D tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.759
10 4.237 gw_gao_inst_0/u_la0_top/word_count_0_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEB tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.676
11 4.257 gw_gao_inst_0/u_la0_top/module_state_3_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1/D tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.708
12 4.257 gw_gao_inst_0/u_la0_top/word_count_0_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEB tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.656
13 4.317 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.648
14 4.320 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.645
15 4.331 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_2_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.634
16 4.331 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_14_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.634
17 4.331 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.634
18 4.337 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_10_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.628
19 4.337 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.628
20 4.340 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_8_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.625
21 4.340 gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.625
22 4.342 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.623
23 4.342 gw_gao_inst_0/u_la0_top/module_state_1_s0/Q gw_gao_inst_0/u_la0_top/capture_mem_addr_max_4_s0/CE tck_pad_i:[R] tck_pad_i:[R] 10.000 0.000 5.623
24 4.284 gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0/CE tck_pad_i:[F] tck_pad_i:[R] 5.000 -1.494 2.176
25 4.284 gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0/CE tck_pad_i:[F] tck_pad_i:[R] 5.000 -1.494 2.176

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.192 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.202
2 0.192 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.202
3 0.192 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.202
4 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
5 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
6 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[15] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
7 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
8 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
9 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
10 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
11 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
12 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[6] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
13 0.225 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.474
14 0.241 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.490
15 0.363 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.612
16 0.363 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.612
17 0.363 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.612
18 0.363 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.612
19 0.363 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.612
20 0.363 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.612
21 0.363 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[12] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.612
22 0.375 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.624
23 0.375 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.624
24 0.378 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11] SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.627
25 0.425 BLC_Top/BLC_top/black_average/Mean_B/bi_2_s0/Q BLC_Top/BLC_top/black_average/Mean_B/bi_2_s0/D SYM_CLK:[R] SYM_CLK:[R] 0.000 0.000 0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
2 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
3 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
4 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
5 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
6 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
7 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
8 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
9 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
10 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
11 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
12 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
13 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
14 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
15 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
16 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
17 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
18 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
19 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
20 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
21 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
22 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
23 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
24 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559
25 10.017 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] 10.000 -1.611 1.559

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
2 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
3 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
4 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
5 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
6 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
7 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
8 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
9 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
10 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
11 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
12 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
13 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
14 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
15 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
16 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
17 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
18 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
19 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
20 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
21 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
22 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
23 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
24 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058
25 10.063 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0/CLEAR SYM_CLK:[F] SYM_CLK:[R] -10.000 -0.984 1.058

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_icon_top/shift_dr_capture_dr_dly_0_s0
2 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
3 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_icon_top/module_id_reg_2_s0
4 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/data_register_41_s0
5 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/data_register_9_s0
6 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/internal_register_select_9_s0
7 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/internal_register_select_1_s0
8 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0
9 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0
10 1.025 2.025 1.000 High Pulse Width tck_pad_i gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.077
Data Arrival Time 13.610
Data Required Time 17.687
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
7.954 0.232 tC2Q RF 25 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
8.647 0.693 tNET FF 1 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
9.100 0.453 tINS FF 20 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
9.849 0.748 tNET FF 1 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
10.404 0.555 tINS FF 27 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
11.379 0.975 tNET FF 1 R33C23[3][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/n211_s1/I1
11.750 0.371 tINS FF 3 R33C23[3][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/n211_s1/F
12.249 0.499 tNET FF 1 R31C21[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I2
12.620 0.371 tINS FF 1 R31C21[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
12.790 0.170 tNET FF 1 R31C20[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I2
13.252 0.462 tINS FR 2 R31C20[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F
13.610 0.357 tNET RR 1 R32C22[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R32C22[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CLK
17.687 -0.035 tSu 1 R32C22[2][A] gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.212, 37.570%; route: 3.444, 58.489%; tC2Q: 0.232, 3.940%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path2

Path Summary:

Slack 4.106
Data Arrival Time 13.581
Data Required Time 17.687
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
7.954 0.232 tC2Q RF 25 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
8.647 0.693 tNET FF 1 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
9.100 0.453 tINS FF 20 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
9.849 0.748 tNET FF 1 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
10.404 0.555 tINS FF 27 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
11.379 0.975 tNET FF 1 R33C23[3][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/n211_s1/I1
11.750 0.371 tINS FF 3 R33C23[3][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/n211_s1/F
12.249 0.499 tNET FF 1 R31C21[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I2
12.620 0.371 tINS FF 1 R31C21[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F
12.790 0.170 tNET FF 1 R31C20[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I2
13.252 0.462 tINS FR 2 R31C20[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F
13.581 0.329 tNET RR 1 R31C22[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R31C22[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK
17.687 -0.035 tSu 1 R31C22[0][A] gw_gao_inst_0/u_la0_top/internal_reg_start_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.212, 37.752%; route: 3.415, 58.289%; tC2Q: 0.232, 3.959%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path3

Path Summary:

Slack 4.112
Data Arrival Time 13.575
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.477 0.517 tINS FF 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.026 1.549 tNET FF 1 R39C26[0][A] gw_gao_inst_0/u_la0_top/n847_s2/I0
13.575 0.549 tINS FR 1 R39C26[0][A] gw_gao_inst_0/u_la0_top/n847_s2/F
13.575 0.000 tNET RR 1 R39C26[0][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R39C26[0][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s1/CLK
17.687 -0.035 tSu 1 R39C26[0][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.547, 43.516%; route: 3.074, 52.520%; tC2Q: 0.232, 3.964%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path4

Path Summary:

Slack 4.147
Data Arrival Time 13.540
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.540 2.031 tNET RR 1 R30C25[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R30C25[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1/CLK
17.687 -0.035 tSu 1 R30C25[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 34.893%; route: 3.556, 61.120%; tC2Q: 0.232, 3.988%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path5

Path Summary:

Slack 4.147
Data Arrival Time 13.540
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_3_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.540 2.031 tNET RR 1 R30C25[0][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R30C25[0][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_3_s1/CLK
17.687 -0.035 tSu 1 R30C25[0][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 34.893%; route: 3.556, 61.120%; tC2Q: 0.232, 3.988%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path6

Path Summary:

Slack 4.147
Data Arrival Time 13.540
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.540 2.031 tNET RR 1 R30C25[1][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R30C25[1][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1/CLK
17.687 -0.035 tSu 1 R30C25[1][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 34.893%; route: 3.556, 61.120%; tC2Q: 0.232, 3.988%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path7

Path Summary:

Slack 4.153
Data Arrival Time 13.534
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.534 2.025 tNET RR 1 R31C24[1][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R31C24[1][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1/CLK
17.687 -0.035 tSu 1 R31C24[1][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 34.928%; route: 3.550, 61.080%; tC2Q: 0.232, 3.992%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path8

Path Summary:

Slack 4.182
Data Arrival Time 22.249
Data Required Time 26.431
From gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk tck_pad_i:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R30C23[0][B] gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/CLK
17.954 0.232 tC2Q RF 4 R30C23[0][B] gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q
18.943 0.989 tNET FF 2 R30C31[0][B] gw_gao_inst_0/u_la0_top/n2269_s21/I0
19.492 0.549 tINS FR 1 R30C31[0][B] gw_gao_inst_0/u_la0_top/n2269_s21/COUT
19.492 0.000 tNET RR 2 R30C31[1][A] gw_gao_inst_0/u_la0_top/n2269_s22/CIN
19.527 0.035 tINS RF 1 R30C31[1][A] gw_gao_inst_0/u_la0_top/n2269_s22/COUT
19.527 0.000 tNET FF 2 R30C31[1][B] gw_gao_inst_0/u_la0_top/n2269_s23/CIN
19.562 0.035 tINS FF 1 R30C31[1][B] gw_gao_inst_0/u_la0_top/n2269_s23/COUT
19.562 0.000 tNET FF 2 R30C31[2][A] gw_gao_inst_0/u_la0_top/n2269_s24/CIN
19.597 0.035 tINS FF 1 R30C31[2][A] gw_gao_inst_0/u_la0_top/n2269_s24/COUT
19.597 0.000 tNET FF 2 R30C31[2][B] gw_gao_inst_0/u_la0_top/n2269_s25/CIN
19.632 0.035 tINS FF 1 R30C31[2][B] gw_gao_inst_0/u_la0_top/n2269_s25/COUT
19.632 0.000 tNET FF 2 R30C32[0][A] gw_gao_inst_0/u_la0_top/n2269_s26/CIN
19.668 0.035 tINS FF 1 R30C32[0][A] gw_gao_inst_0/u_la0_top/n2269_s26/COUT
19.668 0.000 tNET FF 2 R30C32[0][B] gw_gao_inst_0/u_la0_top/n2269_s27/CIN
19.703 0.035 tINS FF 1 R30C32[0][B] gw_gao_inst_0/u_la0_top/n2269_s27/COUT
19.703 0.000 tNET FF 2 R30C32[1][A] gw_gao_inst_0/u_la0_top/n2269_s28/CIN
19.738 0.035 tINS FF 2 R30C32[1][A] gw_gao_inst_0/u_la0_top/n2269_s28/COUT
21.153 1.414 tNET FF 1 R34C22[1][B] gw_gao_inst_0/u_la0_top/start_reg1_s1/I1
21.615 0.462 tINS FR 1 R34C22[1][B] gw_gao_inst_0/u_la0_top/start_reg1_s1/F
21.787 0.172 tNET RR 1 R35C22[1][A] gw_gao_inst_0/u_la0_top/start_reg1_s0/I0
22.249 0.462 tINS RR 1 R35C22[1][A] gw_gao_inst_0/u_la0_top/start_reg1_s0/F
22.249 0.000 tNET RR 1 R35C22[1][A] gw_gao_inst_0/u_la0_top/start_reg_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R35C22[1][A] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
26.466 -0.035 tUnc gw_gao_inst_0/u_la0_top/start_reg_s0
26.431 -0.035 tSu 1 R35C22[1][A] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew -1.221
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 1.719, 37.982%; route: 2.576, 56.893%; tC2Q: 0.232, 5.125%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path9

Path Summary:

Slack 4.206
Data Arrival Time 13.481
Data Required Time 17.687
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/module_state_0_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
7.954 0.232 tC2Q RF 25 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
8.647 0.693 tNET FF 1 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
9.100 0.453 tINS FF 20 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
9.849 0.748 tNET FF 1 R31C34[2][B] gw_gao_inst_0/u_la0_top/op_reg_en_s3/I3
10.404 0.555 tINS FF 39 R31C34[2][B] gw_gao_inst_0/u_la0_top/op_reg_en_s3/F
11.351 0.947 tNET FF 1 R36C33[2][A] gw_gao_inst_0/u_la0_top/module_next_state_0_s29/I3
11.804 0.453 tINS FF 1 R36C33[2][A] gw_gao_inst_0/u_la0_top/module_next_state_0_s29/F
12.217 0.413 tNET FF 1 R39C33[2][B] gw_gao_inst_0/u_la0_top/module_next_state_0_s25/I3
12.766 0.549 tINS FR 1 R39C33[2][B] gw_gao_inst_0/u_la0_top/module_next_state_0_s25/F
12.911 0.144 tNET RR 1 R39C33[0][A] gw_gao_inst_0/u_la0_top/module_next_state_0_s22/I2
13.481 0.570 tINS RR 1 R39C33[0][A] gw_gao_inst_0/u_la0_top/module_next_state_0_s22/F
13.481 0.000 tNET RR 1 R39C33[0][A] gw_gao_inst_0/u_la0_top/module_state_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R39C33[0][A] gw_gao_inst_0/u_la0_top/module_state_0_s0/CLK
17.687 -0.035 tSu 1 R39C33[0][A] gw_gao_inst_0/u_la0_top/module_state_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.580, 44.803%; route: 2.947, 51.168%; tC2Q: 0.232, 4.029%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path10

Path Summary:

Slack 4.237
Data Arrival Time 13.398
Data Required Time 17.635
From gw_gao_inst_0/u_la0_top/word_count_0_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R41C35[2][B] gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
7.954 0.232 tC2Q RF 5 R41C35[2][B] gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
8.387 0.433 tNET FF 1 R40C33[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I0
8.942 0.555 tINS FF 8 R40C33[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F
9.366 0.424 tNET FF 1 R40C34[3][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s1/I0
9.737 0.371 tINS FF 6 R40C34[3][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s1/F
10.005 0.267 tNET FF 1 R38C34[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s7/I0
10.376 0.371 tINS FF 6 R38C34[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s7/F
10.568 0.193 tNET FF 1 R38C33[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I2
11.123 0.555 tINS FF 1 R38C33[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F
11.929 0.806 tNET FF 1 R39C33[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1
12.391 0.462 tINS FR 33 R39C33[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F
13.398 1.007 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB
17.635 -0.087 tSu 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.314, 40.767%; route: 3.130, 55.146%; tC2Q: 0.232, 4.087%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path11

Path Summary:

Slack 4.257
Data Arrival Time 13.431
Data Required Time 17.687
From gw_gao_inst_0/u_la0_top/module_state_3_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R39C34[0][A] gw_gao_inst_0/u_la0_top/module_state_3_s0/CLK
7.954 0.232 tC2Q RF 15 R39C34[0][A] gw_gao_inst_0/u_la0_top/module_state_3_s0/Q
8.640 0.686 tNET FF 1 R36C33[1][B] gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s4/I1
9.189 0.549 tINS FR 2 R36C33[1][B] gw_gao_inst_0/u_la0_top/data_to_addr_counter_9_s4/F
9.192 0.003 tNET RR 1 R36C33[1][A] gw_gao_inst_0/u_la0_top/bit_count_5_s5/I3
9.747 0.555 tINS RF 5 R36C33[1][A] gw_gao_inst_0/u_la0_top/bit_count_5_s5/F
10.416 0.669 tNET FF 1 R34C30[1][B] gw_gao_inst_0/u_la0_top/n801_s6/I0
10.787 0.371 tINS FF 48 R34C30[1][B] gw_gao_inst_0/u_la0_top/n801_s6/F
12.000 1.214 tNET FF 1 R33C24[2][A] gw_gao_inst_0/u_la0_top/n834_s1/I3
12.555 0.555 tINS FF 1 R33C24[2][A] gw_gao_inst_0/u_la0_top/n834_s1/F
12.969 0.413 tNET FF 1 R31C25[0][B] gw_gao_inst_0/u_la0_top/n834_s0/I0
13.431 0.462 tINS FR 1 R31C25[0][B] gw_gao_inst_0/u_la0_top/n834_s0/F
13.431 0.000 tNET RR 1 R31C25[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R31C25[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1/CLK
17.687 -0.035 tSu 1 R31C25[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_12_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.492, 43.654%; route: 2.984, 52.282%; tC2Q: 0.232, 4.064%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path12

Path Summary:

Slack 4.257
Data Arrival Time 13.378
Data Required Time 17.635
From gw_gao_inst_0/u_la0_top/word_count_0_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R41C35[2][B] gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
7.954 0.232 tC2Q RF 5 R41C35[2][B] gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
8.387 0.433 tNET FF 1 R40C33[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/I0
8.942 0.555 tINS FF 8 R40C33[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_4_s1/F
9.366 0.424 tNET FF 1 R40C34[3][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s1/I0
9.737 0.371 tINS FF 6 R40C34[3][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s1/F
10.005 0.267 tNET FF 1 R38C34[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s7/I0
10.376 0.371 tINS FF 6 R38C34[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s7/F
10.568 0.193 tNET FF 1 R38C33[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/I2
11.123 0.555 tINS FF 1 R38C33[3][B] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s1/F
11.929 0.806 tNET FF 1 R39C33[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/I1
12.391 0.462 tINS FR 33 R39C33[3][A] gw_gao_inst_0/u_la0_top/jtag_strobe_i_s0/F
13.378 0.987 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKB
17.635 -0.087 tSu 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.314, 40.912%; route: 3.110, 54.987%; tC2Q: 0.232, 4.102%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path13

Path Summary:

Slack 4.317
Data Arrival Time 13.370
Data Required Time 17.687
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
7.954 0.232 tC2Q RF 25 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
8.647 0.693 tNET FF 1 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
9.100 0.453 tINS FF 20 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
9.849 0.748 tNET FF 1 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
10.404 0.555 tINS FF 27 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
11.370 0.966 tNET FF 1 R33C23[3][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s2/I1
11.823 0.453 tINS FF 1 R33C23[3][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s2/F
12.220 0.397 tNET FF 1 R33C22[3][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/I2
12.790 0.570 tINS FR 16 R33C22[3][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/F
13.370 0.580 tNET RR 1 R32C27[2][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R32C27[2][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK
17.687 -0.035 tSu 1 R32C27[2][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.031, 35.957%; route: 3.385, 59.935%; tC2Q: 0.232, 4.107%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path14

Path Summary:

Slack 4.320
Data Arrival Time 13.367
Data Required Time 17.687
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
7.954 0.232 tC2Q RF 25 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
8.647 0.693 tNET FF 1 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
9.100 0.453 tINS FF 20 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
9.849 0.748 tNET FF 1 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
10.404 0.555 tINS FF 27 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
11.370 0.966 tNET FF 1 R33C23[3][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s2/I1
11.823 0.453 tINS FF 1 R33C23[3][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s2/F
12.220 0.397 tNET FF 1 R33C22[3][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/I2
12.790 0.570 tINS FR 16 R33C22[3][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/F
13.367 0.577 tNET RR 1 R31C26[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R31C26[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
17.687 -0.035 tSu 1 R31C26[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.031, 35.977%; route: 3.382, 59.913%; tC2Q: 0.232, 4.110%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path15

Path Summary:

Slack 4.331
Data Arrival Time 13.356
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_2_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.356 1.847 tNET RR 1 R30C26[1][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R30C26[1][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_2_s1/CLK
17.687 -0.035 tSu 1 R30C26[1][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 36.030%; route: 3.372, 59.852%; tC2Q: 0.232, 4.118%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path16

Path Summary:

Slack 4.331
Data Arrival Time 13.356
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_14_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.356 1.847 tNET RR 1 R30C26[1][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_14_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R30C26[1][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_14_s1/CLK
17.687 -0.035 tSu 1 R30C26[1][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_14_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 36.030%; route: 3.372, 59.852%; tC2Q: 0.232, 4.118%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path17

Path Summary:

Slack 4.331
Data Arrival Time 13.356
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.356 1.847 tNET RR 1 R30C26[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R30C26[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1/CLK
17.687 -0.035 tSu 1 R30C26[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_15_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 36.030%; route: 3.372, 59.852%; tC2Q: 0.232, 4.118%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path18

Path Summary:

Slack 4.337
Data Arrival Time 13.350
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_10_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.350 1.842 tNET RR 1 R31C26[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_10_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R31C26[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_10_s1/CLK
17.687 -0.035 tSu 1 R31C26[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 36.068%; route: 3.366, 59.810%; tC2Q: 0.232, 4.122%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path19

Path Summary:

Slack 4.337
Data Arrival Time 13.350
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.350 1.842 tNET RR 1 R31C26[0][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R31C26[0][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1/CLK
17.687 -0.035 tSu 1 R31C26[0][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 36.068%; route: 3.366, 59.810%; tC2Q: 0.232, 4.122%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path20

Path Summary:

Slack 4.340
Data Arrival Time 13.347
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_8_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.347 1.838 tNET RR 1 R32C24[2][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_8_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R32C24[2][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_8_s1/CLK
17.687 -0.035 tSu 1 R32C24[2][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 36.091%; route: 3.363, 59.784%; tC2Q: 0.232, 4.125%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path21

Path Summary:

Slack 4.340
Data Arrival Time 13.347
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
To gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK
7.954 0.232 tC2Q RF 2 R30C28[0][A] gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/Q
8.111 0.156 tNET FF 1 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/I3
8.666 0.555 tINS FF 8 R30C28[3][B] gw_gao_inst_0/u_la0_top/n20_s1/F
9.449 0.783 tNET FF 1 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/I2
10.004 0.555 tINS FF 3 R34C32[3][A] gw_gao_inst_0/u_la0_top/n801_s4/F
10.409 0.406 tNET FF 1 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/I0
10.780 0.371 tINS FF 48 R34C34[1][B] gw_gao_inst_0/u_la0_top/n801_s2/F
10.960 0.179 tNET FF 1 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/I3
11.509 0.549 tINS FR 48 R35C34[0][B] gw_gao_inst_0/u_la0_top/data_out_shift_reg_46_s3/F
13.347 1.838 tNET RR 1 R32C24[2][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R32C24[2][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1/CLK
17.687 -0.035 tSu 1 R32C24[2][A] gw_gao_inst_0/u_la0_top/data_out_shift_reg_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.030, 36.091%; route: 3.363, 59.784%; tC2Q: 0.232, 4.125%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path22

Path Summary:

Slack 4.342
Data Arrival Time 13.345
Data Required Time 17.687
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
7.954 0.232 tC2Q RF 25 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
8.647 0.693 tNET FF 1 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
9.100 0.453 tINS FF 20 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
9.849 0.748 tNET FF 1 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
10.404 0.555 tINS FF 27 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
11.370 0.966 tNET FF 1 R33C23[3][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s2/I1
11.823 0.453 tINS FF 1 R33C23[3][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s2/F
12.220 0.397 tNET FF 1 R33C22[3][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/I2
12.790 0.570 tINS FR 16 R33C22[3][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/F
13.345 0.555 tNET RR 1 R29C23[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R29C23[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
17.687 -0.035 tSu 1 R29C23[0][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.031, 36.121%; route: 3.360, 59.753%; tC2Q: 0.232, 4.126%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path23

Path Summary:

Slack 4.342
Data Arrival Time 13.345
Data Required Time 17.687
From gw_gao_inst_0/u_la0_top/module_state_1_s0
To gw_gao_inst_0/u_la0_top/capture_mem_addr_max_4_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR 1 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/CLK
7.954 0.232 tC2Q RF 25 R38C33[0][B] gw_gao_inst_0/u_la0_top/module_state_1_s0/Q
8.647 0.693 tNET FF 1 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/I1
9.100 0.453 tINS FF 20 R35C32[3][B] gw_gao_inst_0/u_la0_top/data_to_word_counter_15_s2/F
9.849 0.748 tNET FF 1 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/I3
10.404 0.555 tINS FF 27 R31C34[3][B] gw_gao_inst_0/u_la0_top/regsel_ld_en_s7/F
11.370 0.966 tNET FF 1 R33C23[3][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s2/I1
11.823 0.453 tINS FF 1 R33C23[3][B] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s2/F
12.220 0.397 tNET FF 1 R33C22[3][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/I2
12.790 0.570 tINS FR 16 R33C22[3][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_wr_s0/F
13.345 0.555 tNET RR 1 R29C23[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R29C23[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_4_s0/CLK
17.687 -0.035 tSu 1 R29C23[1][A] gw_gao_inst_0/u_la0_top/capture_mem_addr_max_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%
Arrival Data Path Delay cell: 2.031, 36.121%; route: 3.360, 59.753%; tC2Q: 0.232, 4.126%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path24

Path Summary:

Slack 4.284
Data Arrival Time 13.404
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/enable_reg_2_s0
To gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0
Launch Clk tck_pad_i:[F]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
7.616 2.616 tINS FF 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
7.616 0.000 tNET FF 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
8.303 0.688 tINS FF 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
11.228 2.925 tNET FF 1 R29C30[2][A] gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK
11.460 0.232 tC2Q FF 3 R29C30[2][A] gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q
12.107 0.648 tNET FF 1 R31C28[1][B] gw_gao_inst_0/u_icon_top/n52_s0/I2
12.677 0.570 tINS FR 5 R31C28[1][B] gw_gao_inst_0/u_icon_top/n52_s0/F
13.404 0.726 tNET RR 1 R31C28[0][B] gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R31C28[0][B] gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0/CLK
17.687 -0.035 tSu 1 R31C28[0][B] gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0

Path Statistics:

Clock Skew 1.494
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 3.303, 53.037%; route: 2.925, 46.963%
Arrival Data Path Delay cell: 0.570, 26.198%; route: 1.374, 63.139%; tC2Q: 0.232, 10.663%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Path25

Path Summary:

Slack 4.284
Data Arrival Time 13.404
Data Required Time 17.687
From gw_gao_inst_0/u_icon_top/enable_reg_2_s0
To gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0
Launch Clk tck_pad_i:[F]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
7.616 2.616 tINS FF 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
7.616 0.000 tNET FF 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
8.303 0.688 tINS FF 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
11.228 2.925 tNET FF 1 R29C30[2][A] gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK
11.460 0.232 tC2Q FF 3 R29C30[2][A] gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q
12.107 0.648 tNET FF 1 R31C28[1][B] gw_gao_inst_0/u_icon_top/n52_s0/I2
12.677 0.570 tINS FR 5 R31C28[1][B] gw_gao_inst_0/u_icon_top/n52_s0/F
13.404 0.726 tNET RR 1 R31C28[0][A] gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 tck_pad_i
10.000 0.000 tCL RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/I
14.230 4.230 tINS RR 1 IOR26[A] gw_gao_inst_0/tck_ibuf/O
14.230 0.000 tNET RR 1 R28C51 gw_gao_inst_0/u_gw_jtag/tck_pad_i
14.912 0.683 tINS RR 350 R28C51 gw_gao_inst_0/u_gw_jtag/tck_o
17.722 2.810 tNET RR 1 R31C28[0][A] gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0/CLK
17.687 -0.035 tSu 1 R31C28[0][A] gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0

Path Statistics:

Clock Skew 1.494
Setup Relationship 5.000
Logic Level 2
Arrival Clock Path Delay cell: 3.303, 53.037%; route: 2.925, 46.963%
Arrival Data Path Delay cell: 0.570, 26.198%; route: 1.374, 63.139%; tC2Q: 0.232, 10.663%
Required Clock Path Delay cell: 4.912, 63.614%; route: 2.810, 36.386%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.192
Data Arrival Time 4.840
Data Required Time 4.648
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C18[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
4.840 0.202 tC2Q RR 11 R34C18[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
4.840 0.000 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
4.648 0.010 tHld 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path2

Path Summary:

Slack 0.192
Data Arrival Time 4.840
Data Required Time 4.648
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C18[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
4.840 0.202 tC2Q RR 11 R34C18[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
4.840 0.000 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.648 0.010 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path3

Path Summary:

Slack 0.192
Data Arrival Time 4.840
Data Required Time 4.648
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C18[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
4.840 0.202 tC2Q RR 11 R34C18[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
4.840 0.000 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
4.648 0.010 tHld 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path4

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C21[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/CLK
4.840 0.202 tC2Q RR 1 R38C21[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path5

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/CLK
4.840 0.202 tC2Q RR 1 R38C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path6

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R39C21[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/CLK
4.840 0.202 tC2Q RR 1 R39C21[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path7

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C20[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK
4.840 0.202 tC2Q RR 1 R38C20[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path8

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R40C21[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK
4.840 0.202 tC2Q RR 1 R40C21[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path9

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R40C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/CLK
4.840 0.202 tC2Q RR 1 R40C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path10

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R39C20[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK
4.840 0.202 tC2Q RR 1 R39C20[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path11

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C18[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
4.840 0.202 tC2Q RR 1 R36C18[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path12

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C19[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/CLK
4.840 0.202 tC2Q RR 1 R38C19[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path13

Path Summary:

Slack 0.225
Data Arrival Time 5.112
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C19[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/CLK
4.840 0.202 tC2Q RR 1 R38C19[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q
5.112 0.272 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path14

Path Summary:

Slack 0.241
Data Arrival Time 5.127
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R39C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/CLK
4.840 0.202 tC2Q RR 1 R39C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q
5.127 0.288 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.288, 58.745%; tC2Q: 0.202, 41.255%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path15

Path Summary:

Slack 0.363
Data Arrival Time 5.249
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C20[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/CLK
4.840 0.202 tC2Q RR 1 R38C20[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q
5.249 0.410 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path16

Path Summary:

Slack 0.363
Data Arrival Time 5.249
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK
4.840 0.202 tC2Q RR 1 R36C21[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q
5.249 0.410 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path17

Path Summary:

Slack 0.363
Data Arrival Time 5.249
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/CLK
4.840 0.202 tC2Q RR 1 R36C21[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q
5.249 0.410 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path18

Path Summary:

Slack 0.363
Data Arrival Time 5.249
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R35C20[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK
4.840 0.202 tC2Q RR 1 R35C20[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q
5.249 0.410 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path19

Path Summary:

Slack 0.363
Data Arrival Time 5.249
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C20[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/CLK
4.840 0.202 tC2Q RR 1 R36C20[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q
5.249 0.410 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path20

Path Summary:

Slack 0.363
Data Arrival Time 5.249
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R35C18[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/CLK
4.840 0.202 tC2Q RR 1 R35C18[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q
5.249 0.410 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[15]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path21

Path Summary:

Slack 0.363
Data Arrival Time 5.249
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C18[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/CLK
4.840 0.202 tC2Q RR 1 R36C18[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q
5.249 0.410 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[4] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path22

Path Summary:

Slack 0.375
Data Arrival Time 5.261
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C18[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/CLK
4.840 0.202 tC2Q RR 1 R38C18[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q
5.261 0.422 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path23

Path Summary:

Slack 0.375
Data Arrival Time 5.261
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C18[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/CLK
4.840 0.202 tC2Q RR 1 R38C18[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q
5.261 0.422 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[6] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path24

Path Summary:

Slack 0.378
Data Arrival Time 5.264
Data Required Time 4.887
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R40C21[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/CLK
4.840 0.202 tC2Q RR 1 R40C21[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q
5.264 0.425 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
4.887 0.249 tHld 1 BSRAM_R46[5] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.425, 67.773%; tC2Q: 0.202, 32.227%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path25

Path Summary:

Slack 0.425
Data Arrival Time 5.074
Data Required Time 4.649
From BLC_Top/BLC_top/black_average/Mean_B/bi_2_s0
To BLC_Top/BLC_top/black_average/Mean_B/bi_2_s0
Launch Clk SYM_CLK:[R]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R26C22[1][A] BLC_Top/BLC_top/black_average/Mean_B/bi_2_s0/CLK
4.840 0.202 tC2Q RR 3 R26C22[1][A] BLC_Top/BLC_top/black_average/Mean_B/bi_2_s0/Q
4.842 0.002 tNET RR 2 R26C22[1][A] BLC_Top/BLC_top/black_average/Mean_B/n598_s/I1
5.074 0.232 tINS RF 1 R26C22[1][A] BLC_Top/BLC_top/black_average/Mean_B/n598_s/SUM
5.074 0.000 tNET FF 1 R26C22[1][A] BLC_Top/BLC_top/black_average/Mean_B/bi_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R26C22[1][A] BLC_Top/BLC_top/black_average/Mean_B/bi_2_s0/CLK
4.649 0.011 tHld 1 R26C22[1][A] BLC_Top/BLC_top/black_average/Mean_B/bi_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R39C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R39C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLK
26.466 -0.035 tSu 1 R39C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path2

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R34C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R34C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLK
26.466 -0.035 tSu 1 R34C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path3

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R34C25[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R34C25[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0/CLK
26.466 -0.035 tSu 1 R34C25[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path4

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R34C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R34C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0/CLK
26.466 -0.035 tSu 1 R34C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path5

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R34C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R34C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0/CLK
26.466 -0.035 tSu 1 R34C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path6

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R34C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R34C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0/CLK
26.466 -0.035 tSu 1 R34C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path7

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R35C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R35C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0/CLK
26.466 -0.035 tSu 1 R35C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path8

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R35C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R35C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0/CLK
26.466 -0.035 tSu 1 R35C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path9

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R35C31[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R35C31[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0/CLK
26.466 -0.035 tSu 1 R35C31[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path10

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R34C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R34C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0/CLK
26.466 -0.035 tSu 1 R34C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path11

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R34C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R34C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0/CLK
26.466 -0.035 tSu 1 R34C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path12

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R34C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R34C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0/CLK
26.466 -0.035 tSu 1 R34C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path13

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R36C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R36C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0/CLK
26.466 -0.035 tSu 1 R36C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path14

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R36C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R36C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0/CLK
26.466 -0.035 tSu 1 R36C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path15

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R36C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R36C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0/CLK
26.466 -0.035 tSu 1 R36C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path16

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R35C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R35C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0/CLK
26.466 -0.035 tSu 1 R35C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path17

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R35C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R35C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0/CLK
26.466 -0.035 tSu 1 R35C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path18

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R35C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R35C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0/CLK
26.466 -0.035 tSu 1 R35C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path19

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R36C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R36C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0/CLK
26.466 -0.035 tSu 1 R36C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path20

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R36C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R36C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0/CLK
26.466 -0.035 tSu 1 R36C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path21

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R36C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R36C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0/CLK
26.466 -0.035 tSu 1 R36C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path22

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R38C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R38C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0/CLK
26.466 -0.035 tSu 1 R38C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path23

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R38C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R38C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0/CLK
26.466 -0.035 tSu 1 R38C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path24

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R36C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R36C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0/CLK
26.466 -0.035 tSu 1 R36C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Path25

Path Summary:

Slack 10.017
Data Arrival Time 16.449
Data Required Time 26.466
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.616 2.616 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
14.890 2.274 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
15.122 0.232 tC2Q FF 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.449 1.327 tNET FF 1 R35C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 SYM_CLK
20.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
24.230 4.230 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
26.501 2.271 tNET RR 1 R35C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0/CLK
26.466 -0.035 tSu 1 R35C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0

Path Statistics:

Clock Skew 1.611
Setup Relationship 10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.616, 53.488%; route: 2.274, 46.512%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay cell: 4.230, 65.063%; route: 2.271, 34.937%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R39C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R39C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLK
4.649 0.011 tHld 1 R39C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path2

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R34C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLK
4.649 0.011 tHld 1 R34C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path3

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R34C25[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C25[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0/CLK
4.649 0.011 tHld 1 R34C25[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path4

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R34C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0/CLK
4.649 0.011 tHld 1 R34C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_2_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path5

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R34C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0/CLK
4.649 0.011 tHld 1 R34C27[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_3_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path6

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R34C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0/CLK
4.649 0.011 tHld 1 R34C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_4_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path7

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R35C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R35C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0/CLK
4.649 0.011 tHld 1 R35C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_5_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path8

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R35C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R35C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0/CLK
4.649 0.011 tHld 1 R35C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_6_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path9

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R35C31[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R35C31[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0/CLK
4.649 0.011 tHld 1 R35C31[2][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_7_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path10

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R34C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0/CLK
4.649 0.011 tHld 1 R34C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_8_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path11

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R34C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0/CLK
4.649 0.011 tHld 1 R34C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_9_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path12

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R34C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R34C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0/CLK
4.649 0.011 tHld 1 R34C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_10_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path13

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R36C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0/CLK
4.649 0.011 tHld 1 R36C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_11_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path14

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R36C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0/CLK
4.649 0.011 tHld 1 R36C31[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_12_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path15

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R36C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0/CLK
4.649 0.011 tHld 1 R36C31[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_13_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path16

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R35C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R35C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0/CLK
4.649 0.011 tHld 1 R35C31[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_14_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path17

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R35C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R35C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0/CLK
4.649 0.011 tHld 1 R35C31[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_15_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path18

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R35C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R35C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0/CLK
4.649 0.011 tHld 1 R35C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_16_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path19

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R36C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0/CLK
4.649 0.011 tHld 1 R36C30[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_17_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path20

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R36C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0/CLK
4.649 0.011 tHld 1 R36C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_18_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path21

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R36C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0/CLK
4.649 0.011 tHld 1 R36C30[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_19_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path22

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R38C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0/CLK
4.649 0.011 tHld 1 R38C30[0][B] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_20_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path23

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R38C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R38C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0/CLK
4.649 0.011 tHld 1 R38C29[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_21_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path24

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R36C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R36C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0/CLK
4.649 0.011 tHld 1 R36C27[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_22_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Path25

Path Summary:

Slack 10.063
Data Arrival Time 14.711
Data Required Time 4.649
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0
Launch Clk SYM_CLK:[F]
Latch Clk SYM_CLK:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 SYM_CLK
10.000 0.000 tCL FF 1 IOT27[A] SYM_CLK_ibuf/I
12.140 2.140 tINS FF 926 IOT27[A] SYM_CLK_ibuf/O
13.653 1.514 tNET FF 1 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.855 0.202 tC2Q FR 99 R31C29[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.711 0.856 tNET RR 1 R35C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 IOT27[A] SYM_CLK_ibuf/I
3.126 3.126 tINS RR 926 IOT27[A] SYM_CLK_ibuf/O
4.638 1.511 tNET RR 1 R35C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0/CLK
4.649 0.011 tHld 1 R35C27[0][A] gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_23_s0

Path Statistics:

Clock Skew 0.984
Hold Relationship -10.000
Logic Level 1
Arrival Clock Path Delay cell: 2.140, 58.574%; route: 1.514, 41.426%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay cell: 3.126, 67.413%; route: 1.511, 32.587%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_icon_top/shift_dr_capture_dr_dly_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_icon_top/shift_dr_capture_dr_dly_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_icon_top/shift_dr_capture_dr_dly_0_s0/CLK

MPW2

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_icon_top/module_id_reg_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK

MPW3

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_icon_top/module_id_reg_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CLK

MPW4

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/data_register_41_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_la0_top/data_register_41_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_la0_top/data_register_41_s0/CLK

MPW5

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/data_register_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_la0_top/data_register_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_la0_top/data_register_9_s0/CLK

MPW6

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/internal_register_select_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_la0_top/internal_register_select_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_la0_top/internal_register_select_9_s0/CLK

MPW7

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/internal_register_select_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_la0_top/internal_register_select_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_la0_top/internal_register_select_1_s0/CLK

MPW8

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_1_s0/CLK

MPW9

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_la0_top/capture_mem_addr_max_15_s0/CLK

MPW10

MPW Summary:

Slack: 1.025
Actual Width: 2.025
Required Width: 1.000
Type: High Pulse Width
Clock: tck_pad_i
Objects: gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR gw_gao_inst_0/tck_ibuf/I
4.230 4.230 tINS RR gw_gao_inst_0/tck_ibuf/O
4.230 0.000 tNET RR gw_gao_inst_0/u_gw_jtag/tck_pad_i
4.912 0.683 tINS RR gw_gao_inst_0/u_gw_jtag/tck_o
7.722 2.810 tNET RR gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 tck_pad_i
5.000 0.000 tCL FF gw_gao_inst_0/tck_ibuf/I
7.140 2.140 tINS FF gw_gao_inst_0/tck_ibuf/O
7.140 0.000 tNET FF gw_gao_inst_0/u_gw_jtag/tck_pad_i
7.817 0.678 tINS FF gw_gao_inst_0/u_gw_jtag/tck_o
9.747 1.930 tNET FF gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
926 SYM_CLK_d 10.816 2.274
350 control0[0] 4.077 2.925
115 frame_sync 12.078 4.126
111 frame_end_Z 14.821 2.729
110 n888_6 15.826 1.878
110 n888_6 14.821 2.148
110 n888_6 16.108 2.092
99 rst_ao 10.017 1.327
76 bi_5_9 15.437 0.954
76 bi_5_9 15.752 1.143

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R36C28 88.89%
R18C20 87.50%
R17C25 87.50%
R20C20 87.50%
R36C15 87.50%
R17C33 86.11%
R17C34 86.11%
R20C19 86.11%
R20C21 86.11%
R35C29 86.11%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name SYM_CLK -period 20 -waveform {0 10} [get_ports {SYM_CLK}]
TC_CLOCK Actived create_clock -name tck_pad_i -period 10 -waveform {0 5} [get_ports {tck_pad_i}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {SYM_CLK}] -to [get_clocks {tck_pad_i}]