Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\CSC\data\color_space_convertor.v
C:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\CSC\data\csc_wrapper.v
C:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\CSC\data\static_macro_define.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-6
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Tue Oct 31 11:27:21 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module yc_rgb_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 37.383MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 37.383MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 37.383MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 37.383MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 37.383MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 37.383MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 37.383MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 37.383MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 37.383MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 37.383MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 37.383MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 37.383MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.226s, Peak memory usage = 50.516MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 50.516MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 50.516MB
Total Time and Memory Usage CPU time = 0h 0m 0.527s, Elapsed time = 0h 0m 0.557s, Peak memory usage = 50.516MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 52
I/O Buf 52
    IBUF 27
    OBUF 25
Register 123
    DFFE 45
    DFFC 78
LUT 45
    LUT2 3
    LUT3 18
    LUT4 24
ALU 238
    ALU 238
INV 1
    INV 1
DSP
    MULT18X18 9

Resource Utilization Summary

Resource Usage Utilization
Logic 284(46 LUT, 238 ALU) / 20736 2%
Register 123 / 16509 <1%
  --Register as Latch 0 / 16509 0%
  --Register as FF 123 / 16509 <1%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_clk Base 10.000 100.0 0.000 5.000 I_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 100.0(MHz) 258.2(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.128
Data Arrival Time 4.700
Data Required Time 10.828
From csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst
To csc_wrapper_inst/csc_core_inst/Dout2_sum_31_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 132 I_clk_ibuf/O
0.863 0.180 tNET RR 36 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/CLK
1.085 0.223 tC2Q RF 1 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/DOUT[0]
1.322 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1203_s/I1
1.892 0.570 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1203_s/COUT
1.892 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1202_s/CIN
1.927 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1202_s/COUT
1.927 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1201_s/CIN
1.963 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1201_s/COUT
1.963 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1200_s/CIN
2.433 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1200_s/SUM
2.670 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1200_s1/I0
3.219 0.549 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1200_s1/COUT
3.219 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1199_s1/CIN
3.254 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1199_s1/COUT
3.254 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1198_s1/CIN
3.289 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1198_s1/COUT
3.289 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1197_s1/CIN
3.324 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1197_s1/COUT
3.324 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1196_s1/CIN
3.359 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1196_s1/COUT
3.359 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1195_s1/CIN
3.395 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1195_s1/COUT
3.395 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1194_s1/CIN
3.430 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1194_s1/COUT
3.430 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1193_s1/CIN
3.465 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1193_s1/COUT
3.465 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1192_s1/CIN
3.500 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1192_s1/COUT
3.500 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1191_s1/CIN
3.535 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1191_s1/COUT
3.535 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1190_s1/CIN
3.571 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1190_s1/COUT
3.571 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1189_s1/CIN
3.606 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1189_s1/COUT
3.606 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1188_s1/CIN
3.641 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1188_s1/COUT
3.641 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1187_s1/CIN
3.676 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1187_s1/COUT
3.676 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1186_s1/CIN
3.711 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1186_s1/COUT
3.711 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1185_s1/CIN
3.747 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1185_s1/COUT
3.747 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1184_s1/CIN
3.782 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1184_s1/COUT
3.782 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1183_s1/CIN
3.817 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1183_s1/COUT
3.817 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1182_s1/CIN
3.852 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1182_s1/COUT
3.852 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1181_s1/CIN
3.887 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1181_s1/COUT
3.887 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1180_s1/CIN
3.923 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1180_s1/COUT
3.923 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1179_s1/CIN
3.958 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1179_s1/COUT
3.958 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1178_s1/CIN
3.993 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1178_s1/COUT
3.993 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1172_s1/CIN
4.463 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1172_s1/SUM
4.700 0.237 tNET FF 1 csc_wrapper_inst/csc_core_inst/Dout2_sum_31_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 132 I_clk_ibuf/O
10.863 0.180 tNET RR 1 csc_wrapper_inst/csc_core_inst/Dout2_sum_31_s0/CLK
10.828 -0.035 tSu 1 csc_wrapper_inst/csc_core_inst/Dout2_sum_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.904, 75.670%; route: 0.711, 18.528%; tC2Q: 0.223, 5.802%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 6.128
Data Arrival Time 4.700
Data Required Time 10.828
From csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst
To csc_wrapper_inst/csc_core_inst/Dout1_sum_31_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 132 I_clk_ibuf/O
0.863 0.180 tNET RR 36 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/CLK
1.085 0.223 tC2Q RF 1 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/DOUT[0]
1.322 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1104_s/I1
1.892 0.570 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1104_s/COUT
1.892 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1103_s/CIN
1.927 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1103_s/COUT
1.927 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1102_s/CIN
1.963 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1102_s/COUT
1.963 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1101_s/CIN
2.433 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1101_s/SUM
2.670 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1101_s1/I0
3.219 0.549 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1101_s1/COUT
3.219 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1100_s1/CIN
3.254 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1100_s1/COUT
3.254 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1099_s1/CIN
3.289 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1099_s1/COUT
3.289 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1098_s1/CIN
3.324 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1098_s1/COUT
3.324 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1097_s1/CIN
3.359 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1097_s1/COUT
3.359 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1096_s1/CIN
3.395 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1096_s1/COUT
3.395 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1095_s1/CIN
3.430 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1095_s1/COUT
3.430 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1094_s1/CIN
3.465 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1094_s1/COUT
3.465 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1093_s1/CIN
3.500 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1093_s1/COUT
3.500 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1092_s1/CIN
3.535 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1092_s1/COUT
3.535 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1091_s1/CIN
3.571 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1091_s1/COUT
3.571 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1090_s1/CIN
3.606 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1090_s1/COUT
3.606 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1089_s1/CIN
3.641 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1089_s1/COUT
3.641 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1088_s1/CIN
3.676 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1088_s1/COUT
3.676 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1087_s1/CIN
3.711 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1087_s1/COUT
3.711 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1086_s1/CIN
3.747 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1086_s1/COUT
3.747 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1085_s1/CIN
3.782 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1085_s1/COUT
3.782 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1084_s1/CIN
3.817 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1084_s1/COUT
3.817 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1083_s1/CIN
3.852 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1083_s1/COUT
3.852 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1082_s1/CIN
3.887 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1082_s1/COUT
3.887 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1081_s1/CIN
3.923 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1081_s1/COUT
3.923 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1080_s1/CIN
3.958 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1080_s1/COUT
3.958 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1079_s1/CIN
3.993 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1079_s1/COUT
3.993 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1073_s1/CIN
4.463 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1073_s1/SUM
4.700 0.237 tNET FF 1 csc_wrapper_inst/csc_core_inst/Dout1_sum_31_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 132 I_clk_ibuf/O
10.863 0.180 tNET RR 1 csc_wrapper_inst/csc_core_inst/Dout1_sum_31_s0/CLK
10.828 -0.035 tSu 1 csc_wrapper_inst/csc_core_inst/Dout1_sum_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.904, 75.670%; route: 0.711, 18.528%; tC2Q: 0.223, 5.802%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 6.128
Data Arrival Time 4.700
Data Required Time 10.828
From csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst
To csc_wrapper_inst/csc_core_inst/Dout0_sum_31_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 132 I_clk_ibuf/O
0.863 0.180 tNET RR 36 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst/CLK
1.085 0.223 tC2Q RF 1 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/mult18x18_inst/DOUT[0]
1.322 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1005_s/I1
1.892 0.570 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1005_s/COUT
1.892 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1004_s/CIN
1.927 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1004_s/COUT
1.927 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1003_s/CIN
1.963 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1003_s/COUT
1.963 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1002_s/CIN
2.433 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1002_s/SUM
2.670 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1002_s1/I0
3.219 0.549 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1002_s1/COUT
3.219 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1001_s1/CIN
3.254 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1001_s1/COUT
3.254 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1000_s1/CIN
3.289 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1000_s1/COUT
3.289 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n999_s1/CIN
3.324 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n999_s1/COUT
3.324 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n998_s1/CIN
3.359 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n998_s1/COUT
3.359 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n997_s1/CIN
3.395 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n997_s1/COUT
3.395 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n996_s1/CIN
3.430 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n996_s1/COUT
3.430 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n995_s1/CIN
3.465 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n995_s1/COUT
3.465 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n994_s1/CIN
3.500 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n994_s1/COUT
3.500 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n993_s1/CIN
3.535 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n993_s1/COUT
3.535 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n992_s1/CIN
3.571 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n992_s1/COUT
3.571 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n991_s1/CIN
3.606 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n991_s1/COUT
3.606 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n990_s1/CIN
3.641 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n990_s1/COUT
3.641 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n989_s1/CIN
3.676 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n989_s1/COUT
3.676 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n988_s1/CIN
3.711 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n988_s1/COUT
3.711 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n987_s1/CIN
3.747 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n987_s1/COUT
3.747 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n986_s1/CIN
3.782 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n986_s1/COUT
3.782 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n985_s1/CIN
3.817 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n985_s1/COUT
3.817 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n984_s1/CIN
3.852 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n984_s1/COUT
3.852 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n983_s1/CIN
3.887 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n983_s1/COUT
3.887 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n982_s1/CIN
3.923 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n982_s1/COUT
3.923 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n981_s1/CIN
3.958 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n981_s1/COUT
3.958 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n980_s1/CIN
3.993 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n980_s1/COUT
3.993 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n974_s1/CIN
4.463 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n974_s1/SUM
4.700 0.237 tNET FF 1 csc_wrapper_inst/csc_core_inst/Dout0_sum_31_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 132 I_clk_ibuf/O
10.863 0.180 tNET RR 1 csc_wrapper_inst/csc_core_inst/Dout0_sum_31_s0/CLK
10.828 -0.035 tSu 1 csc_wrapper_inst/csc_core_inst/Dout0_sum_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.904, 75.670%; route: 0.711, 18.528%; tC2Q: 0.223, 5.802%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 6.163
Data Arrival Time 4.665
Data Required Time 10.828
From csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst
To csc_wrapper_inst/csc_core_inst/Dout2_sum_25_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 132 I_clk_ibuf/O
0.863 0.180 tNET RR 36 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/CLK
1.085 0.223 tC2Q RF 1 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/mult18x18_inst/DOUT[0]
1.322 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1203_s/I1
1.892 0.570 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1203_s/COUT
1.892 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1202_s/CIN
1.927 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1202_s/COUT
1.927 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1201_s/CIN
1.963 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1201_s/COUT
1.963 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1200_s/CIN
2.433 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1200_s/SUM
2.670 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1200_s1/I0
3.219 0.549 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1200_s1/COUT
3.219 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1199_s1/CIN
3.254 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1199_s1/COUT
3.254 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1198_s1/CIN
3.289 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1198_s1/COUT
3.289 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1197_s1/CIN
3.324 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1197_s1/COUT
3.324 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1196_s1/CIN
3.359 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1196_s1/COUT
3.359 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1195_s1/CIN
3.395 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1195_s1/COUT
3.395 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1194_s1/CIN
3.430 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1194_s1/COUT
3.430 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1193_s1/CIN
3.465 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1193_s1/COUT
3.465 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1192_s1/CIN
3.500 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1192_s1/COUT
3.500 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1191_s1/CIN
3.535 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1191_s1/COUT
3.535 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1190_s1/CIN
3.571 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1190_s1/COUT
3.571 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1189_s1/CIN
3.606 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1189_s1/COUT
3.606 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1188_s1/CIN
3.641 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1188_s1/COUT
3.641 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1187_s1/CIN
3.676 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1187_s1/COUT
3.676 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1186_s1/CIN
3.711 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1186_s1/COUT
3.711 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1185_s1/CIN
3.747 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1185_s1/COUT
3.747 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1184_s1/CIN
3.782 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1184_s1/COUT
3.782 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1183_s1/CIN
3.817 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1183_s1/COUT
3.817 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1182_s1/CIN
3.852 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1182_s1/COUT
3.852 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1181_s1/CIN
3.887 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1181_s1/COUT
3.887 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1180_s1/CIN
3.923 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1180_s1/COUT
3.923 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1179_s1/CIN
3.958 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1179_s1/COUT
3.958 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1178_s1/CIN
4.428 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1178_s1/SUM
4.665 0.237 tNET FF 1 csc_wrapper_inst/csc_core_inst/Dout2_sum_25_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 132 I_clk_ibuf/O
10.863 0.180 tNET RR 1 csc_wrapper_inst/csc_core_inst/Dout2_sum_25_s0/CLK
10.828 -0.035 tSu 1 csc_wrapper_inst/csc_core_inst/Dout2_sum_25_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.869, 75.445%; route: 0.711, 18.699%; tC2Q: 0.223, 5.856%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.163
Data Arrival Time 4.665
Data Required Time 10.828
From csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst
To csc_wrapper_inst/csc_core_inst/Dout1_sum_25_s0
Launch Clk I_clk[R]
Latch Clk I_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 I_clk_ibuf/I
0.683 0.683 tINS RR 132 I_clk_ibuf/O
0.863 0.180 tNET RR 36 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/CLK
1.085 0.223 tC2Q RF 1 csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/mult18x18_inst/DOUT[0]
1.322 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1104_s/I1
1.892 0.570 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1104_s/COUT
1.892 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1103_s/CIN
1.927 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1103_s/COUT
1.927 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1102_s/CIN
1.963 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1102_s/COUT
1.963 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1101_s/CIN
2.433 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1101_s/SUM
2.670 0.237 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1101_s1/I0
3.219 0.549 tINS FR 1 csc_wrapper_inst/csc_core_inst/n1101_s1/COUT
3.219 0.000 tNET RR 2 csc_wrapper_inst/csc_core_inst/n1100_s1/CIN
3.254 0.035 tINS RF 1 csc_wrapper_inst/csc_core_inst/n1100_s1/COUT
3.254 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1099_s1/CIN
3.289 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1099_s1/COUT
3.289 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1098_s1/CIN
3.324 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1098_s1/COUT
3.324 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1097_s1/CIN
3.359 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1097_s1/COUT
3.359 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1096_s1/CIN
3.395 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1096_s1/COUT
3.395 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1095_s1/CIN
3.430 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1095_s1/COUT
3.430 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1094_s1/CIN
3.465 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1094_s1/COUT
3.465 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1093_s1/CIN
3.500 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1093_s1/COUT
3.500 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1092_s1/CIN
3.535 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1092_s1/COUT
3.535 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1091_s1/CIN
3.571 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1091_s1/COUT
3.571 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1090_s1/CIN
3.606 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1090_s1/COUT
3.606 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1089_s1/CIN
3.641 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1089_s1/COUT
3.641 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1088_s1/CIN
3.676 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1088_s1/COUT
3.676 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1087_s1/CIN
3.711 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1087_s1/COUT
3.711 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1086_s1/CIN
3.747 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1086_s1/COUT
3.747 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1085_s1/CIN
3.782 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1085_s1/COUT
3.782 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1084_s1/CIN
3.817 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1084_s1/COUT
3.817 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1083_s1/CIN
3.852 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1083_s1/COUT
3.852 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1082_s1/CIN
3.887 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1082_s1/COUT
3.887 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1081_s1/CIN
3.923 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1081_s1/COUT
3.923 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1080_s1/CIN
3.958 0.035 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1080_s1/COUT
3.958 0.000 tNET FF 2 csc_wrapper_inst/csc_core_inst/n1079_s1/CIN
4.428 0.470 tINS FF 1 csc_wrapper_inst/csc_core_inst/n1079_s1/SUM
4.665 0.237 tNET FF 1 csc_wrapper_inst/csc_core_inst/Dout1_sum_25_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_clk
10.000 0.000 tCL RR 1 I_clk_ibuf/I
10.682 0.683 tINS RR 132 I_clk_ibuf/O
10.863 0.180 tNET RR 1 csc_wrapper_inst/csc_core_inst/Dout1_sum_25_s0/CLK
10.828 -0.035 tSu 1 csc_wrapper_inst/csc_core_inst/Dout1_sum_25_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.869, 75.445%; route: 0.711, 18.699%; tC2Q: 0.223, 5.856%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%