Power Messages

Report Title Power Analysis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\impl\gwsynthesis\csc_ref_design.vg
Physical Constraints File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\csc_ref_design.cst
Timing Constraints File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\csc_ref_design.sdc
Version V1.9.9 Beta-6
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Tue Oct 31 11:27:54 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Power Summary

Power Information:

Total Power (mW) 136.713
Quiescent Power (mW) 92.907
Dynamic Power (mW) 43.806

Thermal Information:

Junction Temperature 28.259
Theta JA 23.840
Max Allowed Ambient Temperature 81.741

Configure Information:

Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125
Use Vectorless Estimation false
Filter Glitches false
Related Vcd File
Related Saif File
Use Custom Theta JA false
Air Flow LFM_0
Heat Sink None
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Ambient Temperature 25.000

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.000 28.649 61.508 90.157
VCCX 2.500 2.646 11.364 35.024
VCCIO15 1.500 0.106 0.130 0.354
VCCIO25 2.500 0.000 0.055 0.136
VCCIO33 3.300 2.540 0.806 11.041

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 2.953 NA 8.428
IO 26.502 8.699 10.197
PLL 7.845 NA NA
DSP 15.188 NA 4.339

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
video_top 25.986 25.986(25.891)
video_top/Gowin_rPLL_inst/ 7.845 7.845(0.000)
video_top/I2C_MASTER_Top_inst0/ 0.120 0.120(0.120)
video_top/I2C_MASTER_Top_inst0/u_i2c_master/ 0.120 0.120(0.102)
video_top/I2C_MASTER_Top_inst0/u_i2c_master/bit_controller/ 0.066 0.066(0.000)
video_top/I2C_MASTER_Top_inst0/u_i2c_master/byte_controller/ 0.036 0.036(0.000)
video_top/adv7513_iic_init_inst0/ 0.081 0.081(0.000)
video_top/key_debounceN_inst0/ 0.052 0.052(0.000)
video_top/rgb_yc_top_inst/ 8.569 8.569(8.569)
video_top/rgb_yc_top_inst/csc_wrapper_inst/ 8.569 8.569(8.569)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/ 8.569 8.569(7.594)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/ 0.844 0.844(0.000)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/ 0.844 0.844(0.000)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/ 0.844 0.844(0.000)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/ 0.844 0.844(0.000)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/ 0.844 0.844(0.000)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/ 0.844 0.844(0.000)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/ 0.844 0.844(0.000)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/ 0.844 0.844(0.000)
video_top/rgb_yc_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/ 0.844 0.844(0.000)
video_top/testpattern_inst/ 0.275 0.275(0.000)
video_top/yc_rgb_top_inst/ 8.949 8.949(8.949)
video_top/yc_rgb_top_inst/csc_wrapper_inst/ 8.949 8.949(8.949)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/ 8.949 8.949(7.594)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst0/ 0.844 0.844(0.000)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst1/ 0.844 0.844(0.000)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[0].gw_mult_inst2/ 0.844 0.844(0.000)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst0/ 0.844 0.844(0.000)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst1/ 0.844 0.844(0.000)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[1].gw_mult_inst2/ 0.844 0.844(0.000)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst0/ 0.844 0.844(0.000)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst1/ 0.844 0.844(0.000)
video_top/yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/loop1[2].gw_mult_inst2/ 0.844 0.844(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk 75.000 17.862
Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk 50.000 0.296
I_clk 50.000 7.845