Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\adv7513_iic_init.v
E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\color_space_convertor\rgb_yc_top.v
E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\color_space_convertor\yc_rgb_top.v
E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\gowin_rpll\gowin_rpll.v
E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\i2c_master\i2c_master.v
E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\key_debounceN.v
E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\testpattern.v
E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_CSC_RefDesign\project\src\video_top.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-6
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Tue Oct 31 11:27:27 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module video_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.585s, Peak memory usage = 440.320MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 440.320MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 440.320MB
    Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 440.320MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 440.320MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 440.320MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 440.320MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 440.320MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 440.320MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 440.320MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 440.320MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 440.320MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.147s, Peak memory usage = 440.320MB
Generate output files:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 440.320MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 440.320MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 36
I/O Buf 36
    IBUF 2
    OBUF 32
    IOBUF 2
Register 650
    DFF 3
    DFFE 91
    DFFR 32
    DFFP 10
    DFFPE 7
    DFFC 300
    DFFCE 207
LUT 841
    LUT2 93
    LUT3 214
    LUT4 534
ALU 420
    ALU 420
INV 5
    INV 5
DSP
    MULT18X18 18
CLOCK 1
    rPLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1266(846 LUT, 420 ALU) / 20736 7%
Register 650 / 16509 4%
  --Register as Latch 0 / 16509 0%
  --Register as FF 650 / 16509 4%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_clk Base 20.000 50.0 0.000 10.000 I_clk_ibuf/I
Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk Generated 13.333 75.0 0.000 6.667 I_clk_ibuf/I I_clk Gowin_rPLL_inst/rpll_inst/CLKOUT
Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 20.000 50.0 0.000 10.000 I_clk_ibuf/I I_clk Gowin_rPLL_inst/rpll_inst/CLKOUTP
Gowin_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 26.667 37.5 0.000 13.333 I_clk_ibuf/I I_clk Gowin_rPLL_inst/rpll_inst/CLKOUTD
Gowin_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 40.000 25.0 0.000 20.000 I_clk_ibuf/I I_clk Gowin_rPLL_inst/rpll_inst/CLKOUTD3

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk 75.0(MHz) 258.2(MHz) 7 TOP
2 Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk 50.0(MHz) 272.3(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.188
Data Arrival Time 21.618
Data Required Time 27.806
From key_debounceN_inst0/key_n_out1_s1
To yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0
Launch Clk Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]
Latch Clk Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
21.027 1.027 tCL RR 203 Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.207 0.180 tNET RR 1 key_debounceN_inst0/key_n_out1_s1/CLK
21.438 0.231 tC2Q RR 92 key_debounceN_inst0/key_n_out1_s1/Q
21.618 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
26.667 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.696 1.029 tCL RR 466 Gowin_rPLL_inst/rpll_inst/CLKOUT
27.876 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0/CLK
27.841 -0.035 tUnc yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0
27.806 -0.035 tSu 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_12_s0
Path Statistics:
Clock Skew: 0.002
Setup Relationship: 6.667
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.180, 43.796%; tC2Q: 0.231, 56.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 2

Path Summary:
Slack 6.188
Data Arrival Time 21.618
Data Required Time 27.806
From key_debounceN_inst0/key_n_out1_s1
To yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0
Launch Clk Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]
Latch Clk Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
21.027 1.027 tCL RR 203 Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.207 0.180 tNET RR 1 key_debounceN_inst0/key_n_out1_s1/CLK
21.438 0.231 tC2Q RR 92 key_debounceN_inst0/key_n_out1_s1/Q
21.618 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
26.667 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.696 1.029 tCL RR 466 Gowin_rPLL_inst/rpll_inst/CLKOUT
27.876 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0/CLK
27.841 -0.035 tUnc yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0
27.806 -0.035 tSu 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_13_s0
Path Statistics:
Clock Skew: 0.002
Setup Relationship: 6.667
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.180, 43.796%; tC2Q: 0.231, 56.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 3

Path Summary:
Slack 6.188
Data Arrival Time 21.618
Data Required Time 27.806
From key_debounceN_inst0/key_n_out1_s1
To yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0
Launch Clk Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]
Latch Clk Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
21.027 1.027 tCL RR 203 Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.207 0.180 tNET RR 1 key_debounceN_inst0/key_n_out1_s1/CLK
21.438 0.231 tC2Q RR 92 key_debounceN_inst0/key_n_out1_s1/Q
21.618 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
26.667 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.696 1.029 tCL RR 466 Gowin_rPLL_inst/rpll_inst/CLKOUT
27.876 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0/CLK
27.841 -0.035 tUnc yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0
27.806 -0.035 tSu 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_14_s0
Path Statistics:
Clock Skew: 0.002
Setup Relationship: 6.667
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.180, 43.796%; tC2Q: 0.231, 56.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 4

Path Summary:
Slack 6.188
Data Arrival Time 21.618
Data Required Time 27.806
From key_debounceN_inst0/key_n_out1_s1
To yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0
Launch Clk Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]
Latch Clk Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
21.027 1.027 tCL RR 203 Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.207 0.180 tNET RR 1 key_debounceN_inst0/key_n_out1_s1/CLK
21.438 0.231 tC2Q RR 92 key_debounceN_inst0/key_n_out1_s1/Q
21.618 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
26.667 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.696 1.029 tCL RR 466 Gowin_rPLL_inst/rpll_inst/CLKOUT
27.876 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0/CLK
27.841 -0.035 tUnc yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0
27.806 -0.035 tSu 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_15_s0
Path Statistics:
Clock Skew: 0.002
Setup Relationship: 6.667
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.180, 43.796%; tC2Q: 0.231, 56.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 5

Path Summary:
Slack 6.188
Data Arrival Time 21.618
Data Required Time 27.806
From key_debounceN_inst0/key_n_out1_s1
To yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0
Launch Clk Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]
Latch Clk Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk
21.027 1.027 tCL RR 203 Gowin_rPLL_inst/rpll_inst/CLKOUTP
21.207 0.180 tNET RR 1 key_debounceN_inst0/key_n_out1_s1/CLK
21.438 0.231 tC2Q RR 92 key_debounceN_inst0/key_n_out1_s1/Q
21.618 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
26.667 0.000 Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk
27.696 1.029 tCL RR 466 Gowin_rPLL_inst/rpll_inst/CLKOUT
27.876 0.180 tNET RR 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0/CLK
27.841 -0.035 tUnc yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0
27.806 -0.035 tSu 1 yc_rgb_top_inst/csc_wrapper_inst/csc_core_inst/Dout2_sum_16_s0
Path Statistics:
Clock Skew: 0.002
Setup Relationship: 6.667
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.180, 43.796%; tC2Q: 0.231, 56.204%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%