Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Tue Jan 16 09:32:59 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Uart_to_Bus_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.196s, Peak memory usage = 49.246MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 49.246MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 49.246MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 49.246MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 49.246MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 49.246MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 49.246MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 49.246MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 49.246MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 49.246MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 49.246MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 49.246MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 77.137MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.111s, Peak memory usage = 77.137MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 77.137MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 77.137MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 276
I/O Buf 276
    IBUF 102
    OBUF 174
Register 1441
    DFF 194
    DFFE 830
    DFFR 12
    DFFP 5
    DFFPE 4
    DFFC 210
    DFFCE 186
LUT 1076
    LUT2 176
    LUT3 528
    LUT4 372
ALU 40
    ALU 40
INV 11
    INV 11

Resource Utilization Summary

Resource Usage Utilization
Logic 1127(1087 LUT, 40 ALU) / 20736 6%
Register 1441 / 16173 9%
  --Register as Latch 0 / 16173 0%
  --Register as FF 1441 / 16173 9%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 10.000 100.0 0.000 5.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 100.0(MHz) 144.9(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.100
Data Arrival Time 7.907
Data Required Time 11.007
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_23_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1441 clk_i_ibuf/O
1.043 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_23_s0/CLK
1.275 0.232 tC2Q RF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_23_s0/Q
1.748 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s5/I1
2.303 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s5/F
2.777 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/I0
2.880 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/O
3.354 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/I1
3.457 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/O
3.931 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s58/I2
4.384 0.453 tINS FF 4 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s58/F
4.858 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s49/I1
5.413 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s49/F
5.887 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s50/I0
6.404 0.517 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s50/F
6.878 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/I1
7.433 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/F
7.907 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1441 clk_i_ibuf/O
11.042 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/CLK
11.007 -0.035 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%
Arrival Data Path Delay: cell: 2.841, 41.384%; route: 3.792, 55.237%; tC2Q: 0.232, 3.379%
Required Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%

Path 2

Path Summary:
Slack 3.100
Data Arrival Time 7.907
Data Required Time 11.007
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_6_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1441 clk_i_ibuf/O
1.043 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_6_s0/CLK
1.275 0.232 tC2Q RF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_6_s0/Q
1.748 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s3/I1
2.303 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s3/F
2.777 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s1/I0
2.880 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s1/O
3.354 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I0
3.457 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O
3.931 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/I2
4.384 0.453 tINS FF 4 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/F
4.858 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s53/I1
5.413 0.555 tINS FF 4 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s53/F
5.887 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s48/I0
6.404 0.517 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s48/F
6.878 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s47/I1
7.433 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s47/F
7.907 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1441 clk_i_ibuf/O
11.042 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/CLK
11.007 -0.035 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%
Arrival Data Path Delay: cell: 2.841, 41.384%; route: 3.792, 55.237%; tC2Q: 0.232, 3.379%
Required Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%

Path 3

Path Summary:
Slack 3.164
Data Arrival Time 7.843
Data Required Time 11.007
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1441 clk_i_ibuf/O
1.043 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/CLK
1.275 0.232 tC2Q RF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/Q
1.748 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/I1
2.303 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/F
2.777 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I0
2.880 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O
3.354 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1
3.457 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O
3.931 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/I2
4.384 0.453 tINS FF 4 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/F
4.858 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s53/I1
5.413 0.555 tINS FF 4 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s53/F
5.887 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s57/I1
6.442 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s57/F
6.916 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s56/I2
7.369 0.453 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s56/F
7.843 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1441 clk_i_ibuf/O
11.042 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1/CLK
11.007 -0.035 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%
Arrival Data Path Delay: cell: 2.777, 40.832%; route: 3.792, 55.757%; tC2Q: 0.232, 3.411%
Required Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%

Path 4

Path Summary:
Slack 3.202
Data Arrival Time 7.805
Data Required Time 11.007
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_21_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1441 clk_i_ibuf/O
1.043 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_21_s0/CLK
1.275 0.232 tC2Q RF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_21_s0/Q
1.748 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s5/I1
2.303 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s5/F
2.777 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I0
2.880 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O
3.354 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1
3.457 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O
3.931 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s56/I2
4.384 0.453 tINS FF 4 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s56/F
4.858 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s60/I1
5.413 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s60/F
5.887 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s58/I0
6.404 0.517 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s58/F
6.878 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s56/I2
7.331 0.453 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s56/F
7.805 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1441 clk_i_ibuf/O
11.042 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1/CLK
11.007 -0.035 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%
Arrival Data Path Delay: cell: 2.739, 40.500%; route: 3.792, 56.070%; tC2Q: 0.232, 3.430%
Required Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%

Path 5

Path Summary:
Slack 3.246
Data Arrival Time 7.761
Data Required Time 11.007
From uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0
To uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s1
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.683 0.683 tINS RR 1441 clk_i_ibuf/O
1.043 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/CLK
1.275 0.232 tC2Q RF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/Q
1.748 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/I1
2.303 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/F
2.777 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I0
2.880 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O
3.354 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1
3.457 0.103 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O
3.931 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/I2
4.384 0.453 tINS FF 4 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/F
4.858 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s59/I1
5.413 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s59/F
5.887 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s61/I1
6.442 0.555 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s61/F
6.916 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s55/I3
7.287 0.371 tINS FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s55/F
7.761 0.474 tNET FF 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.682 0.683 tINS RR 1441 clk_i_ibuf/O
11.042 0.360 tNET RR 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s1/CLK
11.007 -0.035 tSu 1 uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%
Arrival Data Path Delay: cell: 2.695, 40.110%; route: 3.792, 56.437%; tC2Q: 0.232, 3.453%
Required Clock Path Delay: cell: 0.683, 65.468%; route: 0.360, 34.532%