Top Level Module |
top |
Synthesis Process |
Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 0.994s, Peak memory usage = 943.574MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.159s, Peak memory usage = 943.574MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.142s, Peak memory usage = 943.574MB Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 943.574MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.113s, Peak memory usage = 943.574MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 943.574MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 943.574MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 943.574MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.166s, Peak memory usage = 943.574MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 943.574MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 943.574MB Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 943.574MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.195s, Peak memory usage = 943.574MB Generate output files: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.434s, Peak memory usage = 943.574MB
|
Total Time and Memory Usage |
CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 943.574MB |
Resource |
Usage |
I/O Port |
27 |
I/O Buf |
19 |
    IBUF |
7 |
    OBUF |
6 |
    IOBUF |
2 |
    TLVDS_IBUF |
2 |
    TLVDS_OBUF |
2 |
Register |
6181 |
    DFF |
382 |
    DFFE |
3249 |
    DFFS |
54 |
    DFFSE |
77 |
    DFFR |
259 |
    DFFRE |
1576 |
    DFFP |
8 |
    DFFPE |
4 |
    DFFC |
297 |
    DFFCE |
275 |
LUT |
5601 |
    LUT2 |
593 |
    LUT3 |
1457 |
    LUT4 |
3551 |
ALU |
646 |
    ALU |
646 |
SSRAM |
1 |
    RAM16SDP1 |
1 |
INV |
49 |
    INV |
49 |
IOLOGIC |
3 |
    IDES10 |
1 |
    OSER10 |
2 |
CLOCK |
5 |
    CLKDIV |
3 |
    rPLL |
2 |
Clock Name |
Type |
Period |
Frequency(MHz) |
Rise |
Fall |
Source |
Master |
Object |
i_clk |
Base |
20.000 |
50.0 |
0.000 |
10.000 |
|
|
i_clk_ibuf/I |
RX_CLK_P |
Base |
10.000 |
100.0 |
0.000 |
5.000 |
|
|
lvds_rx_clk_in/I |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT.default_gen_clk |
Generated |
50.000 |
20.0 |
0.000 |
25.000 |
lvds_rx_clk_in/I |
RX_CLK_P |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT |
u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk |
Generated |
16.667 |
60.0 |
0.000 |
8.333 |
i_clk_ibuf/I |
i_clk |
u0_syspll_rPLL/rpll_inst/CLKOUT |
u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk |
Generated |
16.667 |
60.0 |
0.000 |
8.333 |
i_clk_ibuf/I |
i_clk |
u0_syspll_rPLL/rpll_inst/CLKOUTP |
u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk |
Generated |
33.333 |
30.0 |
0.000 |
16.667 |
i_clk_ibuf/I |
i_clk |
u0_syspll_rPLL/rpll_inst/CLKOUTD |
u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk |
Generated |
50.000 |
20.0 |
0.000 |
25.000 |
i_clk_ibuf/I |
i_clk |
u0_syspll_rPLL/rpll_inst/CLKOUTD3 |
u1_CLKDIV/CLKOUT.default_gen_clk |
Generated |
40.000 |
25.0 |
0.000 |
20.000 |
i_clk_ibuf/I |
i_clk |
u1_CLKDIV/CLKOUT |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk |
Generated |
40.000 |
25.0 |
0.000 |
20.000 |
u1_CLKDIV/CLKOUT |
u1_CLKDIV/CLKOUT.default_gen_clk |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk |
Generated |
40.000 |
25.0 |
0.000 |
20.000 |
u1_CLKDIV/CLKOUT |
u1_CLKDIV/CLKOUT.default_gen_clk |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk |
Generated |
80.000 |
12.5 |
0.000 |
40.000 |
u1_CLKDIV/CLKOUT |
u1_CLKDIV/CLKOUT.default_gen_clk |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk |
Generated |
120.000 |
8.3 |
0.000 |
60.000 |
u1_CLKDIV/CLKOUT |
u1_CLKDIV/CLKOUT.default_gen_clk |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk |
Generated |
200.000 |
5.0 |
0.000 |
100.000 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
116.667 |
0.000 |
|
|
|
u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk |
117.845 |
1.179 |
tCL |
RR |
2032 |
u0_syspll_rPLL/rpll_inst/CLKOUT |
118.205 |
0.360 |
tNET |
RR |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/reconfig_cnt_4_s0/CLK |
118.437 |
0.232 |
tC2Q |
RF |
2 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/reconfig_cnt_4_s0/Q |
118.911 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/n132_s33/I1 |
119.466 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/n132_s33/F |
119.940 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/n132_s31/I0 |
120.457 |
0.517 |
tINS |
FF |
2 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/n132_s31/F |
120.931 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/n132_s30/I2 |
121.384 |
0.453 |
tINS |
FF |
2 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/n132_s30/F |
121.858 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/tx_pll_locked_o_d_s0/I2 |
122.311 |
0.453 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/tx_pll_locked_o_d_s0/F |
122.785 |
0.474 |
tNET |
FF |
1 |
u_local2reg/n3540_s74/I1 |
123.340 |
0.555 |
tINS |
FF |
1 |
u_local2reg/n3540_s74/F |
123.814 |
0.474 |
tNET |
FF |
1 |
u_local2reg/n3540_s69/I2 |
124.267 |
0.453 |
tINS |
FF |
1 |
u_local2reg/n3540_s69/F |
124.741 |
0.474 |
tNET |
FF |
1 |
u_local2reg/n3540_s67/I1 |
125.296 |
0.555 |
tINS |
FF |
1 |
u_local2reg/n3540_s67/F |
125.770 |
0.474 |
tNET |
FF |
1 |
u_local2reg/local_rdat_o_0_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
116.667 |
0.000 |
|
|
|
u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk |
117.845 |
1.179 |
tCL |
RR |
2032 |
u0_syspll_rPLL/rpll_inst/CLKOUT |
118.205 |
0.360 |
tNET |
RR |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/remote_link_state_o_1_s1/CLK |
118.437 |
0.232 |
tC2Q |
RF |
6 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/remote_link_state_o_1_s1/Q |
118.911 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s48/I0 |
119.428 |
0.517 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s48/F |
119.902 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s47/I1 |
120.457 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s47/F |
120.931 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s44/I3 |
121.302 |
0.371 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s44/F |
121.776 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s39/I2 |
122.229 |
0.453 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s39/F |
122.703 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s33/I3 |
123.074 |
0.371 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s33/F |
123.548 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s29/I3 |
123.919 |
0.371 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1256_s29/F |
124.393 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/local_rdat_o_13_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
116.667 |
0.000 |
|
|
|
u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk |
117.845 |
1.179 |
tCL |
RR |
2032 |
u0_syspll_rPLL/rpll_inst/CLKOUT |
118.205 |
0.360 |
tNET |
RR |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/comma_symbol_o_4_s0/CLK |
118.437 |
0.232 |
tC2Q |
RF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/comma_symbol_o_4_s0/Q |
118.911 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s3/I1 |
119.466 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s3/F |
119.940 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s1/I2 |
120.393 |
0.453 |
tINS |
FF |
7 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s1/F |
120.867 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4499_s2/I0 |
121.384 |
0.517 |
tINS |
FF |
2 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4499_s2/F |
121.858 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1268_s31/I1 |
122.413 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1268_s31/F |
122.887 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1268_s30/I0 |
123.404 |
0.517 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1268_s30/F |
123.878 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/local_rdat_o_3_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
116.667 |
0.000 |
|
|
|
u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk |
117.845 |
1.179 |
tCL |
RR |
2032 |
u0_syspll_rPLL/rpll_inst/CLKOUT |
118.205 |
0.360 |
tNET |
RR |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_NL_GPIO_nb_0_s0/CLK |
118.437 |
0.232 |
tC2Q |
RF |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_NL_GPIO_nb_0_s0/Q |
118.911 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s48/I1 |
119.466 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s48/F |
119.940 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s45/I1 |
120.495 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s45/F |
120.969 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s36/I3 |
121.340 |
0.371 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s36/F |
121.814 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s32/I1 |
122.369 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s32/F |
122.843 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s30/I1 |
123.398 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1263_s30/F |
123.872 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/local_rdat_o_8_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
116.667 |
0.000 |
|
|
|
u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk |
117.845 |
1.179 |
tCL |
RR |
2032 |
u0_syspll_rPLL/rpll_inst/CLKOUT |
118.205 |
0.360 |
tNET |
RR |
1 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/link_aligment_err_cnt_o_10_s0/CLK |
118.437 |
0.232 |
tC2Q |
RF |
2 |
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/link_aligment_err_cnt_o_10_s0/Q |
118.911 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s49/I1 |
119.466 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s49/F |
119.940 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s46/I1 |
120.495 |
0.555 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s46/F |
120.969 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s36/I2 |
121.422 |
0.453 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s36/F |
121.896 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s31/I2 |
122.349 |
0.453 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s31/F |
122.823 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s30/I0 |
123.340 |
0.517 |
tINS |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/n1261_s30/F |
123.814 |
0.474 |
tNET |
FF |
1 |
u_ltpi_hpm/u_ltpi_core/u_local2reg/local_rdat_o_10_s0/D |