Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\i2c_master\i2c_master.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\i2c_master_cfgport.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\syspll\syspll.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\sysreg.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\top.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\uart_to_bus\uart_to_bus.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Mon Jan 29 10:43:16 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.538s, Peak memory usage = 427.656MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 427.656MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 427.656MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 427.656MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 427.656MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 427.656MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 427.656MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 427.656MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.11s, Peak memory usage = 427.656MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 427.656MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 427.656MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 452.273MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.111s, Peak memory usage = 452.273MB
Generate output files:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 452.273MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 452.273MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 7
I/O Buf 7
    IBUF 2
    OBUF 3
    IOBUF 2
Register 2634
    DFF 197
    DFFE 1854
    DFFR 50
    DFFP 10
    DFFPE 6
    DFFC 203
    DFFCE 314
LUT 1993
    LUT2 129
    LUT3 694
    LUT4 1170
ALU 45
    ALU 45
INV 18
    INV 18
CLOCK 1
    rPLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 2056(2011 LUT, 45 ALU) / 20736 10%
Register 2634 / 16173 17%
  --Register as Latch 0 / 16173 0%
  --Register as FF 2634 / 16173 17%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
i_clk Base 20.000 50.0 0.000 10.000 i_clk_ibuf/I
u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk Generated 10.000 100.0 0.000 5.000 i_clk_ibuf/I i_clk u0_syspll_rPLL/rpll_inst/CLKOUT
u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk Generated 10.000 100.0 0.000 5.000 i_clk_ibuf/I i_clk u0_syspll_rPLL/rpll_inst/CLKOUTP
u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk Generated 20.000 50.0 0.000 10.000 i_clk_ibuf/I i_clk u0_syspll_rPLL/rpll_inst/CLKOUTD
u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk Generated 30.000 33.3 0.000 15.000 i_clk_ibuf/I i_clk u0_syspll_rPLL/rpll_inst/CLKOUTD3

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk 100.000(MHz) 113.212(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.167
Data Arrival Time 10.337
Data Required Time 11.504
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0
To u_local2reg/local_rdat_o_0_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
1.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
1.539 0.360 tNET RR 1 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/CLK
1.771 0.232 tC2Q RF 3 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/Q
2.245 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/I1
2.800 0.555 tINS FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/F
3.274 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I1
3.829 0.555 tINS FF 60 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F
4.303 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_8_s0/I2
4.756 0.453 tINS FF 3 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_8_s0/F
5.230 0.474 tNET FF 1 u_local2reg/n5185_s2/I1
5.785 0.555 tINS FF 19 u_local2reg/n5185_s2/F
6.259 0.474 tNET FF 1 u_local2reg/n5345_s1/I1
6.814 0.555 tINS FF 33 u_local2reg/n5345_s1/F
7.288 0.474 tNET FF 1 u_local2reg/n3540_s75/I0
7.805 0.517 tINS FF 1 u_local2reg/n3540_s75/F
8.279 0.474 tNET FF 1 u_local2reg/n3540_s69/I1
8.834 0.555 tINS FF 1 u_local2reg/n3540_s69/F
9.308 0.474 tNET FF 1 u_local2reg/n3540_s67/I1
9.863 0.555 tINS FF 1 u_local2reg/n3540_s67/F
10.337 0.474 tNET FF 1 u_local2reg/local_rdat_o_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
11.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
11.539 0.360 tNET RR 1 u_local2reg/local_rdat_o_0_s0/CLK
11.504 -0.035 tSu 1 u_local2reg/local_rdat_o_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.300, 48.875%; route: 4.266, 48.488%; tC2Q: 0.232, 2.637%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack 1.167
Data Arrival Time 10.337
Data Required Time 11.504
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0
To u_local2reg/local_rdat_o_1_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
1.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
1.539 0.360 tNET RR 1 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/CLK
1.771 0.232 tC2Q RF 3 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/Q
2.245 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/I1
2.800 0.555 tINS FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/F
3.274 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I1
3.829 0.555 tINS FF 60 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F
4.303 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_8_s0/I2
4.756 0.453 tINS FF 3 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_8_s0/F
5.230 0.474 tNET FF 1 u_local2reg/n5185_s2/I1
5.785 0.555 tINS FF 19 u_local2reg/n5185_s2/F
6.259 0.474 tNET FF 1 u_local2reg/n5345_s1/I1
6.814 0.555 tINS FF 33 u_local2reg/n5345_s1/F
7.288 0.474 tNET FF 1 u_local2reg/n3539_s77/I0
7.805 0.517 tINS FF 1 u_local2reg/n3539_s77/F
8.279 0.474 tNET FF 1 u_local2reg/n3539_s69/I1
8.834 0.555 tINS FF 1 u_local2reg/n3539_s69/F
9.308 0.474 tNET FF 1 u_local2reg/n3539_s67/I1
9.863 0.555 tINS FF 1 u_local2reg/n3539_s67/F
10.337 0.474 tNET FF 1 u_local2reg/local_rdat_o_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
11.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
11.539 0.360 tNET RR 1 u_local2reg/local_rdat_o_1_s0/CLK
11.504 -0.035 tSu 1 u_local2reg/local_rdat_o_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.300, 48.875%; route: 4.266, 48.488%; tC2Q: 0.232, 2.637%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack 1.167
Data Arrival Time 10.337
Data Required Time 11.504
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0
To u_local2reg/local_rdat_o_2_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
1.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
1.539 0.360 tNET RR 1 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/CLK
1.771 0.232 tC2Q RF 3 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/Q
2.245 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/I1
2.800 0.555 tINS FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/F
3.274 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I1
3.829 0.555 tINS FF 60 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F
4.303 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2
4.756 0.453 tINS FF 17 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F
5.230 0.474 tNET FF 1 u_local2reg/n4993_s2/I1
5.785 0.555 tINS FF 12 u_local2reg/n4993_s2/F
6.259 0.474 tNET FF 1 u_local2reg/n4993_s1/I1
6.814 0.555 tINS FF 33 u_local2reg/n4993_s1/F
7.288 0.474 tNET FF 1 u_local2reg/n3538_s77/I0
7.805 0.517 tINS FF 1 u_local2reg/n3538_s77/F
8.279 0.474 tNET FF 1 u_local2reg/n3538_s69/I1
8.834 0.555 tINS FF 1 u_local2reg/n3538_s69/F
9.308 0.474 tNET FF 1 u_local2reg/n3538_s67/I1
9.863 0.555 tINS FF 1 u_local2reg/n3538_s67/F
10.337 0.474 tNET FF 1 u_local2reg/local_rdat_o_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
11.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
11.539 0.360 tNET RR 1 u_local2reg/local_rdat_o_2_s0/CLK
11.504 -0.035 tSu 1 u_local2reg/local_rdat_o_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.300, 48.875%; route: 4.266, 48.488%; tC2Q: 0.232, 2.637%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack 1.167
Data Arrival Time 10.337
Data Required Time 11.504
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0
To u_local2reg/local_rdat_o_3_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
1.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
1.539 0.360 tNET RR 1 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/CLK
1.771 0.232 tC2Q RF 3 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/Q
2.245 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/I1
2.800 0.555 tINS FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/F
3.274 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I1
3.829 0.555 tINS FF 60 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F
4.303 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_8_s0/I2
4.756 0.453 tINS FF 3 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_8_s0/F
5.230 0.474 tNET FF 1 u_local2reg/n5185_s2/I1
5.785 0.555 tINS FF 19 u_local2reg/n5185_s2/F
6.259 0.474 tNET FF 1 u_local2reg/n5345_s1/I1
6.814 0.555 tINS FF 33 u_local2reg/n5345_s1/F
7.288 0.474 tNET FF 1 u_local2reg/n3537_s77/I0
7.805 0.517 tINS FF 1 u_local2reg/n3537_s77/F
8.279 0.474 tNET FF 1 u_local2reg/n3537_s69/I1
8.834 0.555 tINS FF 1 u_local2reg/n3537_s69/F
9.308 0.474 tNET FF 1 u_local2reg/n3537_s67/I1
9.863 0.555 tINS FF 1 u_local2reg/n3537_s67/F
10.337 0.474 tNET FF 1 u_local2reg/local_rdat_o_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
11.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
11.539 0.360 tNET RR 1 u_local2reg/local_rdat_o_3_s0/CLK
11.504 -0.035 tSu 1 u_local2reg/local_rdat_o_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.300, 48.875%; route: 4.266, 48.488%; tC2Q: 0.232, 2.637%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack 1.167
Data Arrival Time 10.337
Data Required Time 11.504
From u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0
To u_local2reg/local_rdat_o_4_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
1.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
1.539 0.360 tNET RR 1 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/CLK
1.771 0.232 tC2Q RF 3 u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/Q
2.245 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/I1
2.800 0.555 tINS FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s2/F
3.274 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I1
3.829 0.555 tINS FF 60 u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F
4.303 0.474 tNET FF 1 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_3_s0/I2
4.756 0.453 tINS FF 17 u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_3_s0/F
5.230 0.474 tNET FF 1 u_local2reg/n5121_s2/I1
5.785 0.555 tINS FF 4 u_local2reg/n5121_s2/F
6.259 0.474 tNET FF 1 u_local2reg/n5121_s1/I1
6.814 0.555 tINS FF 32 u_local2reg/n5121_s1/F
7.288 0.474 tNET FF 1 u_local2reg/n3536_s77/I0
7.805 0.517 tINS FF 1 u_local2reg/n3536_s77/F
8.279 0.474 tNET FF 1 u_local2reg/n3536_s69/I1
8.834 0.555 tINS FF 1 u_local2reg/n3536_s69/F
9.308 0.474 tNET FF 1 u_local2reg/n3536_s67/I1
9.863 0.555 tINS FF 1 u_local2reg/n3536_s67/F
10.337 0.474 tNET FF 1 u_local2reg/local_rdat_o_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
11.179 1.179 tCL RR 2634 u0_syspll_rPLL/rpll_inst/CLKOUT
11.539 0.360 tNET RR 1 u_local2reg/local_rdat_o_4_s0/CLK
11.504 -0.035 tSu 1 u_local2reg/local_rdat_o_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.300, 48.875%; route: 4.266, 48.488%; tC2Q: 0.232, 2.637%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%