Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_SCM\src\dcscm_ltpi\dcscm_ltpi.v
E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_SCM\src\syspll\syspll.v
E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_SCM\src\sysreg.v
E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_SCM\src\top.v
E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_SCM\src\uart_to_bus\uart_to_bus.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Wed Jan 24 09:30:31 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 0.989s, Peak memory usage = 881.289MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 881.289MB
    Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.154s, Peak memory usage = 881.289MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 881.289MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 881.289MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 881.289MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 881.289MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 881.289MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 881.289MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 881.289MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 881.289MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 881.289MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.138s, Peak memory usage = 881.289MB
Generate output files:
    CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.37s, Peak memory usage = 881.289MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 881.289MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 27
I/O Buf 19
    IBUF 7
    OBUF 6
    IOBUF 2
    TLVDS_IBUF 2
    TLVDS_OBUF 2
Register 5047
    DFF 390
    DFFE 2222
    DFFS 54
    DFFSE 88
    DFFR 281
    DFFRE 1435
    DFFP 8
    DFFPE 4
    DFFC 299
    DFFCE 266
LUT 4605
    LUT2 536
    LUT3 1391
    LUT4 2678
ALU 631
    ALU 631
INV 51
    INV 51
IOLOGIC 3
    IDES10 1
    OSER10 2
CLOCK 5
    CLKDIV 3
    rPLL 2

Resource Utilization Summary

Resource Usage Utilization
Logic 5287(4656 LUT, 631 ALU) / 20736 26%
Register 5047 / 16173 32%
  --Register as Latch 0 / 16173 0%
  --Register as FF 5047 / 16173 32%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
i_clk Base 20.000 50.0 0.000 10.000 i_clk_ibuf/I
RX_CLK_P Base 10.000 100.0 0.000 5.000 lvds_rx_clk_in/I
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT.default_gen_clk Generated 50.000 20.0 0.000 25.000 lvds_rx_clk_in/I RX_CLK_P u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT
u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk Generated 16.667 60.0 0.000 8.333 i_clk_ibuf/I i_clk u0_syspll_rPLL/rpll_inst/CLKOUT
u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk Generated 16.667 60.0 0.000 8.333 i_clk_ibuf/I i_clk u0_syspll_rPLL/rpll_inst/CLKOUTP
u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk Generated 33.333 30.0 0.000 16.667 i_clk_ibuf/I i_clk u0_syspll_rPLL/rpll_inst/CLKOUTD
u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk Generated 50.000 20.0 0.000 25.000 i_clk_ibuf/I i_clk u0_syspll_rPLL/rpll_inst/CLKOUTD3
u1_CLKDIV/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 i_clk_ibuf/I i_clk u1_CLKDIV/CLKOUT
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 u1_CLKDIV/CLKOUT u1_CLKDIV/CLKOUT.default_gen_clk u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk Generated 40.000 25.0 0.000 20.000 u1_CLKDIV/CLKOUT u1_CLKDIV/CLKOUT.default_gen_clk u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk Generated 80.000 12.5 0.000 40.000 u1_CLKDIV/CLKOUT u1_CLKDIV/CLKOUT.default_gen_clk u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk Generated 120.000 8.3 0.000 60.000 u1_CLKDIV/CLKOUT u1_CLKDIV/CLKOUT.default_gen_clk u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk Generated 200.000 5.0 0.000 100.000 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT.default_gen_clk 20.000(MHz) 170.999(MHz) 6 TOP
2 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk 60.000(MHz) 144.613(MHz) 7 TOP
3 u1_CLKDIV/CLKOUT.default_gen_clk 25.000(MHz) 93.067(MHz) 11 TOP
4 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk 5.000(MHz) 354.358(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -4.955
Data Arrival Time 125.586
Data Required Time 120.631
From u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/reconfig_cnt_2_s0
To u_local2reg/local_rdat_o_0_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u1_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
116.667 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
117.845 1.179 tCL RR 1919 u0_syspll_rPLL/rpll_inst/CLKOUT
118.205 0.360 tNET RR 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/reconfig_cnt_2_s0/CLK
118.437 0.232 tC2Q RF 2 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/reconfig_cnt_2_s0/Q
118.911 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/reconfig_busy_s6/I1
119.466 0.555 tINS FF 2 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/reconfig_busy_s6/F
119.940 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/n132_s32/I2
120.393 0.453 tINS FF 2 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/n132_s32/F
120.867 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/tx_pll_locked_o_d_s0/I2
121.320 0.453 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/tx_pll_locked_o_d_s0/F
121.794 0.474 tNET FF 1 u_local2reg/n3540_s92/I0
122.311 0.517 tINS FF 1 u_local2reg/n3540_s92/F
122.785 0.474 tNET FF 1 u_local2reg/n3540_s99/I3
123.156 0.371 tINS FF 1 u_local2reg/n3540_s99/F
123.630 0.474 tNET FF 1 u_local2reg/n3540_s70/I1
124.185 0.555 tINS FF 1 u_local2reg/n3540_s70/F
124.659 0.474 tNET FF 1 u_local2reg/n3540_s67/I2
125.112 0.453 tINS FF 1 u_local2reg/n3540_s67/F
125.586 0.474 tNET FF 1 u_local2reg/local_rdat_o_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
120.000 0.000 u1_CLKDIV/CLKOUT.default_gen_clk
120.341 0.341 tCL RR 2897 u1_CLKDIV/CLKOUT
120.701 0.360 tNET RR 1 u_local2reg/local_rdat_o_0_s0/CLK
120.666 -0.035 tUnc u_local2reg/local_rdat_o_0_s0
120.631 -0.035 tSu 1 u_local2reg/local_rdat_o_0_s0
Path Statistics:
Clock Skew: -0.838
Setup Relationship: 3.333
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 3.357, 45.482%; route: 3.792, 51.375%; tC2Q: 0.232, 3.143%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack -4.092
Data Arrival Time 124.723
Data Required Time 120.631
From u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/comma_symbol_o_2_s0
To u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_3_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u1_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
116.667 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
117.845 1.179 tCL RR 1919 u0_syspll_rPLL/rpll_inst/CLKOUT
118.205 0.360 tNET RR 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/comma_symbol_o_2_s0/CLK
118.437 0.232 tC2Q RF 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/comma_symbol_o_2_s0/Q
118.911 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s3/I1
119.466 0.555 tINS FF 2 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s3/F
119.940 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I1
120.495 0.555 tINS FF 3 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F
120.969 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4499_s1/I3
121.340 0.371 tINS FF 2 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4499_s1/F
121.814 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1268_s49/I0
122.331 0.517 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1268_s49/F
122.805 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1268_s31/I2
123.258 0.453 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1268_s31/F
123.732 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1268_s30/I0
124.249 0.517 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1268_s30/F
124.723 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
120.000 0.000 u1_CLKDIV/CLKOUT.default_gen_clk
120.341 0.341 tCL RR 2897 u1_CLKDIV/CLKOUT
120.701 0.360 tNET RR 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_3_s0/CLK
120.666 -0.035 tUnc u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_3_s0
120.631 -0.035 tSu 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_3_s0
Path Statistics:
Clock Skew: -0.838
Setup Relationship: 3.333
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.968, 45.535%; route: 3.318, 50.906%; tC2Q: 0.232, 3.559%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack -3.145
Data Arrival Time 123.776
Data Required Time 120.631
From u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/remote_link_speed_capab_3_s0
To u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_11_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u1_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
116.667 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
117.845 1.179 tCL RR 1919 u0_syspll_rPLL/rpll_inst/CLKOUT
118.205 0.360 tNET RR 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/remote_link_speed_capab_3_s0/CLK
118.437 0.232 tC2Q RF 4 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/remote_link_speed_capab_3_s0/Q
118.911 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s48/I0
119.428 0.517 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s48/F
119.902 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s40/I1
120.457 0.555 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s40/F
120.931 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s34/I2
121.384 0.453 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s34/F
121.858 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s30/I2
122.311 0.453 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s30/F
122.785 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s29/I0
123.302 0.517 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1260_s29/F
123.776 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
120.000 0.000 u1_CLKDIV/CLKOUT.default_gen_clk
120.341 0.341 tCL RR 2897 u1_CLKDIV/CLKOUT
120.701 0.360 tNET RR 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_11_s0/CLK
120.666 -0.035 tUnc u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_11_s0
120.631 -0.035 tSu 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_11_s0
Path Statistics:
Clock Skew: -0.838
Setup Relationship: 3.333
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.495, 44.785%; route: 2.844, 51.051%; tC2Q: 0.232, 4.164%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack -3.139
Data Arrival Time 123.770
Data Required Time 120.631
From u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/unknown_comma_err_cnt_10_s0
To u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_10_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u1_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
116.667 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
117.845 1.179 tCL RR 1919 u0_syspll_rPLL/rpll_inst/CLKOUT
118.205 0.360 tNET RR 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/unknown_comma_err_cnt_10_s0/CLK
118.437 0.232 tC2Q RF 2 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/unknown_comma_err_cnt_10_s0/Q
118.911 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s48/I1
119.466 0.555 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s48/F
119.940 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s49/I1
120.495 0.555 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s49/F
120.969 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s40/I2
121.422 0.453 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s40/F
121.896 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s32/I3
122.267 0.371 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s32/F
122.741 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s30/I1
123.296 0.555 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1261_s30/F
123.770 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
120.000 0.000 u1_CLKDIV/CLKOUT.default_gen_clk
120.341 0.341 tCL RR 2897 u1_CLKDIV/CLKOUT
120.701 0.360 tNET RR 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_10_s0/CLK
120.666 -0.035 tUnc u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_10_s0
120.631 -0.035 tSu 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_10_s0
Path Statistics:
Clock Skew: -0.838
Setup Relationship: 3.333
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.489, 44.726%; route: 2.844, 51.105%; tC2Q: 0.232, 4.169%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack -3.043
Data Arrival Time 123.674
Data Required Time 120.631
From u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_44_s0
To u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_12_s0
Launch Clk u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u1_CLKDIV/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
116.667 0.000 u0_syspll_rPLL/rpll_inst/CLKOUT.default_gen_clk
117.845 1.179 tCL RR 1919 u0_syspll_rPLL/rpll_inst/CLKOUT
118.205 0.360 tNET RR 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_44_s0/CLK
118.437 0.232 tC2Q RF 1 u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_44_s0/Q
118.911 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s46/I0
119.428 0.517 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s46/F
119.902 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s41/I2
120.355 0.453 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s41/F
120.829 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s37/I2
121.282 0.453 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s37/F
121.756 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s32/I0
122.273 0.517 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s32/F
122.747 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s29/I2
123.200 0.453 tINS FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/n1258_s29/F
123.674 0.474 tNET FF 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
120.000 0.000 u1_CLKDIV/CLKOUT.default_gen_clk
120.341 0.341 tCL RR 2897 u1_CLKDIV/CLKOUT
120.701 0.360 tNET RR 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_12_s0/CLK
120.666 -0.035 tUnc u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_12_s0
120.631 -0.035 tSu 1 u_ltpi_scm/u_ltpi_core/u_local2reg/local_rdat_o_12_s0
Path Statistics:
Clock Skew: -0.838
Setup Relationship: 3.333
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.393, 43.756%; route: 2.844, 52.002%; tC2Q: 0.232, 4.242%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%