Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_SCM\impl\gwsynthesis\SCM_LTPI.vg |
Physical Constraints File | E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_SCM\src\top.cst |
Timing Constraint File | E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_SCM\src\top.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Created Time | Wed Jan 24 09:30:48 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 24681 |
Numbers of Endpoints Analyzed | 11538 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
i_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | i_clk | ||
RX_CLK_P | Base | 6.660 | 150.150 | 0.000 | 3.330 | RX_CLK_P | ||
rxdiv5clk | Generated | 33.300 | 30.030 | 0.000 | 16.650 | RX_CLK_P | RX_CLK_P | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/clk5div |
w_clk25m | Generated | 40.000 | 25.000 | 0.000 | 20.000 | i_clk | i_clk | w_clk25m |
w_clk60m | Generated | 16.667 | 60.000 | 0.000 | 8.333 | i_clk | i_clk | w_clk60m |
u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Generated | 16.667 | 60.000 | 0.000 | 8.333 | i_clk_ibuf/I | i_clk | u0_syspll_rPLL/rpll_inst/CLKOUTP |
u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Generated | 33.333 | 30.000 | 0.000 | 16.667 | i_clk_ibuf/I | i_clk | u0_syspll_rPLL/rpll_inst/CLKOUTD |
u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 50.000 | 20.000 | 0.000 | 25.000 | i_clk_ibuf/I | i_clk | u0_syspll_rPLL/rpll_inst/CLKOUTD3 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | u1_CLKDIV/CLKOUT | w_clk25m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | u1_CLKDIV/CLKOUT | w_clk25m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk | Generated | 80.000 | 12.500 | 0.000 | 40.000 | u1_CLKDIV/CLKOUT | w_clk25m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 120.000 | 8.333 | 0.000 | 60.000 | u1_CLKDIV/CLKOUT | w_clk25m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | Generated | 200.000 | 5.000 | 0.000 | 100.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | rxdiv5clk | 30.030(MHz) | 189.588(MHz) | 6 | TOP |
2 | w_clk25m | 25.000(MHz) | 70.989(MHz) | 11 | TOP |
3 | w_clk60m | 60.000(MHz) | 119.573(MHz) | 7 | TOP |
4 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | 5.000(MHz) | 364.654(MHz) | 2 | TOP |
No timing paths to get frequency of i_clk!
No timing paths to get frequency of RX_CLK_P!
No timing paths to get frequency of u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
i_clk | Setup | 0.000 | 0 |
i_clk | Hold | 0.000 | 0 |
RX_CLK_P | Setup | 0.000 | 0 |
RX_CLK_P | Hold | 0.000 | 0 |
rxdiv5clk | Setup | 0.000 | 0 |
rxdiv5clk | Hold | 0.000 | 0 |
w_clk25m | Setup | 0.000 | 0 |
w_clk25m | Hold | 0.000 | 0 |
w_clk60m | Setup | 0.000 | 0 |
w_clk60m | Hold | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 8.304 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 8.328 |
2 | 8.304 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 8.328 |
3 | 8.304 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 8.328 |
4 | 8.335 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 8.297 |
5 | 8.335 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 8.297 |
6 | 8.464 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frame_crc_err_o_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_31_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 8.168 |
7 | 8.607 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frame_crc_err_o_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_0_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 8.025 |
8 | 8.924 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.708 |
9 | 9.029 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.602 |
10 | 9.095 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_0_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.537 |
11 | 9.123 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.508 |
12 | 9.139 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.493 |
13 | 9.149 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_1_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.483 |
14 | 9.149 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_3_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.483 |
15 | 9.149 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_5_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.483 |
16 | 9.149 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_6_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.483 |
17 | 9.156 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_0_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.476 |
18 | 9.320 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/datafrm_valid_o_s0/RESET | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.312 |
19 | 9.374 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.257 |
20 | 9.374 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.257 |
21 | 9.498 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.133 |
22 | 9.521 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.111 |
23 | 9.525 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/opefrm_get_o_8_s1/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.107 |
24 | 9.526 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.106 |
25 | 9.547 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.085 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.087 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.462 |
2 | 0.289 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_1_G[2]_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_2_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.664 |
3 | 0.289 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_2_G[7]_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_7_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.664 |
4 | 0.293 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_0_G[0]_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_0_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.669 |
5 | 0.293 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[1]_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.669 |
6 | 0.293 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[3]_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.669 |
7 | 0.293 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_6_G[4]_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.669 |
8 | 0.293 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_1_G[5]_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_5_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.669 |
9 | 0.293 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[6]_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.669 |
10 | 0.293 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_2_G[9]_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_9_s0/D | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.669 |
11 | 0.307 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr_2_s1/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_2_s1/D | rxdiv5clk:[R] | rxdiv5clk:[R] | 0.000 | 0.000 | 0.318 |
12 | 0.307 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr_3_s1/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_3_s1/D | rxdiv5clk:[R] | rxdiv5clk:[R] | 0.000 | 0.000 | 0.318 |
13 | 0.321 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_valid_o_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rxdata_fp_o_s0/RESET | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.332 |
14 | 0.322 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sync_controller_sda_inst/o_sync_out_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sync_controller_sda_inst/o_falling_edge_s0/RESET | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.333 |
15 | 0.323 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_3_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.334 |
16 | 0.323 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.334 |
17 | 0.323 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_14_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.334 |
18 | 0.323 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.334 |
19 | 0.323 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_13_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.334 |
20 | 0.323 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_22_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.334 |
21 | 0.323 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_23_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.334 |
22 | 0.323 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_24_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.334 |
23 | 0.323 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.334 |
24 | 0.323 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.334 |
25 | 0.323 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.334 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 2.772 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/RESETN | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | -0.547 | 1.043 |
2 | 13.001 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_0_s3/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.630 |
3 | 13.001 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_1_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.630 |
4 | 13.001 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_2_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.630 |
5 | 13.001 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_3_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.630 |
6 | 13.236 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_4_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.395 |
7 | 13.236 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_6_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.395 |
8 | 13.236 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_7_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.395 |
9 | 13.236 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_8_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.395 |
10 | 13.236 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_9_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.395 |
11 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/clear_controller_bit_count_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
12 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sda_oe_o_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
13 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_5_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
14 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
15 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/command_rd_wrn_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
16 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_byte_in_0_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
17 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_0_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
18 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_1_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
19 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/scl_oe_o_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
20 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_0_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
21 | 13.244 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_scl_dly_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.388 |
22 | 13.252 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_0_s3/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.380 |
23 | 13.252 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_1_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.380 |
24 | 13.252 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_valid_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.380 |
25 | 13.252 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_1_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 3.380 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.338 | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/RESETN | w_clk60m:[R] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk:[R] | -0.000 | -0.516 | 0.899 |
2 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
3 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
4 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
5 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
6 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
7 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
8 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
9 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
10 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
11 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
12 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
13 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
14 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
15 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
16 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
17 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
18 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
19 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
20 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
21 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
22 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
23 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
24 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
25 | 0.925 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.936 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | r_clk60_cnt_4_s0 |
2 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_20_s0 |
3 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_7_s0 |
4 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frm_crc_err_cnt_26_s0 |
5 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx3_data_o_3_s0 |
6 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rxb_data_o_3_s0 |
7 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_data_3_s0 |
8 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rd_gray_ptr_4_s1 |
9 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rp_wr_gray_ptr1_1_s1 |
10 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rp_wr_gray_ptr_2_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 8.304 |
Data Arrival Time | 8.571 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 21 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q |
1.661 | 1.186 | tNET | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/I0 |
2.178 | 0.517 | tINS | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/F |
3.182 | 1.003 | tNET | FF | 1 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/I2 |
3.635 | 0.453 | tINS | FF | 2 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/F |
4.054 | 0.419 | tNET | FF | 1 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/I1 |
4.571 | 0.517 | tINS | FF | 2 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/F |
5.680 | 1.109 | tNET | FF | 1 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/I1 |
6.197 | 0.517 | tINS | FF | 2 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/F |
6.764 | 0.567 | tNET | FF | 1 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I2 |
7.217 | 0.453 | tINS | FF | 2 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
7.639 | 0.422 | tNET | FF | 1 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
8.209 | 0.570 | tINS | FR | 5 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
8.571 | 0.362 | tNET | RR | 1 | R32C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R32C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1/CLK |
16.875 | -0.035 | tSu | 1 | R32C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.027, 36.347%; route: 5.069, 60.867%; tC2Q: 0.232, 2.786% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path2
Path Summary:
Slack | 8.304 |
Data Arrival Time | 8.571 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 21 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q |
1.661 | 1.186 | tNET | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/I0 |
2.178 | 0.517 | tINS | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/F |
3.182 | 1.003 | tNET | FF | 1 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/I2 |
3.635 | 0.453 | tINS | FF | 2 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/F |
4.054 | 0.419 | tNET | FF | 1 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/I1 |
4.571 | 0.517 | tINS | FF | 2 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/F |
5.680 | 1.109 | tNET | FF | 1 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/I1 |
6.197 | 0.517 | tINS | FF | 2 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/F |
6.764 | 0.567 | tNET | FF | 1 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I2 |
7.217 | 0.453 | tINS | FF | 2 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
7.639 | 0.422 | tNET | FF | 1 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
8.209 | 0.570 | tINS | FR | 5 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
8.571 | 0.362 | tNET | RR | 1 | R31C44[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R31C44[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CLK |
16.875 | -0.035 | tSu | 1 | R31C44[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.027, 36.347%; route: 5.069, 60.867%; tC2Q: 0.232, 2.786% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
Slack | 8.304 |
Data Arrival Time | 8.571 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 21 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q |
1.661 | 1.186 | tNET | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/I0 |
2.178 | 0.517 | tINS | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/F |
3.182 | 1.003 | tNET | FF | 1 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/I2 |
3.635 | 0.453 | tINS | FF | 2 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/F |
4.054 | 0.419 | tNET | FF | 1 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/I1 |
4.571 | 0.517 | tINS | FF | 2 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/F |
5.680 | 1.109 | tNET | FF | 1 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/I1 |
6.197 | 0.517 | tINS | FF | 2 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/F |
6.764 | 0.567 | tNET | FF | 1 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I2 |
7.217 | 0.453 | tINS | FF | 2 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
7.639 | 0.422 | tNET | FF | 1 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
8.209 | 0.570 | tINS | FR | 5 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
8.571 | 0.362 | tNET | RR | 1 | R32C46[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R32C46[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1/CLK |
16.875 | -0.035 | tSu | 1 | R32C46[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.027, 36.347%; route: 5.069, 60.867%; tC2Q: 0.232, 2.786% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
Slack | 8.335 |
Data Arrival Time | 8.540 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 21 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q |
1.661 | 1.186 | tNET | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/I0 |
2.178 | 0.517 | tINS | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/F |
3.182 | 1.003 | tNET | FF | 1 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/I2 |
3.635 | 0.453 | tINS | FF | 2 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/F |
4.054 | 0.419 | tNET | FF | 1 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/I1 |
4.571 | 0.517 | tINS | FF | 2 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/F |
5.680 | 1.109 | tNET | FF | 1 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/I1 |
6.197 | 0.517 | tINS | FF | 2 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/F |
6.764 | 0.567 | tNET | FF | 1 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I2 |
7.217 | 0.453 | tINS | FF | 2 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
7.639 | 0.422 | tNET | FF | 1 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
8.209 | 0.570 | tINS | FR | 5 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
8.540 | 0.331 | tNET | RR | 1 | R33C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R33C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/CLK |
16.875 | -0.035 | tSu | 1 | R33C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.027, 36.485%; route: 5.038, 60.719%; tC2Q: 0.232, 2.796% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
Slack | 8.335 |
Data Arrival Time | 8.540 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 21 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q |
1.661 | 1.186 | tNET | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/I0 |
2.178 | 0.517 | tINS | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/F |
3.182 | 1.003 | tNET | FF | 1 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/I2 |
3.635 | 0.453 | tINS | FF | 2 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/F |
4.054 | 0.419 | tNET | FF | 1 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/I1 |
4.571 | 0.517 | tINS | FF | 2 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/F |
5.680 | 1.109 | tNET | FF | 1 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/I1 |
6.197 | 0.517 | tINS | FF | 2 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/F |
6.764 | 0.567 | tNET | FF | 1 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I2 |
7.217 | 0.453 | tINS | FF | 2 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
7.639 | 0.422 | tNET | FF | 1 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
8.209 | 0.570 | tINS | FR | 5 | R32C43[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
8.540 | 0.331 | tNET | RR | 1 | R31C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R31C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CLK |
16.875 | -0.035 | tSu | 1 | R31C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.027, 36.485%; route: 5.038, 60.719%; tC2Q: 0.232, 2.796% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
Slack | 8.464 |
Data Arrival Time | 8.411 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frame_crc_err_o_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_31_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C39[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frame_crc_err_o_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C39[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frame_crc_err_o_s0/Q |
2.084 | 1.609 | tNET | FF | 1 | R12C33[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1802_s2/I0 |
2.639 | 0.555 | tINS | FF | 2 | R12C33[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1802_s2/F |
3.057 | 0.418 | tNET | FF | 1 | R14C34[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1802_s1/I2 |
3.428 | 0.371 | tINS | FF | 1 | R14C34[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1802_s1/F |
4.803 | 1.376 | tNET | FF | 1 | R36C34[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1849_s1/I2 |
5.256 | 0.453 | tINS | FF | 2 | R36C34[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1849_s1/F |
6.488 | 1.232 | tNET | FF | 1 | R13C32[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1849_s0/I3 |
7.037 | 0.549 | tINS | FR | 1 | R13C32[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1849_s0/F |
8.411 | 1.374 | tNET | RR | 1 | IOT8[A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_31_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | IOT8[A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_31_s0/CLK |
16.875 | -0.035 | tSu | 1 | IOT8[A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_31_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 1.928, 23.605%; route: 6.008, 73.555%; tC2Q: 0.232, 2.840% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
Slack | 8.607 |
Data Arrival Time | 8.268 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frame_crc_err_o_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_0_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C39[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frame_crc_err_o_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C39[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frame_crc_err_o_s0/Q |
2.084 | 1.609 | tNET | FF | 1 | R12C33[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1802_s2/I0 |
2.639 | 0.555 | tINS | FF | 2 | R12C33[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1802_s2/F |
3.057 | 0.418 | tNET | FF | 1 | R14C34[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1802_s1/I2 |
3.428 | 0.371 | tINS | FF | 1 | R14C34[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1802_s1/F |
4.803 | 1.376 | tNET | FF | 1 | R36C34[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1849_s1/I2 |
5.256 | 0.453 | tINS | FF | 2 | R36C34[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1849_s1/F |
6.488 | 1.232 | tNET | FF | 1 | R13C32[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1865_s0/I3 |
7.037 | 0.549 | tINS | FR | 1 | R13C32[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n1865_s0/F |
8.268 | 1.232 | tNET | RR | 1 | IOT8[B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | IOT8[B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_0_s0/CLK |
16.875 | -0.035 | tSu | 1 | IOT8[B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/nl_gpio_out_o_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 1.928, 24.025%; route: 5.865, 73.084%; tC2Q: 0.232, 2.891% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
Slack | 8.924 |
Data Arrival Time | 7.951 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 21 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q |
1.661 | 1.186 | tNET | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/I0 |
2.178 | 0.517 | tINS | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/F |
3.182 | 1.003 | tNET | FF | 1 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/I2 |
3.635 | 0.453 | tINS | FF | 2 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/F |
4.054 | 0.419 | tNET | FF | 1 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/I1 |
4.571 | 0.517 | tINS | FF | 2 | R30C46[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s12/F |
5.680 | 1.109 | tNET | FF | 1 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/I1 |
6.197 | 0.517 | tINS | FF | 2 | R31C45[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s5/F |
6.764 | 0.567 | tNET | FF | 1 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I2 |
7.226 | 0.462 | tINS | FR | 2 | R31C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
7.402 | 0.176 | tNET | RR | 1 | R31C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1041_s3/I0 |
7.951 | 0.549 | tINS | RR | 1 | R31C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1041_s3/F |
7.951 | 0.000 | tNET | RR | 1 | R31C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R31C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CLK |
16.875 | -0.035 | tSu | 1 | R31C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.015, 39.118%; route: 4.461, 57.872%; tC2Q: 0.232, 3.010% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
Slack | 9.029 |
Data Arrival Time | 7.846 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q |
1.452 | 0.977 | tNET | FF | 1 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/I1 |
1.969 | 0.517 | tINS | FF | 8 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/F |
3.200 | 1.231 | tNET | FF | 1 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/I1 |
3.755 | 0.555 | tINS | FF | 17 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/F |
4.732 | 0.977 | tNET | FF | 1 | R23C49[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s11/I0 |
5.287 | 0.555 | tINS | FF | 2 | R23C49[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s11/F |
5.704 | 0.418 | tNET | FF | 1 | R21C50[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s8/I1 |
6.259 | 0.555 | tINS | FF | 2 | R21C50[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s8/F |
6.919 | 0.660 | tNET | FF | 1 | R24C49[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s9/I1 |
7.489 | 0.570 | tINS | FR | 1 | R24C49[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s9/F |
7.846 | 0.356 | tNET | RR | 1 | R24C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R24C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/CLK |
16.875 | -0.035 | tSu | 1 | R24C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.752, 36.200%; route: 4.618, 60.748%; tC2Q: 0.232, 3.052% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
Slack | 9.095 |
Data Arrival Time | 7.780 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_0_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q |
1.452 | 0.977 | tNET | FF | 1 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/I1 |
1.969 | 0.517 | tINS | FF | 8 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/F |
3.200 | 1.231 | tNET | FF | 1 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/I1 |
3.755 | 0.555 | tINS | FF | 17 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/F |
4.655 | 0.900 | tNET | FF | 1 | R26C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s11/I0 |
5.108 | 0.453 | tINS | FF | 2 | R26C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s11/F |
5.525 | 0.418 | tNET | FF | 1 | R25C47[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s11/I2 |
6.080 | 0.555 | tINS | FF | 2 | R25C47[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s11/F |
6.498 | 0.418 | tNET | FF | 1 | R23C48[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s9/I3 |
6.869 | 0.371 | tINS | FF | 1 | R23C48[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s9/F |
6.873 | 0.004 | tNET | FF | 1 | R23C48[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s6/I2 |
7.422 | 0.549 | tINS | FR | 2 | R23C48[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s6/F |
7.780 | 0.357 | tNET | RR | 1 | R22C47[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_0_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R22C47[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_0_s1/CLK |
16.875 | -0.035 | tSu | 1 | R22C47[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.000, 39.806%; route: 4.305, 57.116%; tC2Q: 0.232, 3.078% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
Slack | 9.123 |
Data Arrival Time | 7.752 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q |
1.452 | 0.977 | tNET | FF | 1 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/I1 |
1.969 | 0.517 | tINS | FF | 8 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/F |
3.200 | 1.231 | tNET | FF | 1 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/I1 |
3.755 | 0.555 | tINS | FF | 17 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/F |
4.655 | 0.900 | tNET | FF | 1 | R26C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s11/I0 |
5.108 | 0.453 | tINS | FF | 2 | R26C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s11/F |
5.525 | 0.418 | tNET | FF | 1 | R25C47[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s11/I2 |
6.080 | 0.555 | tINS | FF | 2 | R25C47[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s11/F |
6.498 | 0.418 | tNET | FF | 1 | R23C48[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s9/I3 |
6.869 | 0.371 | tINS | FF | 1 | R23C48[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s9/F |
6.873 | 0.004 | tNET | FF | 1 | R23C48[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s6/I2 |
7.422 | 0.549 | tINS | FR | 2 | R23C48[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s6/F |
7.752 | 0.329 | tNET | RR | 1 | R23C49[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R23C49[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1/CLK |
16.875 | -0.035 | tSu | 1 | R23C49[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.000, 39.956%; route: 4.276, 56.954%; tC2Q: 0.232, 3.090% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
Slack | 9.139 |
Data Arrival Time | 7.736 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q |
1.452 | 0.977 | tNET | FF | 1 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/I1 |
1.969 | 0.517 | tINS | FF | 8 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/F |
3.200 | 1.231 | tNET | FF | 1 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/I1 |
3.755 | 0.555 | tINS | FF | 17 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/F |
4.503 | 0.748 | tNET | FF | 1 | R25C48[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n261_s56/I1 |
4.874 | 0.371 | tINS | FF | 2 | R25C48[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n261_s56/F |
5.125 | 0.252 | tNET | FF | 1 | R23C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s69/I1 |
5.680 | 0.555 | tINS | FF | 2 | R23C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s69/F |
6.085 | 0.405 | tNET | FF | 1 | R23C46[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s9/I3 |
6.640 | 0.555 | tINS | FF | 1 | R23C46[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s9/F |
7.053 | 0.413 | tNET | FF | 1 | R23C49[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s7/I2 |
7.380 | 0.327 | tINS | FR | 1 | R23C49[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s7/F |
7.736 | 0.356 | tNET | RR | 1 | R22C50[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R22C50[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s1/CLK |
16.875 | -0.035 | tSu | 1 | R22C50[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.880, 38.435%; route: 4.381, 58.468%; tC2Q: 0.232, 3.096% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
Slack | 9.149 |
Data Arrival Time | 7.726 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_1_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q |
2.230 | 1.755 | tNET | FF | 1 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/I2 |
2.747 | 0.517 | tINS | FF | 6 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/F |
3.182 | 0.435 | tNET | FF | 1 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/I2 |
3.737 | 0.555 | tINS | FF | 2 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/F |
3.989 | 0.252 | tNET | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/I3 |
4.442 | 0.453 | tINS | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/F |
4.596 | 0.154 | tNET | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I2 |
5.151 | 0.555 | tINS | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
5.398 | 0.247 | tNET | FF | 1 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
5.851 | 0.453 | tINS | FF | 8 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
6.779 | 0.928 | tNET | FF | 1 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/I0 |
7.349 | 0.570 | tINS | FR | 7 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/F |
7.726 | 0.377 | tNET | RR | 1 | R13C42[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R13C42[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_1_s0/CLK |
16.875 | -0.035 | tSu | 1 | R13C42[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.103, 41.466%; route: 4.148, 55.433%; tC2Q: 0.232, 3.100% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
Slack | 9.149 |
Data Arrival Time | 7.726 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_3_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q |
2.230 | 1.755 | tNET | FF | 1 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/I2 |
2.747 | 0.517 | tINS | FF | 6 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/F |
3.182 | 0.435 | tNET | FF | 1 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/I2 |
3.737 | 0.555 | tINS | FF | 2 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/F |
3.989 | 0.252 | tNET | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/I3 |
4.442 | 0.453 | tINS | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/F |
4.596 | 0.154 | tNET | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I2 |
5.151 | 0.555 | tINS | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
5.398 | 0.247 | tNET | FF | 1 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
5.851 | 0.453 | tINS | FF | 8 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
6.779 | 0.928 | tNET | FF | 1 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/I0 |
7.349 | 0.570 | tINS | FR | 7 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/F |
7.726 | 0.377 | tNET | RR | 1 | R13C42[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R13C42[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_3_s0/CLK |
16.875 | -0.035 | tSu | 1 | R13C42[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.103, 41.466%; route: 4.148, 55.433%; tC2Q: 0.232, 3.100% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
Slack | 9.149 |
Data Arrival Time | 7.726 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_5_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q |
2.230 | 1.755 | tNET | FF | 1 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/I2 |
2.747 | 0.517 | tINS | FF | 6 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/F |
3.182 | 0.435 | tNET | FF | 1 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/I2 |
3.737 | 0.555 | tINS | FF | 2 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/F |
3.989 | 0.252 | tNET | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/I3 |
4.442 | 0.453 | tINS | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/F |
4.596 | 0.154 | tNET | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I2 |
5.151 | 0.555 | tINS | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
5.398 | 0.247 | tNET | FF | 1 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
5.851 | 0.453 | tINS | FF | 8 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
6.779 | 0.928 | tNET | FF | 1 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/I0 |
7.349 | 0.570 | tINS | FR | 7 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/F |
7.726 | 0.377 | tNET | RR | 1 | R13C42[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_5_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R13C42[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_5_s0/CLK |
16.875 | -0.035 | tSu | 1 | R13C42[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.103, 41.466%; route: 4.148, 55.433%; tC2Q: 0.232, 3.100% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
Slack | 9.149 |
Data Arrival Time | 7.726 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_6_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q |
2.230 | 1.755 | tNET | FF | 1 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/I2 |
2.747 | 0.517 | tINS | FF | 6 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/F |
3.182 | 0.435 | tNET | FF | 1 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/I2 |
3.737 | 0.555 | tINS | FF | 2 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/F |
3.989 | 0.252 | tNET | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/I3 |
4.442 | 0.453 | tINS | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/F |
4.596 | 0.154 | tNET | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I2 |
5.151 | 0.555 | tINS | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
5.398 | 0.247 | tNET | FF | 1 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
5.851 | 0.453 | tINS | FF | 8 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
6.779 | 0.928 | tNET | FF | 1 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/I0 |
7.349 | 0.570 | tINS | FR | 7 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/F |
7.726 | 0.377 | tNET | RR | 1 | R13C42[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_6_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R13C42[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_6_s0/CLK |
16.875 | -0.035 | tSu | 1 | R13C42[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.103, 41.466%; route: 4.148, 55.433%; tC2Q: 0.232, 3.100% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
Slack | 9.156 |
Data Arrival Time | 7.719 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_0_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q |
2.230 | 1.755 | tNET | FF | 1 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/I2 |
2.747 | 0.517 | tINS | FF | 6 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/F |
3.182 | 0.435 | tNET | FF | 1 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/I2 |
3.737 | 0.555 | tINS | FF | 2 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/F |
3.989 | 0.252 | tNET | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/I3 |
4.442 | 0.453 | tINS | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/F |
4.596 | 0.154 | tNET | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I2 |
5.151 | 0.555 | tINS | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
5.398 | 0.247 | tNET | FF | 1 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
5.851 | 0.453 | tINS | FF | 8 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
6.779 | 0.928 | tNET | FF | 1 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/I0 |
7.349 | 0.570 | tINS | FR | 7 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/F |
7.719 | 0.370 | tNET | RR | 1 | R13C41[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R13C41[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_0_s0/CLK |
16.875 | -0.035 | tSu | 1 | R13C41[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.103, 41.507%; route: 4.141, 55.389%; tC2Q: 0.232, 3.103% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
Slack | 9.320 |
Data Arrival Time | 7.555 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/datafrm_valid_o_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R35C34[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 3 | R35C34[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
1.486 | 1.011 | tNET | FF | 1 | R38C41[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4201_s3/I3 |
2.003 | 0.517 | tINS | FF | 3 | R38C41[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4201_s3/F |
2.651 | 0.648 | tNET | FF | 1 | R38C44[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I3 |
3.206 | 0.555 | tINS | FF | 2 | R38C44[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
3.458 | 0.252 | tNET | FF | 1 | R36C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s5/I1 |
3.829 | 0.371 | tINS | FF | 39 | R36C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s5/F |
5.234 | 1.406 | tNET | FF | 1 | R39C49[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n754_s1/I2 |
5.605 | 0.371 | tINS | FF | 21 | R39C49[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n754_s1/F |
6.841 | 1.236 | tNET | FF | 1 | R25C41[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n5945_s2/I3 |
7.411 | 0.570 | tINS | FR | 1 | R25C41[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n5945_s2/F |
7.555 | 0.144 | tNET | RR | 1 | R25C41[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/datafrm_valid_o_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R25C41[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/datafrm_valid_o_s0/CLK |
16.875 | -0.035 | tSu | 1 | R25C41[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/datafrm_valid_o_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.384, 32.604%; route: 4.696, 64.223%; tC2Q: 0.232, 3.173% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
Slack | 9.374 |
Data Arrival Time | 7.501 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q |
2.230 | 1.755 | tNET | FF | 1 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/I2 |
2.747 | 0.517 | tINS | FF | 6 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/F |
3.182 | 0.435 | tNET | FF | 1 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/I2 |
3.737 | 0.555 | tINS | FF | 2 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/F |
3.989 | 0.252 | tNET | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/I3 |
4.442 | 0.453 | tINS | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/F |
4.596 | 0.154 | tNET | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I2 |
5.151 | 0.555 | tINS | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
5.398 | 0.247 | tNET | FF | 1 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
5.851 | 0.453 | tINS | FF | 8 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
6.779 | 0.928 | tNET | FF | 1 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/I0 |
7.349 | 0.570 | tINS | FR | 7 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/F |
7.501 | 0.151 | tNET | RR | 1 | R13C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R13C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0/CLK |
16.875 | -0.035 | tSu | 1 | R13C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.103, 42.757%; route: 3.922, 54.046%; tC2Q: 0.232, 3.197% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
Slack | 9.374 |
Data Arrival Time | 7.501 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q |
2.230 | 1.755 | tNET | FF | 1 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/I2 |
2.747 | 0.517 | tINS | FF | 6 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/F |
3.182 | 0.435 | tNET | FF | 1 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/I2 |
3.737 | 0.555 | tINS | FF | 2 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/F |
3.989 | 0.252 | tNET | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/I3 |
4.442 | 0.453 | tINS | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/F |
4.596 | 0.154 | tNET | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I2 |
5.151 | 0.555 | tINS | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
5.398 | 0.247 | tNET | FF | 1 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
5.851 | 0.453 | tINS | FF | 8 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
6.779 | 0.928 | tNET | FF | 1 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/I0 |
7.349 | 0.570 | tINS | FR | 7 | R13C38[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s2/F |
7.501 | 0.151 | tNET | RR | 1 | R13C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R13C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0/CLK |
16.875 | -0.035 | tSu | 1 | R13C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.103, 42.757%; route: 3.922, 54.046%; tC2Q: 0.232, 3.197% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
Slack | 9.498 |
Data Arrival Time | 7.377 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/CLK |
0.475 | 0.232 | tC2Q | RF | 20 | R21C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q |
1.452 | 0.977 | tNET | FF | 1 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/I1 |
1.969 | 0.517 | tINS | FF | 8 | R12C28[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/F |
3.200 | 1.231 | tNET | FF | 1 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/I1 |
3.755 | 0.555 | tINS | FF | 17 | R18C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/F |
4.503 | 0.748 | tNET | FF | 1 | R25C48[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n261_s56/I1 |
4.874 | 0.371 | tINS | FF | 2 | R25C48[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n261_s56/F |
5.125 | 0.252 | tNET | FF | 1 | R23C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s69/I1 |
5.680 | 0.555 | tINS | FF | 2 | R23C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s69/F |
6.085 | 0.405 | tNET | FF | 1 | R23C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s67/I1 |
6.634 | 0.549 | tINS | FR | 1 | R23C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s67/F |
6.807 | 0.172 | tNET | RR | 1 | R24C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s65/I1 |
7.377 | 0.570 | tINS | RR | 1 | R24C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s65/F |
7.377 | 0.000 | tNET | RR | 1 | R24C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R24C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/CLK |
16.875 | -0.035 | tSu | 1 | R24C46[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.117, 43.697%; route: 3.784, 53.051%; tC2Q: 0.232, 3.252% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
Slack | 9.521 |
Data Arrival Time | 7.354 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 21 | R30C41[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_11_s0/Q |
1.661 | 1.186 | tNET | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/I0 |
2.178 | 0.517 | tINS | FF | 1 | R30C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s52/F |
3.182 | 1.003 | tNET | FF | 1 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/I2 |
3.635 | 0.453 | tINS | FF | 2 | R31C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s27/F |
4.054 | 0.419 | tNET | FF | 1 | R30C46[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s13/I0 |
4.571 | 0.517 | tINS | FF | 2 | R30C46[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s13/F |
5.469 | 0.899 | tNET | FF | 1 | R31C45[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s6/I0 |
6.024 | 0.555 | tINS | FF | 2 | R31C45[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s6/F |
6.442 | 0.418 | tNET | FF | 1 | R32C43[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s6/I0 |
6.813 | 0.371 | tINS | FF | 1 | R32C43[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s6/F |
6.983 | 0.170 | tNET | FF | 1 | R33C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s3/I2 |
7.354 | 0.371 | tINS | FF | 1 | R33C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s3/F |
7.354 | 0.000 | tNET | FF | 1 | R33C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R33C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/CLK |
16.875 | -0.035 | tSu | 1 | R33C43[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.784, 39.151%; route: 4.095, 57.586%; tC2Q: 0.232, 3.263% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
Slack | 9.525 |
Data Arrival Time | 7.350 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/opefrm_get_o_8_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R35C34[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 3 | R35C34[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
1.486 | 1.011 | tNET | FF | 1 | R38C41[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4201_s3/I3 |
2.003 | 0.517 | tINS | FF | 3 | R38C41[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4201_s3/F |
2.651 | 0.648 | tNET | FF | 1 | R38C44[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I3 |
3.206 | 0.555 | tINS | FF | 2 | R38C44[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
3.458 | 0.252 | tNET | FF | 1 | R36C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s5/I1 |
3.829 | 0.371 | tINS | FF | 39 | R36C44[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s5/F |
5.234 | 1.406 | tNET | FF | 1 | R39C49[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n754_s1/I2 |
5.605 | 0.371 | tINS | FF | 21 | R39C49[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n754_s1/F |
6.801 | 1.196 | tNET | FF | 1 | R40C36[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n808_s0/I2 |
7.350 | 0.549 | tINS | FR | 1 | R40C36[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n808_s0/F |
7.350 | 0.000 | tNET | RR | 1 | R40C36[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/opefrm_get_o_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R40C36[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/opefrm_get_o_8_s1/CLK |
16.875 | -0.035 | tSu | 1 | R40C36[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/opefrm_get_o_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 2.363, 33.250%; route: 4.512, 63.485%; tC2Q: 0.232, 3.265% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
Slack | 9.526 |
Data Arrival Time | 7.349 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q |
2.230 | 1.755 | tNET | FF | 1 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/I2 |
2.747 | 0.517 | tINS | FF | 6 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/F |
3.182 | 0.435 | tNET | FF | 1 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/I2 |
3.737 | 0.555 | tINS | FF | 2 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/F |
3.989 | 0.252 | tNET | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/I3 |
4.442 | 0.453 | tINS | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/F |
4.596 | 0.154 | tNET | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I2 |
5.151 | 0.555 | tINS | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
5.398 | 0.247 | tNET | FF | 1 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
5.851 | 0.453 | tINS | FF | 8 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
6.779 | 0.928 | tNET | FF | 1 | R13C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n118_s3/I3 |
7.349 | 0.570 | tINS | FR | 1 | R13C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n118_s3/F |
7.349 | 0.000 | tNET | RR | 1 | R13C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R13C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0/CLK |
16.875 | -0.035 | tSu | 1 | R13C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.103, 43.668%; route: 3.771, 53.067%; tC2Q: 0.232, 3.265% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
Slack | 9.547 |
Data Arrival Time | 7.328 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 4 | R40C31[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_2_s0/Q |
2.230 | 1.755 | tNET | FF | 1 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/I2 |
2.747 | 0.517 | tINS | FF | 6 | R13C40[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s20/F |
3.182 | 0.435 | tNET | FF | 1 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/I2 |
3.737 | 0.555 | tINS | FF | 2 | R13C41[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s15/F |
3.989 | 0.252 | tNET | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/I3 |
4.442 | 0.453 | tINS | FF | 1 | R13C39[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s27/F |
4.596 | 0.154 | tNET | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I2 |
5.151 | 0.555 | tINS | FF | 1 | R13C39[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
5.398 | 0.247 | tNET | FF | 1 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
5.851 | 0.453 | tINS | FF | 8 | R13C41[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
6.779 | 0.928 | tNET | FF | 1 | R13C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n116_s3/I3 |
7.328 | 0.549 | tINS | FR | 1 | R13C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n116_s3/F |
7.328 | 0.000 | tNET | RR | 1 | R13C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R13C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0/CLK |
16.875 | -0.035 | tSu | 1 | R13C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.082, 43.501%; route: 3.771, 53.224%; tC2Q: 0.232, 3.275% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.087 |
Data Arrival Time | 200.647 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R16C28[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_s0/CLK |
200.386 | 0.202 | tC2Q | RR | 1 | R16C28[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_s0/Q |
200.647 | 0.260 | tNET | RR | 1 | R15C26[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R15C26[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0 | |||
200.560 | 0.011 | tHld | 1 | R15C26[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
Slack | 0.289 |
Data Arrival Time | 200.848 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_1_G[2]_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_2_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R16C29[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_1_G[2]_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 1 | R16C29[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_1_G[2]_s0/Q |
200.502 | 0.117 | tNET | FF | 1 | R16C29[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_14_G[0]_s5/I0 |
200.734 | 0.232 | tINS | FF | 1 | R16C29[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_14_G[0]_s5/F |
200.734 | 0.000 | tNET | FF | 1 | R16C29[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_14_G[0]_s2/I0 |
200.786 | 0.052 | tINS | FF | 1 | R16C29[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_14_G[0]_s2/O |
200.786 | 0.000 | tNET | FF | 1 | R16C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_14_G[0]_s0/I1 |
200.838 | 0.052 | tINS | FF | 1 | R16C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_14_G[0]_s0/O |
200.848 | 0.010 | tNET | FF | 1 | R16C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R16C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_2_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_2_s0 | |||
200.560 | 0.011 | tHld | 1 | R16C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_2_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.336, 50.612%; route: 0.127, 19.112%; tC2Q: 0.201, 30.277% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
Slack | 0.289 |
Data Arrival Time | 200.848 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_2_G[7]_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_7_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R17C33[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_2_G[7]_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 1 | R17C33[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_2_G[7]_s0/Q |
200.502 | 0.117 | tNET | FF | 1 | R17C33[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_49_G[0]_s4/I0 |
200.734 | 0.232 | tINS | FF | 1 | R17C33[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_49_G[0]_s4/F |
200.734 | 0.000 | tNET | FF | 1 | R17C33[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_49_G[0]_s1/I1 |
200.786 | 0.052 | tINS | FF | 1 | R17C33[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_49_G[0]_s1/O |
200.786 | 0.000 | tNET | FF | 1 | R17C33[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_49_G[0]_s0/I0 |
200.838 | 0.052 | tINS | FF | 1 | R17C33[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_49_G[0]_s0/O |
200.848 | 0.010 | tNET | FF | 1 | R17C33[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R17C33[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_7_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_7_s0 | |||
200.560 | 0.011 | tHld | 1 | R17C33[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_7_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.336, 50.612%; route: 0.127, 19.112%; tC2Q: 0.201, 30.277% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
Slack | 0.293 |
Data Arrival Time | 200.853 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_0_G[0]_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_0_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R16C29[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_0_G[0]_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 1 | R16C29[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_0_G[0]_s0/Q |
200.507 | 0.122 | tNET | FF | 1 | R15C29[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_0_G[0]_s3/I0 |
200.739 | 0.232 | tINS | FF | 1 | R15C29[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_0_G[0]_s3/F |
200.739 | 0.000 | tNET | FF | 1 | R15C29[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_0_G[0]_s1/I0 |
200.791 | 0.052 | tINS | FF | 1 | R15C29[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_0_G[0]_s1/O |
200.791 | 0.000 | tNET | FF | 1 | R15C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_0_G[0]_s0/I0 |
200.843 | 0.052 | tINS | FF | 1 | R15C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_0_G[0]_s0/O |
200.853 | 0.010 | tNET | FF | 1 | R15C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R15C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_0_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_0_s0 | |||
200.560 | 0.011 | tHld | 1 | R15C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_0_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.336, 50.239%; route: 0.132, 19.707%; tC2Q: 0.201, 30.054% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
Slack | 0.293 |
Data Arrival Time | 200.853 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[1]_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R17C30[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[1]_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 1 | R17C30[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[1]_s0/Q |
200.507 | 0.122 | tNET | FF | 1 | R16C30[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s5/I1 |
200.739 | 0.232 | tINS | FF | 1 | R16C30[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s5/F |
200.739 | 0.000 | tNET | FF | 1 | R16C30[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s2/I0 |
200.791 | 0.052 | tINS | FF | 1 | R16C30[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s2/O |
200.791 | 0.000 | tNET | FF | 1 | R16C30[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s0/I1 |
200.843 | 0.052 | tINS | FF | 1 | R16C30[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s0/O |
200.853 | 0.010 | tNET | FF | 1 | R16C30[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R16C30[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0 | |||
200.560 | 0.011 | tHld | 1 | R16C30[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.336, 50.239%; route: 0.132, 19.707%; tC2Q: 0.201, 30.054% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
Slack | 0.293 |
Data Arrival Time | 200.853 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[3]_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R17C32[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[3]_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 1 | R17C32[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[3]_s0/Q |
200.507 | 0.122 | tNET | FF | 1 | R17C31[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s5/I1 |
200.739 | 0.232 | tINS | FF | 1 | R17C31[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s5/F |
200.739 | 0.000 | tNET | FF | 1 | R17C31[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s2/I0 |
200.791 | 0.052 | tINS | FF | 1 | R17C31[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s2/O |
200.791 | 0.000 | tNET | FF | 1 | R17C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s0/I1 |
200.843 | 0.052 | tINS | FF | 1 | R17C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s0/O |
200.853 | 0.010 | tNET | FF | 1 | R17C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R17C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0 | |||
200.560 | 0.011 | tHld | 1 | R17C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.336, 50.239%; route: 0.132, 19.707%; tC2Q: 0.201, 30.054% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
Slack | 0.293 |
Data Arrival Time | 200.853 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_6_G[4]_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R17C31[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_6_G[4]_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 1 | R17C31[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_6_G[4]_s0/Q |
200.507 | 0.122 | tNET | FF | 1 | R16C31[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s4/I1 |
200.739 | 0.232 | tINS | FF | 1 | R16C31[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s4/F |
200.739 | 0.000 | tNET | FF | 1 | R16C31[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s1/I1 |
200.791 | 0.052 | tINS | FF | 1 | R16C31[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s1/O |
200.791 | 0.000 | tNET | FF | 1 | R16C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s0/I0 |
200.843 | 0.052 | tINS | FF | 1 | R16C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s0/O |
200.853 | 0.010 | tNET | FF | 1 | R16C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R16C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0 | |||
200.560 | 0.011 | tHld | 1 | R16C31[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.336, 50.239%; route: 0.132, 19.707%; tC2Q: 0.201, 30.054% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
Slack | 0.293 |
Data Arrival Time | 200.853 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_1_G[5]_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_5_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R17C32[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_1_G[5]_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 1 | R17C32[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_1_G[5]_s0/Q |
200.507 | 0.122 | tNET | FF | 1 | R16C32[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_35_G[0]_s5/I0 |
200.739 | 0.232 | tINS | FF | 1 | R16C32[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_35_G[0]_s5/F |
200.739 | 0.000 | tNET | FF | 1 | R16C32[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_35_G[0]_s2/I0 |
200.791 | 0.052 | tINS | FF | 1 | R16C32[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_35_G[0]_s2/O |
200.791 | 0.000 | tNET | FF | 1 | R16C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_35_G[0]_s0/I1 |
200.843 | 0.052 | tINS | FF | 1 | R16C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_35_G[0]_s0/O |
200.853 | 0.010 | tNET | FF | 1 | R16C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R16C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_5_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_5_s0 | |||
200.560 | 0.011 | tHld | 1 | R16C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_5_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.336, 50.239%; route: 0.132, 19.707%; tC2Q: 0.201, 30.054% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
Slack | 0.293 |
Data Arrival Time | 200.853 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[6]_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R18C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[6]_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 1 | R18C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[6]_s0/Q |
200.507 | 0.122 | tNET | FF | 1 | R17C32[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s5/I1 |
200.739 | 0.232 | tINS | FF | 1 | R17C32[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s5/F |
200.739 | 0.000 | tNET | FF | 1 | R17C32[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s2/I0 |
200.791 | 0.052 | tINS | FF | 1 | R17C32[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s2/O |
200.791 | 0.000 | tNET | FF | 1 | R17C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s0/I1 |
200.843 | 0.052 | tINS | FF | 1 | R17C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s0/O |
200.853 | 0.010 | tNET | FF | 1 | R17C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R17C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0 | |||
200.560 | 0.011 | tHld | 1 | R17C32[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.336, 50.239%; route: 0.132, 19.707%; tC2Q: 0.201, 30.054% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 0.293 |
Data Arrival Time | 200.853 |
Data Required Time | 200.560 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_2_G[9]_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_9_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R18C29[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_2_G[9]_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 1 | R18C29[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_2_G[9]_s0/Q |
200.507 | 0.122 | tNET | FF | 1 | R17C29[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_63_G[0]_s4/I0 |
200.739 | 0.232 | tINS | FF | 1 | R17C29[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_63_G[0]_s4/F |
200.739 | 0.000 | tNET | FF | 1 | R17C29[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_63_G[0]_s1/I1 |
200.791 | 0.052 | tINS | FF | 1 | R17C29[3][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_63_G[0]_s1/O |
200.791 | 0.000 | tNET | FF | 1 | R17C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_63_G[0]_s0/I0 |
200.843 | 0.052 | tINS | FF | 1 | R17C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_63_G[0]_s0/O |
200.853 | 0.010 | tNET | FF | 1 | R17C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
200.514 | 0.184 | tNET | RR | 1 | R17C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_9_s0/CLK |
200.549 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_9_s0 | |||
200.560 | 0.011 | tHld | 1 | R17C29[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_9_s0 |
Path Statistics:
Clock Skew | 0.329 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.336, 50.239%; route: 0.132, 19.707%; tC2Q: 0.201, 30.054% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 0.307 |
Data Arrival Time | 0.502 |
Data Required Time | 0.195 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr_2_s1 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_2_s1 |
Launch Clk | rxdiv5clk:[R] |
Latch Clk | rxdiv5clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rxdiv5clk | ||||
0.000 | 0.000 | tCL | RR | 206 | TOPSIDE[1] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr_2_s1/CLK |
0.385 | 0.201 | tC2Q | RF | 1 | R30C38[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr_2_s1/Q |
0.502 | 0.117 | tNET | FF | 1 | R30C38[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rxdiv5clk | ||||
0.000 | 0.000 | tCL | RR | 206 | TOPSIDE[1] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C38[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_2_s1/CLK |
0.195 | 0.011 | tHld | 1 | R30C38[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 0.307 |
Data Arrival Time | 0.502 |
Data Required Time | 0.195 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr_3_s1 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_3_s1 |
Launch Clk | rxdiv5clk:[R] |
Latch Clk | rxdiv5clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rxdiv5clk | ||||
0.000 | 0.000 | tCL | RR | 206 | TOPSIDE[1] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr_3_s1/CLK |
0.385 | 0.201 | tC2Q | RF | 1 | R30C38[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr_3_s1/Q |
0.502 | 0.117 | tNET | FF | 1 | R30C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | rxdiv5clk | ||||
0.000 | 0.000 | tCL | RR | 206 | TOPSIDE[1] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_3_s1/CLK |
0.195 | 0.011 | tHld | 1 | R30C38[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/wp_rd_gray_ptr1_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 0.321 |
Data Arrival Time | 0.516 |
Data Required Time | 0.195 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_valid_o_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rxdata_fp_o_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R35C45[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_valid_o_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 7 | R35C45[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_valid_o_s0/Q |
0.516 | 0.130 | tNET | RR | 1 | R35C45[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rxdata_fp_o_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R35C45[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rxdata_fp_o_s0/CLK |
0.195 | 0.011 | tHld | 1 | R35C45[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rxdata_fp_o_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.130, 39.090%; tC2Q: 0.202, 60.910% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 0.322 |
Data Arrival Time | 0.517 |
Data Required Time | 0.195 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sync_controller_sda_inst/o_sync_out_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sync_controller_sda_inst/o_falling_edge_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C46[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sync_controller_sda_inst/o_sync_out_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R11C46[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sync_controller_sda_inst/o_sync_out_s0/Q |
0.517 | 0.131 | tNET | RR | 1 | R11C46[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sync_controller_sda_inst/o_falling_edge_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C46[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sync_controller_sda_inst/o_falling_edge_s0/CLK |
0.195 | 0.011 | tHld | 1 | R11C46[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sync_controller_sda_inst/o_falling_edge_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.131, 39.314%; tC2Q: 0.202, 60.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.518 |
Data Required Time | 0.195 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_3_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C46[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 31 | R27C46[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0/Q |
0.518 | 0.132 | tNET | RR | 1 | R27C45[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C45[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R27C45[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.481%; tC2Q: 0.202, 60.519% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.518 |
Data Required Time | 0.195 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C46[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 31 | R27C46[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0/Q |
0.518 | 0.132 | tNET | RR | 1 | R27C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CLK |
0.195 | 0.011 | tHld | 1 | R27C44[2][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.481%; tC2Q: 0.202, 60.519% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.518 |
Data Required Time | 0.195 |
From | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_14_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C46[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 31 | R27C46[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_en_s0/Q |
0.518 | 0.132 | tNET | RR | 1 | R27C44[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_14_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C44[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_14_s0/CLK |
0.195 | 0.011 | tHld | 1 | R27C44[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.481%; tC2Q: 0.202, 60.519% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.519 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 52 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
0.519 | 0.132 | tNET | RR | 1 | R31C8[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R31C8[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0/CLK |
0.195 | 0.011 | tHld | 1 | R31C8[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.581%; tC2Q: 0.202, 60.419% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.519 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_13_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 52 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
0.519 | 0.132 | tNET | RR | 1 | R29C8[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_13_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C8[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_13_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C8[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.581%; tC2Q: 0.202, 60.419% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.519 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_22_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 52 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
0.519 | 0.132 | tNET | RR | 1 | R29C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_22_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_22_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_22_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.581%; tC2Q: 0.202, 60.419% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.519 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_23_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 52 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
0.519 | 0.132 | tNET | RR | 1 | R30C10[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_23_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C10[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_23_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C10[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_23_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.581%; tC2Q: 0.202, 60.419% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.519 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_24_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 52 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
0.519 | 0.132 | tNET | RR | 1 | R29C8[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_24_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C8[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_24_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C8[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.581%; tC2Q: 0.202, 60.419% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.519 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 52 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
0.519 | 0.132 | tNET | RR | 1 | R30C10[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C10[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C10[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.581%; tC2Q: 0.202, 60.419% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.519 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 52 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
0.519 | 0.132 | tNET | RR | 1 | R29C8[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C8[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C8[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.581%; tC2Q: 0.202, 60.419% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
Slack | 0.323 |
Data Arrival Time | 0.519 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 52 | R30C8[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
0.519 | 0.132 | tNET | RR | 1 | R30C10[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C10[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C10[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.132, 39.581%; tC2Q: 0.202, 60.419% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 2.772 |
Data Arrival Time | 117.953 |
Data Required Time | 120.725 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
116.667 | 116.667 | active clock edge time | ||||
116.667 | 0.000 | w_clk60m | ||||
116.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
116.910 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
117.141 | 0.231 | tC2Q | RR | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
117.953 | 0.812 | tNET | RR | 1 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/RESETN |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
120.000 | 120.000 | active clock edge time | ||||
120.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | ||||
120.415 | 0.415 | tCL | RR | 2 | PLL_R[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
120.790 | 0.375 | tNET | RR | 5 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/HCLKIN |
120.755 | -0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV | |||
120.725 | -0.030 | tSu | 1 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV |
Path Statistics:
Clock Skew | 0.547 |
Setup Relationship | 3.333 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.812, 77.847%; tC2Q: 0.231, 22.153% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path2
Path Summary:
Slack | 13.001 |
Data Arrival Time | 3.874 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_0_s3 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.874 | 1.413 | tNET | FF | 1 | R12C51[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R12C51[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_0_s3/CLK |
16.875 | -0.035 | tSu | 1 | R12C51[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 14.241%; route: 2.881, 79.368%; tC2Q: 0.232, 6.391% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
Slack | 13.001 |
Data Arrival Time | 3.874 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_1_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.874 | 1.413 | tNET | FF | 1 | R11C51[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R11C51[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_1_s1/CLK |
16.875 | -0.035 | tSu | 1 | R11C51[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 14.241%; route: 2.881, 79.368%; tC2Q: 0.232, 6.391% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
Slack | 13.001 |
Data Arrival Time | 3.874 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_2_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.874 | 1.413 | tNET | FF | 1 | R11C51[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R11C51[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_2_s1/CLK |
16.875 | -0.035 | tSu | 1 | R11C51[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 14.241%; route: 2.881, 79.368%; tC2Q: 0.232, 6.391% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
Slack | 13.001 |
Data Arrival Time | 3.874 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_3_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.874 | 1.413 | tNET | FF | 1 | R12C51[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R12C51[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_3_s1/CLK |
16.875 | -0.035 | tSu | 1 | R12C51[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_bit_count_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 14.241%; route: 2.881, 79.368%; tC2Q: 0.232, 6.391% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
Slack | 13.236 |
Data Arrival Time | 3.639 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_4_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.639 | 1.178 | tNET | FF | 1 | R7C47[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R7C47[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_4_s1/CLK |
16.875 | -0.035 | tSu | 1 | R7C47[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.226%; route: 2.646, 77.941%; tC2Q: 0.232, 6.833% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
Slack | 13.236 |
Data Arrival Time | 3.639 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_6_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.639 | 1.178 | tNET | FF | 1 | R7C47[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R7C47[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_6_s1/CLK |
16.875 | -0.035 | tSu | 1 | R7C47[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.226%; route: 2.646, 77.941%; tC2Q: 0.232, 6.833% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
Slack | 13.236 |
Data Arrival Time | 3.639 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_7_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.639 | 1.178 | tNET | FF | 1 | R7C47[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R7C47[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_7_s1/CLK |
16.875 | -0.035 | tSu | 1 | R7C47[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.226%; route: 2.646, 77.941%; tC2Q: 0.232, 6.833% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
Slack | 13.236 |
Data Arrival Time | 3.639 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_8_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.639 | 1.178 | tNET | FF | 1 | R7C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R7C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_8_s1/CLK |
16.875 | -0.035 | tSu | 1 | R7C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.226%; route: 2.646, 77.941%; tC2Q: 0.232, 6.833% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
Slack | 13.236 |
Data Arrival Time | 3.639 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_9_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.639 | 1.178 | tNET | FF | 1 | R7C47[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R7C47[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_9_s1/CLK |
16.875 | -0.035 | tSu | 1 | R7C47[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.226%; route: 2.646, 77.941%; tC2Q: 0.232, 6.833% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/clear_controller_bit_count_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R12C50[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/clear_controller_bit_count_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R12C50[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/clear_controller_bit_count_s1/CLK |
16.875 | -0.035 | tSu | 1 | R12C50[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/clear_controller_bit_count_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sda_oe_o_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R8C48[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sda_oe_o_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R8C48[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sda_oe_o_s1/CLK |
16.875 | -0.035 | tSu | 1 | R8C48[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/sda_oe_o_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_5_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R8C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R8C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_5_s1/CLK |
16.875 | -0.035 | tSu | 1 | R8C47[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R12C50[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R12C50[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_s1/CLK |
16.875 | -0.035 | tSu | 1 | R12C50[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/command_rd_wrn_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R11C48[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/command_rd_wrn_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R11C48[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/command_rd_wrn_s1/CLK |
16.875 | -0.035 | tSu | 1 | R11C48[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/command_rd_wrn_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_byte_in_0_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R11C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_byte_in_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R11C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_byte_in_0_s1/CLK |
16.875 | -0.035 | tSu | 1 | R11C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_byte_in_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_0_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R8C47[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R8C47[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_0_s0/CLK |
16.875 | -0.035 | tSu | 1 | R8C47[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_1_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R8C47[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R8C47[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_1_s0/CLK |
16.875 | -0.035 | tSu | 1 | R8C47[1][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/setup_timeout_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/scl_oe_o_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R8C48[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/scl_oe_o_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R8C48[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/scl_oe_o_s0/CLK |
16.875 | -0.035 | tSu | 1 | R8C48[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/scl_oe_o_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_0_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R8C49[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R8C49[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_0_s0/CLK |
16.875 | -0.035 | tSu | 1 | R8C49[0][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
Slack | 13.244 |
Data Arrival Time | 3.631 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_scl_dly_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.631 | 1.170 | tNET | FF | 1 | R8C49[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_scl_dly_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R8C49[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_scl_dly_s0/CLK |
16.875 | -0.035 | tSu | 1 | R8C49[1][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_scl_dly_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.262%; route: 2.639, 77.890%; tC2Q: 0.232, 6.849% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
Slack | 13.252 |
Data Arrival Time | 3.623 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_0_s3 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.623 | 1.162 | tNET | FF | 1 | R6C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R6C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_0_s3/CLK |
16.875 | -0.035 | tSu | 1 | R6C48[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.297%; route: 2.631, 77.839%; tC2Q: 0.232, 6.864% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
Slack | 13.252 |
Data Arrival Time | 3.623 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_1_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.623 | 1.162 | tNET | FF | 1 | R6C47[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R6C47[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_1_s1/CLK |
16.875 | -0.035 | tSu | 1 | R6C47[2][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/target_scl_hold_count_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.297%; route: 2.631, 77.839%; tC2Q: 0.232, 6.864% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
Slack | 13.252 |
Data Arrival Time | 3.623 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_valid_s1 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.623 | 1.162 | tNET | FF | 1 | R12C49[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_valid_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R12C49[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_valid_s1/CLK |
16.875 | -0.035 | tSu | 1 | R12C49[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/controller_read_nack_valid_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.297%; route: 2.631, 77.839%; tC2Q: 0.232, 6.864% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
Slack | 13.252 |
Data Arrival Time | 3.623 |
Data Required Time | 16.875 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_1_s0 |
Launch Clk | w_clk60m:[R] |
Latch Clk | w_clk60m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk60m | ||||
0.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
1.944 | 1.469 | tNET | FF | 1 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/I2 |
2.461 | 0.517 | tINS | FF | 60 | R8C43[3][B] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/n124_s1/F |
3.623 | 1.162 | tNET | FF | 1 | R8C50[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | w_clk60m | ||||
16.667 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.910 | 0.243 | tNET | RR | 1 | R8C50[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_1_s0/CLK |
16.875 | -0.035 | tSu | 1 | R8C50[0][A] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_controller_0/relay_state_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.517, 15.297%; route: 2.631, 77.839%; tC2Q: 0.232, 6.864% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.338 |
Data Arrival Time | 201.083 |
Data Required Time | 200.745 |
From | u_ltpi_scm/u_ltpi_core/r_rstn_s0 |
To | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV |
Launch Clk | w_clk60m:[R] |
Latch Clk | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | w_clk60m | ||||
200.000 | 0.000 | tCL | RR | 1919 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
200.184 | 0.184 | tNET | RR | 1 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/CLK |
200.385 | 0.201 | tC2Q | RF | 26 | R21C28[1][B] | u_ltpi_scm/u_ltpi_core/r_rstn_s0/Q |
201.083 | 0.698 | tNET | FF | 1 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/RESETN |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
200.000 | 200.000 | active clock edge time | ||||
200.000 | 0.000 | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | ||||
200.415 | 0.415 | tCL | RR | 2 | PLL_R[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
200.700 | 0.285 | tNET | RR | 5 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/HCLKIN |
200.735 | 0.035 | tUnc | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV | |||
200.745 | 0.010 | tHld | 1 | TOPSIDE[0] | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV |
Path Statistics:
Clock Skew | 0.516 |
Hold Relationship | -0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.698, 77.631%; tC2Q: 0.201, 22.369% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.285, 100.000% |
Path2
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R30C12[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C12[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1/CLK |
0.195 | 0.011 | tHld | 1 | R30C12[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C12[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C12[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1/CLK |
0.195 | 0.011 | tHld | 1 | R29C12[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C12[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C12[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C12[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C11[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C11[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C11[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R30C21[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C21[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C21[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C22[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C22[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C22[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R30C24[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C24[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C24[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C21[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C21[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C21[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C21[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C21[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C21[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C22[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C22[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C22[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C21[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C21[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C21[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R30C25[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C25[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C25[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C22[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C22[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C22[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R30C21[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C21[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C21[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C14[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C14[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C14[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C17[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C17[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C17[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C14[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C14[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C14[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R30C15[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C15[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C15[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C18[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C18[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C18[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R30C18[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C18[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C18[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C18[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C18[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C18[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R30C24[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R30C24[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0/CLK |
0.195 | 0.011 | tHld | 1 | R30C24[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C21[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C21[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C21[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
Slack | 0.925 |
Data Arrival Time | 1.120 |
Data Required Time | 0.195 |
From | r_clk25_cnt_5_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0 |
Launch Clk | w_clk25m:[R] |
Latch Clk | w_clk25m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R27C26[2][B] | r_clk25_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 719 | R27C26[2][B] | r_clk25_cnt_5_s0/Q |
1.120 | 0.734 | tNET | RR | 1 | R29C12[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk25m | ||||
0.000 | 0.000 | tCL | RR | 2897 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R29C12[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0/CLK |
0.195 | 0.011 | tHld | 1 | R29C12[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | r_clk60_cnt_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | r_clk60_cnt_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | r_clk60_cnt_4_s0/CLK |
MPW2
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_20_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_20_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_20_s0/CLK |
MPW3
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_7_s0/CLK |
MPW4
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frm_crc_err_cnt_26_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frm_crc_err_cnt_26_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/frm_crc_err_cnt_26_s0/CLK |
MPW5
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx3_data_o_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx3_data_o_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx3_data_o_3_s0/CLK |
MPW6
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rxb_data_o_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rxb_data_o_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rxb_data_o_3_s0/CLK |
MPW7
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_data_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_data_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/read_data_3_s0/CLK |
MPW8
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rd_gray_ptr_4_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rd_gray_ptr_4_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rd_gray_ptr_4_s1/CLK |
MPW9
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rp_wr_gray_ptr1_1_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rp_wr_gray_ptr1_1_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rp_wr_gray_ptr1_1_s1/CLK |
MPW10
MPW Summary:
Slack: | 7.256 |
Actual Width: | 8.256 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk60m |
Objects: | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rp_wr_gray_ptr_2_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | w_clk60m | ||
8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
8.595 | 0.261 | tNET | FF | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rp_wr_gray_ptr_2_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
16.667 | 0.000 | active clock edge time | ||
16.667 | 0.000 | w_clk60m | ||
16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
16.851 | 0.184 | tNET | RR | u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/rp_wr_gray_ptr_2_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
2897 | w_clk25m | 25.913 | 0.261 |
1919 | w_clk60m | 2.772 | 0.261 |
719 | r_clk25_cnt[5] | 36.382 | 1.483 |
207 | n5753_6 | 11.522 | 1.357 |
206 | clk5div | 28.025 | 0.261 |
196 | rd_ptr[2] | 36.020 | 1.986 |
195 | n491_4 | 11.015 | 1.627 |
192 | rd_ptr[2] | 36.515 | 1.193 |
155 | n1033_6 | 13.079 | 2.097 |
145 | phy_rx_rstn | 13.261 | 1.841 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R22C37 | 91.67% |
R49C12 | 91.67% |
R30C38 | 90.28% |
R29C16 | 90.28% |
R22C42 | 88.89% |
R36C41 | 88.89% |
R38C39 | 88.89% |
R39C31 | 88.89% |
R39C32 | 88.89% |
R39C35 | 88.89% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name i_clk -period 20 -waveform {0 10} [get_ports {i_clk}] |
TC_CLOCK | Actived | create_clock -name RX_CLK_P -period 6.66 -waveform {0 3.33} [get_ports {RX_CLK_P}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name rxdiv5clk -source [get_ports {RX_CLK_P}] -master_clock RX_CLK_P -divide_by 5 -multiply_by 1 [get_nets {u_ltpi_scm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/clk5div}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name w_clk25m -source [get_ports {i_clk}] -master_clock i_clk -divide_by 2 -multiply_by 1 [get_nets {w_clk25m}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name w_clk60m -source [get_ports {i_clk}] -master_clock i_clk -divide_by 5 -multiply_by 6 [get_nets {w_clk60m}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {w_clk60m}] -group [get_clocks {w_clk25m}] -group [get_clocks {i_clk} ] -group [get_clocks {rxdiv5clk} ] |