Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\impl\gwsynthesis\IIC_MASTER.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\top.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\top.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Created Time | Mon Jan 29 10:51:59 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 10811 |
Numbers of Endpoints Analyzed | 5394 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
i_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | i_clk | ||
w_clk100m | Generated | 10.000 | 100.000 | 0.000 | 5.000 | i_clk | i_clk | w_clk100m |
u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | i_clk_ibuf/I | i_clk | u0_syspll_rPLL/rpll_inst/CLKOUTP |
u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | i_clk_ibuf/I | i_clk | u0_syspll_rPLL/rpll_inst/CLKOUTD |
u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 30.000 | 33.333 | 0.000 | 15.000 | i_clk_ibuf/I | i_clk | u0_syspll_rPLL/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | w_clk100m | 100.000(MHz) | 100.006(MHz) | 9 | TOP |
No timing paths to get frequency of i_clk!
No timing paths to get frequency of u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
i_clk | Setup | 0.000 | 0 |
i_clk | Hold | 0.000 | 0 |
w_clk100m | Setup | 0.000 | 0 |
w_clk100m | Hold | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.001 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_6_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.964 |
2 | 0.008 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_11_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.957 |
3 | 0.012 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_30_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.953 |
4 | 0.014 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_9_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.951 |
5 | 0.028 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_7_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.937 |
6 | 0.030 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_3_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.935 |
7 | 0.032 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_8_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.933 |
8 | 0.033 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_27_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.932 |
9 | 0.037 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_18_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.928 |
10 | 0.038 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.927 |
11 | 0.042 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_4_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.923 |
12 | 0.052 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_21_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.913 |
13 | 0.054 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.911 |
14 | 0.060 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_26_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.905 |
15 | 0.085 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_2_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.880 |
16 | 0.106 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_16_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.859 |
17 | 0.115 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_10_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.850 |
18 | 0.123 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_15_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.842 |
19 | 0.132 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_1_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.833 |
20 | 0.138 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_22_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.827 |
21 | 0.138 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/reg0x000B_10_s0/CE | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.827 |
22 | 0.139 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_25_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.826 |
23 | 0.140 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_12_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.825 |
24 | 0.146 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_19_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.819 |
25 | 0.166 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q | u_local2reg/local_rdat_o_14_s0/D | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 9.799 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.317 | u_i2c_master_cfgport/r1_cfg_wren_s0/Q | u_i2c_master_cfgport/cfg_wdat_rdy_o_s0/RESET | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.328 |
2 | 0.327 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_28_s0/CE | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.338 |
3 | 0.327 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_24_s0/CE | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.338 |
4 | 0.327 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_4_s0/CE | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.338 |
5 | 0.327 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_0_s0/CE | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.338 |
6 | 0.425 | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
7 | 0.425 | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_8_s1/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_8_s1/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
8 | 0.425 | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_12_s1/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_12_s1/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
9 | 0.425 | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_14_s1/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_14_s1/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
10 | 0.425 | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_15_s1/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_15_s1/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
11 | 0.425 | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_2_s1/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_2_s1/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
12 | 0.425 | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/CORE_CMD_2_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/CORE_CMD_2_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
13 | 0.425 | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/irq_flag_s4/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/irq_flag_s4/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
14 | 0.425 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_7_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_7_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
15 | 0.425 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_9_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_9_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
16 | 0.425 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
17 | 0.425 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_3_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_3_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
18 | 0.425 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
19 | 0.425 | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_3_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_3_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
20 | 0.425 | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
21 | 0.425 | r_clk100_cnt_2_s0/Q | r_clk100_cnt_2_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.436 |
22 | 0.427 | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_0_s3/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_0_s3/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.438 |
23 | 0.427 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.438 |
24 | 0.427 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr2_ptr_0_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr2_ptr_0_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.438 |
25 | 0.427 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr2_ptr_3_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr2_ptr_3_s0/D | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 0.438 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
2 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
3 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1/PRESET | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
4 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1/PRESET | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
5 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
6 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
7 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
8 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
9 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
10 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
11 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
12 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
13 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
14 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
15 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
16 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
17 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
18 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
19 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
20 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
21 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
22 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
23 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
24 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
25 | 7.836 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 10.000 | 0.000 | 2.129 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
2 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
3 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1/PRESET | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
4 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1/PRESET | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
5 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
6 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
7 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
8 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
9 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
10 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
11 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
12 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
13 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
14 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
15 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
16 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
17 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
18 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
19 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
20 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
21 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
22 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
23 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
24 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
25 | 1.372 | r_clk100_cnt_5_s0/Q | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1/CLEAR | w_clk100m:[R] | w_clk100m:[R] | 0.000 | 0.000 | 1.383 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | r_clk100_cnt_4_s0 |
2 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | r_clk100_cnt_2_s0 |
3 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0 |
4 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | u_Uart_to_Bus_Top/uart_bus_core/u1.apb0_ena_r_s0 |
5 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_40_s0 |
6 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_8_s1 |
7 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr1_ptr_1_s0 |
8 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ram_rdata_15_s0 |
9 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ram_ram_RAMREG_4_G[43]_s0 |
10 | 3.923 | 4.923 | 1.000 | Low Pulse Width | w_clk100m | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_RAMREG_2_G[7]_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.001 |
Data Arrival Time | 10.208 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_6_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
2.753 | 0.457 | tNET | FF | 1 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/I2 |
3.270 | 0.517 | tINS | FF | 3 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/F |
4.743 | 1.473 | tNET | FF | 1 | R9C9[0][B] | u_local2reg/n5185_s2/I0 |
5.114 | 0.371 | tINS | FF | 19 | R9C9[0][B] | u_local2reg/n5185_s2/F |
6.075 | 0.961 | tNET | FF | 1 | R13C13[0][B] | u_local2reg/n5633_s1/I1 |
6.446 | 0.371 | tINS | FF | 32 | R13C13[0][B] | u_local2reg/n5633_s1/F |
7.689 | 1.243 | tNET | FF | 1 | R18C26[0][B] | u_local2reg/n3534_s80/I3 |
8.142 | 0.453 | tINS | FF | 1 | R18C26[0][B] | u_local2reg/n3534_s80/F |
8.539 | 0.397 | tNET | FF | 1 | R18C24[1][B] | u_local2reg/n3534_s70/I0 |
8.910 | 0.371 | tINS | FF | 1 | R18C24[1][B] | u_local2reg/n3534_s70/F |
9.837 | 0.927 | tNET | FF | 1 | R21C19[1][A] | u_local2reg/n3534_s67/I2 |
10.208 | 0.371 | tINS | FF | 1 | R21C19[1][A] | u_local2reg/n3534_s67/F |
10.208 | 0.000 | tNET | FF | 1 | R21C19[1][A] | u_local2reg/local_rdat_o_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R21C19[1][A] | u_local2reg/local_rdat_o_6_s0/CLK |
10.208 | -0.035 | tSu | 1 | R21C19[1][A] | u_local2reg/local_rdat_o_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.462, 34.744%; route: 6.270, 62.928%; tC2Q: 0.232, 2.328% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path2
Path Summary:
Slack | 0.008 |
Data Arrival Time | 10.200 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_11_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][A] | u_local2reg/n4674_s3/I2 |
5.305 | 0.517 | tINS | FF | 13 | R13C9[3][A] | u_local2reg/n4674_s3/F |
6.245 | 0.940 | tNET | FF | 1 | R7C12[3][B] | u_local2reg/n4674_s1/I0 |
6.762 | 0.517 | tINS | FF | 22 | R7C12[3][B] | u_local2reg/n4674_s1/F |
7.986 | 1.224 | tNET | FF | 1 | R16C23[2][B] | u_local2reg/n3529_s75/I0 |
8.357 | 0.371 | tINS | FF | 1 | R16C23[2][B] | u_local2reg/n3529_s75/F |
8.770 | 0.413 | tNET | FF | 1 | R17C22[3][B] | u_local2reg/n3529_s68/I3 |
9.325 | 0.555 | tINS | FF | 1 | R17C22[3][B] | u_local2reg/n3529_s68/F |
9.738 | 0.413 | tNET | FF | 1 | R16C23[0][A] | u_local2reg/n3529_s67/I0 |
10.200 | 0.462 | tINS | FR | 1 | R16C23[0][A] | u_local2reg/n3529_s67/F |
10.200 | 0.000 | tNET | RR | 1 | R16C23[0][A] | u_local2reg/local_rdat_o_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C23[0][A] | u_local2reg/local_rdat_o_11_s0/CLK |
10.208 | -0.035 | tSu | 1 | R16C23[0][A] | u_local2reg/local_rdat_o_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.947, 39.641%; route: 5.778, 58.029%; tC2Q: 0.232, 2.330% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
Slack | 0.012 |
Data Arrival Time | 10.197 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_30_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][B] | u_local2reg/n5057_s2/I2 |
5.305 | 0.517 | tINS | FF | 14 | R13C9[3][B] | u_local2reg/n5057_s2/F |
6.074 | 0.770 | tNET | FF | 1 | R7C7[0][A] | u_local2reg/n5057_s1/I1 |
6.591 | 0.517 | tINS | FF | 22 | R7C7[0][A] | u_local2reg/n5057_s1/F |
8.303 | 1.712 | tNET | FF | 1 | R12C14[3][B] | u_local2reg/n3510_s75/I0 |
8.858 | 0.555 | tINS | FF | 1 | R12C14[3][B] | u_local2reg/n3510_s75/F |
9.271 | 0.413 | tNET | FF | 1 | R11C15[3][A] | u_local2reg/n3510_s68/I3 |
9.733 | 0.462 | tINS | FR | 1 | R11C15[3][A] | u_local2reg/n3510_s68/F |
9.735 | 0.001 | tNET | RR | 1 | R11C15[0][B] | u_local2reg/n3510_s67/I0 |
10.197 | 0.462 | tINS | RR | 1 | R11C15[0][B] | u_local2reg/n3510_s67/F |
10.197 | 0.000 | tNET | RR | 1 | R11C15[0][B] | u_local2reg/local_rdat_o_30_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R11C15[0][B] | u_local2reg/local_rdat_o_30_s0/CLK |
10.208 | -0.035 | tSu | 1 | R11C15[0][B] | u_local2reg/local_rdat_o_30_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.038, 40.569%; route: 5.683, 57.100%; tC2Q: 0.232, 2.331% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
Slack | 0.014 |
Data Arrival Time | 10.194 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_9_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][A] | u_local2reg/n4674_s3/I2 |
5.305 | 0.517 | tINS | FF | 13 | R13C9[3][A] | u_local2reg/n4674_s3/F |
5.974 | 0.669 | tNET | FF | 1 | R9C8[3][B] | u_local2reg/n5185_s1/I0 |
6.345 | 0.371 | tINS | FF | 33 | R9C8[3][B] | u_local2reg/n5185_s1/F |
8.131 | 1.786 | tNET | FF | 1 | R21C20[2][B] | u_local2reg/n3531_s86/I0 |
8.584 | 0.453 | tINS | FF | 1 | R21C20[2][B] | u_local2reg/n3531_s86/F |
9.074 | 0.490 | tNET | FF | 1 | R20C21[1][B] | u_local2reg/n3531_s71/I2 |
9.623 | 0.549 | tINS | FR | 1 | R20C21[1][B] | u_local2reg/n3531_s71/F |
9.624 | 0.001 | tNET | RR | 1 | R20C21[0][A] | u_local2reg/n3531_s67/I3 |
10.194 | 0.570 | tINS | RR | 1 | R20C21[0][A] | u_local2reg/n3531_s67/F |
10.194 | 0.000 | tNET | RR | 1 | R20C21[0][A] | u_local2reg/local_rdat_o_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C21[0][A] | u_local2reg/local_rdat_o_9_s0/CLK |
10.208 | -0.035 | tSu | 1 | R20C21[0][A] | u_local2reg/local_rdat_o_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.985, 40.046%; route: 5.734, 57.622%; tC2Q: 0.232, 2.331% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
Slack | 0.028 |
Data Arrival Time | 10.181 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_7_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
2.826 | 0.531 | tNET | FF | 1 | R6C29[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_6_s0/I2 |
3.343 | 0.517 | tINS | FF | 3 | R6C29[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_6_s0/F |
4.550 | 1.206 | tNET | FF | 1 | R6C8[2][A] | u_local2reg/n4674_s4/I0 |
5.067 | 0.517 | tINS | FF | 58 | R6C8[2][A] | u_local2reg/n4674_s4/F |
6.029 | 0.962 | tNET | FF | 1 | R9C13[3][A] | u_local2reg/n5121_s1/I0 |
6.546 | 0.517 | tINS | FF | 32 | R9C13[3][A] | u_local2reg/n5121_s1/F |
8.042 | 1.497 | tNET | FF | 1 | R22C26[0][B] | u_local2reg/n3533_s81/I3 |
8.413 | 0.371 | tINS | FF | 1 | R22C26[0][B] | u_local2reg/n3533_s81/F |
9.069 | 0.656 | tNET | FF | 1 | R21C23[0][A] | u_local2reg/n3533_s70/I1 |
9.440 | 0.371 | tINS | FF | 1 | R21C23[0][A] | u_local2reg/n3533_s70/F |
9.611 | 0.170 | tNET | FF | 1 | R21C24[2][A] | u_local2reg/n3533_s67/I2 |
10.181 | 0.570 | tINS | FR | 1 | R21C24[2][A] | u_local2reg/n3533_s67/F |
10.181 | 0.000 | tNET | RR | 1 | R21C24[2][A] | u_local2reg/local_rdat_o_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R21C24[2][A] | u_local2reg/local_rdat_o_7_s0/CLK |
10.208 | -0.035 | tSu | 1 | R21C24[2][A] | u_local2reg/local_rdat_o_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.871, 38.954%; route: 5.834, 58.711%; tC2Q: 0.232, 2.335% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
Slack | 0.030 |
Data Arrival Time | 10.178 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_3_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
2.826 | 0.531 | tNET | FF | 1 | R6C29[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_6_s0/I2 |
3.343 | 0.517 | tINS | FF | 3 | R6C29[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_6_s0/F |
4.550 | 1.206 | tNET | FF | 1 | R6C8[2][A] | u_local2reg/n4674_s4/I0 |
5.067 | 0.517 | tINS | FF | 58 | R6C8[2][A] | u_local2reg/n4674_s4/F |
6.029 | 0.962 | tNET | FF | 1 | R9C13[3][A] | u_local2reg/n5121_s1/I0 |
6.546 | 0.517 | tINS | FF | 32 | R9C13[3][A] | u_local2reg/n5121_s1/F |
8.269 | 1.723 | tNET | FF | 1 | R22C24[3][A] | u_local2reg/n3537_s85/I0 |
8.839 | 0.570 | tINS | FR | 1 | R22C24[3][A] | u_local2reg/n3537_s85/F |
9.011 | 0.172 | tNET | RR | 1 | R22C25[2][B] | u_local2reg/n3537_s71/I1 |
9.382 | 0.371 | tINS | RF | 1 | R22C25[2][B] | u_local2reg/n3537_s71/F |
9.629 | 0.247 | tNET | FF | 1 | R22C26[1][A] | u_local2reg/n3537_s67/I3 |
10.178 | 0.549 | tINS | FR | 1 | R22C26[1][A] | u_local2reg/n3537_s67/F |
10.178 | 0.000 | tNET | RR | 1 | R22C26[1][A] | u_local2reg/local_rdat_o_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R22C26[1][A] | u_local2reg/local_rdat_o_3_s0/CLK |
10.208 | -0.035 | tSu | 1 | R22C26[1][A] | u_local2reg/local_rdat_o_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.049, 40.754%; route: 5.654, 56.910%; tC2Q: 0.232, 2.335% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
Slack | 0.032 |
Data Arrival Time | 10.176 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_8_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][B] | u_local2reg/n5057_s2/I2 |
5.305 | 0.517 | tINS | FF | 14 | R13C9[3][B] | u_local2reg/n5057_s2/F |
5.832 | 0.527 | tNET | FF | 1 | R9C10[3][A] | u_local2reg/n5569_s1/I0 |
6.285 | 0.453 | tINS | FF | 32 | R9C10[3][A] | u_local2reg/n5569_s1/F |
8.341 | 2.057 | tNET | FF | 1 | R11C24[0][B] | u_local2reg/n3532_s73/I3 |
8.890 | 0.549 | tINS | FR | 1 | R11C24[0][B] | u_local2reg/n3532_s73/F |
9.063 | 0.172 | tNET | RR | 1 | R11C25[2][B] | u_local2reg/n3532_s68/I1 |
9.633 | 0.570 | tINS | RR | 1 | R11C25[2][B] | u_local2reg/n3532_s68/F |
9.805 | 0.172 | tNET | RR | 1 | R12C25[0][A] | u_local2reg/n3532_s67/I0 |
10.176 | 0.371 | tINS | RF | 1 | R12C25[0][A] | u_local2reg/n3532_s67/F |
10.176 | 0.000 | tNET | FF | 1 | R12C25[0][A] | u_local2reg/local_rdat_o_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R12C25[0][A] | u_local2reg/local_rdat_o_8_s0/CLK |
10.208 | -0.035 | tSu | 1 | R12C25[0][A] | u_local2reg/local_rdat_o_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.985, 40.118%; route: 5.716, 57.546%; tC2Q: 0.232, 2.336% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
Slack | 0.033 |
Data Arrival Time | 10.175 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_27_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][B] | u_local2reg/n5057_s2/I2 |
5.305 | 0.517 | tINS | FF | 14 | R13C9[3][B] | u_local2reg/n5057_s2/F |
6.074 | 0.770 | tNET | FF | 1 | R7C7[0][A] | u_local2reg/n5057_s1/I1 |
6.591 | 0.517 | tINS | FF | 22 | R7C7[0][A] | u_local2reg/n5057_s1/F |
8.441 | 1.850 | tNET | FF | 1 | R4C17[0][B] | u_local2reg/n3513_s80/I0 |
8.990 | 0.549 | tINS | FR | 1 | R4C17[0][B] | u_local2reg/n3513_s80/F |
9.163 | 0.172 | tNET | RR | 1 | R4C18[2][B] | u_local2reg/n3513_s70/I0 |
9.625 | 0.462 | tINS | RR | 1 | R4C18[2][B] | u_local2reg/n3513_s70/F |
9.626 | 0.001 | tNET | RR | 1 | R4C18[1][A] | u_local2reg/n3513_s67/I2 |
10.175 | 0.549 | tINS | RR | 1 | R4C18[1][A] | u_local2reg/n3513_s67/F |
10.175 | 0.000 | tNET | RR | 1 | R4C18[1][A] | u_local2reg/local_rdat_o_27_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R4C18[1][A] | u_local2reg/local_rdat_o_27_s0/CLK |
10.208 | -0.035 | tSu | 1 | R4C18[1][A] | u_local2reg/local_rdat_o_27_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.119, 41.473%; route: 5.581, 56.191%; tC2Q: 0.232, 2.336% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
Slack | 0.037 |
Data Arrival Time | 10.171 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_18_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
2.826 | 0.531 | tNET | FF | 1 | R6C29[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_6_s0/I2 |
3.343 | 0.517 | tINS | FF | 3 | R6C29[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_6_s0/F |
4.550 | 1.206 | tNET | FF | 1 | R6C8[2][A] | u_local2reg/n4674_s4/I0 |
5.067 | 0.517 | tINS | FF | 58 | R6C8[2][A] | u_local2reg/n4674_s4/F |
6.057 | 0.990 | tNET | FF | 1 | R13C13[1][B] | u_local2reg/n4929_s1/I0 |
6.574 | 0.517 | tINS | FF | 28 | R13C13[1][B] | u_local2reg/n4929_s1/F |
7.557 | 0.983 | tNET | FF | 1 | R21C8[0][B] | u_local2reg/n3522_s77/I0 |
7.928 | 0.371 | tINS | FF | 1 | R21C8[0][B] | u_local2reg/n3522_s77/F |
8.854 | 0.927 | tNET | FF | 1 | R18C13[1][B] | u_local2reg/n3522_s69/I1 |
9.225 | 0.371 | tINS | FF | 1 | R18C13[1][B] | u_local2reg/n3522_s69/F |
9.622 | 0.397 | tNET | FF | 1 | R20C13[1][A] | u_local2reg/n3522_s67/I1 |
10.171 | 0.549 | tINS | FR | 1 | R20C13[1][A] | u_local2reg/n3522_s67/F |
10.171 | 0.000 | tNET | RR | 1 | R20C13[1][A] | u_local2reg/local_rdat_o_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C13[1][A] | u_local2reg/local_rdat_o_18_s0/CLK |
10.208 | -0.035 | tSu | 1 | R20C13[1][A] | u_local2reg/local_rdat_o_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.850, 38.779%; route: 5.846, 58.884%; tC2Q: 0.232, 2.337% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
Slack | 0.038 |
Data Arrival Time | 10.170 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R5C28[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s/I1 |
3.386 | 0.371 | tINS | FF | 60 | R5C28[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s/F |
5.414 | 2.028 | tNET | FF | 1 | R24C6[3][B] | u_apb2local/w_apb0_rdy_s/I2 |
5.931 | 0.517 | tINS | FF | 2 | R24C6[3][B] | u_apb2local/w_apb0_rdy_s/F |
7.841 | 1.910 | tNET | FF | 1 | R5C25[3][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n47_s3/I1 |
8.212 | 0.371 | tINS | FF | 2 | R5C25[3][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n47_s3/F |
9.006 | 0.795 | tNET | FF | 1 | R6C37[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n47_s2/I0 |
9.377 | 0.371 | tINS | FF | 3 | R6C37[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n47_s2/F |
9.799 | 0.422 | tNET | FF | 1 | R7C35[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_next_1_s5/I1 |
10.170 | 0.371 | tINS | FF | 1 | R7C35[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_next_1_s5/F |
10.170 | 0.000 | tNET | FF | 1 | R7C35[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R7C35[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0/CLK |
10.208 | -0.035 | tSu | 1 | R7C35[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.009, 30.312%; route: 6.686, 67.351%; tC2Q: 0.232, 2.337% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
Slack | 0.042 |
Data Arrival Time | 10.166 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_4_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][B] | u_local2reg/n5057_s2/I2 |
5.305 | 0.517 | tINS | FF | 14 | R13C9[3][B] | u_local2reg/n5057_s2/F |
6.074 | 0.770 | tNET | FF | 1 | R7C7[0][A] | u_local2reg/n5057_s1/I1 |
6.591 | 0.517 | tINS | FF | 22 | R7C7[0][A] | u_local2reg/n5057_s1/F |
8.126 | 1.534 | tNET | FF | 1 | R23C22[2][B] | u_local2reg/n3536_s82/I3 |
8.643 | 0.517 | tINS | FF | 1 | R23C22[2][B] | u_local2reg/n3536_s82/F |
9.133 | 0.490 | tNET | FF | 1 | R21C23[2][A] | u_local2reg/n3536_s70/I2 |
9.703 | 0.570 | tINS | FR | 1 | R21C23[2][A] | u_local2reg/n3536_s70/F |
9.704 | 0.001 | tNET | RR | 1 | R21C23[0][B] | u_local2reg/n3536_s67/I2 |
10.166 | 0.462 | tINS | RR | 1 | R21C23[0][B] | u_local2reg/n3536_s67/F |
10.166 | 0.000 | tNET | RR | 1 | R21C23[0][B] | u_local2reg/local_rdat_o_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R21C23[0][B] | u_local2reg/local_rdat_o_4_s0/CLK |
10.208 | -0.035 | tSu | 1 | R21C23[0][B] | u_local2reg/local_rdat_o_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 4.108, 41.400%; route: 5.583, 56.262%; tC2Q: 0.232, 2.338% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
Slack | 0.052 |
Data Arrival Time | 10.156 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_21_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
2.753 | 0.457 | tNET | FF | 1 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/I2 |
3.270 | 0.517 | tINS | FF | 3 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/F |
4.743 | 1.473 | tNET | FF | 1 | R9C9[0][B] | u_local2reg/n5185_s2/I0 |
5.114 | 0.371 | tINS | FF | 19 | R9C9[0][B] | u_local2reg/n5185_s2/F |
5.824 | 0.710 | tNET | FF | 1 | R13C10[3][B] | u_local2reg/n5217_s1/I1 |
6.341 | 0.517 | tINS | FF | 32 | R13C10[3][B] | u_local2reg/n5217_s1/F |
8.263 | 1.922 | tNET | FF | 1 | R11C17[0][B] | u_local2reg/n3519_s74/I0 |
8.725 | 0.462 | tINS | FR | 1 | R11C17[0][B] | u_local2reg/n3519_s74/F |
8.726 | 0.001 | tNET | RR | 1 | R11C17[2][B] | u_local2reg/n3519_s68/I2 |
9.281 | 0.555 | tINS | RF | 1 | R11C17[2][B] | u_local2reg/n3519_s68/F |
9.694 | 0.413 | tNET | FF | 1 | R9C18[1][A] | u_local2reg/n3519_s67/I0 |
10.156 | 0.462 | tINS | FR | 1 | R9C18[1][A] | u_local2reg/n3519_s67/F |
10.156 | 0.000 | tNET | RR | 1 | R9C18[1][A] | u_local2reg/local_rdat_o_21_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R9C18[1][A] | u_local2reg/local_rdat_o_21_s0/CLK |
10.208 | -0.035 | tSu | 1 | R9C18[1][A] | u_local2reg/local_rdat_o_21_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.892, 39.262%; route: 5.789, 58.398%; tC2Q: 0.232, 2.340% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
Slack | 0.054 |
Data Arrival Time | 10.154 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R5C28[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s/I1 |
3.386 | 0.371 | tINS | FF | 60 | R5C28[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s/F |
5.414 | 2.028 | tNET | FF | 1 | R24C6[3][B] | u_apb2local/w_apb0_rdy_s/I2 |
5.931 | 0.517 | tINS | FF | 2 | R24C6[3][B] | u_apb2local/w_apb0_rdy_s/F |
7.841 | 1.910 | tNET | FF | 1 | R5C25[3][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n47_s3/I1 |
8.212 | 0.371 | tINS | FF | 2 | R5C25[3][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n47_s3/F |
9.006 | 0.795 | tNET | FF | 1 | R6C37[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n47_s2/I0 |
9.377 | 0.371 | tINS | FF | 3 | R6C37[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n47_s2/F |
9.783 | 0.406 | tNET | FF | 1 | R6C35[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n160_s0/I0 |
10.154 | 0.371 | tINS | FF | 1 | R6C35[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/n160_s0/F |
10.154 | 0.000 | tNET | FF | 1 | R6C35[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R6C35[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0/CLK |
10.208 | -0.035 | tSu | 1 | R6C35[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wen_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.009, 30.361%; route: 6.670, 67.298%; tC2Q: 0.232, 2.341% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
Slack | 0.060 |
Data Arrival Time | 10.148 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_26_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
2.753 | 0.457 | tNET | FF | 1 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/I2 |
3.270 | 0.517 | tINS | FF | 3 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/F |
4.743 | 1.473 | tNET | FF | 1 | R9C9[0][B] | u_local2reg/n5185_s2/I0 |
5.114 | 0.371 | tINS | FF | 19 | R9C9[0][B] | u_local2reg/n5185_s2/F |
5.826 | 0.712 | tNET | FF | 1 | R13C8[2][A] | u_local2reg/n5313_s1/I1 |
6.197 | 0.371 | tINS | FF | 33 | R13C8[2][A] | u_local2reg/n5313_s1/F |
8.001 | 1.804 | tNET | FF | 1 | R4C24[0][B] | u_local2reg/n3514_s82/I0 |
8.372 | 0.371 | tINS | FF | 1 | R4C24[0][B] | u_local2reg/n3514_s82/F |
9.028 | 0.656 | tNET | FF | 1 | R4C27[0][B] | u_local2reg/n3514_s70/I2 |
9.577 | 0.549 | tINS | FR | 1 | R4C27[0][B] | u_local2reg/n3514_s70/F |
9.578 | 0.001 | tNET | RR | 1 | R4C27[0][A] | u_local2reg/n3514_s67/I2 |
10.148 | 0.570 | tINS | RR | 1 | R4C27[0][A] | u_local2reg/n3514_s67/F |
10.148 | 0.000 | tNET | RR | 1 | R4C27[0][A] | u_local2reg/local_rdat_o_26_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R4C27[0][A] | u_local2reg/local_rdat_o_26_s0/CLK |
10.208 | -0.035 | tSu | 1 | R4C27[0][A] | u_local2reg/local_rdat_o_26_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.757, 37.930%; route: 5.916, 59.727%; tC2Q: 0.232, 2.342% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
Slack | 0.085 |
Data Arrival Time | 10.123 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_2_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
5.163 | 1.632 | tNET | FF | 1 | R14C10[3][B] | u_local2reg/n5153_s2/I2 |
5.712 | 0.549 | tINS | FR | 2 | R14C10[3][B] | u_local2reg/n5153_s2/F |
5.715 | 0.003 | tNET | RR | 1 | R14C10[3][A] | u_local2reg/n5665_s1/I0 |
6.232 | 0.517 | tINS | RF | 33 | R14C10[3][A] | u_local2reg/n5665_s1/F |
8.522 | 2.290 | tNET | FF | 1 | R12C21[2][B] | u_local2reg/n3538_s92/I0 |
8.893 | 0.371 | tINS | FF | 1 | R12C21[2][B] | u_local2reg/n3538_s92/F |
8.897 | 0.004 | tNET | FF | 1 | R12C21[3][A] | u_local2reg/n3538_s70/I2 |
9.414 | 0.517 | tINS | FF | 1 | R12C21[3][A] | u_local2reg/n3538_s70/F |
9.661 | 0.247 | tNET | FF | 1 | R12C23[0][A] | u_local2reg/n3538_s67/I2 |
10.123 | 0.462 | tINS | FR | 1 | R12C23[0][A] | u_local2reg/n3538_s67/F |
10.123 | 0.000 | tNET | RR | 1 | R12C23[0][A] | u_local2reg/local_rdat_o_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R12C23[0][A] | u_local2reg/local_rdat_o_2_s0/CLK |
10.208 | -0.035 | tSu | 1 | R12C23[0][A] | u_local2reg/local_rdat_o_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.941, 39.889%; route: 5.707, 57.763%; tC2Q: 0.232, 2.348% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
Slack | 0.106 |
Data Arrival Time | 10.102 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_16_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R7C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_5_s0/I2 |
3.386 | 0.371 | tINS | FF | 17 | R7C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_5_s0/F |
4.897 | 1.511 | tNET | FF | 1 | R13C9[1][B] | u_local2reg/n4769_s2/I1 |
5.350 | 0.453 | tINS | FF | 9 | R13C9[1][B] | u_local2reg/n4769_s2/F |
7.638 | 2.288 | tNET | FF | 1 | R12C20[3][A] | u_local2reg/n3524_s91/I2 |
8.155 | 0.517 | tINS | FF | 1 | R12C20[3][A] | u_local2reg/n3524_s91/F |
8.811 | 0.656 | tNET | FF | 1 | R11C22[3][A] | u_local2reg/n3524_s70/I0 |
9.381 | 0.570 | tINS | FR | 1 | R11C22[3][A] | u_local2reg/n3524_s70/F |
9.553 | 0.172 | tNET | RR | 1 | R11C23[0][A] | u_local2reg/n3524_s67/I2 |
10.102 | 0.549 | tINS | RR | 1 | R11C23[0][A] | u_local2reg/n3524_s67/F |
10.102 | 0.000 | tNET | RR | 1 | R11C23[0][A] | u_local2reg/local_rdat_o_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R11C23[0][A] | u_local2reg/local_rdat_o_16_s0/CLK |
10.208 | -0.035 | tSu | 1 | R11C23[0][A] | u_local2reg/local_rdat_o_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.468, 35.176%; route: 6.159, 62.471%; tC2Q: 0.232, 2.353% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
Slack | 0.115 |
Data Arrival Time | 10.093 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_10_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][B] | u_local2reg/n5057_s2/I2 |
5.305 | 0.517 | tINS | FF | 14 | R13C9[3][B] | u_local2reg/n5057_s2/F |
6.074 | 0.770 | tNET | FF | 1 | R7C7[0][A] | u_local2reg/n5057_s1/I1 |
6.591 | 0.517 | tINS | FF | 22 | R7C7[0][A] | u_local2reg/n5057_s1/F |
8.547 | 1.955 | tNET | FF | 1 | R18C27[1][B] | u_local2reg/n3530_s75/I3 |
8.918 | 0.371 | tINS | FF | 1 | R18C27[1][B] | u_local2reg/n3530_s75/F |
9.088 | 0.170 | tNET | FF | 1 | R17C27[3][A] | u_local2reg/n3530_s68/I3 |
9.550 | 0.462 | tINS | FR | 1 | R17C27[3][A] | u_local2reg/n3530_s68/F |
9.722 | 0.172 | tNET | RR | 1 | R16C27[0][A] | u_local2reg/n3530_s67/I0 |
10.093 | 0.371 | tINS | RF | 1 | R16C27[0][A] | u_local2reg/n3530_s67/F |
10.093 | 0.000 | tNET | FF | 1 | R16C27[0][A] | u_local2reg/local_rdat_o_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C27[0][A] | u_local2reg/local_rdat_o_10_s0/CLK |
10.208 | -0.035 | tSu | 1 | R16C27[0][A] | u_local2reg/local_rdat_o_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.763, 38.203%; route: 5.855, 59.442%; tC2Q: 0.232, 2.355% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
Slack | 0.123 |
Data Arrival Time | 10.085 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_15_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][A] | u_local2reg/n4674_s3/I2 |
5.305 | 0.517 | tINS | FF | 13 | R13C9[3][A] | u_local2reg/n4674_s3/F |
5.974 | 0.669 | tNET | FF | 1 | R9C8[3][B] | u_local2reg/n5185_s1/I0 |
6.345 | 0.371 | tINS | FF | 33 | R9C8[3][B] | u_local2reg/n5185_s1/F |
8.318 | 1.973 | tNET | FF | 1 | R21C14[2][B] | u_local2reg/n3525_s87/I3 |
8.689 | 0.371 | tINS | FF | 1 | R21C14[2][B] | u_local2reg/n3525_s87/F |
8.693 | 0.004 | tNET | FF | 1 | R21C14[3][A] | u_local2reg/n3525_s71/I3 |
9.210 | 0.517 | tINS | FF | 1 | R21C14[3][A] | u_local2reg/n3525_s71/F |
9.623 | 0.413 | tNET | FF | 1 | R22C12[0][A] | u_local2reg/n3525_s67/I3 |
10.085 | 0.462 | tINS | FR | 1 | R22C12[0][A] | u_local2reg/n3525_s67/F |
10.085 | 0.000 | tNET | RR | 1 | R22C12[0][A] | u_local2reg/local_rdat_o_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R22C12[0][A] | u_local2reg/local_rdat_o_15_s0/CLK |
10.208 | -0.035 | tSu | 1 | R22C12[0][A] | u_local2reg/local_rdat_o_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.763, 38.235%; route: 5.847, 59.408%; tC2Q: 0.232, 2.357% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
Slack | 0.132 |
Data Arrival Time | 10.076 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_1_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][A] | u_local2reg/n4674_s3/I2 |
5.305 | 0.517 | tINS | FF | 13 | R13C9[3][A] | u_local2reg/n4674_s3/F |
5.974 | 0.669 | tNET | FF | 1 | R9C8[3][B] | u_local2reg/n5185_s1/I0 |
6.345 | 0.371 | tINS | FF | 33 | R9C8[3][B] | u_local2reg/n5185_s1/F |
8.001 | 1.656 | tNET | FF | 1 | R13C15[3][B] | u_local2reg/n3539_s78/I3 |
8.550 | 0.549 | tINS | FR | 1 | R13C15[3][B] | u_local2reg/n3539_s78/F |
8.722 | 0.172 | tNET | RR | 1 | R13C16[3][A] | u_local2reg/n3539_s69/I2 |
9.093 | 0.371 | tINS | RF | 1 | R13C16[3][A] | u_local2reg/n3539_s69/F |
9.506 | 0.413 | tNET | FF | 1 | R14C15[2][A] | u_local2reg/n3539_s67/I1 |
10.076 | 0.570 | tINS | FR | 1 | R14C15[2][A] | u_local2reg/n3539_s67/F |
10.076 | 0.000 | tNET | RR | 1 | R14C15[2][A] | u_local2reg/local_rdat_o_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R14C15[2][A] | u_local2reg/local_rdat_o_1_s0/CLK |
10.208 | -0.035 | tSu | 1 | R14C15[2][A] | u_local2reg/local_rdat_o_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.903, 39.692%; route: 5.698, 57.948%; tC2Q: 0.232, 2.359% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
Slack | 0.138 |
Data Arrival Time | 10.070 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_22_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][A] | u_local2reg/n4674_s3/I2 |
5.305 | 0.517 | tINS | FF | 13 | R13C9[3][A] | u_local2reg/n4674_s3/F |
5.974 | 0.669 | tNET | FF | 1 | R9C8[3][B] | u_local2reg/n5185_s1/I0 |
6.345 | 0.371 | tINS | FF | 33 | R9C8[3][B] | u_local2reg/n5185_s1/F |
7.589 | 1.244 | tNET | FF | 1 | R16C12[1][B] | u_local2reg/n3518_s85/I0 |
8.144 | 0.555 | tINS | FF | 1 | R16C12[1][B] | u_local2reg/n3518_s85/F |
8.634 | 0.490 | tNET | FF | 1 | R16C14[3][B] | u_local2reg/n3518_s71/I1 |
9.087 | 0.453 | tINS | FF | 1 | R16C14[3][B] | u_local2reg/n3518_s71/F |
9.500 | 0.413 | tNET | FF | 1 | R16C16[0][A] | u_local2reg/n3518_s67/I3 |
10.070 | 0.570 | tINS | FR | 1 | R16C16[0][A] | u_local2reg/n3518_s67/F |
10.070 | 0.000 | tNET | RR | 1 | R16C16[0][A] | u_local2reg/local_rdat_o_22_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C16[0][A] | u_local2reg/local_rdat_o_22_s0/CLK |
10.208 | -0.035 | tSu | 1 | R16C16[0][A] | u_local2reg/local_rdat_o_22_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.991, 40.612%; route: 5.604, 57.027%; tC2Q: 0.232, 2.361% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
Slack | 0.138 |
Data Arrival Time | 10.070 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/reg0x000B_10_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
2.826 | 0.531 | tNET | FF | 1 | R6C29[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_6_s0/I2 |
3.343 | 0.517 | tINS | FF | 3 | R6C29[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_6_s0/F |
4.550 | 1.206 | tNET | FF | 1 | R6C8[2][A] | u_local2reg/n4674_s4/I0 |
5.067 | 0.517 | tINS | FF | 58 | R6C8[2][A] | u_local2reg/n4674_s4/F |
6.000 | 0.934 | tNET | FF | 1 | R9C11[2][B] | u_local2reg/n5025_s1/I0 |
6.517 | 0.517 | tINS | FF | 32 | R9C11[2][B] | u_local2reg/n5025_s1/F |
7.491 | 0.974 | tNET | FF | 1 | R15C7[3][B] | u_local2reg/n5025_s3/I3 |
7.953 | 0.462 | tINS | FR | 32 | R15C7[3][B] | u_local2reg/n5025_s3/F |
10.070 | 2.117 | tNET | RR | 1 | R17C28[2][A] | u_local2reg/reg0x000B_10_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R17C28[2][A] | u_local2reg/reg0x000B_10_s0/CLK |
10.208 | -0.035 | tSu | 1 | R17C28[2][A] | u_local2reg/reg0x000B_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.021, 30.742%; route: 6.574, 66.897%; tC2Q: 0.232, 2.361% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
Slack | 0.139 |
Data Arrival Time | 10.069 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_25_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
2.753 | 0.457 | tNET | FF | 1 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/I2 |
3.270 | 0.517 | tINS | FF | 3 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/F |
4.743 | 1.473 | tNET | FF | 1 | R9C9[0][B] | u_local2reg/n5185_s2/I0 |
5.114 | 0.371 | tINS | FF | 19 | R9C9[0][B] | u_local2reg/n5185_s2/F |
5.826 | 0.712 | tNET | FF | 1 | R13C8[2][A] | u_local2reg/n5313_s1/I1 |
6.197 | 0.371 | tINS | FF | 33 | R13C8[2][A] | u_local2reg/n5313_s1/F |
7.913 | 1.715 | tNET | FF | 1 | R6C18[3][A] | u_local2reg/n3515_s86/I3 |
8.468 | 0.555 | tINS | FF | 1 | R6C18[3][A] | u_local2reg/n3515_s86/F |
8.865 | 0.397 | tNET | FF | 1 | R6C19[3][A] | u_local2reg/n3515_s71/I2 |
9.435 | 0.570 | tINS | FR | 1 | R6C19[3][A] | u_local2reg/n3515_s71/F |
9.607 | 0.172 | tNET | RR | 1 | R7C19[2][A] | u_local2reg/n3515_s67/I3 |
10.069 | 0.462 | tINS | RR | 1 | R7C19[2][A] | u_local2reg/n3515_s67/F |
10.069 | 0.000 | tNET | RR | 1 | R7C19[2][A] | u_local2reg/local_rdat_o_25_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R7C19[2][A] | u_local2reg/local_rdat_o_25_s0/CLK |
10.208 | -0.035 | tSu | 1 | R7C19[2][A] | u_local2reg/local_rdat_o_25_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.854, 39.224%; route: 5.740, 58.415%; tC2Q: 0.232, 2.361% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
Slack | 0.140 |
Data Arrival Time | 10.069 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_12_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R7C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_5_s0/I2 |
3.386 | 0.371 | tINS | FF | 17 | R7C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_5_s0/F |
4.997 | 1.612 | tNET | FF | 1 | R14C8[3][A] | u_local2reg/n4993_s2/I3 |
5.514 | 0.517 | tINS | FF | 12 | R14C8[3][A] | u_local2reg/n4993_s2/F |
8.216 | 2.701 | tNET | FF | 1 | R7C11[3][B] | u_local2reg/n3528_s90/I2 |
8.786 | 0.570 | tINS | FR | 1 | R7C11[3][B] | u_local2reg/n3528_s90/F |
8.930 | 0.144 | tNET | RR | 1 | R7C11[3][A] | u_local2reg/n3528_s71/I2 |
9.301 | 0.371 | tINS | RF | 1 | R7C11[3][A] | u_local2reg/n3528_s71/F |
9.698 | 0.397 | tNET | FF | 1 | R7C12[0][A] | u_local2reg/n3528_s67/I3 |
10.069 | 0.371 | tINS | FF | 1 | R7C12[0][A] | u_local2reg/n3528_s67/F |
10.069 | 0.000 | tNET | FF | 1 | R7C12[0][A] | u_local2reg/local_rdat_o_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R7C12[0][A] | u_local2reg/local_rdat_o_12_s0/CLK |
10.208 | -0.035 | tSu | 1 | R7C12[0][A] | u_local2reg/local_rdat_o_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.208, 32.650%; route: 6.385, 64.989%; tC2Q: 0.232, 2.361% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
Slack | 0.146 |
Data Arrival Time | 10.062 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_19_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
3.015 | 0.719 | tNET | FF | 1 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/I2 |
3.532 | 0.517 | tINS | FF | 17 | R8C24[1][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_4_s0/F |
4.788 | 1.256 | tNET | FF | 1 | R13C9[3][A] | u_local2reg/n4674_s3/I2 |
5.305 | 0.517 | tINS | FF | 13 | R13C9[3][A] | u_local2reg/n4674_s3/F |
6.245 | 0.940 | tNET | FF | 1 | R7C12[3][B] | u_local2reg/n4674_s1/I0 |
6.762 | 0.517 | tINS | FF | 22 | R7C12[3][B] | u_local2reg/n4674_s1/F |
8.239 | 1.477 | tNET | FF | 1 | R21C10[1][B] | u_local2reg/n3521_s85/I0 |
8.610 | 0.371 | tINS | FF | 1 | R21C10[1][B] | u_local2reg/n3521_s85/F |
8.857 | 0.247 | tNET | FF | 1 | R21C12[0][A] | u_local2reg/n3521_s71/I1 |
9.427 | 0.570 | tINS | FR | 1 | R21C12[0][A] | u_local2reg/n3521_s71/F |
9.600 | 0.172 | tNET | RR | 1 | R20C12[1][A] | u_local2reg/n3521_s67/I3 |
10.062 | 0.462 | tINS | RR | 1 | R20C12[1][A] | u_local2reg/n3521_s67/F |
10.062 | 0.000 | tNET | RR | 1 | R20C12[1][A] | u_local2reg/local_rdat_o_19_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C12[1][A] | u_local2reg/local_rdat_o_19_s0/CLK |
10.208 | -0.035 | tSu | 1 | R20C12[1][A] | u_local2reg/local_rdat_o_19_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.962, 40.352%; route: 5.625, 57.285%; tC2Q: 0.232, 2.363% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
Slack | 0.166 |
Data Arrival Time | 10.042 |
Data Required Time | 10.208 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
To | u_local2reg/local_rdat_o_14_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 2 | R8C30[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
0.891 | 0.415 | tNET | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/I3 |
1.344 | 0.453 | tINS | FF | 1 | R8C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s3/F |
1.741 | 0.397 | tNET | FF | 1 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/I2 |
2.296 | 0.555 | tINS | FF | 60 | R6C33[3][A] | u_Uart_to_Bus_Top/uart_bus_core/apb0_sel_o_d_s0/F |
2.753 | 0.457 | tNET | FF | 1 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/I2 |
3.270 | 0.517 | tINS | FF | 3 | R6C30[3][B] | u_Uart_to_Bus_Top/uart_bus_core/apb0_addr_o_d_7_s0/F |
4.743 | 1.473 | tNET | FF | 1 | R9C9[0][B] | u_local2reg/n5185_s2/I0 |
5.114 | 0.371 | tINS | FF | 19 | R9C9[0][B] | u_local2reg/n5185_s2/F |
6.075 | 0.961 | tNET | FF | 1 | R13C13[0][B] | u_local2reg/n5633_s1/I1 |
6.446 | 0.371 | tINS | FF | 32 | R13C13[0][B] | u_local2reg/n5633_s1/F |
8.332 | 1.886 | tNET | FF | 1 | R21C12[3][B] | u_local2reg/n3526_s76/I3 |
8.703 | 0.371 | tINS | FF | 1 | R21C12[3][B] | u_local2reg/n3526_s76/F |
8.950 | 0.247 | tNET | FF | 1 | R21C14[0][B] | u_local2reg/n3526_s69/I0 |
9.499 | 0.549 | tINS | FR | 1 | R21C14[0][B] | u_local2reg/n3526_s69/F |
9.671 | 0.172 | tNET | RR | 1 | R22C14[2][A] | u_local2reg/n3526_s67/I1 |
10.042 | 0.371 | tINS | RF | 1 | R22C14[2][A] | u_local2reg/n3526_s67/F |
10.042 | 0.000 | tNET | FF | 1 | R22C14[2][A] | u_local2reg/local_rdat_o_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R22C14[2][A] | u_local2reg/local_rdat_o_14_s0/CLK |
10.208 | -0.035 | tSu | 1 | R22C14[2][A] | u_local2reg/local_rdat_o_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 3.558, 36.309%; route: 6.009, 61.323%; tC2Q: 0.232, 2.368% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.317 |
Data Arrival Time | 0.512 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/r1_cfg_wren_s0 |
To | u_i2c_master_cfgport/cfg_wdat_rdy_o_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R4C6[0][B] | u_i2c_master_cfgport/r1_cfg_wren_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R4C6[0][B] | u_i2c_master_cfgport/r1_cfg_wren_s0/Q |
0.512 | 0.126 | tNET | RR | 1 | R4C4[1][A] | u_i2c_master_cfgport/cfg_wdat_rdy_o_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R4C4[1][A] | u_i2c_master_cfgport/cfg_wdat_rdy_o_s0/CLK |
0.195 | 0.011 | tHld | 1 | R4C4[1][A] | u_i2c_master_cfgport/cfg_wdat_rdy_o_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 38.456%; tC2Q: 0.202, 61.544% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
Slack | 0.327 |
Data Arrival Time | 0.522 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_28_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C45[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 48 | R20C45[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/Q |
0.522 | 0.136 | tNET | RR | 1 | R20C45[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_28_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C45[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_28_s0/CLK |
0.195 | 0.011 | tHld | 1 | R20C45[2][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_28_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.206%; tC2Q: 0.202, 59.794% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
Slack | 0.327 |
Data Arrival Time | 0.522 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_24_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C45[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 48 | R20C45[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/Q |
0.522 | 0.136 | tNET | RR | 1 | R20C45[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_24_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C45[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_24_s0/CLK |
0.195 | 0.011 | tHld | 1 | R20C45[2][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.206%; tC2Q: 0.202, 59.794% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
Slack | 0.327 |
Data Arrival Time | 0.522 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_4_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C45[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 48 | R20C45[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/Q |
0.522 | 0.136 | tNET | RR | 1 | R20C45[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C45[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_4_s0/CLK |
0.195 | 0.011 | tHld | 1 | R20C45[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.206%; tC2Q: 0.202, 59.794% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
Slack | 0.327 |
Data Arrival Time | 0.522 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_0_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C45[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 48 | R20C45[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_ren_1dly_s0/Q |
0.522 | 0.136 | tNET | RR | 1 | R20C45[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C45[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R20C45[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.206%; tC2Q: 0.202, 59.794% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/Q |
0.389 | 0.002 | tNET | RR | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n231_s5/I1 |
0.621 | 0.232 | tINS | RF | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n231_s5/F |
0.621 | 0.000 | tNET | FF | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/CLK |
0.195 | 0.011 | tHld | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_8_s1 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_8_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_8_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R21C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_8_s1/Q |
0.389 | 0.002 | tNET | RR | 1 | R21C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n38_s0/I2 |
0.621 | 0.232 | tINS | RF | 1 | R21C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n38_s0/F |
0.621 | 0.000 | tNET | FF | 1 | R21C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_8_s1/CLK |
0.195 | 0.011 | tHld | 1 | R21C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_12_s1 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_12_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_12_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R21C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_12_s1/Q |
0.389 | 0.002 | tNET | RR | 1 | R21C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n34_s0/I2 |
0.621 | 0.232 | tINS | RF | 1 | R21C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n34_s0/F |
0.621 | 0.000 | tNET | FF | 1 | R21C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_12_s1/CLK |
0.195 | 0.011 | tHld | 1 | R21C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_14_s1 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_14_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_14_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R22C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_14_s1/Q |
0.389 | 0.002 | tNET | RR | 1 | R22C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n32_s0/I2 |
0.621 | 0.232 | tINS | RF | 1 | R22C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n32_s0/F |
0.621 | 0.000 | tNET | FF | 1 | R22C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_14_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_14_s1/CLK |
0.195 | 0.011 | tHld | 1 | R22C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_14_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_15_s1 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_15_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_15_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R22C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_15_s1/Q |
0.389 | 0.002 | tNET | RR | 1 | R22C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n31_s0/I3 |
0.621 | 0.232 | tINS | RF | 1 | R22C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/n31_s0/F |
0.621 | 0.000 | tNET | FF | 1 | R22C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_15_s1/CLK |
0.195 | 0.011 | tHld | 1 | R22C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_2_s1 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_2_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R9C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_2_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R9C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_2_s1/Q |
0.389 | 0.002 | tNET | RR | 1 | R9C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/n50_s1/I3 |
0.621 | 0.232 | tINS | RF | 1 | R9C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/n50_s1/F |
0.621 | 0.000 | tNET | FF | 1 | R9C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R9C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_2_s1/CLK |
0.195 | 0.011 | tHld | 1 | R9C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/CORE_CMD_2_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/CORE_CMD_2_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/CORE_CMD_2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R11C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/CORE_CMD_2_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R11C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/n200_s2/I0 |
0.621 | 0.232 | tINS | RF | 1 | R11C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/n200_s2/F |
0.621 | 0.000 | tNET | FF | 1 | R11C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/CORE_CMD_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/CORE_CMD_2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R11C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/CORE_CMD_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/irq_flag_s4 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/irq_flag_s4 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R7C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/irq_flag_s4/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R7C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/irq_flag_s4/Q |
0.389 | 0.002 | tNET | RR | 1 | R7C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/n220_s5/I0 |
0.621 | 0.232 | tINS | RF | 1 | R7C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/n220_s5/F |
0.621 | 0.000 | tNET | FF | 1 | R7C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/irq_flag_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R7C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/irq_flag_s4/CLK |
0.195 | 0.011 | tHld | 1 | R7C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/irq_flag_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_7_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_7_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_7_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_7_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/n169_s2/I3 |
0.621 | 0.232 | tINS | RF | 1 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/n169_s2/F |
0.621 | 0.000 | tNET | FF | 1 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_7_s0/CLK |
0.195 | 0.011 | tHld | 1 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_9_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_9_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R16C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_9_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 3 | R16C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_9_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R16C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/n167_s2/I3 |
0.621 | 0.232 | tINS | RF | 1 | R16C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/n167_s2/F |
0.621 | 0.000 | tNET | FF | 1 | R16C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R16C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_9_s0/CLK |
0.195 | 0.011 | tHld | 1 | R16C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/divclk_cnt_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R22C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R22C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/n102_s2/I2 |
0.621 | 0.232 | tINS | RF | 1 | R22C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/n102_s2/F |
0.621 | 0.000 | tNET | FF | 1 | R22C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0/CLK |
0.195 | 0.011 | tHld | 1 | R22C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_3_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_3_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R12C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_3_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 4 | R12C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_3_s0/Q |
0.389 | 0.002 | tNET | RR | 1 | R12C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/n135_s0/I3 |
0.621 | 0.232 | tINS | RF | 1 | R12C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/n135_s0/F |
0.621 | 0.000 | tNET | FF | 1 | R12C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R12C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R12C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr1_ptr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C42[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R22C42[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/Q |
0.389 | 0.002 | tNET | RR | 1 | R22C42[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/I1 |
0.621 | 0.232 | tINS | RF | 1 | R22C42[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/F |
0.621 | 0.000 | tNET | FF | 1 | R22C42[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C42[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/CLK |
0.195 | 0.011 | tHld | 1 | R22C42[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_3_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_3_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C52[1][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_3_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R11C52[1][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_3_s0/Q |
0.389 | 0.002 | tNET | RR | 2 | R11C52[1][A] | u_Uart_to_Bus_Top/uart_bus_core/n1756_s/I1 |
0.621 | 0.232 | tINS | RF | 1 | R11C52[1][A] | u_Uart_to_Bus_Top/uart_bus_core/n1756_s/SUM |
0.621 | 0.000 | tNET | FF | 1 | R11C52[1][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C52[1][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R11C52[1][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C53[0][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R11C53[0][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0/Q |
0.389 | 0.002 | tNET | RR | 2 | R11C53[0][A] | u_Uart_to_Bus_Top/uart_bus_core/n1752_s/I1 |
0.621 | 0.232 | tINS | RF | 1 | R11C53[0][A] | u_Uart_to_Bus_Top/uart_bus_core/n1752_s/SUM |
0.621 | 0.000 | tNET | FF | 1 | R11C53[0][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C53[0][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0/CLK |
0.195 | 0.011 | tHld | 1 | R11C53[0][A] | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
Slack | 0.425 |
Data Arrival Time | 0.621 |
Data Required Time | 0.195 |
From | r_clk100_cnt_2_s0 |
To | r_clk100_cnt_2_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[1][A] | r_clk100_cnt_2_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 2 | R11C6[1][A] | r_clk100_cnt_2_s0/Q |
0.389 | 0.002 | tNET | RR | 2 | R11C6[1][A] | n16_s/I1 |
0.621 | 0.232 | tINS | RF | 1 | R11C6[1][A] | n16_s/SUM |
0.621 | 0.000 | tNET | FF | 1 | R11C6[1][A] | r_clk100_cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[1][A] | r_clk100_cnt_2_s0/CLK |
0.195 | 0.011 | tHld | 1 | R11C6[1][A] | r_clk100_cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
Slack | 0.427 |
Data Arrival Time | 0.622 |
Data Required Time | 0.195 |
From | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_0_s3 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_0_s3 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R8C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_0_s3/CLK |
0.386 | 0.202 | tC2Q | RR | 4 | R8C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_0_s3/Q |
0.390 | 0.004 | tNET | RR | 1 | R8C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/n52_s3/I1 |
0.622 | 0.232 | tINS | RF | 1 | R8C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/n52_s3/F |
0.622 | 0.000 | tNET | FF | 1 | R8C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R8C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_0_s3/CLK |
0.195 | 0.011 | tHld | 1 | R8C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/dcnt_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
Slack | 0.427 |
Data Arrival Time | 0.622 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/CLK |
0.386 | 0.202 | tC2Q | RR | 6 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/Q |
0.390 | 0.004 | tNET | RR | 1 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/n103_s5/I2 |
0.622 | 0.232 | tINS | RF | 1 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/n103_s5/F |
0.622 | 0.000 | tNET | FF | 1 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/CLK |
0.195 | 0.011 | tHld | 1 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
Slack | 0.427 |
Data Arrival Time | 0.622 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr2_ptr_0_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr2_ptr_0_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C44[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr2_ptr_0_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 5 | R11C44[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr2_ptr_0_s0/Q |
0.390 | 0.004 | tNET | RR | 1 | R11C44[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/n155_s2/I0 |
0.622 | 0.232 | tINS | RF | 1 | R11C44[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/n155_s2/F |
0.622 | 0.000 | tNET | FF | 1 | R11C44[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr2_ptr_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C44[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr2_ptr_0_s0/CLK |
0.195 | 0.011 | tHld | 1 | R11C44[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wr2_ptr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
Slack | 0.427 |
Data Arrival Time | 0.622 |
Data Required Time | 0.195 |
From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr2_ptr_3_s0 |
To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr2_ptr_3_s0 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C31[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr2_ptr_3_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 4 | R13C31[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr2_ptr_3_s0/Q |
0.390 | 0.004 | tNET | RR | 1 | R13C31[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/n152_s0/I3 |
0.622 | 0.232 | tINS | RF | 1 | R13C31[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/n152_s0/F |
0.622 | 0.000 | tNET | FF | 1 | R13C31[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr2_ptr_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R13C31[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr2_ptr_3_s0/CLK |
0.195 | 0.011 | tHld | 1 | R13C31[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr2_ptr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/CLK |
10.208 | -0.035 | tSu | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path2
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R23C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R23C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4/CLK |
10.208 | -0.035 | tSu | 1 | R23C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R17C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R17C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1/CLK |
10.208 | -0.035 | tSu | 1 | R17C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R18C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R18C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1/CLK |
10.208 | -0.035 | tSu | 1 | R18C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R17C5[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R17C5[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1/CLK |
10.208 | -0.035 | tSu | 1 | R17C5[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R20C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1/CLK |
10.208 | -0.035 | tSu | 1 | R20C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R18C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R18C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1/CLK |
10.208 | -0.035 | tSu | 1 | R18C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R16C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1/CLK |
10.208 | -0.035 | tSu | 1 | R16C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R17C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R17C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1/CLK |
10.208 | -0.035 | tSu | 1 | R17C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R17C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R17C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1/CLK |
10.208 | -0.035 | tSu | 1 | R17C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R20C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1/CLK |
10.208 | -0.035 | tSu | 1 | R20C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R20C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1/CLK |
10.208 | -0.035 | tSu | 1 | R20C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R20C6[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C6[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1/CLK |
10.208 | -0.035 | tSu | 1 | R20C6[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R16C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1/CLK |
10.208 | -0.035 | tSu | 1 | R16C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R17C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R17C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1/CLK |
10.208 | -0.035 | tSu | 1 | R17C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R17C5[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R17C5[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1/CLK |
10.208 | -0.035 | tSu | 1 | R17C5[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R20C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1/CLK |
10.208 | -0.035 | tSu | 1 | R20C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R16C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R16C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1/CLK |
10.208 | -0.035 | tSu | 1 | R16C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R18C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R18C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1/CLK |
10.208 | -0.035 | tSu | 1 | R18C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R20C6[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C6[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1/CLK |
10.208 | -0.035 | tSu | 1 | R20C6[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R20C6[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R20C6[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1/CLK |
10.208 | -0.035 | tSu | 1 | R20C6[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R22C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R22C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1/CLK |
10.208 | -0.035 | tSu | 1 | R22C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R21C4[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R21C4[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1/CLK |
10.208 | -0.035 | tSu | 1 | R21C4[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R21C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R21C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1/CLK |
10.208 | -0.035 | tSu | 1 | R21C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
Slack | 7.836 |
Data Arrival Time | 2.373 |
Data Required Time | 10.208 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.243 | 0.243 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.475 | 0.232 | tC2Q | RF | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
2.373 | 1.897 | tNET | FF | 1 | R21C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | w_clk100m | ||||
10.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.243 | 0.243 | tNET | RR | 1 | R21C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1/CLK |
10.208 | -0.035 | tSu | 1 | R21C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3/CLK |
0.195 | 0.011 | tHld | 1 | R18C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/sda_chk_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R23C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R23C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4/CLK |
0.195 | 0.011 | tHld | 1 | R23C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/BUSY_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R17C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1/CLK |
0.195 | 0.011 | tHld | 1 | R17C4[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SDA_OEN_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R18C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1/CLK |
0.195 | 0.011 | tHld | 1 | R18C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/SCL_OEN_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R17C5[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C5[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1/CLK |
0.195 | 0.011 | tHld | 1 | R17C5[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R20C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1/CLK |
0.195 | 0.011 | tHld | 1 | R20C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R18C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1/CLK |
0.195 | 0.011 | tHld | 1 | R18C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R16C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R16C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1/CLK |
0.195 | 0.011 | tHld | 1 | R16C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R17C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1/CLK |
0.195 | 0.011 | tHld | 1 | R17C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R17C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1/CLK |
0.195 | 0.011 | tHld | 1 | R17C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R20C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1/CLK |
0.195 | 0.011 | tHld | 1 | R20C5[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R20C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1/CLK |
0.195 | 0.011 | tHld | 1 | R20C5[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R20C6[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C6[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1/CLK |
0.195 | 0.011 | tHld | 1 | R20C6[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R16C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R16C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1/CLK |
0.195 | 0.011 | tHld | 1 | R16C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R17C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1/CLK |
0.195 | 0.011 | tHld | 1 | R17C5[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R17C5[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R17C5[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1/CLK |
0.195 | 0.011 | tHld | 1 | R17C5[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R20C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1/CLK |
0.195 | 0.011 | tHld | 1 | R20C6[0][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R16C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R16C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1/CLK |
0.195 | 0.011 | tHld | 1 | R16C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R18C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R18C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1/CLK |
0.195 | 0.011 | tHld | 1 | R18C4[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_14_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R20C6[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C6[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1/CLK |
0.195 | 0.011 | tHld | 1 | R20C6[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R20C6[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R20C6[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1/CLK |
0.195 | 0.011 | tHld | 1 | R20C6[1][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/c_state_16_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R22C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R22C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1/CLK |
0.195 | 0.011 | tHld | 1 | R22C6[0][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R21C4[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C4[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1/CLK |
0.195 | 0.011 | tHld | 1 | R21C4[1][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R21C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1/CLK |
0.195 | 0.011 | tHld | 1 | R21C4[2][B] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
Slack | 1.372 |
Data Arrival Time | 1.568 |
Data Required Time | 0.195 |
From | r_clk100_cnt_5_s0 |
To | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1 |
Launch Clk | w_clk100m:[R] |
Latch Clk | w_clk100m:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R11C6[2][B] | r_clk100_cnt_5_s0/CLK |
0.386 | 0.202 | tC2Q | RR | 571 | R11C6[2][B] | r_clk100_cnt_5_s0/Q |
1.568 | 1.181 | tNET | RR | 1 | R21C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | w_clk100m | ||||
0.000 | 0.000 | tCL | RR | 2634 | PLL_R[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
0.184 | 0.184 | tNET | RR | 1 | R21C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1/CLK |
0.195 | 0.011 | tHld | 1 | R21C4[2][A] | u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.181, 85.399%; tC2Q: 0.202, 14.601% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | r_clk100_cnt_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | r_clk100_cnt_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | r_clk100_cnt_4_s0/CLK |
MPW2
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | r_clk100_cnt_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | r_clk100_cnt_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | r_clk100_cnt_2_s0/CLK |
MPW3
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | u_Uart_to_Bus_Top/uart_bus_core/r_timeout_cnt_7_s0/CLK |
MPW4
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | u_Uart_to_Bus_Top/uart_bus_core/u1.apb0_ena_r_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | u_Uart_to_Bus_Top/uart_bus_core/u1.apb0_ena_r_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | u_Uart_to_Bus_Top/uart_bus_core/u1.apb0_ena_r_s0/CLK |
MPW5
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_40_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_40_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_40_s0/CLK |
MPW6
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_8_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_8_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_8_s1/CLK |
MPW7
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr1_ptr_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr1_ptr_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/wr1_ptr_1_s0/CLK |
MPW8
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ram_rdata_15_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ram_rdata_15_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ram_rdata_15_s0/CLK |
MPW9
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ram_ram_RAMREG_4_G[43]_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ram_ram_RAMREG_4_G[43]_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ram_ram_RAMREG_4_G[43]_s0/CLK |
MPW10
MPW Summary:
Slack: | 3.923 |
Actual Width: | 4.923 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | w_clk100m |
Objects: | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_RAMREG_2_G[7]_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | w_clk100m | ||
5.000 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
5.261 | 0.261 | tNET | FF | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_RAMREG_2_G[7]_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | w_clk100m | ||
10.000 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
10.184 | 0.184 | tNET | RR | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ram_ram_RAMREG_2_G[7]_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
2634 | w_clk100m | 0.001 | 0.261 |
571 | r_clk100_cnt[5] | 5.980 | 2.146 |
196 | rd_ptr[2] | 5.836 | 2.363 |
192 | rd_ptr[2] | 5.922 | 2.063 |
98 | rd_ptr[1] | 6.748 | 1.657 |
96 | rd_ptr[1] | 6.130 | 2.162 |
91 | cpu_addr_Z[8] | 0.933 | 1.612 |
72 | n465_5 | 2.632 | 1.352 |
60 | w_apb0_sel | 0.038 | 3.178 |
60 | apb0_sel_o_d_4 | 0.001 | 1.617 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R21C11 | 88.89% |
R9C26 | 87.50% |
R11C43 | 87.50% |
R12C20 | 87.50% |
R16C25 | 86.11% |
R9C25 | 84.72% |
R12C24 | 84.72% |
R22C24 | 84.72% |
R21C25 | 83.33% |
R21C27 | 83.33% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name i_clk -period 20 -waveform {0 10} [get_ports {i_clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name w_clk100m -source [get_ports {i_clk}] -master_clock i_clk -divide_by 1 -multiply_by 2 [get_nets {w_clk100m}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {w_clk100m}] -group [get_clocks {i_clk}] |