Power Messages

Report Title Power Analysis Report
Design File E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_HPM\impl\gwsynthesis\HPM_LTPI.vg
Physical Constraints File E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_HPM\src\top.cst
Timing Constraints File E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_HPM\src\top.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Wed Jan 24 09:31:33 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Power Summary

Power Information:

Total Power (mW) 114.292
Quiescent Power (mW) 92.416
Dynamic Power (mW) 21.876

Thermal Information:

Junction Temperature 28.660
Theta JA 32.020
Max Allowed Ambient Temperature 81.340

Configure Information:

Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125
Use Vectorless Estimation false
Filter Glitches false
Related Vcd File
Related Saif File
Use Custom Theta JA false
Air Flow LFM_0
Heat Sink None
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Ambient Temperature 25.000

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.000 16.011 61.513 77.523
VCCX 2.500 1.059 11.364 31.056
VCCIO15 1.500 0.095 0.194 0.434
VCCIO25 2.500 1.068 0.464 3.830
VCCIO33 3.300 0.124 0.316 1.450

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 6.035 NA 4.884
IO 11.309 4.400 12.210
PLL 8.891 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
top 14.926 14.926(14.890)
top/u0_syspll_rPLL/ 6.276 6.276(0.000)
top/u1_apb2local/ 0.009 0.009(0.000)
top/u1_local2reg/ 0.353 0.353(0.000)
top/u_Uart_to_Bus_Top/ 0.511 0.511(0.511)
top/u_Uart_to_Bus_Top/uart_bus_core/ 0.511 0.511(0.446)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/ 0.446 0.446(0.446)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/ 0.018 0.018(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/ 0.214 0.214(0.214)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/ 0.196 0.196(0.154)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ 0.154 0.154(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/ 0.018 0.018(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/ 0.215 0.215(0.215)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/ 0.192 0.192(0.159)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ 0.159 0.159(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/ 0.022 0.022(0.000)
top/u_apb2local/ 0.008 0.008(0.000)
top/u_local2reg/ 0.346 0.346(0.000)
top/u_ltpi_hpm/ 7.388 7.388(7.388)
top/u_ltpi_hpm/u_ltpi_core/ 7.388 7.388(7.386)
top/u_ltpi_hpm/u_ltpi_core/u_apb2local/ 0.008 0.008(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_local2reg/ 0.261 0.261(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/ 7.117 7.117(7.117)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_target/ 0.239 0.239(0.239)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_target/u_datchl_target_fsm/ 0.035 0.035(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_target/u_datchl_target_inf/ 0.204 0.204(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/ 0.049 0.049(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/OEM.u_ltpi_oem/ 0.010 0.010(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/ 0.236 0.236(0.235)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].smbus_echo_inst/ 0.094 0.094(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/ 0.141 0.141(0.010)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/sync_controller_scl_inst/ 0.005 0.005(0.001)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/sync_controller_scl_inst/u_sync/ 0.001 0.001(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/sync_controller_sda_inst/ 0.005 0.005(0.001)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/sync_controller_sda_inst/u_sync/ 0.001 0.001(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/UART.u_ltpi_uart/ 0.011 0.011(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/ 6.571 6.571(6.570)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/ 2.727 2.727(2.615)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/ 2.615 2.615(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/ 0.146 0.146(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/ 1.805 1.805(0.502)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/ 0.502 0.502(0.404)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/crc8_check/ 0.011 0.011(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/ 0.033 0.033(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/ 0.360 0.360(0.346)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/ 0.169 0.169(0.058)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_rd_cmd_fifo/u_gw_ram_style/ 0.058 0.058(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/ 0.177 0.177(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/ 1.892 1.892(0.156)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/ 0.156 0.156(0.108)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/crc8_gen/ 0.011 0.011(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_encoder_8b10_nolut/ 0.036 0.036(0.000)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/ 0.061 0.061(0.060)
top/u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/ 0.060 0.060(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
w_clk25m 25.000 4.057
w_clk60m 60.000 4.522
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk 5.000 0.002
rxdiv5clk 30.030 0.097
RX_CLK_P 150.150 0.010
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk 25.000 0.002
u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk 25.000 0.002
i_clk 50.000 6.276